./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.03.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 9bd2c7ff Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6c9540ec-3801-4729-bad6-c9d6c2d08c90/bin/uautomizer-verify-uCwYo4JHxu/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6c9540ec-3801-4729-bad6-c9d6c2d08c90/bin/uautomizer-verify-uCwYo4JHxu/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6c9540ec-3801-4729-bad6-c9d6c2d08c90/bin/uautomizer-verify-uCwYo4JHxu/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6c9540ec-3801-4729-bad6-c9d6c2d08c90/bin/uautomizer-verify-uCwYo4JHxu/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.03.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6c9540ec-3801-4729-bad6-c9d6c2d08c90/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6c9540ec-3801-4729-bad6-c9d6c2d08c90/bin/uautomizer-verify-uCwYo4JHxu --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e96a4dadf08c19b3d92d901d7f9116f0323f4fb1660ac2537112df0afe321751 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-9bd2c7f [2023-11-19 07:46:13,602 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-19 07:46:13,708 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6c9540ec-3801-4729-bad6-c9d6c2d08c90/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-19 07:46:13,714 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-19 07:46:13,715 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-19 07:46:13,749 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-19 07:46:13,750 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-19 07:46:13,751 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-19 07:46:13,752 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-19 07:46:13,753 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-19 07:46:13,754 INFO L153 SettingsManager]: * Use SBE=true [2023-11-19 07:46:13,755 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-19 07:46:13,756 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-19 07:46:13,757 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-19 07:46:13,758 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-19 07:46:13,758 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-19 07:46:13,759 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-19 07:46:13,760 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-19 07:46:13,761 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-19 07:46:13,761 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-19 07:46:13,762 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-19 07:46:13,764 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-19 07:46:13,765 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-19 07:46:13,766 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-19 07:46:13,766 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-19 07:46:13,767 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-19 07:46:13,768 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-19 07:46:13,768 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-19 07:46:13,769 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-19 07:46:13,770 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-19 07:46:13,772 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-19 07:46:13,772 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-19 07:46:13,773 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-19 07:46:13,773 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-19 07:46:13,774 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-19 07:46:13,775 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-19 07:46:13,775 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6c9540ec-3801-4729-bad6-c9d6c2d08c90/bin/uautomizer-verify-uCwYo4JHxu/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6c9540ec-3801-4729-bad6-c9d6c2d08c90/bin/uautomizer-verify-uCwYo4JHxu Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e96a4dadf08c19b3d92d901d7f9116f0323f4fb1660ac2537112df0afe321751 [2023-11-19 07:46:14,228 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-19 07:46:14,270 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-19 07:46:14,273 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-19 07:46:14,276 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-19 07:46:14,277 INFO L274 PluginConnector]: CDTParser initialized [2023-11-19 07:46:14,278 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6c9540ec-3801-4729-bad6-c9d6c2d08c90/bin/uautomizer-verify-uCwYo4JHxu/../../sv-benchmarks/c/systemc/token_ring.03.cil-1.c [2023-11-19 07:46:17,728 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-19 07:46:18,006 INFO L384 CDTParser]: Found 1 translation units. [2023-11-19 07:46:18,007 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6c9540ec-3801-4729-bad6-c9d6c2d08c90/sv-benchmarks/c/systemc/token_ring.03.cil-1.c [2023-11-19 07:46:18,023 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6c9540ec-3801-4729-bad6-c9d6c2d08c90/bin/uautomizer-verify-uCwYo4JHxu/data/86b95c15e/76085fb593ca4914b8b63d144a23fb05/FLAG9c78b9985 [2023-11-19 07:46:18,038 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6c9540ec-3801-4729-bad6-c9d6c2d08c90/bin/uautomizer-verify-uCwYo4JHxu/data/86b95c15e/76085fb593ca4914b8b63d144a23fb05 [2023-11-19 07:46:18,041 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-19 07:46:18,043 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-19 07:46:18,044 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-19 07:46:18,045 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-19 07:46:18,053 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-19 07:46:18,054 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:46:18" (1/1) ... [2023-11-19 07:46:18,055 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@556274a4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:46:18, skipping insertion in model container [2023-11-19 07:46:18,055 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:46:18" (1/1) ... [2023-11-19 07:46:18,103 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-19 07:46:18,311 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:46:18,325 INFO L202 MainTranslator]: Completed pre-run [2023-11-19 07:46:18,375 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:46:18,400 INFO L206 MainTranslator]: Completed translation [2023-11-19 07:46:18,401 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:46:18 WrapperNode [2023-11-19 07:46:18,401 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-19 07:46:18,402 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-19 07:46:18,403 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-19 07:46:18,403 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-19 07:46:18,410 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:46:18" (1/1) ... [2023-11-19 07:46:18,421 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:46:18" (1/1) ... [2023-11-19 07:46:18,475 INFO L138 Inliner]: procedures = 34, calls = 42, calls flagged for inlining = 37, calls inlined = 65, statements flattened = 836 [2023-11-19 07:46:18,475 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-19 07:46:18,476 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-19 07:46:18,476 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-19 07:46:18,476 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-19 07:46:18,487 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:46:18" (1/1) ... [2023-11-19 07:46:18,489 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:46:18" (1/1) ... [2023-11-19 07:46:18,497 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:46:18" (1/1) ... [2023-11-19 07:46:18,506 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:46:18" (1/1) ... [2023-11-19 07:46:18,524 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:46:18" (1/1) ... [2023-11-19 07:46:18,537 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:46:18" (1/1) ... [2023-11-19 07:46:18,552 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:46:18" (1/1) ... [2023-11-19 07:46:18,556 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:46:18" (1/1) ... [2023-11-19 07:46:18,563 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-19 07:46:18,564 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-19 07:46:18,564 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-19 07:46:18,564 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-19 07:46:18,565 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:46:18" (1/1) ... [2023-11-19 07:46:18,577 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 07:46:18,593 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6c9540ec-3801-4729-bad6-c9d6c2d08c90/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:46:18,614 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6c9540ec-3801-4729-bad6-c9d6c2d08c90/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 07:46:18,633 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6c9540ec-3801-4729-bad6-c9d6c2d08c90/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-19 07:46:18,674 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-19 07:46:18,675 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-19 07:46:18,675 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-19 07:46:18,675 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-19 07:46:18,814 INFO L236 CfgBuilder]: Building ICFG [2023-11-19 07:46:18,817 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-19 07:46:19,821 INFO L277 CfgBuilder]: Performing block encoding [2023-11-19 07:46:19,846 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-19 07:46:19,847 INFO L302 CfgBuilder]: Removed 6 assume(true) statements. [2023-11-19 07:46:19,862 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:46:19 BoogieIcfgContainer [2023-11-19 07:46:19,863 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-19 07:46:19,864 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-19 07:46:19,864 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-19 07:46:19,869 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-19 07:46:19,870 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:46:19,870 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 07:46:18" (1/3) ... [2023-11-19 07:46:19,872 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@493333b5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:46:19, skipping insertion in model container [2023-11-19 07:46:19,872 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:46:19,872 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:46:18" (2/3) ... [2023-11-19 07:46:19,874 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@493333b5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:46:19, skipping insertion in model container [2023-11-19 07:46:19,874 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:46:19,875 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:46:19" (3/3) ... [2023-11-19 07:46:19,877 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.03.cil-1.c [2023-11-19 07:46:19,979 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-19 07:46:19,979 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-19 07:46:19,979 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-19 07:46:19,980 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-19 07:46:19,980 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-19 07:46:19,980 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-19 07:46:19,981 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-19 07:46:19,981 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-19 07:46:19,991 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 337 states, 336 states have (on average 1.5297619047619047) internal successors, (514), 336 states have internal predecessors, (514), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:20,070 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 278 [2023-11-19 07:46:20,070 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:46:20,070 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:46:20,086 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:20,087 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:20,087 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-19 07:46:20,089 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 337 states, 336 states have (on average 1.5297619047619047) internal successors, (514), 336 states have internal predecessors, (514), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:20,103 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 278 [2023-11-19 07:46:20,104 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:46:20,104 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:46:20,112 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:20,112 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:20,124 INFO L748 eck$LassoCheckResult]: Stem: 211#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 222#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 331#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 219#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 288#L304true assume !(1 == ~m_i~0);~m_st~0 := 2; 124#L304-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 27#L309-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 242#L314-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 139#L319-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32#L441true assume !(0 == ~M_E~0); 122#L441-2true assume !(0 == ~T1_E~0); 258#L446-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 96#L451-1true assume !(0 == ~T3_E~0); 279#L456-1true assume !(0 == ~E_M~0); 234#L461-1true assume !(0 == ~E_1~0); 254#L466-1true assume !(0 == ~E_2~0); 303#L471-1true assume !(0 == ~E_3~0); 49#L476-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87#L220true assume 1 == ~m_pc~0; 268#L221true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 105#L231true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 189#is_master_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 67#L543true assume !(0 != activate_threads_~tmp~1#1); 329#L543-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 207#L239true assume !(1 == ~t1_pc~0); 230#L239-2true is_transmit1_triggered_~__retres1~1#1 := 0; 275#L250true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 212#L551true assume !(0 != activate_threads_~tmp___0~0#1); 333#L551-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 213#L258true assume 1 == ~t2_pc~0; 252#L259true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 86#L269true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 335#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 228#L559true assume !(0 != activate_threads_~tmp___1~0#1); 131#L559-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 173#L277true assume !(1 == ~t3_pc~0); 330#L277-2true is_transmit3_triggered_~__retres1~3#1 := 0; 38#L288true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 64#L567true assume !(0 != activate_threads_~tmp___2~0#1); 93#L567-2true havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 311#L489true assume !(1 == ~M_E~0); 231#L489-2true assume !(1 == ~T1_E~0); 151#L494-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 59#L499-1true assume !(1 == ~T3_E~0); 125#L504-1true assume !(1 == ~E_M~0); 267#L509-1true assume !(1 == ~E_1~0); 51#L514-1true assume !(1 == ~E_2~0); 181#L519-1true assume !(1 == ~E_3~0); 56#L524-1true assume { :end_inline_reset_delta_events } true; 37#L690-2true [2023-11-19 07:46:20,133 INFO L750 eck$LassoCheckResult]: Loop: 37#L690-2true assume !false; 52#L691true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 192#L416-1true assume false; 114#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 154#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 199#L441-3true assume 0 == ~M_E~0;~M_E~0 := 1; 9#L441-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 260#L446-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 195#L451-3true assume !(0 == ~T3_E~0); 35#L456-3true assume 0 == ~E_M~0;~E_M~0 := 1; 72#L461-3true assume 0 == ~E_1~0;~E_1~0 := 1; 156#L466-3true assume 0 == ~E_2~0;~E_2~0 := 1; 263#L471-3true assume 0 == ~E_3~0;~E_3~0 := 1; 65#L476-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 106#L220-15true assume !(1 == ~m_pc~0); 162#L220-17true is_master_triggered_~__retres1~0#1 := 0; 210#L231-5true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 107#is_master_triggered_returnLabel#6true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 224#L543-15true assume !(0 != activate_threads_~tmp~1#1); 132#L543-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123#L239-15true assume !(1 == ~t1_pc~0); 266#L239-17true is_transmit1_triggered_~__retres1~1#1 := 0; 286#L250-5true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 91#is_transmit1_triggered_returnLabel#6true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 28#L551-15true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 321#L551-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 320#L258-15true assume !(1 == ~t2_pc~0); 95#L258-17true is_transmit2_triggered_~__retres1~2#1 := 0; 283#L269-5true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 284#is_transmit2_triggered_returnLabel#6true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 338#L559-15true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 237#L559-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 307#L277-15true assume !(1 == ~t3_pc~0); 14#L277-17true is_transmit3_triggered_~__retres1~3#1 := 0; 332#L288-5true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 247#is_transmit3_triggered_returnLabel#6true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 274#L567-15true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33#L567-17true havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29#L489-3true assume 1 == ~M_E~0;~M_E~0 := 2; 176#L489-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 225#L494-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 305#L499-3true assume !(1 == ~T3_E~0); 108#L504-3true assume 1 == ~E_M~0;~E_M~0 := 2; 18#L509-3true assume 1 == ~E_1~0;~E_1~0 := 2; 304#L514-3true assume 1 == ~E_2~0;~E_2~0 := 2; 167#L519-3true assume 1 == ~E_3~0;~E_3~0 := 2; 42#L524-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 53#L332-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 57#L354-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 287#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 152#L709true assume !(0 == start_simulation_~tmp~3#1); 8#L709-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 116#L332-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 55#L354-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 47#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 54#L664true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 157#L671true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 178#stop_simulation_returnLabel#1true start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 85#L722true assume !(0 != start_simulation_~tmp___0~1#1); 37#L690-2true [2023-11-19 07:46:20,141 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:20,141 INFO L85 PathProgramCache]: Analyzing trace with hash 1917692997, now seen corresponding path program 1 times [2023-11-19 07:46:20,151 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:20,152 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2023096847] [2023-11-19 07:46:20,153 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:20,153 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:20,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:46:20,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:46:20,474 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:46:20,475 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2023096847] [2023-11-19 07:46:20,476 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2023096847] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:46:20,476 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:46:20,476 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:46:20,479 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1007241174] [2023-11-19 07:46:20,480 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:46:20,485 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:46:20,486 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:20,487 INFO L85 PathProgramCache]: Analyzing trace with hash 1950122617, now seen corresponding path program 1 times [2023-11-19 07:46:20,487 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:20,487 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1685849744] [2023-11-19 07:46:20,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:20,488 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:20,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:46:20,562 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:46:20,563 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:46:20,563 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1685849744] [2023-11-19 07:46:20,563 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1685849744] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:46:20,564 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:46:20,564 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:46:20,564 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [517614013] [2023-11-19 07:46:20,564 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:46:20,566 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:46:20,567 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:46:20,617 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:46:20,617 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:46:20,620 INFO L87 Difference]: Start difference. First operand has 337 states, 336 states have (on average 1.5297619047619047) internal successors, (514), 336 states have internal predecessors, (514), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:20,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:46:20,675 INFO L93 Difference]: Finished difference Result 333 states and 495 transitions. [2023-11-19 07:46:20,677 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 333 states and 495 transitions. [2023-11-19 07:46:20,681 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2023-11-19 07:46:20,688 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 333 states to 327 states and 489 transitions. [2023-11-19 07:46:20,689 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 327 [2023-11-19 07:46:20,690 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 327 [2023-11-19 07:46:20,691 INFO L73 IsDeterministic]: Start isDeterministic. Operand 327 states and 489 transitions. [2023-11-19 07:46:20,694 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:46:20,694 INFO L218 hiAutomatonCegarLoop]: Abstraction has 327 states and 489 transitions. [2023-11-19 07:46:20,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states and 489 transitions. [2023-11-19 07:46:20,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 327. [2023-11-19 07:46:20,758 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 327 states, 327 states have (on average 1.4954128440366972) internal successors, (489), 326 states have internal predecessors, (489), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:20,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 327 states to 327 states and 489 transitions. [2023-11-19 07:46:20,761 INFO L240 hiAutomatonCegarLoop]: Abstraction has 327 states and 489 transitions. [2023-11-19 07:46:20,763 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:46:20,767 INFO L428 stractBuchiCegarLoop]: Abstraction has 327 states and 489 transitions. [2023-11-19 07:46:20,767 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-19 07:46:20,767 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 327 states and 489 transitions. [2023-11-19 07:46:20,771 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2023-11-19 07:46:20,771 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:46:20,771 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:46:20,773 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:20,773 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:20,774 INFO L748 eck$LassoCheckResult]: Stem: 956#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 957#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 969#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 967#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 968#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 887#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 737#L309-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 738#L314-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 906#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 745#L441 assume !(0 == ~M_E~0); 746#L441-2 assume !(0 == ~T1_E~0); 883#L446-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 850#L451-1 assume !(0 == ~T3_E~0); 851#L456-1 assume !(0 == ~E_M~0); 973#L461-1 assume !(0 == ~E_1~0); 974#L466-1 assume !(0 == ~E_2~0); 984#L471-1 assume !(0 == ~E_3~0); 780#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 781#L220 assume 1 == ~m_pc~0; 840#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 813#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 864#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 808#L543 assume !(0 != activate_threads_~tmp~1#1); 809#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 955#L239 assume !(1 == ~t1_pc~0); 953#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 954#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 776#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 777#L551 assume !(0 != activate_threads_~tmp___0~0#1); 958#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 959#L258 assume 1 == ~t2_pc~0; 960#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 837#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 838#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 971#L559 assume !(0 != activate_threads_~tmp___1~0#1); 895#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 896#L277 assume !(1 == ~t3_pc~0); 934#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 756#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 712#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 713#L567 assume !(0 != activate_threads_~tmp___2~0#1); 804#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 845#L489 assume !(1 == ~M_E~0); 972#L489-2 assume !(1 == ~T1_E~0); 917#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 795#L499-1 assume !(1 == ~T3_E~0); 796#L504-1 assume !(1 == ~E_M~0); 888#L509-1 assume !(1 == ~E_1~0); 782#L514-1 assume !(1 == ~E_2~0); 783#L519-1 assume !(1 == ~E_3~0); 789#L524-1 assume { :end_inline_reset_delta_events } true; 754#L690-2 [2023-11-19 07:46:20,775 INFO L750 eck$LassoCheckResult]: Loop: 754#L690-2 assume !false; 755#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 784#L416-1 assume !false; 818#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 819#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 763#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 714#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 715#L369 assume !(0 != eval_~tmp~0#1); 874#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 875#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 919#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 695#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 696#L446-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 944#L451-3 assume !(0 == ~T3_E~0); 750#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 751#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 817#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 921#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 806#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 807#L220-15 assume 1 == ~m_pc~0; 701#L221-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 702#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 865#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 866#L543-15 assume !(0 != activate_threads_~tmp~1#1); 894#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 884#L239-15 assume 1 == ~t1_pc~0; 885#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 987#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 839#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 735#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 736#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1005#L258-15 assume 1 == ~t2_pc~0; 918#L259-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 847#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 995#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 996#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 975#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 976#L277-15 assume 1 == ~t3_pc~0; 816#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 708#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 980#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 981#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 747#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 739#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 740#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 937#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 970#L499-3 assume !(1 == ~T3_E~0); 863#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 716#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 717#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 928#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 764#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 765#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 786#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 790#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 916#L709 assume !(0 == start_simulation_~tmp~3#1); 691#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 692#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 788#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 769#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 770#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 787#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 920#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 836#L722 assume !(0 != start_simulation_~tmp___0~1#1); 754#L690-2 [2023-11-19 07:46:20,776 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:20,776 INFO L85 PathProgramCache]: Analyzing trace with hash -2024185917, now seen corresponding path program 1 times [2023-11-19 07:46:20,776 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:20,777 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1750467880] [2023-11-19 07:46:20,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:20,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:20,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:46:20,841 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:46:20,841 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:46:20,841 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1750467880] [2023-11-19 07:46:20,842 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1750467880] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:46:20,842 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:46:20,842 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:46:20,843 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [79812314] [2023-11-19 07:46:20,843 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:46:20,843 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:46:20,844 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:20,844 INFO L85 PathProgramCache]: Analyzing trace with hash 67370114, now seen corresponding path program 1 times [2023-11-19 07:46:20,845 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:20,845 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [48830616] [2023-11-19 07:46:20,845 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:20,846 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:20,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:46:20,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:46:20,976 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:46:20,976 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [48830616] [2023-11-19 07:46:20,977 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [48830616] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:46:20,977 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:46:20,977 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:46:20,978 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2011212318] [2023-11-19 07:46:20,979 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:46:20,980 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:46:20,980 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:46:20,981 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:46:20,981 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:46:20,982 INFO L87 Difference]: Start difference. First operand 327 states and 489 transitions. cyclomatic complexity: 163 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:21,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:46:21,027 INFO L93 Difference]: Finished difference Result 327 states and 488 transitions. [2023-11-19 07:46:21,028 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 327 states and 488 transitions. [2023-11-19 07:46:21,032 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2023-11-19 07:46:21,043 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 327 states to 327 states and 488 transitions. [2023-11-19 07:46:21,044 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 327 [2023-11-19 07:46:21,046 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 327 [2023-11-19 07:46:21,046 INFO L73 IsDeterministic]: Start isDeterministic. Operand 327 states and 488 transitions. [2023-11-19 07:46:21,052 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:46:21,053 INFO L218 hiAutomatonCegarLoop]: Abstraction has 327 states and 488 transitions. [2023-11-19 07:46:21,054 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states and 488 transitions. [2023-11-19 07:46:21,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 327. [2023-11-19 07:46:21,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 327 states, 327 states have (on average 1.492354740061162) internal successors, (488), 326 states have internal predecessors, (488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:21,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 327 states to 327 states and 488 transitions. [2023-11-19 07:46:21,086 INFO L240 hiAutomatonCegarLoop]: Abstraction has 327 states and 488 transitions. [2023-11-19 07:46:21,086 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:46:21,087 INFO L428 stractBuchiCegarLoop]: Abstraction has 327 states and 488 transitions. [2023-11-19 07:46:21,088 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-19 07:46:21,088 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 327 states and 488 transitions. [2023-11-19 07:46:21,091 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2023-11-19 07:46:21,091 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:46:21,091 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:46:21,093 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:21,093 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:21,094 INFO L748 eck$LassoCheckResult]: Stem: 1619#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 1620#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1632#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1630#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1631#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 1551#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1400#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1401#L314-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1569#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1408#L441 assume !(0 == ~M_E~0); 1409#L441-2 assume !(0 == ~T1_E~0); 1546#L446-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1511#L451-1 assume !(0 == ~T3_E~0); 1512#L456-1 assume !(0 == ~E_M~0); 1636#L461-1 assume !(0 == ~E_1~0); 1637#L466-1 assume !(0 == ~E_2~0); 1647#L471-1 assume !(0 == ~E_3~0); 1441#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1442#L220 assume 1 == ~m_pc~0; 1502#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1476#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1526#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1471#L543 assume !(0 != activate_threads_~tmp~1#1); 1472#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1618#L239 assume !(1 == ~t1_pc~0); 1616#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1617#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1439#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1440#L551 assume !(0 != activate_threads_~tmp___0~0#1); 1621#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1622#L258 assume 1 == ~t2_pc~0; 1623#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1500#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1501#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1634#L559 assume !(0 != activate_threads_~tmp___1~0#1); 1557#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1558#L277 assume !(1 == ~t3_pc~0); 1596#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1419#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1375#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1376#L567 assume !(0 != activate_threads_~tmp___2~0#1); 1467#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1508#L489 assume !(1 == ~M_E~0); 1635#L489-2 assume !(1 == ~T1_E~0); 1579#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1456#L499-1 assume !(1 == ~T3_E~0); 1457#L504-1 assume !(1 == ~E_M~0); 1550#L509-1 assume !(1 == ~E_1~0); 1445#L514-1 assume !(1 == ~E_2~0); 1446#L519-1 assume !(1 == ~E_3~0); 1452#L524-1 assume { :end_inline_reset_delta_events } true; 1417#L690-2 [2023-11-19 07:46:21,094 INFO L750 eck$LassoCheckResult]: Loop: 1417#L690-2 assume !false; 1418#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1447#L416-1 assume !false; 1481#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1482#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1426#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1377#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1378#L369 assume !(0 != eval_~tmp~0#1); 1536#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1537#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1581#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1358#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1359#L446-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1607#L451-3 assume !(0 == ~T3_E~0); 1413#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1414#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1480#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1583#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1469#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1470#L220-15 assume 1 == ~m_pc~0; 1364#L221-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1365#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1527#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1528#L543-15 assume !(0 != activate_threads_~tmp~1#1); 1559#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1547#L239-15 assume 1 == ~t1_pc~0; 1548#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1650#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1506#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1398#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1399#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1668#L258-15 assume !(1 == ~t2_pc~0); 1509#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 1510#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1658#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1659#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1638#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1639#L277-15 assume 1 == ~t3_pc~0; 1479#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1371#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1643#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1644#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1410#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1402#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1403#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1600#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1633#L499-3 assume !(1 == ~T3_E~0); 1529#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1379#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1380#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1591#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1427#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1428#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1449#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1453#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1580#L709 assume !(0 == start_simulation_~tmp~3#1); 1356#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1357#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1451#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1437#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 1438#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1450#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1584#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1499#L722 assume !(0 != start_simulation_~tmp___0~1#1); 1417#L690-2 [2023-11-19 07:46:21,095 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:21,095 INFO L85 PathProgramCache]: Analyzing trace with hash 1377295041, now seen corresponding path program 1 times [2023-11-19 07:46:21,095 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:21,095 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [868649667] [2023-11-19 07:46:21,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:21,096 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:21,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:46:21,159 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:46:21,161 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:46:21,162 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [868649667] [2023-11-19 07:46:21,162 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [868649667] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:46:21,162 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:46:21,162 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:46:21,163 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [82664267] [2023-11-19 07:46:21,164 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:46:21,165 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:46:21,166 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:21,166 INFO L85 PathProgramCache]: Analyzing trace with hash -1509187645, now seen corresponding path program 1 times [2023-11-19 07:46:21,166 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:21,167 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2022386379] [2023-11-19 07:46:21,167 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:21,168 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:21,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:46:21,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:46:21,325 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:46:21,325 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2022386379] [2023-11-19 07:46:21,325 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2022386379] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:46:21,326 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:46:21,326 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:46:21,327 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [367122096] [2023-11-19 07:46:21,327 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:46:21,328 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:46:21,328 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:46:21,328 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:46:21,329 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:46:21,329 INFO L87 Difference]: Start difference. First operand 327 states and 488 transitions. cyclomatic complexity: 162 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:21,343 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:46:21,343 INFO L93 Difference]: Finished difference Result 327 states and 487 transitions. [2023-11-19 07:46:21,344 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 327 states and 487 transitions. [2023-11-19 07:46:21,348 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2023-11-19 07:46:21,351 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 327 states to 327 states and 487 transitions. [2023-11-19 07:46:21,352 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 327 [2023-11-19 07:46:21,352 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 327 [2023-11-19 07:46:21,353 INFO L73 IsDeterministic]: Start isDeterministic. Operand 327 states and 487 transitions. [2023-11-19 07:46:21,354 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:46:21,354 INFO L218 hiAutomatonCegarLoop]: Abstraction has 327 states and 487 transitions. [2023-11-19 07:46:21,358 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states and 487 transitions. [2023-11-19 07:46:21,375 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 327. [2023-11-19 07:46:21,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 327 states, 327 states have (on average 1.489296636085627) internal successors, (487), 326 states have internal predecessors, (487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:21,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 327 states to 327 states and 487 transitions. [2023-11-19 07:46:21,386 INFO L240 hiAutomatonCegarLoop]: Abstraction has 327 states and 487 transitions. [2023-11-19 07:46:21,387 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:46:21,389 INFO L428 stractBuchiCegarLoop]: Abstraction has 327 states and 487 transitions. [2023-11-19 07:46:21,389 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-19 07:46:21,389 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 327 states and 487 transitions. [2023-11-19 07:46:21,392 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2023-11-19 07:46:21,393 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:46:21,393 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:46:21,397 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:21,397 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:21,401 INFO L748 eck$LassoCheckResult]: Stem: 2282#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 2283#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2295#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2293#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2294#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 2213#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2061#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2062#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2232#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2071#L441 assume !(0 == ~M_E~0); 2072#L441-2 assume !(0 == ~T1_E~0); 2209#L446-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2174#L451-1 assume !(0 == ~T3_E~0); 2175#L456-1 assume !(0 == ~E_M~0); 2299#L461-1 assume !(0 == ~E_1~0); 2300#L466-1 assume !(0 == ~E_2~0); 2310#L471-1 assume !(0 == ~E_3~0); 2104#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2105#L220 assume 1 == ~m_pc~0; 2165#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2139#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2189#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2134#L543 assume !(0 != activate_threads_~tmp~1#1); 2135#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2281#L239 assume !(1 == ~t1_pc~0); 2279#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2280#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2102#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2103#L551 assume !(0 != activate_threads_~tmp___0~0#1); 2284#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2285#L258 assume 1 == ~t2_pc~0; 2286#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2163#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2164#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2297#L559 assume !(0 != activate_threads_~tmp___1~0#1); 2220#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2221#L277 assume !(1 == ~t3_pc~0); 2259#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2082#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2038#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2039#L567 assume !(0 != activate_threads_~tmp___2~0#1); 2130#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2171#L489 assume !(1 == ~M_E~0); 2298#L489-2 assume !(1 == ~T1_E~0); 2242#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2119#L499-1 assume !(1 == ~T3_E~0); 2120#L504-1 assume !(1 == ~E_M~0); 2214#L509-1 assume !(1 == ~E_1~0); 2108#L514-1 assume !(1 == ~E_2~0); 2109#L519-1 assume !(1 == ~E_3~0); 2115#L524-1 assume { :end_inline_reset_delta_events } true; 2080#L690-2 [2023-11-19 07:46:21,402 INFO L750 eck$LassoCheckResult]: Loop: 2080#L690-2 assume !false; 2081#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2110#L416-1 assume !false; 2144#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2145#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2089#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2040#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2041#L369 assume !(0 != eval_~tmp~0#1); 2199#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2200#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2244#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2021#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2022#L446-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2270#L451-3 assume !(0 == ~T3_E~0); 2076#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2077#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2143#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2246#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2132#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2133#L220-15 assume 1 == ~m_pc~0; 2027#L221-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2028#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2190#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2191#L543-15 assume !(0 != activate_threads_~tmp~1#1); 2222#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2210#L239-15 assume 1 == ~t1_pc~0; 2211#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2313#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2169#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2063#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2064#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2331#L258-15 assume 1 == ~t2_pc~0; 2245#L259-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2173#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2321#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2322#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2301#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2302#L277-15 assume !(1 == ~t3_pc~0); 2033#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 2034#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2306#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2307#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2073#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2065#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2066#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2263#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2296#L499-3 assume !(1 == ~T3_E~0); 2192#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2042#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2043#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2254#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2090#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2091#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2112#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2116#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 2243#L709 assume !(0 == start_simulation_~tmp~3#1); 2019#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2020#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2114#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2100#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 2101#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2113#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2247#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2162#L722 assume !(0 != start_simulation_~tmp___0~1#1); 2080#L690-2 [2023-11-19 07:46:21,403 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:21,404 INFO L85 PathProgramCache]: Analyzing trace with hash -868284413, now seen corresponding path program 1 times [2023-11-19 07:46:21,404 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:21,404 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1432623936] [2023-11-19 07:46:21,404 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:21,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:21,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:46:21,554 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:46:21,554 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:46:21,555 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1432623936] [2023-11-19 07:46:21,555 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1432623936] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:46:21,555 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:46:21,555 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:46:21,556 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1666368226] [2023-11-19 07:46:21,556 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:46:21,556 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:46:21,557 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:21,557 INFO L85 PathProgramCache]: Analyzing trace with hash -1605147517, now seen corresponding path program 1 times [2023-11-19 07:46:21,557 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:21,558 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [967161548] [2023-11-19 07:46:21,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:21,558 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:21,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:46:21,652 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:46:21,652 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:46:21,652 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [967161548] [2023-11-19 07:46:21,653 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [967161548] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:46:21,653 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:46:21,653 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:46:21,653 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1354143484] [2023-11-19 07:46:21,653 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:46:21,654 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:46:21,654 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:46:21,654 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:46:21,655 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:46:21,655 INFO L87 Difference]: Start difference. First operand 327 states and 487 transitions. cyclomatic complexity: 161 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:21,797 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:46:21,797 INFO L93 Difference]: Finished difference Result 569 states and 842 transitions. [2023-11-19 07:46:21,797 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 569 states and 842 transitions. [2023-11-19 07:46:21,805 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 506 [2023-11-19 07:46:21,811 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 569 states to 569 states and 842 transitions. [2023-11-19 07:46:21,811 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 569 [2023-11-19 07:46:21,812 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 569 [2023-11-19 07:46:21,812 INFO L73 IsDeterministic]: Start isDeterministic. Operand 569 states and 842 transitions. [2023-11-19 07:46:21,814 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:46:21,814 INFO L218 hiAutomatonCegarLoop]: Abstraction has 569 states and 842 transitions. [2023-11-19 07:46:21,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 569 states and 842 transitions. [2023-11-19 07:46:21,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 569 to 569. [2023-11-19 07:46:21,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 569 states, 569 states have (on average 1.4797891036906854) internal successors, (842), 568 states have internal predecessors, (842), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:21,834 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 569 states to 569 states and 842 transitions. [2023-11-19 07:46:21,834 INFO L240 hiAutomatonCegarLoop]: Abstraction has 569 states and 842 transitions. [2023-11-19 07:46:21,834 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:46:21,837 INFO L428 stractBuchiCegarLoop]: Abstraction has 569 states and 842 transitions. [2023-11-19 07:46:21,838 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-19 07:46:21,840 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 569 states and 842 transitions. [2023-11-19 07:46:21,844 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 506 [2023-11-19 07:46:21,848 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:46:21,848 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:46:21,854 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:21,855 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:21,855 INFO L748 eck$LassoCheckResult]: Stem: 3218#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 3219#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3234#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3231#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3232#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 3128#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2969#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2970#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3148#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2980#L441 assume !(0 == ~M_E~0); 2981#L441-2 assume !(0 == ~T1_E~0); 3124#L446-1 assume !(0 == ~T2_E~0); 3086#L451-1 assume !(0 == ~T3_E~0); 3087#L456-1 assume !(0 == ~E_M~0); 3241#L461-1 assume !(0 == ~E_1~0); 3242#L466-1 assume !(0 == ~E_2~0); 3255#L471-1 assume !(0 == ~E_3~0); 3013#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3014#L220 assume 1 == ~m_pc~0; 3076#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3049#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3101#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3044#L543 assume !(0 != activate_threads_~tmp~1#1); 3045#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3216#L239 assume !(1 == ~t1_pc~0); 3214#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3215#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3011#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3012#L551 assume !(0 != activate_threads_~tmp___0~0#1); 3220#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3221#L258 assume 1 == ~t2_pc~0; 3222#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3074#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3075#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3237#L559 assume !(0 != activate_threads_~tmp___1~0#1); 3136#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3137#L277 assume !(1 == ~t3_pc~0); 3180#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2991#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2946#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2947#L567 assume !(0 != activate_threads_~tmp___2~0#1); 3040#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3083#L489 assume 1 == ~M_E~0;~M_E~0 := 2; 3278#L489-2 assume !(1 == ~T1_E~0); 3364#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3160#L499-1 assume !(1 == ~T3_E~0); 3333#L504-1 assume !(1 == ~E_M~0); 3332#L509-1 assume !(1 == ~E_1~0); 3330#L514-1 assume !(1 == ~E_2~0); 3329#L519-1 assume !(1 == ~E_3~0); 3025#L524-1 assume { :end_inline_reset_delta_events } true; 2989#L690-2 [2023-11-19 07:46:21,855 INFO L750 eck$LassoCheckResult]: Loop: 2989#L690-2 assume !false; 2990#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3019#L416-1 assume !false; 3054#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3055#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3249#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3250#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3226#L369 assume !(0 != eval_~tmp~0#1); 3228#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3162#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3163#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3282#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3456#L446-3 assume !(0 == ~T2_E~0); 3455#L451-3 assume !(0 == ~T3_E~0); 3454#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3453#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3452#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3451#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3450#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3449#L220-15 assume 1 == ~m_pc~0; 3447#L221-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3446#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3445#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3444#L543-15 assume !(0 != activate_threads_~tmp~1#1); 3443#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3442#L239-15 assume 1 == ~t1_pc~0; 3440#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3439#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3438#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3437#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3436#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3435#L258-15 assume 1 == ~t2_pc~0; 3433#L259-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3432#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3431#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3430#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3429#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3428#L277-15 assume 1 == ~t3_pc~0; 3426#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3425#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3424#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3423#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3422#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3421#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2974#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3420#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3235#L499-3 assume !(1 == ~T3_E~0); 3419#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3418#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3417#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3416#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2999#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3000#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3411#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3410#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 3409#L709 assume !(0 == start_simulation_~tmp~3#1); 3188#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3115#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3024#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3009#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 3010#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3023#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3331#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 3073#L722 assume !(0 != start_simulation_~tmp___0~1#1); 2989#L690-2 [2023-11-19 07:46:21,856 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:21,856 INFO L85 PathProgramCache]: Analyzing trace with hash 1374817215, now seen corresponding path program 1 times [2023-11-19 07:46:21,856 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:21,856 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [984587166] [2023-11-19 07:46:21,856 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:21,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:21,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:46:21,913 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:46:21,914 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:46:21,914 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [984587166] [2023-11-19 07:46:21,914 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [984587166] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:46:21,914 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:46:21,914 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:46:21,915 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [370416776] [2023-11-19 07:46:21,915 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:46:21,915 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:46:21,916 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:21,916 INFO L85 PathProgramCache]: Analyzing trace with hash 1605710144, now seen corresponding path program 1 times [2023-11-19 07:46:21,917 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:21,917 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [191468374] [2023-11-19 07:46:21,917 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:21,917 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:21,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:46:22,000 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:46:22,000 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:46:22,001 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [191468374] [2023-11-19 07:46:22,001 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [191468374] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:46:22,001 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:46:22,001 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:46:22,001 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [978891356] [2023-11-19 07:46:22,001 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:46:22,002 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:46:22,003 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:46:22,003 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:46:22,003 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:46:22,003 INFO L87 Difference]: Start difference. First operand 569 states and 842 transitions. cyclomatic complexity: 275 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:22,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:46:22,066 INFO L93 Difference]: Finished difference Result 1047 states and 1523 transitions. [2023-11-19 07:46:22,066 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1047 states and 1523 transitions. [2023-11-19 07:46:22,076 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 983 [2023-11-19 07:46:22,085 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1047 states to 1047 states and 1523 transitions. [2023-11-19 07:46:22,086 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1047 [2023-11-19 07:46:22,087 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1047 [2023-11-19 07:46:22,087 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1047 states and 1523 transitions. [2023-11-19 07:46:22,089 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:46:22,090 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1047 states and 1523 transitions. [2023-11-19 07:46:22,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1047 states and 1523 transitions. [2023-11-19 07:46:22,113 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1047 to 993. [2023-11-19 07:46:22,115 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.459214501510574) internal successors, (1449), 992 states have internal predecessors, (1449), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:22,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1449 transitions. [2023-11-19 07:46:22,120 INFO L240 hiAutomatonCegarLoop]: Abstraction has 993 states and 1449 transitions. [2023-11-19 07:46:22,120 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:46:22,122 INFO L428 stractBuchiCegarLoop]: Abstraction has 993 states and 1449 transitions. [2023-11-19 07:46:22,123 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-19 07:46:22,123 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1449 transitions. [2023-11-19 07:46:22,129 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 929 [2023-11-19 07:46:22,129 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:46:22,129 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:46:22,131 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:22,131 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:22,131 INFO L748 eck$LassoCheckResult]: Stem: 4841#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 4842#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4857#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4854#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4855#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 4757#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4596#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4597#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4778#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4604#L441 assume !(0 == ~M_E~0); 4605#L441-2 assume !(0 == ~T1_E~0); 4751#L446-1 assume !(0 == ~T2_E~0); 4713#L451-1 assume !(0 == ~T3_E~0); 4714#L456-1 assume !(0 == ~E_M~0); 4861#L461-1 assume !(0 == ~E_1~0); 4862#L466-1 assume !(0 == ~E_2~0); 4875#L471-1 assume !(0 == ~E_3~0); 4639#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4640#L220 assume !(1 == ~m_pc~0); 4672#L220-2 is_master_triggered_~__retres1~0#1 := 0; 4673#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4730#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4668#L543 assume !(0 != activate_threads_~tmp~1#1); 4669#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4840#L239 assume !(1 == ~t1_pc~0); 4838#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4839#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4635#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4636#L551 assume !(0 != activate_threads_~tmp___0~0#1); 4843#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4844#L258 assume 1 == ~t2_pc~0; 4845#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4700#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4701#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4859#L559 assume !(0 != activate_threads_~tmp___1~0#1); 4766#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4767#L277 assume !(1 == ~t3_pc~0); 4813#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4615#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4571#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4572#L567 assume !(0 != activate_threads_~tmp___2~0#1); 4664#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4708#L489 assume 1 == ~M_E~0;~M_E~0 := 2; 4860#L489-2 assume !(1 == ~T1_E~0); 4793#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4655#L499-1 assume !(1 == ~T3_E~0); 4656#L504-1 assume !(1 == ~E_M~0); 4758#L509-1 assume !(1 == ~E_1~0); 5106#L514-1 assume !(1 == ~E_2~0); 5093#L519-1 assume !(1 == ~E_3~0); 5085#L524-1 assume { :end_inline_reset_delta_events } true; 5078#L690-2 [2023-11-19 07:46:22,131 INFO L750 eck$LassoCheckResult]: Loop: 5078#L690-2 assume !false; 5072#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5068#L416-1 assume !false; 5067#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 5065#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 5062#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 5061#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5059#L369 assume !(0 != eval_~tmp~0#1); 5058#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5056#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5053#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5054#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5273#L446-3 assume !(0 == ~T2_E~0); 5272#L451-3 assume !(0 == ~T3_E~0); 5271#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5270#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5269#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5268#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5267#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5266#L220-15 assume !(1 == ~m_pc~0); 5265#L220-17 is_master_triggered_~__retres1~0#1 := 0; 5031#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5028#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5029#L543-15 assume !(0 != activate_threads_~tmp~1#1); 5024#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5025#L239-15 assume 1 == ~t1_pc~0; 5018#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5019#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5007#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5008#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5000#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5001#L258-15 assume 1 == ~t2_pc~0; 5246#L259-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4992#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4989#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4990#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4981#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4982#L277-15 assume 1 == ~t3_pc~0; 5237#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4971#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4972#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4965#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4966#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4959#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4960#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4953#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4954#L499-3 assume !(1 == ~T3_E~0); 4948#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4949#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4939#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4940#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4930#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4931#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4915#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4916#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 5139#L709 assume !(0 == start_simulation_~tmp~3#1); 5132#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 5124#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 5118#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 5116#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 5114#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5107#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5094#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 5086#L722 assume !(0 != start_simulation_~tmp___0~1#1); 5078#L690-2 [2023-11-19 07:46:22,132 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:22,132 INFO L85 PathProgramCache]: Analyzing trace with hash -201740544, now seen corresponding path program 1 times [2023-11-19 07:46:22,133 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:22,133 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [911986138] [2023-11-19 07:46:22,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:22,134 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:22,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:46:22,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:46:22,197 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:46:22,197 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [911986138] [2023-11-19 07:46:22,197 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [911986138] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:46:22,197 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:46:22,197 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:46:22,198 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1687943410] [2023-11-19 07:46:22,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:46:22,198 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:46:22,199 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:22,199 INFO L85 PathProgramCache]: Analyzing trace with hash 732232449, now seen corresponding path program 1 times [2023-11-19 07:46:22,200 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:22,204 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1293808742] [2023-11-19 07:46:22,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:22,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:22,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:46:22,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:46:22,296 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:46:22,296 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1293808742] [2023-11-19 07:46:22,296 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1293808742] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:46:22,297 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:46:22,297 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:46:22,297 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [921398565] [2023-11-19 07:46:22,297 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:46:22,297 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:46:22,298 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:46:22,298 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:46:22,298 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:46:22,298 INFO L87 Difference]: Start difference. First operand 993 states and 1449 transitions. cyclomatic complexity: 460 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:22,449 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:46:22,449 INFO L93 Difference]: Finished difference Result 2247 states and 3226 transitions. [2023-11-19 07:46:22,449 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2247 states and 3226 transitions. [2023-11-19 07:46:22,468 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2114 [2023-11-19 07:46:22,518 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2247 states to 2247 states and 3226 transitions. [2023-11-19 07:46:22,519 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2247 [2023-11-19 07:46:22,522 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2247 [2023-11-19 07:46:22,522 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2247 states and 3226 transitions. [2023-11-19 07:46:22,526 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:46:22,526 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2247 states and 3226 transitions. [2023-11-19 07:46:22,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2247 states and 3226 transitions. [2023-11-19 07:46:22,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2247 to 1777. [2023-11-19 07:46:22,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1777 states, 1777 states have (on average 1.4490714687675859) internal successors, (2575), 1776 states have internal predecessors, (2575), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:22,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1777 states to 1777 states and 2575 transitions. [2023-11-19 07:46:22,573 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1777 states and 2575 transitions. [2023-11-19 07:46:22,573 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:46:22,574 INFO L428 stractBuchiCegarLoop]: Abstraction has 1777 states and 2575 transitions. [2023-11-19 07:46:22,574 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-19 07:46:22,574 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1777 states and 2575 transitions. [2023-11-19 07:46:22,584 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1712 [2023-11-19 07:46:22,584 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:46:22,584 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:46:22,586 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:22,586 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:22,586 INFO L748 eck$LassoCheckResult]: Stem: 8089#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 8090#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 8101#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8099#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8100#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 8005#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7845#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7846#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8026#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7855#L441 assume !(0 == ~M_E~0); 7856#L441-2 assume !(0 == ~T1_E~0); 8001#L446-1 assume !(0 == ~T2_E~0); 7963#L451-1 assume !(0 == ~T3_E~0); 7964#L456-1 assume !(0 == ~E_M~0); 8105#L461-1 assume !(0 == ~E_1~0); 8106#L466-1 assume !(0 == ~E_2~0); 8121#L471-1 assume !(0 == ~E_3~0); 7888#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7889#L220 assume !(1 == ~m_pc~0); 7922#L220-2 is_master_triggered_~__retres1~0#1 := 0; 7923#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7978#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7918#L543 assume !(0 != activate_threads_~tmp~1#1); 7919#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8088#L239 assume !(1 == ~t1_pc~0); 8086#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8087#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7886#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7887#L551 assume !(0 != activate_threads_~tmp___0~0#1); 8091#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8092#L258 assume !(1 == ~t2_pc~0); 8093#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7950#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7951#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8103#L559 assume !(0 != activate_threads_~tmp___1~0#1); 8013#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8014#L277 assume !(1 == ~t3_pc~0); 8062#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7866#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7823#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7824#L567 assume !(0 != activate_threads_~tmp___2~0#1); 7914#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7960#L489 assume 1 == ~M_E~0;~M_E~0 := 2; 8152#L489-2 assume !(1 == ~T1_E~0); 9492#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8039#L499-1 assume !(1 == ~T3_E~0); 9489#L504-1 assume !(1 == ~E_M~0); 8125#L509-1 assume !(1 == ~E_1~0); 7892#L514-1 assume !(1 == ~E_2~0); 7893#L519-1 assume !(1 == ~E_3~0); 7899#L524-1 assume { :end_inline_reset_delta_events } true; 7864#L690-2 [2023-11-19 07:46:22,587 INFO L750 eck$LassoCheckResult]: Loop: 7864#L690-2 assume !false; 7865#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7894#L416-1 assume !false; 7928#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 7929#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 7873#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 7825#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7826#L369 assume !(0 != eval_~tmp~0#1); 7989#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7990#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8042#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7806#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7807#L446-3 assume !(0 == ~T2_E~0); 8075#L451-3 assume !(0 == ~T3_E~0); 7860#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7861#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7927#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8046#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7916#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7917#L220-15 assume !(1 == ~m_pc~0); 7979#L220-17 is_master_triggered_~__retres1~0#1 := 0; 8052#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7980#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7981#L543-15 assume !(0 != activate_threads_~tmp~1#1); 8015#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8002#L239-15 assume 1 == ~t1_pc~0; 8003#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8124#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7956#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7847#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7848#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8157#L258-15 assume !(1 == ~t2_pc~0); 7961#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 7962#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8136#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8137#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8108#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8109#L277-15 assume 1 == ~t3_pc~0; 7926#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7819#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8116#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8117#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7857#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7849#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7850#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8066#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8102#L499-3 assume !(1 == ~T3_E~0); 7982#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7827#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7828#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8057#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7874#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 7875#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 7896#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 7900#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 8040#L709 assume !(0 == start_simulation_~tmp~3#1); 7804#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 7805#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 7898#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 7884#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 7885#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7897#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8047#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 7949#L722 assume !(0 != start_simulation_~tmp___0~1#1); 7864#L690-2 [2023-11-19 07:46:22,587 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:22,587 INFO L85 PathProgramCache]: Analyzing trace with hash -1175229503, now seen corresponding path program 1 times [2023-11-19 07:46:22,587 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:22,588 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [213776220] [2023-11-19 07:46:22,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:22,588 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:22,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:46:22,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:46:22,641 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:46:22,641 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [213776220] [2023-11-19 07:46:22,641 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [213776220] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:46:22,642 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:46:22,642 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:46:22,642 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [530416722] [2023-11-19 07:46:22,642 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:46:22,642 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:46:22,642 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:22,643 INFO L85 PathProgramCache]: Analyzing trace with hash -844325310, now seen corresponding path program 1 times [2023-11-19 07:46:22,643 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:22,643 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [804546259] [2023-11-19 07:46:22,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:22,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:22,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:46:22,698 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:46:22,698 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:46:22,698 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [804546259] [2023-11-19 07:46:22,699 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [804546259] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:46:22,699 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:46:22,699 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:46:22,699 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [649605593] [2023-11-19 07:46:22,699 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:46:22,700 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:46:22,700 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:46:22,700 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:46:22,700 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:46:22,700 INFO L87 Difference]: Start difference. First operand 1777 states and 2575 transitions. cyclomatic complexity: 802 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:22,745 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:46:22,745 INFO L93 Difference]: Finished difference Result 2591 states and 3752 transitions. [2023-11-19 07:46:22,745 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2591 states and 3752 transitions. [2023-11-19 07:46:22,773 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2526 [2023-11-19 07:46:22,796 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2591 states to 2591 states and 3752 transitions. [2023-11-19 07:46:22,796 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2591 [2023-11-19 07:46:22,801 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2591 [2023-11-19 07:46:22,801 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2591 states and 3752 transitions. [2023-11-19 07:46:22,806 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:46:22,806 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2591 states and 3752 transitions. [2023-11-19 07:46:22,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2591 states and 3752 transitions. [2023-11-19 07:46:22,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2591 to 1801. [2023-11-19 07:46:22,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4519711271515825) internal successors, (2615), 1800 states have internal predecessors, (2615), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:22,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2615 transitions. [2023-11-19 07:46:22,857 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2615 transitions. [2023-11-19 07:46:22,857 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:46:22,858 INFO L428 stractBuchiCegarLoop]: Abstraction has 1801 states and 2615 transitions. [2023-11-19 07:46:22,858 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-19 07:46:22,859 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2615 transitions. [2023-11-19 07:46:22,870 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1744 [2023-11-19 07:46:22,870 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:46:22,870 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:46:22,872 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:22,872 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:22,872 INFO L748 eck$LassoCheckResult]: Stem: 12469#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 12470#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 12482#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12480#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12481#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 12381#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12222#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12223#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12402#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12232#L441 assume !(0 == ~M_E~0); 12233#L441-2 assume !(0 == ~T1_E~0); 12377#L446-1 assume !(0 == ~T2_E~0); 12337#L451-1 assume !(0 == ~T3_E~0); 12338#L456-1 assume !(0 == ~E_M~0); 12488#L461-1 assume !(0 == ~E_1~0); 12489#L466-1 assume !(0 == ~E_2~0); 12506#L471-1 assume !(0 == ~E_3~0); 12265#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12266#L220 assume !(1 == ~m_pc~0); 12300#L220-2 is_master_triggered_~__retres1~0#1 := 0; 12301#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12353#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12296#L543 assume !(0 != activate_threads_~tmp~1#1); 12297#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12467#L239 assume !(1 == ~t1_pc~0); 12465#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12466#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12263#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12264#L551 assume !(0 != activate_threads_~tmp___0~0#1); 12471#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12472#L258 assume !(1 == ~t2_pc~0); 12473#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12326#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12327#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12485#L559 assume !(0 != activate_threads_~tmp___1~0#1); 12388#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12389#L277 assume !(1 == ~t3_pc~0); 12439#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12243#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12200#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12201#L567 assume !(0 != activate_threads_~tmp___2~0#1); 12292#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12334#L489 assume !(1 == ~M_E~0); 12486#L489-2 assume !(1 == ~T1_E~0); 12416#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12281#L499-1 assume !(1 == ~T3_E~0); 12282#L504-1 assume !(1 == ~E_M~0); 12382#L509-1 assume !(1 == ~E_1~0); 12269#L514-1 assume !(1 == ~E_2~0); 12270#L519-1 assume !(1 == ~E_3~0); 12277#L524-1 assume { :end_inline_reset_delta_events } true; 12241#L690-2 [2023-11-19 07:46:22,872 INFO L750 eck$LassoCheckResult]: Loop: 12241#L690-2 assume !false; 12242#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12271#L416-1 assume !false; 12455#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 13588#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13583#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 13579#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 13575#L369 assume !(0 != eval_~tmp~0#1); 12365#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12366#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12420#L441-3 assume !(0 == ~M_E~0); 12183#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12184#L446-3 assume !(0 == ~T2_E~0); 12456#L451-3 assume !(0 == ~T3_E~0); 12237#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12238#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12305#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12422#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12509#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13958#L220-15 assume !(1 == ~m_pc~0); 13957#L220-17 is_master_triggered_~__retres1~0#1 := 0; 13956#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13955#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13954#L543-15 assume !(0 != activate_threads_~tmp~1#1); 13953#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13952#L239-15 assume 1 == ~t1_pc~0; 13950#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13949#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12332#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12224#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12225#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12552#L258-15 assume !(1 == ~t2_pc~0); 12553#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 13924#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13920#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13918#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12491#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12492#L277-15 assume 1 == ~t3_pc~0; 12304#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12196#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12502#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12503#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13793#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13792#L489-3 assume !(1 == ~M_E~0); 13691#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13791#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13790#L499-3 assume !(1 == ~T3_E~0); 13789#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12204#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12205#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12434#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12251#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 12252#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13747#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 12534#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 12417#L709 assume !(0 == start_simulation_~tmp~3#1); 12181#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 12182#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 12276#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 12261#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 12262#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12275#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12423#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 12325#L722 assume !(0 != start_simulation_~tmp___0~1#1); 12241#L690-2 [2023-11-19 07:46:22,873 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:22,873 INFO L85 PathProgramCache]: Analyzing trace with hash -495171133, now seen corresponding path program 1 times [2023-11-19 07:46:22,873 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:22,873 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [435579677] [2023-11-19 07:46:22,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:22,873 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:22,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:46:22,926 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:46:22,927 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:46:22,928 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [435579677] [2023-11-19 07:46:22,928 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [435579677] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:46:22,929 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:46:22,929 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:46:22,934 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1035266719] [2023-11-19 07:46:22,934 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:46:22,935 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:46:22,935 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:22,935 INFO L85 PathProgramCache]: Analyzing trace with hash 454395522, now seen corresponding path program 1 times [2023-11-19 07:46:22,935 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:22,938 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1766798171] [2023-11-19 07:46:22,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:22,938 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:22,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:46:22,989 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:46:22,989 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:46:22,989 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1766798171] [2023-11-19 07:46:22,991 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1766798171] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:46:22,992 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:46:22,992 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:46:22,992 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [834880778] [2023-11-19 07:46:22,992 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:46:22,992 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:46:22,993 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:46:22,993 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:46:22,993 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:46:22,993 INFO L87 Difference]: Start difference. First operand 1801 states and 2615 transitions. cyclomatic complexity: 816 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:23,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:46:23,077 INFO L93 Difference]: Finished difference Result 2585 states and 3720 transitions. [2023-11-19 07:46:23,078 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2585 states and 3720 transitions. [2023-11-19 07:46:23,098 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2526 [2023-11-19 07:46:23,121 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2585 states to 2585 states and 3720 transitions. [2023-11-19 07:46:23,122 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2585 [2023-11-19 07:46:23,125 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2585 [2023-11-19 07:46:23,125 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2585 states and 3720 transitions. [2023-11-19 07:46:23,129 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:46:23,130 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2585 states and 3720 transitions. [2023-11-19 07:46:23,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2585 states and 3720 transitions. [2023-11-19 07:46:23,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2585 to 1801. [2023-11-19 07:46:23,170 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4425319267073848) internal successors, (2598), 1800 states have internal predecessors, (2598), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:23,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2598 transitions. [2023-11-19 07:46:23,178 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2598 transitions. [2023-11-19 07:46:23,178 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:46:23,180 INFO L428 stractBuchiCegarLoop]: Abstraction has 1801 states and 2598 transitions. [2023-11-19 07:46:23,180 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-19 07:46:23,180 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2598 transitions. [2023-11-19 07:46:23,193 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1744 [2023-11-19 07:46:23,193 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:46:23,193 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:46:23,194 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:23,195 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:23,195 INFO L748 eck$LassoCheckResult]: Stem: 16855#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 16856#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 16867#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16865#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16866#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 16777#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16622#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16623#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16798#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16630#L441 assume !(0 == ~M_E~0); 16631#L441-2 assume !(0 == ~T1_E~0); 16773#L446-1 assume !(0 == ~T2_E~0); 16737#L451-1 assume !(0 == ~T3_E~0); 16738#L456-1 assume !(0 == ~E_M~0); 16873#L461-1 assume !(0 == ~E_1~0); 16874#L466-1 assume !(0 == ~E_2~0); 16888#L471-1 assume !(0 == ~E_3~0); 16665#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16666#L220 assume !(1 == ~m_pc~0); 16698#L220-2 is_master_triggered_~__retres1~0#1 := 0; 16699#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16754#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16694#L543 assume !(0 != activate_threads_~tmp~1#1); 16695#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16854#L239 assume !(1 == ~t1_pc~0); 16852#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16853#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16661#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16662#L551 assume !(0 != activate_threads_~tmp___0~0#1); 16857#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16858#L258 assume !(1 == ~t2_pc~0); 16859#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16724#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16725#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16870#L559 assume !(0 != activate_threads_~tmp___1~0#1); 16784#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16785#L277 assume !(1 == ~t3_pc~0); 16831#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16641#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16598#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16599#L567 assume !(0 != activate_threads_~tmp___2~0#1); 16690#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16734#L489 assume !(1 == ~M_E~0); 16871#L489-2 assume !(1 == ~T1_E~0); 16812#L494-1 assume !(1 == ~T2_E~0); 16679#L499-1 assume !(1 == ~T3_E~0); 16680#L504-1 assume !(1 == ~E_M~0); 16778#L509-1 assume !(1 == ~E_1~0); 16667#L514-1 assume !(1 == ~E_2~0); 16668#L519-1 assume !(1 == ~E_3~0); 16674#L524-1 assume { :end_inline_reset_delta_events } true; 16675#L690-2 [2023-11-19 07:46:23,195 INFO L750 eck$LassoCheckResult]: Loop: 16675#L690-2 assume !false; 17669#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17661#L416-1 assume !false; 17657#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 17651#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 17645#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 17641#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 17636#L369 assume !(0 != eval_~tmp~0#1); 17631#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17625#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17620#L441-3 assume !(0 == ~M_E~0); 17616#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17612#L446-3 assume !(0 == ~T2_E~0); 17608#L451-3 assume !(0 == ~T3_E~0); 17602#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17590#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17576#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17568#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17561#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17554#L220-15 assume !(1 == ~m_pc~0); 17551#L220-17 is_master_triggered_~__retres1~0#1 := 0; 17544#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17536#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 17528#L543-15 assume !(0 != activate_threads_~tmp~1#1); 17521#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17516#L239-15 assume 1 == ~t1_pc~0; 17513#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17511#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17506#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17504#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17502#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17499#L258-15 assume !(1 == ~t2_pc~0); 17449#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 17496#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17494#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17492#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17490#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17488#L277-15 assume 1 == ~t3_pc~0; 17485#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17483#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17481#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17479#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17477#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17475#L489-3 assume !(1 == ~M_E~0); 17383#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17472#L494-3 assume !(1 == ~T2_E~0); 17470#L499-3 assume !(1 == ~T3_E~0); 17468#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17466#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17464#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17461#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17459#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 17457#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 17452#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 17450#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 16810#L709 assume !(0 == start_simulation_~tmp~3#1); 16811#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 17723#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 17717#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 17713#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 17710#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17706#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17691#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 17683#L722 assume !(0 != start_simulation_~tmp___0~1#1); 16675#L690-2 [2023-11-19 07:46:23,196 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:23,196 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 1 times [2023-11-19 07:46:23,196 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:23,196 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1877234840] [2023-11-19 07:46:23,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:23,197 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:23,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:23,208 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:46:23,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:23,244 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:46:23,245 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:23,245 INFO L85 PathProgramCache]: Analyzing trace with hash -1234548220, now seen corresponding path program 1 times [2023-11-19 07:46:23,245 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:23,246 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2023403752] [2023-11-19 07:46:23,246 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:23,246 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:23,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:46:23,302 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:46:23,302 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:46:23,302 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2023403752] [2023-11-19 07:46:23,302 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2023403752] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:46:23,302 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:46:23,302 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:46:23,302 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2115925202] [2023-11-19 07:46:23,303 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:46:23,303 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:46:23,303 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:46:23,303 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 07:46:23,304 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 07:46:23,304 INFO L87 Difference]: Start difference. First operand 1801 states and 2598 transitions. cyclomatic complexity: 799 Second operand has 5 states, 5 states have (on average 12.8) internal successors, (64), 5 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:23,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:46:23,426 INFO L93 Difference]: Finished difference Result 3157 states and 4474 transitions. [2023-11-19 07:46:23,426 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3157 states and 4474 transitions. [2023-11-19 07:46:23,446 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3096 [2023-11-19 07:46:23,472 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3157 states to 3157 states and 4474 transitions. [2023-11-19 07:46:23,472 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3157 [2023-11-19 07:46:23,475 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3157 [2023-11-19 07:46:23,475 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3157 states and 4474 transitions. [2023-11-19 07:46:23,481 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:46:23,481 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3157 states and 4474 transitions. [2023-11-19 07:46:23,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3157 states and 4474 transitions. [2023-11-19 07:46:23,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3157 to 1825. [2023-11-19 07:46:23,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1825 states, 1825 states have (on average 1.4367123287671233) internal successors, (2622), 1824 states have internal predecessors, (2622), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:23,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1825 states to 1825 states and 2622 transitions. [2023-11-19 07:46:23,534 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1825 states and 2622 transitions. [2023-11-19 07:46:23,535 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-19 07:46:23,535 INFO L428 stractBuchiCegarLoop]: Abstraction has 1825 states and 2622 transitions. [2023-11-19 07:46:23,535 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-19 07:46:23,535 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1825 states and 2622 transitions. [2023-11-19 07:46:23,545 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1768 [2023-11-19 07:46:23,545 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:46:23,545 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:46:23,546 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:23,546 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:23,546 INFO L748 eck$LassoCheckResult]: Stem: 21848#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 21849#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 21860#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21858#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21859#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 21763#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21595#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21596#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21785#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21605#L441 assume !(0 == ~M_E~0); 21606#L441-2 assume !(0 == ~T1_E~0); 21759#L446-1 assume !(0 == ~T2_E~0); 21717#L451-1 assume !(0 == ~T3_E~0); 21718#L456-1 assume !(0 == ~E_M~0); 21866#L461-1 assume !(0 == ~E_1~0); 21867#L466-1 assume !(0 == ~E_2~0); 21883#L471-1 assume !(0 == ~E_3~0); 21639#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21640#L220 assume !(1 == ~m_pc~0); 21676#L220-2 is_master_triggered_~__retres1~0#1 := 0; 21677#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21732#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21672#L543 assume !(0 != activate_threads_~tmp~1#1); 21673#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21847#L239 assume !(1 == ~t1_pc~0); 21845#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21846#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21637#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21638#L551 assume !(0 != activate_threads_~tmp___0~0#1); 21850#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21851#L258 assume !(1 == ~t2_pc~0); 21852#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21705#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21706#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21864#L559 assume !(0 != activate_threads_~tmp___1~0#1); 21771#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21772#L277 assume !(1 == ~t3_pc~0); 21823#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21616#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21573#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21574#L567 assume !(0 != activate_threads_~tmp___2~0#1); 21667#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21714#L489 assume !(1 == ~M_E~0); 21865#L489-2 assume !(1 == ~T1_E~0); 21798#L494-1 assume !(1 == ~T2_E~0); 21656#L499-1 assume !(1 == ~T3_E~0); 21657#L504-1 assume !(1 == ~E_M~0); 21764#L509-1 assume !(1 == ~E_1~0); 21643#L514-1 assume !(1 == ~E_2~0); 21644#L519-1 assume !(1 == ~E_3~0); 21651#L524-1 assume { :end_inline_reset_delta_events } true; 21652#L690-2 [2023-11-19 07:46:23,547 INFO L750 eck$LassoCheckResult]: Loop: 21652#L690-2 assume !false; 23304#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23219#L416-1 assume !false; 22933#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 22924#L332 assume !(0 == ~m_st~0); 22925#L336 assume !(0 == ~t1_st~0); 22922#L340 assume !(0 == ~t2_st~0); 22923#L344 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 21874#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21875#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22422#L369 assume !(0 != eval_~tmp~0#1); 22907#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22905#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22903#L441-3 assume !(0 == ~M_E~0); 22898#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22899#L446-3 assume !(0 == ~T2_E~0); 22888#L451-3 assume !(0 == ~T3_E~0); 22889#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22880#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22881#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22872#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22873#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22862#L220-15 assume !(1 == ~m_pc~0); 22863#L220-17 is_master_triggered_~__retres1~0#1 := 0; 22849#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22850#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 22009#L543-15 assume !(0 != activate_threads_~tmp~1#1); 22010#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23004#L239-15 assume 1 == ~t1_pc~0; 23002#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21902#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21710#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21597#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21598#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21922#L258-15 assume !(1 == ~t2_pc~0); 21715#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 21716#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21899#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21900#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21869#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21870#L277-15 assume 1 == ~t3_pc~0; 21680#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21569#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21879#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21880#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21607#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21599#L489-3 assume !(1 == ~M_E~0); 21600#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21827#L494-3 assume !(1 == ~T2_E~0); 21917#L499-3 assume !(1 == ~T3_E~0); 21918#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21577#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21578#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21817#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21818#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21646#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21648#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21653#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 21799#L709 assume !(0 == start_simulation_~tmp~3#1); 21800#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 23347#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 23343#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 23342#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 23341#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23340#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23306#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 23305#L722 assume !(0 != start_simulation_~tmp___0~1#1); 21652#L690-2 [2023-11-19 07:46:23,547 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:23,547 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 2 times [2023-11-19 07:46:23,548 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:23,548 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [389998171] [2023-11-19 07:46:23,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:23,548 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:23,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:23,569 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:46:23,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:23,586 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:46:23,586 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:23,587 INFO L85 PathProgramCache]: Analyzing trace with hash 435870986, now seen corresponding path program 1 times [2023-11-19 07:46:23,587 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:23,587 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2073189529] [2023-11-19 07:46:23,587 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:23,587 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:23,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:46:23,647 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:46:23,647 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:46:23,647 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2073189529] [2023-11-19 07:46:23,648 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2073189529] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:46:23,648 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:46:23,648 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:46:23,648 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1000465299] [2023-11-19 07:46:23,648 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:46:23,649 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:46:23,649 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:46:23,649 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:46:23,649 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:46:23,650 INFO L87 Difference]: Start difference. First operand 1825 states and 2622 transitions. cyclomatic complexity: 799 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:23,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:46:23,711 INFO L93 Difference]: Finished difference Result 3273 states and 4622 transitions. [2023-11-19 07:46:23,711 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3273 states and 4622 transitions. [2023-11-19 07:46:23,733 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3216 [2023-11-19 07:46:23,760 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3273 states to 3273 states and 4622 transitions. [2023-11-19 07:46:23,760 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3273 [2023-11-19 07:46:23,764 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3273 [2023-11-19 07:46:23,764 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3273 states and 4622 transitions. [2023-11-19 07:46:23,771 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:46:23,771 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3273 states and 4622 transitions. [2023-11-19 07:46:23,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3273 states and 4622 transitions. [2023-11-19 07:46:23,833 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3273 to 3183. [2023-11-19 07:46:23,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3183 states, 3183 states have (on average 1.413760603204524) internal successors, (4500), 3182 states have internal predecessors, (4500), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:23,851 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3183 states to 3183 states and 4500 transitions. [2023-11-19 07:46:23,851 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3183 states and 4500 transitions. [2023-11-19 07:46:23,852 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:46:23,852 INFO L428 stractBuchiCegarLoop]: Abstraction has 3183 states and 4500 transitions. [2023-11-19 07:46:23,852 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-19 07:46:23,852 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3183 states and 4500 transitions. [2023-11-19 07:46:23,865 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3126 [2023-11-19 07:46:23,865 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:46:23,866 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:46:23,867 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:23,867 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:23,867 INFO L748 eck$LassoCheckResult]: Stem: 26950#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 26951#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 26963#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26961#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26962#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 26865#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26701#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26702#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26888#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26709#L441 assume !(0 == ~M_E~0); 26710#L441-2 assume !(0 == ~T1_E~0); 26861#L446-1 assume !(0 == ~T2_E~0); 26823#L451-1 assume !(0 == ~T3_E~0); 26824#L456-1 assume !(0 == ~E_M~0); 26970#L461-1 assume !(0 == ~E_1~0); 26971#L466-1 assume !(0 == ~E_2~0); 26988#L471-1 assume !(0 == ~E_3~0); 26745#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26746#L220 assume !(1 == ~m_pc~0); 26778#L220-2 is_master_triggered_~__retres1~0#1 := 0; 26779#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26841#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 26776#L543 assume !(0 != activate_threads_~tmp~1#1); 26777#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26949#L239 assume !(1 == ~t1_pc~0); 26947#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26948#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26741#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26742#L551 assume !(0 != activate_threads_~tmp___0~0#1); 26952#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26953#L258 assume !(1 == ~t2_pc~0); 26954#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26808#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26809#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 26966#L559 assume !(0 != activate_threads_~tmp___1~0#1); 26875#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26876#L277 assume !(1 == ~t3_pc~0); 26927#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26720#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26679#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 26680#L567 assume !(0 != activate_threads_~tmp___2~0#1); 26770#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26818#L489 assume !(1 == ~M_E~0); 26967#L489-2 assume !(1 == ~T1_E~0); 26903#L494-1 assume !(1 == ~T2_E~0); 26761#L499-1 assume !(1 == ~T3_E~0); 26762#L504-1 assume !(1 == ~E_M~0); 26866#L509-1 assume !(1 == ~E_1~0); 26748#L514-1 assume !(1 == ~E_2~0); 26749#L519-1 assume !(1 == ~E_3~0); 26753#L524-1 assume { :end_inline_reset_delta_events } true; 26754#L690-2 [2023-11-19 07:46:23,868 INFO L750 eck$LassoCheckResult]: Loop: 26754#L690-2 assume !false; 28954#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28950#L416-1 assume !false; 28947#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 28944#L332 assume !(0 == ~m_st~0); 28945#L336 assume !(0 == ~t1_st~0); 29329#L340 assume !(0 == ~t2_st~0); 29327#L344 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 29326#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 29325#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 29324#L369 assume !(0 != eval_~tmp~0#1); 29322#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29319#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29318#L441-3 assume !(0 == ~M_E~0); 29314#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29313#L446-3 assume !(0 == ~T2_E~0); 29312#L451-3 assume !(0 == ~T3_E~0); 27059#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 27054#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27048#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27044#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26772#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26773#L220-15 assume !(1 == ~m_pc~0); 26838#L220-17 is_master_triggered_~__retres1~0#1 := 0; 26915#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26839#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 26840#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26964#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29306#L239-15 assume 1 == ~t1_pc~0; 29303#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29301#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29299#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 29296#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29294#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29292#L258-15 assume !(1 == ~t2_pc~0); 28870#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 29288#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29286#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 29284#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29282#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29280#L277-15 assume 1 == ~t3_pc~0; 29278#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29276#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29274#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 29268#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29105#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29102#L489-3 assume !(1 == ~M_E~0); 29098#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29096#L494-3 assume !(1 == ~T2_E~0); 29094#L499-3 assume !(1 == ~T3_E~0); 29092#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29089#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29081#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29075#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29068#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 29061#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 29056#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 29050#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 29044#L709 assume !(0 == start_simulation_~tmp~3#1); 29036#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 29028#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 29022#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 29015#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 29009#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28991#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28984#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 28975#L722 assume !(0 != start_simulation_~tmp___0~1#1); 26754#L690-2 [2023-11-19 07:46:23,868 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:23,868 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 3 times [2023-11-19 07:46:23,869 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:23,869 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [640484435] [2023-11-19 07:46:23,869 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:23,869 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:23,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:23,878 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:46:23,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:23,894 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:46:23,895 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:23,895 INFO L85 PathProgramCache]: Analyzing trace with hash 12224264, now seen corresponding path program 1 times [2023-11-19 07:46:23,895 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:23,895 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1948947444] [2023-11-19 07:46:23,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:23,895 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:23,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:46:23,968 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:46:23,969 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:46:23,969 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1948947444] [2023-11-19 07:46:23,969 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1948947444] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:46:23,969 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:46:23,969 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:46:23,969 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [947681874] [2023-11-19 07:46:23,969 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:46:23,970 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:46:23,970 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:46:23,970 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 07:46:23,970 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 07:46:23,970 INFO L87 Difference]: Start difference. First operand 3183 states and 4500 transitions. cyclomatic complexity: 1319 Second operand has 5 states, 5 states have (on average 13.4) internal successors, (67), 5 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:24,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:46:24,128 INFO L93 Difference]: Finished difference Result 4479 states and 6259 transitions. [2023-11-19 07:46:24,128 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4479 states and 6259 transitions. [2023-11-19 07:46:24,151 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4422 [2023-11-19 07:46:24,179 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4479 states to 4479 states and 6259 transitions. [2023-11-19 07:46:24,179 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4479 [2023-11-19 07:46:24,183 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4479 [2023-11-19 07:46:24,183 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4479 states and 6259 transitions. [2023-11-19 07:46:24,188 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:46:24,188 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4479 states and 6259 transitions. [2023-11-19 07:46:24,193 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4479 states and 6259 transitions. [2023-11-19 07:46:24,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4479 to 2806. [2023-11-19 07:46:24,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2806 states, 2806 states have (on average 1.3927298645759087) internal successors, (3908), 2805 states have internal predecessors, (3908), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:24,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2806 states to 2806 states and 3908 transitions. [2023-11-19 07:46:24,257 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2806 states and 3908 transitions. [2023-11-19 07:46:24,257 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-19 07:46:24,258 INFO L428 stractBuchiCegarLoop]: Abstraction has 2806 states and 3908 transitions. [2023-11-19 07:46:24,258 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-19 07:46:24,258 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2806 states and 3908 transitions. [2023-11-19 07:46:24,284 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2749 [2023-11-19 07:46:24,284 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:46:24,284 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:46:24,285 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:24,285 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:24,285 INFO L748 eck$LassoCheckResult]: Stem: 34638#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 34639#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 34650#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34648#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34649#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 34544#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34375#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34376#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34566#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34383#L441 assume !(0 == ~M_E~0); 34384#L441-2 assume !(0 == ~T1_E~0); 34540#L446-1 assume !(0 == ~T2_E~0); 34497#L451-1 assume !(0 == ~T3_E~0); 34498#L456-1 assume !(0 == ~E_M~0); 34658#L461-1 assume !(0 == ~E_1~0); 34659#L466-1 assume !(0 == ~E_2~0); 34679#L471-1 assume !(0 == ~E_3~0); 34420#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34421#L220 assume !(1 == ~m_pc~0); 34454#L220-2 is_master_triggered_~__retres1~0#1 := 0; 34455#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34518#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 34452#L543 assume !(0 != activate_threads_~tmp~1#1); 34453#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34635#L239 assume !(1 == ~t1_pc~0); 34632#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34633#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34416#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 34417#L551 assume !(0 != activate_threads_~tmp___0~0#1); 34640#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34641#L258 assume !(1 == ~t2_pc~0); 34642#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34484#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34485#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 34655#L559 assume !(0 != activate_threads_~tmp___1~0#1); 34553#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34554#L277 assume !(1 == ~t3_pc~0); 34608#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34395#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34353#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 34354#L567 assume !(0 != activate_threads_~tmp___2~0#1); 34446#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34494#L489 assume !(1 == ~M_E~0); 34657#L489-2 assume !(1 == ~T1_E~0); 34583#L494-1 assume !(1 == ~T2_E~0); 34435#L499-1 assume !(1 == ~T3_E~0); 34436#L504-1 assume !(1 == ~E_M~0); 34545#L509-1 assume !(1 == ~E_1~0); 34424#L514-1 assume !(1 == ~E_2~0); 34425#L519-1 assume !(1 == ~E_3~0); 34429#L524-1 assume { :end_inline_reset_delta_events } true; 34430#L690-2 assume !false; 34889#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34881#L416-1 [2023-11-19 07:46:24,285 INFO L750 eck$LassoCheckResult]: Loop: 34881#L416-1 assume !false; 34874#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 34867#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 34861#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 34856#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 34851#L369 assume 0 != eval_~tmp~0#1; 34842#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 34835#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 34830#L377-2 havoc eval_~tmp_ndt_1~0#1; 34822#L374-1 assume !(0 == ~t1_st~0); 34816#L388-1 assume !(0 == ~t2_st~0); 34817#L402-1 assume !(0 == ~t3_st~0); 34881#L416-1 [2023-11-19 07:46:24,286 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:24,286 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 1 times [2023-11-19 07:46:24,286 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:24,286 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [834977574] [2023-11-19 07:46:24,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:24,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:24,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:24,296 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:46:24,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:24,319 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:46:24,320 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:24,321 INFO L85 PathProgramCache]: Analyzing trace with hash -583220711, now seen corresponding path program 1 times [2023-11-19 07:46:24,321 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:24,321 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [161053003] [2023-11-19 07:46:24,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:24,321 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:24,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:24,326 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:46:24,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:24,330 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:46:24,331 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:24,331 INFO L85 PathProgramCache]: Analyzing trace with hash 979003743, now seen corresponding path program 1 times [2023-11-19 07:46:24,331 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:24,331 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [156754401] [2023-11-19 07:46:24,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:24,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:24,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:46:24,370 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:46:24,370 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:46:24,370 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [156754401] [2023-11-19 07:46:24,371 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [156754401] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:46:24,371 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:46:24,371 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:46:24,371 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [564606284] [2023-11-19 07:46:24,371 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:46:24,448 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:46:24,448 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:46:24,448 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:46:24,448 INFO L87 Difference]: Start difference. First operand 2806 states and 3908 transitions. cyclomatic complexity: 1105 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:24,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:46:24,511 INFO L93 Difference]: Finished difference Result 5036 states and 6937 transitions. [2023-11-19 07:46:24,511 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5036 states and 6937 transitions. [2023-11-19 07:46:24,538 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4928 [2023-11-19 07:46:24,566 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5036 states to 5036 states and 6937 transitions. [2023-11-19 07:46:24,567 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5036 [2023-11-19 07:46:24,572 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5036 [2023-11-19 07:46:24,572 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5036 states and 6937 transitions. [2023-11-19 07:46:24,578 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:46:24,578 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5036 states and 6937 transitions. [2023-11-19 07:46:24,585 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5036 states and 6937 transitions. [2023-11-19 07:46:24,660 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5036 to 4791. [2023-11-19 07:46:24,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4791 states, 4791 states have (on average 1.3821749112920059) internal successors, (6622), 4790 states have internal predecessors, (6622), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:24,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4791 states to 4791 states and 6622 transitions. [2023-11-19 07:46:24,684 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4791 states and 6622 transitions. [2023-11-19 07:46:24,684 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:46:24,684 INFO L428 stractBuchiCegarLoop]: Abstraction has 4791 states and 6622 transitions. [2023-11-19 07:46:24,685 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-19 07:46:24,685 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4791 states and 6622 transitions. [2023-11-19 07:46:24,705 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4683 [2023-11-19 07:46:24,705 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:46:24,708 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:46:24,708 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:24,709 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:24,709 INFO L748 eck$LassoCheckResult]: Stem: 42512#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 42513#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 42526#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42523#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42524#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 42398#L304-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 42399#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42542#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42543#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42234#L441 assume !(0 == ~M_E~0); 42235#L441-2 assume !(0 == ~T1_E~0); 42556#L446-1 assume !(0 == ~T2_E~0); 42557#L451-1 assume !(0 == ~T3_E~0); 42574#L456-1 assume !(0 == ~E_M~0); 42575#L461-1 assume !(0 == ~E_1~0); 42552#L466-1 assume !(0 == ~E_2~0); 42553#L471-1 assume !(0 == ~E_3~0); 42271#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42272#L220 assume !(1 == ~m_pc~0); 42306#L220-2 is_master_triggered_~__retres1~0#1 := 0; 42307#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42489#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 42490#L543 assume !(0 != activate_threads_~tmp~1#1); 42608#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42609#L239 assume !(1 == ~t1_pc~0); 42506#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42507#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42267#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 42268#L551 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42515#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42516#L258 assume !(1 == ~t2_pc~0); 42517#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 42335#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42336#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 42528#L559 assume !(0 != activate_threads_~tmp___1~0#1); 42529#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42469#L277 assume !(1 == ~t3_pc~0); 42470#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 42245#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42246#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 42297#L567 assume !(0 != activate_threads_~tmp___2~0#1); 42298#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42596#L489 assume !(1 == ~M_E~0); 42597#L489-2 assume !(1 == ~T1_E~0); 42441#L494-1 assume !(1 == ~T2_E~0); 42442#L499-1 assume !(1 == ~T3_E~0); 42400#L504-1 assume !(1 == ~E_M~0); 42401#L509-1 assume !(1 == ~E_1~0); 42273#L514-1 assume !(1 == ~E_2~0); 42274#L519-1 assume !(1 == ~E_3~0); 42280#L524-1 assume { :end_inline_reset_delta_events } true; 42281#L690-2 assume !false; 44011#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44007#L416-1 [2023-11-19 07:46:24,709 INFO L750 eck$LassoCheckResult]: Loop: 44007#L416-1 assume !false; 44005#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 44002#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 44001#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 43999#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 43997#L369 assume 0 != eval_~tmp~0#1; 43993#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 43990#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 43988#L377-2 havoc eval_~tmp_ndt_1~0#1; 43985#L374-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 43549#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 43980#L391-2 havoc eval_~tmp_ndt_2~0#1; 43978#L388-1 assume !(0 == ~t2_st~0); 43979#L402-1 assume !(0 == ~t3_st~0); 44007#L416-1 [2023-11-19 07:46:24,712 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:24,712 INFO L85 PathProgramCache]: Analyzing trace with hash -934376957, now seen corresponding path program 1 times [2023-11-19 07:46:24,713 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:24,713 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [509664293] [2023-11-19 07:46:24,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:24,713 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:24,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:46:24,753 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:46:24,753 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:46:24,753 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [509664293] [2023-11-19 07:46:24,753 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [509664293] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:46:24,753 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:46:24,753 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:46:24,754 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [162511692] [2023-11-19 07:46:24,754 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:46:24,754 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:46:24,754 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:24,754 INFO L85 PathProgramCache]: Analyzing trace with hash 2039297175, now seen corresponding path program 1 times [2023-11-19 07:46:24,755 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:24,755 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [749497526] [2023-11-19 07:46:24,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:24,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:24,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:24,759 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:46:24,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:24,763 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:46:24,825 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:46:24,825 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:46:24,825 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:46:24,826 INFO L87 Difference]: Start difference. First operand 4791 states and 6622 transitions. cyclomatic complexity: 1834 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:24,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:46:24,854 INFO L93 Difference]: Finished difference Result 4742 states and 6553 transitions. [2023-11-19 07:46:24,854 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4742 states and 6553 transitions. [2023-11-19 07:46:24,878 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4683 [2023-11-19 07:46:24,895 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4742 states to 4742 states and 6553 transitions. [2023-11-19 07:46:24,896 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4742 [2023-11-19 07:46:24,900 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4742 [2023-11-19 07:46:24,900 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4742 states and 6553 transitions. [2023-11-19 07:46:24,966 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:46:24,966 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4742 states and 6553 transitions. [2023-11-19 07:46:24,971 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4742 states and 6553 transitions. [2023-11-19 07:46:25,045 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4742 to 4742. [2023-11-19 07:46:25,055 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4742 states, 4742 states have (on average 1.381906368620835) internal successors, (6553), 4741 states have internal predecessors, (6553), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:25,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4742 states to 4742 states and 6553 transitions. [2023-11-19 07:46:25,068 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4742 states and 6553 transitions. [2023-11-19 07:46:25,069 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:46:25,070 INFO L428 stractBuchiCegarLoop]: Abstraction has 4742 states and 6553 transitions. [2023-11-19 07:46:25,070 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-19 07:46:25,070 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4742 states and 6553 transitions. [2023-11-19 07:46:25,090 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4683 [2023-11-19 07:46:25,090 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:46:25,090 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:46:25,091 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:25,091 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:25,091 INFO L748 eck$LassoCheckResult]: Stem: 52021#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 52022#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 52035#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 52032#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 52033#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 51934#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51765#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 51766#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 51956#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 51773#L441 assume !(0 == ~M_E~0); 51774#L441-2 assume !(0 == ~T1_E~0); 51930#L446-1 assume !(0 == ~T2_E~0); 51889#L451-1 assume !(0 == ~T3_E~0); 51890#L456-1 assume !(0 == ~E_M~0); 52040#L461-1 assume !(0 == ~E_1~0); 52041#L466-1 assume !(0 == ~E_2~0); 52054#L471-1 assume !(0 == ~E_3~0); 51809#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51810#L220 assume !(1 == ~m_pc~0); 51843#L220-2 is_master_triggered_~__retres1~0#1 := 0; 51844#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51907#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 51841#L543 assume !(0 != activate_threads_~tmp~1#1); 51842#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52020#L239 assume !(1 == ~t1_pc~0); 52018#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 52019#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51805#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 51806#L551 assume !(0 != activate_threads_~tmp___0~0#1); 52023#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52024#L258 assume !(1 == ~t2_pc~0); 52025#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 51874#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51875#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 52037#L559 assume !(0 != activate_threads_~tmp___1~0#1); 51943#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51944#L277 assume !(1 == ~t3_pc~0); 51994#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 51784#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51742#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 51743#L567 assume !(0 != activate_threads_~tmp___2~0#1); 51835#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51884#L489 assume !(1 == ~M_E~0); 52038#L489-2 assume !(1 == ~T1_E~0); 51971#L494-1 assume !(1 == ~T2_E~0); 51826#L499-1 assume !(1 == ~T3_E~0); 51827#L504-1 assume !(1 == ~E_M~0); 51935#L509-1 assume !(1 == ~E_1~0); 51813#L514-1 assume !(1 == ~E_2~0); 51814#L519-1 assume !(1 == ~E_3~0); 51818#L524-1 assume { :end_inline_reset_delta_events } true; 51819#L690-2 assume !false; 53147#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53142#L416-1 [2023-11-19 07:46:25,091 INFO L750 eck$LassoCheckResult]: Loop: 53142#L416-1 assume !false; 53140#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 53138#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 53136#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 53134#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 53132#L369 assume 0 != eval_~tmp~0#1; 53129#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 53125#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 53126#L377-2 havoc eval_~tmp_ndt_1~0#1; 53523#L374-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 53520#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 53519#L391-2 havoc eval_~tmp_ndt_2~0#1; 53515#L388-1 assume !(0 == ~t2_st~0); 53145#L402-1 assume !(0 == ~t3_st~0); 53142#L416-1 [2023-11-19 07:46:25,092 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:25,092 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 2 times [2023-11-19 07:46:25,092 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:25,092 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1928373004] [2023-11-19 07:46:25,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:25,093 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:25,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:25,112 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:46:25,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:25,131 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:46:25,132 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:25,132 INFO L85 PathProgramCache]: Analyzing trace with hash 2039297175, now seen corresponding path program 2 times [2023-11-19 07:46:25,132 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:25,132 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [662018170] [2023-11-19 07:46:25,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:25,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:25,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:25,136 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:46:25,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:25,140 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:46:25,141 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:25,142 INFO L85 PathProgramCache]: Analyzing trace with hash 98443869, now seen corresponding path program 1 times [2023-11-19 07:46:25,142 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:25,142 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1244419925] [2023-11-19 07:46:25,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:25,142 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:25,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:46:25,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:46:25,197 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:46:25,197 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1244419925] [2023-11-19 07:46:25,197 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1244419925] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:46:25,197 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:46:25,198 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:46:25,198 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [833186862] [2023-11-19 07:46:25,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:46:25,263 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:46:25,264 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:46:25,264 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:46:25,264 INFO L87 Difference]: Start difference. First operand 4742 states and 6553 transitions. cyclomatic complexity: 1814 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:25,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:46:25,346 INFO L93 Difference]: Finished difference Result 8573 states and 11766 transitions. [2023-11-19 07:46:25,346 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8573 states and 11766 transitions. [2023-11-19 07:46:25,393 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 8510 [2023-11-19 07:46:25,424 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8573 states to 8573 states and 11766 transitions. [2023-11-19 07:46:25,424 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8573 [2023-11-19 07:46:25,432 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8573 [2023-11-19 07:46:25,433 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8573 states and 11766 transitions. [2023-11-19 07:46:25,440 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:46:25,440 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8573 states and 11766 transitions. [2023-11-19 07:46:25,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8573 states and 11766 transitions. [2023-11-19 07:46:25,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8573 to 8419. [2023-11-19 07:46:25,662 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8419 states, 8419 states have (on average 1.374272478916736) internal successors, (11570), 8418 states have internal predecessors, (11570), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:25,686 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8419 states to 8419 states and 11570 transitions. [2023-11-19 07:46:25,687 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8419 states and 11570 transitions. [2023-11-19 07:46:25,687 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:46:25,688 INFO L428 stractBuchiCegarLoop]: Abstraction has 8419 states and 11570 transitions. [2023-11-19 07:46:25,688 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-19 07:46:25,688 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8419 states and 11570 transitions. [2023-11-19 07:46:25,722 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 8356 [2023-11-19 07:46:25,722 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:46:25,722 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:46:25,723 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:25,723 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:25,724 INFO L748 eck$LassoCheckResult]: Stem: 65354#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 65355#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 65366#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 65364#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 65365#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 65254#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 65085#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 65086#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 65276#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 65096#L441 assume !(0 == ~M_E~0); 65097#L441-2 assume !(0 == ~T1_E~0); 65250#L446-1 assume !(0 == ~T2_E~0); 65208#L451-1 assume !(0 == ~T3_E~0); 65209#L456-1 assume !(0 == ~E_M~0); 65373#L461-1 assume !(0 == ~E_1~0); 65374#L466-1 assume !(0 == ~E_2~0); 65391#L471-1 assume !(0 == ~E_3~0); 65130#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65131#L220 assume !(1 == ~m_pc~0); 65166#L220-2 is_master_triggered_~__retres1~0#1 := 0; 65167#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65226#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 65162#L543 assume !(0 != activate_threads_~tmp~1#1); 65163#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65351#L239 assume !(1 == ~t1_pc~0); 65349#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 65350#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65128#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 65129#L551 assume !(0 != activate_threads_~tmp___0~0#1); 65356#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65357#L258 assume !(1 == ~t2_pc~0); 65358#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 65197#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65198#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 65371#L559 assume !(0 != activate_threads_~tmp___1~0#1); 65262#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65263#L277 assume !(1 == ~t3_pc~0); 65321#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 65107#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65063#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 65064#L567 assume !(0 != activate_threads_~tmp___2~0#1); 65157#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65205#L489 assume !(1 == ~M_E~0); 65372#L489-2 assume !(1 == ~T1_E~0); 65293#L494-1 assume !(1 == ~T2_E~0); 65146#L499-1 assume !(1 == ~T3_E~0); 65147#L504-1 assume !(1 == ~E_M~0); 65255#L509-1 assume !(1 == ~E_1~0); 65134#L514-1 assume !(1 == ~E_2~0); 65135#L519-1 assume !(1 == ~E_3~0); 65140#L524-1 assume { :end_inline_reset_delta_events } true; 65141#L690-2 assume !false; 67688#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 67684#L416-1 [2023-11-19 07:46:25,724 INFO L750 eck$LassoCheckResult]: Loop: 67684#L416-1 assume !false; 67683#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 67680#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 67681#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 67819#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 67673#L369 assume 0 != eval_~tmp~0#1; 67674#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 67801#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 67797#L377-2 havoc eval_~tmp_ndt_1~0#1; 67696#L374-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 67694#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 67693#L391-2 havoc eval_~tmp_ndt_2~0#1; 67692#L388-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 67177#L405 assume !(0 != eval_~tmp_ndt_3~0#1); 67691#L405-2 havoc eval_~tmp_ndt_3~0#1; 67686#L402-1 assume !(0 == ~t3_st~0); 67684#L416-1 [2023-11-19 07:46:25,725 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:25,725 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 3 times [2023-11-19 07:46:25,725 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:25,725 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [748517735] [2023-11-19 07:46:25,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:25,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:25,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:25,737 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:46:25,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:25,751 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:46:25,752 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:25,752 INFO L85 PathProgramCache]: Analyzing trace with hash 1255454681, now seen corresponding path program 1 times [2023-11-19 07:46:25,752 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:25,752 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [375657204] [2023-11-19 07:46:25,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:25,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:25,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:25,757 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:46:25,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:25,761 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:46:25,762 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:25,762 INFO L85 PathProgramCache]: Analyzing trace with hash 111234079, now seen corresponding path program 1 times [2023-11-19 07:46:25,763 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:25,763 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1294005964] [2023-11-19 07:46:25,763 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:25,763 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:25,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:46:25,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:46:25,801 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:46:25,801 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1294005964] [2023-11-19 07:46:25,802 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1294005964] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:46:25,802 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:46:25,802 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:46:25,802 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [897281199] [2023-11-19 07:46:25,802 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:46:25,879 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:46:25,880 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:46:25,880 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:46:25,881 INFO L87 Difference]: Start difference. First operand 8419 states and 11570 transitions. cyclomatic complexity: 3154 Second operand has 3 states, 2 states have (on average 34.5) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:26,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:46:26,092 INFO L93 Difference]: Finished difference Result 14179 states and 19370 transitions. [2023-11-19 07:46:26,092 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14179 states and 19370 transitions. [2023-11-19 07:46:26,196 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 14108 [2023-11-19 07:46:26,273 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14179 states to 14179 states and 19370 transitions. [2023-11-19 07:46:26,273 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14179 [2023-11-19 07:46:26,291 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14179 [2023-11-19 07:46:26,291 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14179 states and 19370 transitions. [2023-11-19 07:46:26,306 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:46:26,306 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14179 states and 19370 transitions. [2023-11-19 07:46:26,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14179 states and 19370 transitions. [2023-11-19 07:46:26,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14179 to 13955. [2023-11-19 07:46:26,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13955 states, 13955 states have (on average 1.371981368685059) internal successors, (19146), 13954 states have internal predecessors, (19146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:46:26,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13955 states to 13955 states and 19146 transitions. [2023-11-19 07:46:26,664 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13955 states and 19146 transitions. [2023-11-19 07:46:26,665 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:46:26,666 INFO L428 stractBuchiCegarLoop]: Abstraction has 13955 states and 19146 transitions. [2023-11-19 07:46:26,666 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-19 07:46:26,666 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13955 states and 19146 transitions. [2023-11-19 07:46:26,724 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 13884 [2023-11-19 07:46:26,724 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:46:26,724 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:46:26,725 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:26,725 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:46:26,726 INFO L748 eck$LassoCheckResult]: Stem: 87955#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 87956#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 87968#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 87966#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 87967#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 87857#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 87691#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 87692#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 87880#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 87702#L441 assume !(0 == ~M_E~0); 87703#L441-2 assume !(0 == ~T1_E~0); 87853#L446-1 assume !(0 == ~T2_E~0); 87815#L451-1 assume !(0 == ~T3_E~0); 87816#L456-1 assume !(0 == ~E_M~0); 87973#L461-1 assume !(0 == ~E_1~0); 87974#L466-1 assume !(0 == ~E_2~0); 87993#L471-1 assume !(0 == ~E_3~0); 87735#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87736#L220 assume !(1 == ~m_pc~0); 87772#L220-2 is_master_triggered_~__retres1~0#1 := 0; 87773#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87830#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 87768#L543 assume !(0 != activate_threads_~tmp~1#1); 87769#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 87951#L239 assume !(1 == ~t1_pc~0); 87949#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 87950#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 87733#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 87734#L551 assume !(0 != activate_threads_~tmp___0~0#1); 87957#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 87958#L258 assume !(1 == ~t2_pc~0); 87959#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 87801#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87802#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 87971#L559 assume !(0 != activate_threads_~tmp___1~0#1); 87865#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 87866#L277 assume !(1 == ~t3_pc~0); 87920#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 87713#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 87669#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 87670#L567 assume !(0 != activate_threads_~tmp___2~0#1); 87763#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 87812#L489 assume !(1 == ~M_E~0); 87972#L489-2 assume !(1 == ~T1_E~0); 87894#L494-1 assume !(1 == ~T2_E~0); 87752#L499-1 assume !(1 == ~T3_E~0); 87753#L504-1 assume !(1 == ~E_M~0); 87858#L509-1 assume !(1 == ~E_1~0); 87739#L514-1 assume !(1 == ~E_2~0); 87740#L519-1 assume !(1 == ~E_3~0); 87746#L524-1 assume { :end_inline_reset_delta_events } true; 87747#L690-2 assume !false; 91827#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 91825#L416-1 [2023-11-19 07:46:26,727 INFO L750 eck$LassoCheckResult]: Loop: 91825#L416-1 assume !false; 91824#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 91821#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 91819#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 91817#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 91816#L369 assume 0 != eval_~tmp~0#1; 91813#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 91809#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 91807#L377-2 havoc eval_~tmp_ndt_1~0#1; 91805#L374-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 91773#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 91803#L391-2 havoc eval_~tmp_ndt_2~0#1; 91550#L388-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 91547#L405 assume !(0 != eval_~tmp_ndt_3~0#1); 91548#L405-2 havoc eval_~tmp_ndt_3~0#1; 91650#L402-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 90948#L419 assume !(0 != eval_~tmp_ndt_4~0#1); 91646#L419-2 havoc eval_~tmp_ndt_4~0#1; 91825#L416-1 [2023-11-19 07:46:26,727 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:26,728 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 4 times [2023-11-19 07:46:26,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:26,728 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [563069892] [2023-11-19 07:46:26,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:26,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:26,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:26,747 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:46:26,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:26,763 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:46:26,764 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:26,764 INFO L85 PathProgramCache]: Analyzing trace with hash -393961001, now seen corresponding path program 1 times [2023-11-19 07:46:26,764 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:26,764 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1825914731] [2023-11-19 07:46:26,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:26,764 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:26,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:26,771 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:46:26,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:26,780 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:46:26,780 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:46:26,781 INFO L85 PathProgramCache]: Analyzing trace with hash -478331747, now seen corresponding path program 1 times [2023-11-19 07:46:26,781 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:46:26,781 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1312178563] [2023-11-19 07:46:26,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:46:26,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:46:26,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:26,802 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:46:26,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:26,824 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:46:28,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:28,368 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:46:28,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:46:28,558 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 19.11 07:46:28 BoogieIcfgContainer [2023-11-19 07:46:28,558 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-19 07:46:28,559 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-19 07:46:28,559 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-19 07:46:28,559 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-19 07:46:28,560 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:46:19" (3/4) ... [2023-11-19 07:46:28,562 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-19 07:46:28,672 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6c9540ec-3801-4729-bad6-c9d6c2d08c90/bin/uautomizer-verify-uCwYo4JHxu/witness.graphml [2023-11-19 07:46:28,672 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-19 07:46:28,673 INFO L158 Benchmark]: Toolchain (without parser) took 10630.02ms. Allocated memory was 130.0MB in the beginning and 599.8MB in the end (delta: 469.8MB). Free memory was 85.3MB in the beginning and 442.2MB in the end (delta: -356.8MB). Peak memory consumption was 179.3MB. Max. memory is 16.1GB. [2023-11-19 07:46:28,673 INFO L158 Benchmark]: CDTParser took 0.95ms. Allocated memory is still 130.0MB. Free memory is still 101.9MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-19 07:46:28,673 INFO L158 Benchmark]: CACSL2BoogieTranslator took 357.29ms. Allocated memory is still 130.0MB. Free memory was 85.3MB in the beginning and 70.5MB in the end (delta: 14.8MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2023-11-19 07:46:28,674 INFO L158 Benchmark]: Boogie Procedure Inliner took 72.98ms. Allocated memory is still 130.0MB. Free memory was 70.5MB in the beginning and 67.0MB in the end (delta: 3.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-19 07:46:28,674 INFO L158 Benchmark]: Boogie Preprocessor took 86.83ms. Allocated memory is still 130.0MB. Free memory was 67.0MB in the beginning and 63.8MB in the end (delta: 3.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-19 07:46:28,675 INFO L158 Benchmark]: RCFGBuilder took 1298.97ms. Allocated memory is still 130.0MB. Free memory was 63.3MB in the beginning and 78.9MB in the end (delta: -15.6MB). Peak memory consumption was 29.9MB. Max. memory is 16.1GB. [2023-11-19 07:46:28,675 INFO L158 Benchmark]: BuchiAutomizer took 8694.48ms. Allocated memory was 130.0MB in the beginning and 299.9MB in the end (delta: 169.9MB). Free memory was 78.9MB in the beginning and 80.0MB in the end (delta: -1.1MB). Peak memory consumption was 168.2MB. Max. memory is 16.1GB. [2023-11-19 07:46:28,676 INFO L158 Benchmark]: Witness Printer took 113.16ms. Allocated memory was 299.9MB in the beginning and 599.8MB in the end (delta: 299.9MB). Free memory was 80.0MB in the beginning and 442.2MB in the end (delta: -362.2MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-19 07:46:28,679 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.95ms. Allocated memory is still 130.0MB. Free memory is still 101.9MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 357.29ms. Allocated memory is still 130.0MB. Free memory was 85.3MB in the beginning and 70.5MB in the end (delta: 14.8MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 72.98ms. Allocated memory is still 130.0MB. Free memory was 70.5MB in the beginning and 67.0MB in the end (delta: 3.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 86.83ms. Allocated memory is still 130.0MB. Free memory was 67.0MB in the beginning and 63.8MB in the end (delta: 3.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1298.97ms. Allocated memory is still 130.0MB. Free memory was 63.3MB in the beginning and 78.9MB in the end (delta: -15.6MB). Peak memory consumption was 29.9MB. Max. memory is 16.1GB. * BuchiAutomizer took 8694.48ms. Allocated memory was 130.0MB in the beginning and 299.9MB in the end (delta: 169.9MB). Free memory was 78.9MB in the beginning and 80.0MB in the end (delta: -1.1MB). Peak memory consumption was 168.2MB. Max. memory is 16.1GB. * Witness Printer took 113.16ms. Allocated memory was 299.9MB in the beginning and 599.8MB in the end (delta: 299.9MB). Free memory was 80.0MB in the beginning and 442.2MB in the end (delta: -362.2MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 15 terminating modules (15 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.15 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 13955 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 8.4s and 16 iterations. TraceHistogramMax:1. Analysis of lassos took 4.3s. Construction of modules took 0.5s. Büchi inclusion checks took 3.1s. Highest rank in rank-based complementation 0. Minimization of det autom 15. Minimization of nondet autom 0. Automata minimization 1.3s AutomataMinimizationTime, 15 MinimizatonAttempts, 5816 StatesRemovedByMinimization, 10 NontrivialMinimizations. Non-live state removal took 0.7s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 8516 SdHoareTripleChecker+Valid, 0.6s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 8516 mSDsluCounter, 14720 SdHoareTripleChecker+Invalid, 0.5s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 6913 mSDsCounter, 150 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 377 IncrementalHoareTripleChecker+Invalid, 527 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 150 mSolverCounterUnsat, 7807 mSDtfsCounter, 377 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc3 concLT0 SILN1 SILU0 SILI8 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 364]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int t3_st ; [L32] int m_i ; [L33] int t1_i ; [L34] int t2_i ; [L35] int t3_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L49] int token ; [L51] int local ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, token=0] [L735] int __retres1 ; [L739] CALL init_model() [L648] m_i = 1 [L649] t1_i = 1 [L650] t2_i = 1 [L651] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L739] RET init_model() [L740] CALL start_simulation() [L676] int kernel_st ; [L677] int tmp ; [L678] int tmp___0 ; [L682] kernel_st = 0 [L683] FCALL update_channels() [L684] CALL init_threads() [L304] COND TRUE m_i == 1 [L305] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L309] COND TRUE t1_i == 1 [L310] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L314] COND TRUE t2_i == 1 [L315] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L319] COND TRUE t3_i == 1 [L320] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L684] RET init_threads() [L685] CALL fire_delta_events() [L441] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L446] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L451] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L456] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L461] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L466] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L471] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L476] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L685] RET fire_delta_events() [L686] CALL activate_threads() [L534] int tmp ; [L535] int tmp___0 ; [L536] int tmp___1 ; [L537] int tmp___2 ; [L541] CALL, EXPR is_master_triggered() [L217] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L220] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L230] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L232] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L541] RET, EXPR is_master_triggered() [L541] tmp = is_master_triggered() [L543] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, token=0] [L549] CALL, EXPR is_transmit1_triggered() [L236] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L239] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L249] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L251] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L549] RET, EXPR is_transmit1_triggered() [L549] tmp___0 = is_transmit1_triggered() [L551] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, token=0] [L557] CALL, EXPR is_transmit2_triggered() [L255] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L258] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L268] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L270] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L557] RET, EXPR is_transmit2_triggered() [L557] tmp___1 = is_transmit2_triggered() [L559] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L565] CALL, EXPR is_transmit3_triggered() [L274] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L277] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L287] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L289] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L565] RET, EXPR is_transmit3_triggered() [L565] tmp___2 = is_transmit3_triggered() [L567] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L686] RET activate_threads() [L687] CALL reset_delta_events() [L489] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L494] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L499] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L504] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L509] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L514] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L519] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L524] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L687] RET reset_delta_events() [L690] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, kernel_st=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L693] kernel_st = 1 [L694] CALL eval() [L360] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] Loop: [L364] COND TRUE 1 [L367] CALL, EXPR exists_runnable_thread() [L329] int __retres1 ; [L332] COND TRUE m_st == 0 [L333] __retres1 = 1 [L355] return (__retres1); [L367] RET, EXPR exists_runnable_thread() [L367] tmp = exists_runnable_thread() [L369] COND TRUE \read(tmp) [L374] COND TRUE m_st == 0 [L375] int tmp_ndt_1; [L376] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L377] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L374-L385] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L388] COND TRUE t1_st == 0 [L389] int tmp_ndt_2; [L390] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L391] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L388-L399] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L402] COND TRUE t2_st == 0 [L403] int tmp_ndt_3; [L404] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L405] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L402-L413] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L416] COND TRUE t3_st == 0 [L417] int tmp_ndt_4; [L418] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L419] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L416-L427] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 364]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int t3_st ; [L32] int m_i ; [L33] int t1_i ; [L34] int t2_i ; [L35] int t3_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L49] int token ; [L51] int local ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, token=0] [L735] int __retres1 ; [L739] CALL init_model() [L648] m_i = 1 [L649] t1_i = 1 [L650] t2_i = 1 [L651] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L739] RET init_model() [L740] CALL start_simulation() [L676] int kernel_st ; [L677] int tmp ; [L678] int tmp___0 ; [L682] kernel_st = 0 [L683] FCALL update_channels() [L684] CALL init_threads() [L304] COND TRUE m_i == 1 [L305] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L309] COND TRUE t1_i == 1 [L310] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L314] COND TRUE t2_i == 1 [L315] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L319] COND TRUE t3_i == 1 [L320] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L684] RET init_threads() [L685] CALL fire_delta_events() [L441] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L446] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L451] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L456] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L461] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L466] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L471] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L476] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L685] RET fire_delta_events() [L686] CALL activate_threads() [L534] int tmp ; [L535] int tmp___0 ; [L536] int tmp___1 ; [L537] int tmp___2 ; [L541] CALL, EXPR is_master_triggered() [L217] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L220] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L230] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L232] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L541] RET, EXPR is_master_triggered() [L541] tmp = is_master_triggered() [L543] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, token=0] [L549] CALL, EXPR is_transmit1_triggered() [L236] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L239] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L249] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L251] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L549] RET, EXPR is_transmit1_triggered() [L549] tmp___0 = is_transmit1_triggered() [L551] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, token=0] [L557] CALL, EXPR is_transmit2_triggered() [L255] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L258] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L268] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L270] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L557] RET, EXPR is_transmit2_triggered() [L557] tmp___1 = is_transmit2_triggered() [L559] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L565] CALL, EXPR is_transmit3_triggered() [L274] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L277] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L287] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L289] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L565] RET, EXPR is_transmit3_triggered() [L565] tmp___2 = is_transmit3_triggered() [L567] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L686] RET activate_threads() [L687] CALL reset_delta_events() [L489] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L494] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L499] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L504] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L509] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L514] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L519] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L524] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L687] RET reset_delta_events() [L690] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, kernel_st=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L693] kernel_st = 1 [L694] CALL eval() [L360] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] Loop: [L364] COND TRUE 1 [L367] CALL, EXPR exists_runnable_thread() [L329] int __retres1 ; [L332] COND TRUE m_st == 0 [L333] __retres1 = 1 [L355] return (__retres1); [L367] RET, EXPR exists_runnable_thread() [L367] tmp = exists_runnable_thread() [L369] COND TRUE \read(tmp) [L374] COND TRUE m_st == 0 [L375] int tmp_ndt_1; [L376] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L377] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L374-L385] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L388] COND TRUE t1_st == 0 [L389] int tmp_ndt_2; [L390] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L391] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L388-L399] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L402] COND TRUE t2_st == 0 [L403] int tmp_ndt_3; [L404] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L405] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L402-L413] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L416] COND TRUE t3_st == 0 [L417] int tmp_ndt_4; [L418] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L419] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L416-L427] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-19 07:46:28,817 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6c9540ec-3801-4729-bad6-c9d6c2d08c90/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)