./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.04.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 9bd2c7ff Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a7be7761-ee72-4f7f-80ea-03dd6347eac3/bin/uautomizer-verify-uCwYo4JHxu/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a7be7761-ee72-4f7f-80ea-03dd6347eac3/bin/uautomizer-verify-uCwYo4JHxu/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a7be7761-ee72-4f7f-80ea-03dd6347eac3/bin/uautomizer-verify-uCwYo4JHxu/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a7be7761-ee72-4f7f-80ea-03dd6347eac3/bin/uautomizer-verify-uCwYo4JHxu/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.04.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a7be7761-ee72-4f7f-80ea-03dd6347eac3/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a7be7761-ee72-4f7f-80ea-03dd6347eac3/bin/uautomizer-verify-uCwYo4JHxu --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d4710f8f3a918a0191222414f5c33a367ff98c09c2e8598fa3213223c4c35dba --- Real Ultimate output --- This is Ultimate 0.2.3-dev-9bd2c7f [2023-11-19 07:47:57,952 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-19 07:47:58,044 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a7be7761-ee72-4f7f-80ea-03dd6347eac3/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-19 07:47:58,050 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-19 07:47:58,051 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-19 07:47:58,082 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-19 07:47:58,083 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-19 07:47:58,084 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-19 07:47:58,085 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-19 07:47:58,086 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-19 07:47:58,086 INFO L153 SettingsManager]: * Use SBE=true [2023-11-19 07:47:58,087 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-19 07:47:58,088 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-19 07:47:58,088 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-19 07:47:58,089 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-19 07:47:58,089 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-19 07:47:58,090 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-19 07:47:58,091 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-19 07:47:58,091 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-19 07:47:58,092 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-19 07:47:58,093 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-19 07:47:58,098 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-19 07:47:58,098 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-19 07:47:58,099 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-19 07:47:58,109 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-19 07:47:58,110 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-19 07:47:58,110 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-19 07:47:58,111 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-19 07:47:58,111 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-19 07:47:58,112 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-19 07:47:58,113 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-19 07:47:58,114 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-19 07:47:58,114 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-19 07:47:58,115 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-19 07:47:58,115 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-19 07:47:58,116 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-19 07:47:58,116 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a7be7761-ee72-4f7f-80ea-03dd6347eac3/bin/uautomizer-verify-uCwYo4JHxu/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a7be7761-ee72-4f7f-80ea-03dd6347eac3/bin/uautomizer-verify-uCwYo4JHxu Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d4710f8f3a918a0191222414f5c33a367ff98c09c2e8598fa3213223c4c35dba [2023-11-19 07:47:58,445 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-19 07:47:58,480 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-19 07:47:58,483 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-19 07:47:58,484 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-19 07:47:58,485 INFO L274 PluginConnector]: CDTParser initialized [2023-11-19 07:47:58,486 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a7be7761-ee72-4f7f-80ea-03dd6347eac3/bin/uautomizer-verify-uCwYo4JHxu/../../sv-benchmarks/c/systemc/token_ring.04.cil-1.c [2023-11-19 07:48:01,528 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-19 07:48:01,823 INFO L384 CDTParser]: Found 1 translation units. [2023-11-19 07:48:01,824 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a7be7761-ee72-4f7f-80ea-03dd6347eac3/sv-benchmarks/c/systemc/token_ring.04.cil-1.c [2023-11-19 07:48:01,837 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a7be7761-ee72-4f7f-80ea-03dd6347eac3/bin/uautomizer-verify-uCwYo4JHxu/data/84a7fb6aa/6a16467fbae543c8b1cf0806b418ee05/FLAGeaa03d4ff [2023-11-19 07:48:01,859 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a7be7761-ee72-4f7f-80ea-03dd6347eac3/bin/uautomizer-verify-uCwYo4JHxu/data/84a7fb6aa/6a16467fbae543c8b1cf0806b418ee05 [2023-11-19 07:48:01,862 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-19 07:48:01,864 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-19 07:48:01,865 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-19 07:48:01,865 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-19 07:48:01,872 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-19 07:48:01,873 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:48:01" (1/1) ... [2023-11-19 07:48:01,874 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@74643919 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:01, skipping insertion in model container [2023-11-19 07:48:01,874 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:48:01" (1/1) ... [2023-11-19 07:48:01,919 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-19 07:48:02,171 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:48:02,190 INFO L202 MainTranslator]: Completed pre-run [2023-11-19 07:48:02,241 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:48:02,264 INFO L206 MainTranslator]: Completed translation [2023-11-19 07:48:02,265 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:02 WrapperNode [2023-11-19 07:48:02,265 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-19 07:48:02,266 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-19 07:48:02,267 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-19 07:48:02,267 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-19 07:48:02,275 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:02" (1/1) ... [2023-11-19 07:48:02,295 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:02" (1/1) ... [2023-11-19 07:48:02,356 INFO L138 Inliner]: procedures = 36, calls = 44, calls flagged for inlining = 39, calls inlined = 78, statements flattened = 1073 [2023-11-19 07:48:02,356 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-19 07:48:02,357 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-19 07:48:02,357 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-19 07:48:02,358 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-19 07:48:02,368 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:02" (1/1) ... [2023-11-19 07:48:02,369 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:02" (1/1) ... [2023-11-19 07:48:02,376 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:02" (1/1) ... [2023-11-19 07:48:02,377 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:02" (1/1) ... [2023-11-19 07:48:02,421 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:02" (1/1) ... [2023-11-19 07:48:02,449 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:02" (1/1) ... [2023-11-19 07:48:02,453 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:02" (1/1) ... [2023-11-19 07:48:02,458 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:02" (1/1) ... [2023-11-19 07:48:02,471 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-19 07:48:02,472 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-19 07:48:02,476 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-19 07:48:02,476 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-19 07:48:02,477 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:02" (1/1) ... [2023-11-19 07:48:02,489 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 07:48:02,505 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a7be7761-ee72-4f7f-80ea-03dd6347eac3/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:48:02,520 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a7be7761-ee72-4f7f-80ea-03dd6347eac3/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 07:48:02,553 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a7be7761-ee72-4f7f-80ea-03dd6347eac3/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-19 07:48:02,586 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-19 07:48:02,586 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-19 07:48:02,587 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-19 07:48:02,587 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-19 07:48:02,736 INFO L236 CfgBuilder]: Building ICFG [2023-11-19 07:48:02,742 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-19 07:48:03,917 INFO L277 CfgBuilder]: Performing block encoding [2023-11-19 07:48:03,940 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-19 07:48:03,940 INFO L302 CfgBuilder]: Removed 7 assume(true) statements. [2023-11-19 07:48:03,949 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:48:03 BoogieIcfgContainer [2023-11-19 07:48:03,949 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-19 07:48:03,950 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-19 07:48:03,950 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-19 07:48:03,955 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-19 07:48:03,956 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:48:03,956 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 07:48:01" (1/3) ... [2023-11-19 07:48:03,957 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3df040e2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:48:03, skipping insertion in model container [2023-11-19 07:48:03,957 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:48:03,957 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:02" (2/3) ... [2023-11-19 07:48:03,958 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3df040e2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:48:03, skipping insertion in model container [2023-11-19 07:48:03,958 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:48:03,958 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:48:03" (3/3) ... [2023-11-19 07:48:03,960 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.04.cil-1.c [2023-11-19 07:48:04,040 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-19 07:48:04,041 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-19 07:48:04,041 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-19 07:48:04,041 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-19 07:48:04,041 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-19 07:48:04,042 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-19 07:48:04,042 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-19 07:48:04,043 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-19 07:48:04,057 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 437 states, 436 states have (on average 1.525229357798165) internal successors, (665), 436 states have internal predecessors, (665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:04,136 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 366 [2023-11-19 07:48:04,137 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:04,137 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:04,155 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:04,155 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:04,156 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-19 07:48:04,157 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 437 states, 436 states have (on average 1.525229357798165) internal successors, (665), 436 states have internal predecessors, (665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:04,171 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 366 [2023-11-19 07:48:04,172 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:04,172 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:04,184 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:04,184 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:04,197 INFO L748 eck$LassoCheckResult]: Stem: 128#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 363#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 208#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 359#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 73#L353true assume !(1 == ~m_i~0);~m_st~0 := 2; 293#L353-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 370#L358-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 43#L363-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 415#L368-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 122#L373-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 57#L514true assume !(0 == ~M_E~0); 384#L514-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 322#L519-1true assume !(0 == ~T2_E~0); 36#L524-1true assume !(0 == ~T3_E~0); 105#L529-1true assume !(0 == ~T4_E~0); 325#L534-1true assume !(0 == ~E_M~0); 259#L539-1true assume !(0 == ~E_1~0); 291#L544-1true assume !(0 == ~E_2~0); 292#L549-1true assume !(0 == ~E_3~0); 330#L554-1true assume 0 == ~E_4~0;~E_4~0 := 1; 34#L559-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 174#L250true assume 1 == ~m_pc~0; 396#L251true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 323#L261true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 114#is_master_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 295#L637true assume !(0 != activate_threads_~tmp~1#1); 37#L637-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49#L269true assume !(1 == ~t1_pc~0); 102#L269-2true is_transmit1_triggered_~__retres1~1#1 := 0; 180#L280true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 324#L645true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 147#L645-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 232#L288true assume 1 == ~t2_pc~0; 355#L289true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 244#L299true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 212#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 254#L653true assume !(0 != activate_threads_~tmp___1~0#1); 306#L653-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 165#L307true assume !(1 == ~t3_pc~0); 223#L307-2true is_transmit3_triggered_~__retres1~3#1 := 0; 205#L318true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 301#L661true assume !(0 != activate_threads_~tmp___2~0#1); 127#L661-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 348#L326true assume 1 == ~t4_pc~0; 342#L327true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 163#L337true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 302#L669true assume !(0 != activate_threads_~tmp___3~0#1); 257#L669-2true havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 297#L572true assume !(1 == ~M_E~0); 343#L572-2true assume !(1 == ~T1_E~0); 41#L577-1true assume !(1 == ~T2_E~0); 239#L582-1true assume !(1 == ~T3_E~0); 247#L587-1true assume !(1 == ~T4_E~0); 375#L592-1true assume !(1 == ~E_M~0); 11#L597-1true assume 1 == ~E_1~0;~E_1~0 := 2; 417#L602-1true assume !(1 == ~E_2~0); 140#L607-1true assume !(1 == ~E_3~0); 421#L612-1true assume !(1 == ~E_4~0); 104#L617-1true assume { :end_inline_reset_delta_events } true; 436#L803-2true [2023-11-19 07:48:04,207 INFO L750 eck$LassoCheckResult]: Loop: 436#L803-2true assume !false; 218#L804true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 188#L489-1true assume !true; 63#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 307#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 194#L514-3true assume !(0 == ~M_E~0); 154#L514-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 313#L519-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 237#L524-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 86#L529-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 172#L534-3true assume 0 == ~E_M~0;~E_M~0 := 1; 6#L539-3true assume 0 == ~E_1~0;~E_1~0 := 1; 328#L544-3true assume 0 == ~E_2~0;~E_2~0 := 1; 401#L549-3true assume !(0 == ~E_3~0); 118#L554-3true assume 0 == ~E_4~0;~E_4~0 := 1; 191#L559-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 269#L250-18true assume !(1 == ~m_pc~0); 378#L250-20true is_master_triggered_~__retres1~0#1 := 0; 203#L261-6true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 137#is_master_triggered_returnLabel#7true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 267#L637-18true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 91#L637-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26#L269-18true assume 1 == ~t1_pc~0; 195#L270-6true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 67#L280-6true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 366#is_transmit1_triggered_returnLabel#7true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 182#L645-18true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 285#L645-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 110#L288-18true assume !(1 == ~t2_pc~0); 397#L288-20true is_transmit2_triggered_~__retres1~2#1 := 0; 10#L299-6true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 202#is_transmit2_triggered_returnLabel#7true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 170#L653-18true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 95#L653-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 310#L307-18true assume 1 == ~t3_pc~0; 141#L308-6true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 121#L318-6true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 222#is_transmit3_triggered_returnLabel#7true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 84#L661-18true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 346#L661-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 270#L326-18true assume 1 == ~t4_pc~0; 367#L327-6true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 280#L337-6true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 155#is_transmit4_triggered_returnLabel#7true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4#L669-18true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 371#L669-20true havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 425#L572-3true assume 1 == ~M_E~0;~M_E~0 := 2; 93#L572-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 109#L577-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 33#L582-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 374#L587-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 190#L592-3true assume !(1 == ~E_M~0); 245#L597-3true assume 1 == ~E_1~0;~E_1~0 := 2; 132#L602-3true assume 1 == ~E_2~0;~E_2~0 := 2; 318#L607-3true assume 1 == ~E_3~0;~E_3~0 := 2; 100#L612-3true assume 1 == ~E_4~0;~E_4~0 := 2; 192#L617-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 136#L386-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 125#L413-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 185#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 164#L822true assume !(0 == start_simulation_~tmp~3#1); 265#L822-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 395#L386-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 407#L413-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 30#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 19#L777true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 198#L784true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 319#stop_simulation_returnLabel#1true start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 311#L835true assume !(0 != start_simulation_~tmp___0~1#1); 436#L803-2true [2023-11-19 07:48:04,218 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:04,219 INFO L85 PathProgramCache]: Analyzing trace with hash 1553035642, now seen corresponding path program 1 times [2023-11-19 07:48:04,234 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:04,234 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [531891975] [2023-11-19 07:48:04,235 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:04,236 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:04,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:04,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:04,602 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:04,603 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [531891975] [2023-11-19 07:48:04,604 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [531891975] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:04,604 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:04,604 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:04,606 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1654753379] [2023-11-19 07:48:04,607 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:04,612 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:04,614 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:04,614 INFO L85 PathProgramCache]: Analyzing trace with hash 868114677, now seen corresponding path program 1 times [2023-11-19 07:48:04,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:04,615 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1579546713] [2023-11-19 07:48:04,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:04,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:04,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:04,693 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:04,709 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:04,710 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1579546713] [2023-11-19 07:48:04,710 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1579546713] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:04,715 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:04,715 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:48:04,715 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [22259177] [2023-11-19 07:48:04,716 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:04,717 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:04,718 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:04,752 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:04,753 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:04,757 INFO L87 Difference]: Start difference. First operand has 437 states, 436 states have (on average 1.525229357798165) internal successors, (665), 436 states have internal predecessors, (665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:04,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:04,823 INFO L93 Difference]: Finished difference Result 435 states and 647 transitions. [2023-11-19 07:48:04,824 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 435 states and 647 transitions. [2023-11-19 07:48:04,830 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2023-11-19 07:48:04,838 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 435 states to 430 states and 642 transitions. [2023-11-19 07:48:04,839 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2023-11-19 07:48:04,840 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2023-11-19 07:48:04,841 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 642 transitions. [2023-11-19 07:48:04,844 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:04,845 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430 states and 642 transitions. [2023-11-19 07:48:04,864 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 642 transitions. [2023-11-19 07:48:04,928 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2023-11-19 07:48:04,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.4930232558139536) internal successors, (642), 429 states have internal predecessors, (642), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:04,933 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 642 transitions. [2023-11-19 07:48:04,934 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 642 transitions. [2023-11-19 07:48:04,939 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:04,943 INFO L428 stractBuchiCegarLoop]: Abstraction has 430 states and 642 transitions. [2023-11-19 07:48:04,943 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-19 07:48:04,943 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 642 transitions. [2023-11-19 07:48:04,947 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2023-11-19 07:48:04,947 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:04,947 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:04,949 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:04,949 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:04,956 INFO L748 eck$LassoCheckResult]: Stem: 1110#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1111#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1210#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1211#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1022#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 1023#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1277#L358-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 966#L363-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 967#L368-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1103#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 994#L514 assume !(0 == ~M_E~0); 995#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1291#L519-1 assume !(0 == ~T2_E~0); 954#L524-1 assume !(0 == ~T3_E~0); 955#L529-1 assume !(0 == ~T4_E~0); 1079#L534-1 assume !(0 == ~E_M~0); 1255#L539-1 assume !(0 == ~E_1~0); 1256#L544-1 assume !(0 == ~E_2~0); 1275#L549-1 assume !(0 == ~E_3~0); 1276#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 949#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 950#L250 assume 1 == ~m_pc~0; 1168#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1279#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1092#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1093#L637 assume !(0 != activate_threads_~tmp~1#1); 956#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 957#L269 assume !(1 == ~t1_pc~0); 894#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 893#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 944#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 945#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1137#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1138#L288 assume 1 == ~t2_pc~0; 1231#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1134#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1215#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1216#L653 assume !(0 != activate_threads_~tmp___1~0#1); 1251#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1158#L307 assume !(1 == ~t3_pc~0); 1095#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1096#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 897#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 898#L661 assume !(0 != activate_threads_~tmp___2~0#1); 1108#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1109#L326 assume 1 == ~t4_pc~0; 1300#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 910#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 998#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 999#L669 assume !(0 != activate_threads_~tmp___3~0#1); 1252#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1253#L572 assume !(1 == ~M_E~0); 1280#L572-2 assume !(1 == ~T1_E~0); 962#L577-1 assume !(1 == ~T2_E~0); 963#L582-1 assume !(1 == ~T3_E~0); 1235#L587-1 assume !(1 == ~T4_E~0); 1244#L592-1 assume !(1 == ~E_M~0); 901#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 902#L602-1 assume !(1 == ~E_2~0); 1130#L607-1 assume !(1 == ~E_3~0); 1131#L612-1 assume !(1 == ~E_4~0); 1077#L617-1 assume { :end_inline_reset_delta_events } true; 1078#L803-2 [2023-11-19 07:48:04,958 INFO L750 eck$LassoCheckResult]: Loop: 1078#L803-2 assume !false; 1222#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1188#L489-1 assume !false; 1189#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1159#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1008#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1074#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1224#L428 assume !(0 != eval_~tmp~0#1); 1003#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1004#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1193#L514-3 assume !(0 == ~M_E~0); 1143#L514-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1144#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1234#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1048#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1049#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 890#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 891#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1293#L549-3 assume !(0 == ~E_3~0); 1099#L554-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1100#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1192#L250-18 assume 1 == ~m_pc~0; 1229#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1202#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1126#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1127#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1058#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 933#L269-18 assume 1 == ~t1_pc~0; 934#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1010#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1011#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1181#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1182#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1085#L288-18 assume 1 == ~t2_pc~0; 1069#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 899#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 900#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1167#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1064#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1065#L307-18 assume !(1 == ~t3_pc~0); 1031#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 1032#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1102#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1045#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1046#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1262#L326-18 assume 1 == ~t4_pc~0; 1264#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1270#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1145#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 886#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 887#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1305#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1061#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1062#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 947#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 948#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1190#L592-3 assume !(1 == ~E_M~0); 1191#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1117#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1118#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1072#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1073#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1124#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1089#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1106#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1156#L822 assume !(0 == start_simulation_~tmp~3#1); 1157#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1259#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1197#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 943#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 918#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 919#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1195#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1287#L835 assume !(0 != start_simulation_~tmp___0~1#1); 1078#L803-2 [2023-11-19 07:48:04,959 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:04,959 INFO L85 PathProgramCache]: Analyzing trace with hash 1119306556, now seen corresponding path program 1 times [2023-11-19 07:48:04,960 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:04,960 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [245884855] [2023-11-19 07:48:04,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:04,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:04,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:05,088 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:05,088 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:05,089 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [245884855] [2023-11-19 07:48:05,089 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [245884855] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:05,089 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:05,089 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:05,090 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [202156473] [2023-11-19 07:48:05,090 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:05,091 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:05,092 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:05,092 INFO L85 PathProgramCache]: Analyzing trace with hash -691501310, now seen corresponding path program 1 times [2023-11-19 07:48:05,093 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:05,093 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1333897550] [2023-11-19 07:48:05,093 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:05,094 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:05,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:05,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:05,183 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:05,184 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1333897550] [2023-11-19 07:48:05,184 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1333897550] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:05,184 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:05,184 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:05,185 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1722502180] [2023-11-19 07:48:05,185 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:05,186 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:05,186 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:05,186 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:05,187 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:05,187 INFO L87 Difference]: Start difference. First operand 430 states and 642 transitions. cyclomatic complexity: 213 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:05,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:05,232 INFO L93 Difference]: Finished difference Result 430 states and 641 transitions. [2023-11-19 07:48:05,234 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 641 transitions. [2023-11-19 07:48:05,240 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2023-11-19 07:48:05,244 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 641 transitions. [2023-11-19 07:48:05,244 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2023-11-19 07:48:05,245 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2023-11-19 07:48:05,245 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 641 transitions. [2023-11-19 07:48:05,250 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:05,250 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430 states and 641 transitions. [2023-11-19 07:48:05,252 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 641 transitions. [2023-11-19 07:48:05,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2023-11-19 07:48:05,279 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.4906976744186047) internal successors, (641), 429 states have internal predecessors, (641), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:05,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 641 transitions. [2023-11-19 07:48:05,283 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 641 transitions. [2023-11-19 07:48:05,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:05,285 INFO L428 stractBuchiCegarLoop]: Abstraction has 430 states and 641 transitions. [2023-11-19 07:48:05,285 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-19 07:48:05,285 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 641 transitions. [2023-11-19 07:48:05,289 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2023-11-19 07:48:05,289 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:05,289 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:05,291 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:05,291 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:05,291 INFO L748 eck$LassoCheckResult]: Stem: 1977#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1978#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2077#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2078#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1889#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 1890#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2144#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1833#L363-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1834#L368-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1970#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1861#L514 assume !(0 == ~M_E~0); 1862#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2158#L519-1 assume !(0 == ~T2_E~0); 1821#L524-1 assume !(0 == ~T3_E~0); 1822#L529-1 assume !(0 == ~T4_E~0); 1946#L534-1 assume !(0 == ~E_M~0); 2122#L539-1 assume !(0 == ~E_1~0); 2123#L544-1 assume !(0 == ~E_2~0); 2142#L549-1 assume !(0 == ~E_3~0); 2143#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1816#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1817#L250 assume 1 == ~m_pc~0; 2035#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2146#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1959#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1960#L637 assume !(0 != activate_threads_~tmp~1#1); 1823#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1824#L269 assume !(1 == ~t1_pc~0); 1761#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1760#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1811#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1812#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2004#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2005#L288 assume 1 == ~t2_pc~0; 2098#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2001#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2082#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2083#L653 assume !(0 != activate_threads_~tmp___1~0#1); 2118#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2025#L307 assume !(1 == ~t3_pc~0); 1962#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1963#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1764#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1765#L661 assume !(0 != activate_threads_~tmp___2~0#1); 1975#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1976#L326 assume 1 == ~t4_pc~0; 2167#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1777#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1865#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1866#L669 assume !(0 != activate_threads_~tmp___3~0#1); 2119#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2120#L572 assume !(1 == ~M_E~0); 2147#L572-2 assume !(1 == ~T1_E~0); 1829#L577-1 assume !(1 == ~T2_E~0); 1830#L582-1 assume !(1 == ~T3_E~0); 2102#L587-1 assume !(1 == ~T4_E~0); 2111#L592-1 assume !(1 == ~E_M~0); 1768#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1769#L602-1 assume !(1 == ~E_2~0); 1997#L607-1 assume !(1 == ~E_3~0); 1998#L612-1 assume !(1 == ~E_4~0); 1944#L617-1 assume { :end_inline_reset_delta_events } true; 1945#L803-2 [2023-11-19 07:48:05,292 INFO L750 eck$LassoCheckResult]: Loop: 1945#L803-2 assume !false; 2089#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2055#L489-1 assume !false; 2056#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2026#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1875#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1941#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2091#L428 assume !(0 != eval_~tmp~0#1); 1870#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1871#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2060#L514-3 assume !(0 == ~M_E~0); 2010#L514-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2011#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2101#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1915#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1916#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1757#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1758#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2160#L549-3 assume !(0 == ~E_3~0); 1966#L554-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1967#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2059#L250-18 assume 1 == ~m_pc~0; 2096#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2069#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1993#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1994#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1925#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1800#L269-18 assume 1 == ~t1_pc~0; 1801#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1877#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1878#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2048#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2049#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1952#L288-18 assume 1 == ~t2_pc~0; 1936#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1766#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1767#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2034#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1931#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1932#L307-18 assume !(1 == ~t3_pc~0); 1898#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 1899#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1969#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1912#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1913#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2129#L326-18 assume !(1 == ~t4_pc~0); 2130#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 2137#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2012#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1753#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1754#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2172#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1928#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1929#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1814#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1815#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2057#L592-3 assume !(1 == ~E_M~0); 2058#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1984#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1985#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1939#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1940#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1991#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1956#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1973#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2023#L822 assume !(0 == start_simulation_~tmp~3#1); 2024#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2126#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2064#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1810#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 1785#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1786#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2062#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2154#L835 assume !(0 != start_simulation_~tmp___0~1#1); 1945#L803-2 [2023-11-19 07:48:05,292 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:05,293 INFO L85 PathProgramCache]: Analyzing trace with hash 1078631806, now seen corresponding path program 1 times [2023-11-19 07:48:05,293 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:05,293 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1403617217] [2023-11-19 07:48:05,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:05,294 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:05,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:05,343 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:05,343 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:05,343 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1403617217] [2023-11-19 07:48:05,344 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1403617217] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:05,344 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:05,344 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:05,344 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [237952853] [2023-11-19 07:48:05,345 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:05,345 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:05,345 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:05,346 INFO L85 PathProgramCache]: Analyzing trace with hash -1663175997, now seen corresponding path program 1 times [2023-11-19 07:48:05,346 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:05,346 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [150672962] [2023-11-19 07:48:05,346 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:05,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:05,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:05,409 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:05,410 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:05,410 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [150672962] [2023-11-19 07:48:05,410 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [150672962] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:05,411 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:05,411 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:05,411 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1331390442] [2023-11-19 07:48:05,411 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:05,412 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:05,412 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:05,412 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:05,413 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:05,413 INFO L87 Difference]: Start difference. First operand 430 states and 641 transitions. cyclomatic complexity: 212 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:05,429 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:05,430 INFO L93 Difference]: Finished difference Result 430 states and 640 transitions. [2023-11-19 07:48:05,430 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 640 transitions. [2023-11-19 07:48:05,435 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2023-11-19 07:48:05,439 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 640 transitions. [2023-11-19 07:48:05,439 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2023-11-19 07:48:05,440 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2023-11-19 07:48:05,440 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 640 transitions. [2023-11-19 07:48:05,441 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:05,441 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430 states and 640 transitions. [2023-11-19 07:48:05,442 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 640 transitions. [2023-11-19 07:48:05,450 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2023-11-19 07:48:05,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.4883720930232558) internal successors, (640), 429 states have internal predecessors, (640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:05,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 640 transitions. [2023-11-19 07:48:05,454 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 640 transitions. [2023-11-19 07:48:05,455 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:05,456 INFO L428 stractBuchiCegarLoop]: Abstraction has 430 states and 640 transitions. [2023-11-19 07:48:05,456 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-19 07:48:05,456 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 640 transitions. [2023-11-19 07:48:05,460 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2023-11-19 07:48:05,460 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:05,460 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:05,462 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:05,462 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:05,462 INFO L748 eck$LassoCheckResult]: Stem: 2844#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2845#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2944#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2945#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2756#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 2757#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3011#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2700#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2701#L368-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2837#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2728#L514 assume !(0 == ~M_E~0); 2729#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3025#L519-1 assume !(0 == ~T2_E~0); 2688#L524-1 assume !(0 == ~T3_E~0); 2689#L529-1 assume !(0 == ~T4_E~0); 2813#L534-1 assume !(0 == ~E_M~0); 2989#L539-1 assume !(0 == ~E_1~0); 2990#L544-1 assume !(0 == ~E_2~0); 3009#L549-1 assume !(0 == ~E_3~0); 3010#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2683#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2684#L250 assume 1 == ~m_pc~0; 2902#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3013#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2826#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2827#L637 assume !(0 != activate_threads_~tmp~1#1); 2690#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2691#L269 assume !(1 == ~t1_pc~0); 2628#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2627#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2678#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2679#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2871#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2872#L288 assume 1 == ~t2_pc~0; 2965#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2868#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2949#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2950#L653 assume !(0 != activate_threads_~tmp___1~0#1); 2985#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2892#L307 assume !(1 == ~t3_pc~0); 2829#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2830#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2631#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2632#L661 assume !(0 != activate_threads_~tmp___2~0#1); 2842#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2843#L326 assume 1 == ~t4_pc~0; 3034#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2644#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2732#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2733#L669 assume !(0 != activate_threads_~tmp___3~0#1); 2986#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2987#L572 assume !(1 == ~M_E~0); 3014#L572-2 assume !(1 == ~T1_E~0); 2696#L577-1 assume !(1 == ~T2_E~0); 2697#L582-1 assume !(1 == ~T3_E~0); 2969#L587-1 assume !(1 == ~T4_E~0); 2978#L592-1 assume !(1 == ~E_M~0); 2635#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2636#L602-1 assume !(1 == ~E_2~0); 2864#L607-1 assume !(1 == ~E_3~0); 2865#L612-1 assume !(1 == ~E_4~0); 2811#L617-1 assume { :end_inline_reset_delta_events } true; 2812#L803-2 [2023-11-19 07:48:05,463 INFO L750 eck$LassoCheckResult]: Loop: 2812#L803-2 assume !false; 2956#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2922#L489-1 assume !false; 2923#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2893#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2742#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2808#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2958#L428 assume !(0 != eval_~tmp~0#1); 2737#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2738#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2927#L514-3 assume !(0 == ~M_E~0); 2877#L514-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2878#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2968#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2782#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2783#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2624#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2625#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3027#L549-3 assume !(0 == ~E_3~0); 2833#L554-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2834#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2926#L250-18 assume 1 == ~m_pc~0; 2963#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2936#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2860#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2861#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2792#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2667#L269-18 assume 1 == ~t1_pc~0; 2668#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2744#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2745#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2915#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2916#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2819#L288-18 assume 1 == ~t2_pc~0; 2803#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2633#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2634#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2901#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2798#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2799#L307-18 assume 1 == ~t3_pc~0; 2866#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2766#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2836#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2779#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2780#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2996#L326-18 assume !(1 == ~t4_pc~0); 2997#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 3004#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2879#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2620#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2621#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3039#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2795#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2796#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2681#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2682#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2924#L592-3 assume !(1 == ~E_M~0); 2925#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2851#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2852#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2806#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2807#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2858#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2823#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2840#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2890#L822 assume !(0 == start_simulation_~tmp~3#1); 2891#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2993#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2931#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2677#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 2652#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2653#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2929#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3021#L835 assume !(0 != start_simulation_~tmp___0~1#1); 2812#L803-2 [2023-11-19 07:48:05,463 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:05,464 INFO L85 PathProgramCache]: Analyzing trace with hash -308153604, now seen corresponding path program 1 times [2023-11-19 07:48:05,464 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:05,464 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1799148483] [2023-11-19 07:48:05,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:05,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:05,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:05,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:05,508 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:05,508 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1799148483] [2023-11-19 07:48:05,509 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1799148483] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:05,509 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:05,509 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:05,509 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1330582927] [2023-11-19 07:48:05,509 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:05,510 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:05,510 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:05,510 INFO L85 PathProgramCache]: Analyzing trace with hash 1580342210, now seen corresponding path program 1 times [2023-11-19 07:48:05,511 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:05,511 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2065103792] [2023-11-19 07:48:05,511 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:05,511 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:05,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:05,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:05,603 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:05,603 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2065103792] [2023-11-19 07:48:05,603 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2065103792] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:05,603 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:05,603 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:05,604 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1153800051] [2023-11-19 07:48:05,604 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:05,604 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:05,605 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:05,605 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:05,605 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:05,606 INFO L87 Difference]: Start difference. First operand 430 states and 640 transitions. cyclomatic complexity: 211 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:05,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:05,625 INFO L93 Difference]: Finished difference Result 430 states and 639 transitions. [2023-11-19 07:48:05,626 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 639 transitions. [2023-11-19 07:48:05,631 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2023-11-19 07:48:05,635 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 639 transitions. [2023-11-19 07:48:05,635 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2023-11-19 07:48:05,636 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2023-11-19 07:48:05,636 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 639 transitions. [2023-11-19 07:48:05,637 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:05,637 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430 states and 639 transitions. [2023-11-19 07:48:05,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 639 transitions. [2023-11-19 07:48:05,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2023-11-19 07:48:05,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.486046511627907) internal successors, (639), 429 states have internal predecessors, (639), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:05,651 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 639 transitions. [2023-11-19 07:48:05,651 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 639 transitions. [2023-11-19 07:48:05,652 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:05,654 INFO L428 stractBuchiCegarLoop]: Abstraction has 430 states and 639 transitions. [2023-11-19 07:48:05,655 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-19 07:48:05,662 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 639 transitions. [2023-11-19 07:48:05,668 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2023-11-19 07:48:05,668 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:05,669 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:05,670 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:05,671 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:05,671 INFO L748 eck$LassoCheckResult]: Stem: 3711#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3712#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3811#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3812#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3623#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 3624#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3879#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3567#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3568#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3704#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3597#L514 assume !(0 == ~M_E~0); 3598#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3892#L519-1 assume !(0 == ~T2_E~0); 3555#L524-1 assume !(0 == ~T3_E~0); 3556#L529-1 assume !(0 == ~T4_E~0); 3680#L534-1 assume !(0 == ~E_M~0); 3856#L539-1 assume !(0 == ~E_1~0); 3857#L544-1 assume !(0 == ~E_2~0); 3876#L549-1 assume !(0 == ~E_3~0); 3877#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 3550#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3551#L250 assume 1 == ~m_pc~0; 3769#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3880#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3693#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3694#L637 assume !(0 != activate_threads_~tmp~1#1); 3557#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3558#L269 assume !(1 == ~t1_pc~0); 3495#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3494#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3545#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3546#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3738#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3739#L288 assume 1 == ~t2_pc~0; 3832#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3735#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3816#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3817#L653 assume !(0 != activate_threads_~tmp___1~0#1); 3852#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3759#L307 assume !(1 == ~t3_pc~0); 3696#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3697#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3498#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3499#L661 assume !(0 != activate_threads_~tmp___2~0#1); 3709#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3710#L326 assume 1 == ~t4_pc~0; 3901#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3511#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3599#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3600#L669 assume !(0 != activate_threads_~tmp___3~0#1); 3853#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3854#L572 assume !(1 == ~M_E~0); 3881#L572-2 assume !(1 == ~T1_E~0); 3563#L577-1 assume !(1 == ~T2_E~0); 3564#L582-1 assume !(1 == ~T3_E~0); 3836#L587-1 assume !(1 == ~T4_E~0); 3845#L592-1 assume !(1 == ~E_M~0); 3502#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3503#L602-1 assume !(1 == ~E_2~0); 3731#L607-1 assume !(1 == ~E_3~0); 3732#L612-1 assume !(1 == ~E_4~0); 3678#L617-1 assume { :end_inline_reset_delta_events } true; 3679#L803-2 [2023-11-19 07:48:05,672 INFO L750 eck$LassoCheckResult]: Loop: 3679#L803-2 assume !false; 3823#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3789#L489-1 assume !false; 3790#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3760#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3609#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3675#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3825#L428 assume !(0 != eval_~tmp~0#1); 3604#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3605#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3794#L514-3 assume !(0 == ~M_E~0); 3744#L514-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3745#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3835#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3649#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3650#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3491#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3492#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3894#L549-3 assume !(0 == ~E_3~0); 3700#L554-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3701#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3793#L250-18 assume 1 == ~m_pc~0; 3830#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3803#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3727#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3728#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3659#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3534#L269-18 assume !(1 == ~t1_pc~0); 3536#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 3611#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3612#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3782#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3783#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3686#L288-18 assume 1 == ~t2_pc~0; 3670#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3500#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3501#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3768#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3665#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3666#L307-18 assume !(1 == ~t3_pc~0); 3632#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 3633#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3703#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3646#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3647#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3863#L326-18 assume !(1 == ~t4_pc~0); 3864#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 3871#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3746#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3487#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3488#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3906#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3662#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3663#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3548#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3549#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3791#L592-3 assume !(1 == ~E_M~0); 3792#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3718#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3719#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3673#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3674#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3725#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3690#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3707#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 3757#L822 assume !(0 == start_simulation_~tmp~3#1); 3758#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3860#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3798#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3544#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 3519#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3520#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3796#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3888#L835 assume !(0 != start_simulation_~tmp___0~1#1); 3679#L803-2 [2023-11-19 07:48:05,672 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:05,672 INFO L85 PathProgramCache]: Analyzing trace with hash -1184172610, now seen corresponding path program 1 times [2023-11-19 07:48:05,673 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:05,673 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [469929191] [2023-11-19 07:48:05,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:05,673 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:05,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:05,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:05,737 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:05,737 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [469929191] [2023-11-19 07:48:05,737 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [469929191] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:05,738 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:05,738 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:48:05,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2053793943] [2023-11-19 07:48:05,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:05,739 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:05,739 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:05,739 INFO L85 PathProgramCache]: Analyzing trace with hash 738349124, now seen corresponding path program 1 times [2023-11-19 07:48:05,740 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:05,740 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1679891521] [2023-11-19 07:48:05,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:05,740 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:05,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:05,796 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:05,797 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:05,797 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1679891521] [2023-11-19 07:48:05,797 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1679891521] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:05,797 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:05,798 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:05,798 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1897024707] [2023-11-19 07:48:05,798 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:05,798 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:05,799 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:05,799 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:05,799 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:05,800 INFO L87 Difference]: Start difference. First operand 430 states and 639 transitions. cyclomatic complexity: 210 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:05,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:05,823 INFO L93 Difference]: Finished difference Result 430 states and 634 transitions. [2023-11-19 07:48:05,823 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 634 transitions. [2023-11-19 07:48:05,828 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2023-11-19 07:48:05,832 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 634 transitions. [2023-11-19 07:48:05,832 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2023-11-19 07:48:05,833 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2023-11-19 07:48:05,833 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 634 transitions. [2023-11-19 07:48:05,835 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:05,836 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430 states and 634 transitions. [2023-11-19 07:48:05,836 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 634 transitions. [2023-11-19 07:48:05,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2023-11-19 07:48:05,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.4744186046511627) internal successors, (634), 429 states have internal predecessors, (634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:05,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 634 transitions. [2023-11-19 07:48:05,858 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 634 transitions. [2023-11-19 07:48:05,868 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:05,869 INFO L428 stractBuchiCegarLoop]: Abstraction has 430 states and 634 transitions. [2023-11-19 07:48:05,869 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-19 07:48:05,869 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 634 transitions. [2023-11-19 07:48:05,872 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2023-11-19 07:48:05,872 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:05,872 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:05,873 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:05,874 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:05,874 INFO L748 eck$LassoCheckResult]: Stem: 4578#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 4579#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4678#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4679#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4490#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 4491#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4745#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4434#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4435#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4571#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4462#L514 assume !(0 == ~M_E~0); 4463#L514-2 assume !(0 == ~T1_E~0); 4759#L519-1 assume !(0 == ~T2_E~0); 4422#L524-1 assume !(0 == ~T3_E~0); 4423#L529-1 assume !(0 == ~T4_E~0); 4547#L534-1 assume !(0 == ~E_M~0); 4723#L539-1 assume !(0 == ~E_1~0); 4724#L544-1 assume !(0 == ~E_2~0); 4743#L549-1 assume !(0 == ~E_3~0); 4744#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4417#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4418#L250 assume 1 == ~m_pc~0; 4639#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4747#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4560#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4561#L637 assume !(0 != activate_threads_~tmp~1#1); 4424#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4425#L269 assume !(1 == ~t1_pc~0); 4362#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4361#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4412#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4413#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4605#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4606#L288 assume 1 == ~t2_pc~0; 4699#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4602#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4683#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4684#L653 assume !(0 != activate_threads_~tmp___1~0#1); 4719#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4626#L307 assume !(1 == ~t3_pc~0); 4563#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4564#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4365#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4366#L661 assume !(0 != activate_threads_~tmp___2~0#1); 4576#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4577#L326 assume 1 == ~t4_pc~0; 4768#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4378#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4466#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4467#L669 assume !(0 != activate_threads_~tmp___3~0#1); 4720#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4721#L572 assume !(1 == ~M_E~0); 4748#L572-2 assume !(1 == ~T1_E~0); 4430#L577-1 assume !(1 == ~T2_E~0); 4431#L582-1 assume !(1 == ~T3_E~0); 4704#L587-1 assume !(1 == ~T4_E~0); 4713#L592-1 assume !(1 == ~E_M~0); 4369#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4370#L602-1 assume !(1 == ~E_2~0); 4598#L607-1 assume !(1 == ~E_3~0); 4599#L612-1 assume !(1 == ~E_4~0); 4545#L617-1 assume { :end_inline_reset_delta_events } true; 4546#L803-2 [2023-11-19 07:48:05,874 INFO L750 eck$LassoCheckResult]: Loop: 4546#L803-2 assume !false; 4691#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4656#L489-1 assume !false; 4657#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4627#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4476#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4542#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4692#L428 assume !(0 != eval_~tmp~0#1); 4471#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4472#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4661#L514-3 assume !(0 == ~M_E~0); 4612#L514-5 assume !(0 == ~T1_E~0); 4613#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4702#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4518#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4519#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4358#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4359#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4761#L549-3 assume !(0 == ~E_3~0); 4567#L554-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4568#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4660#L250-18 assume 1 == ~m_pc~0; 4697#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4670#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4594#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4595#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4526#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4401#L269-18 assume 1 == ~t1_pc~0; 4402#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4478#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4479#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4649#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4650#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4553#L288-18 assume 1 == ~t2_pc~0; 4534#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4367#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4368#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4635#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4532#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4533#L307-18 assume !(1 == ~t3_pc~0); 4497#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 4498#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4570#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4510#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4511#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4730#L326-18 assume !(1 == ~t4_pc~0); 4731#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 4738#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4611#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4354#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4355#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4773#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4529#L572-5 assume !(1 == ~T1_E~0); 4530#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4415#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4416#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4658#L592-3 assume !(1 == ~E_M~0); 4659#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4585#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4586#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4540#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4541#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4592#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4557#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4573#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 4624#L822 assume !(0 == start_simulation_~tmp~3#1); 4625#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4726#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4665#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4411#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 4386#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4387#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4663#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4755#L835 assume !(0 != start_simulation_~tmp___0~1#1); 4546#L803-2 [2023-11-19 07:48:05,875 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:05,875 INFO L85 PathProgramCache]: Analyzing trace with hash 1082208576, now seen corresponding path program 1 times [2023-11-19 07:48:05,875 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:05,875 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [51080516] [2023-11-19 07:48:05,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:05,876 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:05,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:05,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:05,986 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:05,987 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [51080516] [2023-11-19 07:48:05,987 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [51080516] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:05,987 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:05,987 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:05,988 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1893524235] [2023-11-19 07:48:05,988 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:05,988 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:05,989 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:05,989 INFO L85 PathProgramCache]: Analyzing trace with hash -1861717885, now seen corresponding path program 1 times [2023-11-19 07:48:05,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:05,994 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [395518800] [2023-11-19 07:48:05,994 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:05,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:06,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:06,053 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:06,053 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:06,053 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [395518800] [2023-11-19 07:48:06,054 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [395518800] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:06,054 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:06,054 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:06,055 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [708425494] [2023-11-19 07:48:06,055 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:06,056 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:06,056 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:06,056 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:48:06,056 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:48:06,057 INFO L87 Difference]: Start difference. First operand 430 states and 634 transitions. cyclomatic complexity: 205 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:06,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:06,204 INFO L93 Difference]: Finished difference Result 720 states and 1058 transitions. [2023-11-19 07:48:06,204 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 720 states and 1058 transitions. [2023-11-19 07:48:06,210 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 642 [2023-11-19 07:48:06,216 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 720 states to 720 states and 1058 transitions. [2023-11-19 07:48:06,216 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 720 [2023-11-19 07:48:06,217 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 720 [2023-11-19 07:48:06,217 INFO L73 IsDeterministic]: Start isDeterministic. Operand 720 states and 1058 transitions. [2023-11-19 07:48:06,218 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:06,218 INFO L218 hiAutomatonCegarLoop]: Abstraction has 720 states and 1058 transitions. [2023-11-19 07:48:06,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 720 states and 1058 transitions. [2023-11-19 07:48:06,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 720 to 719. [2023-11-19 07:48:06,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 719 states, 719 states have (on average 1.4700973574408902) internal successors, (1057), 718 states have internal predecessors, (1057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:06,243 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 719 states to 719 states and 1057 transitions. [2023-11-19 07:48:06,243 INFO L240 hiAutomatonCegarLoop]: Abstraction has 719 states and 1057 transitions. [2023-11-19 07:48:06,243 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:48:06,246 INFO L428 stractBuchiCegarLoop]: Abstraction has 719 states and 1057 transitions. [2023-11-19 07:48:06,246 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-19 07:48:06,246 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 719 states and 1057 transitions. [2023-11-19 07:48:06,250 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 642 [2023-11-19 07:48:06,251 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:06,254 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:06,258 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:06,258 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:06,258 INFO L748 eck$LassoCheckResult]: Stem: 5741#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 5742#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5848#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5849#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5650#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 5651#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5926#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5594#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5595#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5734#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5622#L514 assume !(0 == ~M_E~0); 5623#L514-2 assume !(0 == ~T1_E~0); 5946#L519-1 assume !(0 == ~T2_E~0); 5582#L524-1 assume !(0 == ~T3_E~0); 5583#L529-1 assume !(0 == ~T4_E~0); 5709#L534-1 assume !(0 == ~E_M~0); 5901#L539-1 assume !(0 == ~E_1~0); 5902#L544-1 assume !(0 == ~E_2~0); 5924#L549-1 assume !(0 == ~E_3~0); 5925#L554-1 assume !(0 == ~E_4~0); 5577#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5578#L250 assume 1 == ~m_pc~0; 5805#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5928#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5723#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5724#L637 assume !(0 != activate_threads_~tmp~1#1); 5584#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5585#L269 assume !(1 == ~t1_pc~0); 5522#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5521#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5572#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5573#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5768#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5769#L288 assume 1 == ~t2_pc~0; 5874#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5765#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5853#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5854#L653 assume !(0 != activate_threads_~tmp___1~0#1); 5897#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5791#L307 assume !(1 == ~t3_pc~0); 5726#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5727#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5525#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5526#L661 assume !(0 != activate_threads_~tmp___2~0#1); 5739#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5740#L326 assume 1 == ~t4_pc~0; 5955#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5538#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5626#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5627#L669 assume !(0 != activate_threads_~tmp___3~0#1); 5898#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5899#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 5929#L572-2 assume !(1 == ~T1_E~0); 5590#L577-1 assume !(1 == ~T2_E~0); 5591#L582-1 assume !(1 == ~T3_E~0); 5880#L587-1 assume !(1 == ~T4_E~0); 5890#L592-1 assume !(1 == ~E_M~0); 5962#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6079#L602-1 assume !(1 == ~E_2~0); 5998#L607-1 assume !(1 == ~E_3~0); 5997#L612-1 assume !(1 == ~E_4~0); 5707#L617-1 assume { :end_inline_reset_delta_events } true; 5708#L803-2 [2023-11-19 07:48:06,258 INFO L750 eck$LassoCheckResult]: Loop: 5708#L803-2 assume !false; 5861#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5862#L489-1 assume !false; 5985#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5984#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5703#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5704#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5978#L428 assume !(0 != eval_~tmp~0#1); 5977#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5938#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5939#L514-3 assume !(0 == ~M_E~0); 5777#L514-5 assume !(0 == ~T1_E~0); 5778#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5878#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5676#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5677#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5518#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5519#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5948#L549-3 assume !(0 == ~E_3~0); 5730#L554-3 assume !(0 == ~E_4~0); 5731#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5826#L250-18 assume !(1 == ~m_pc~0); 5872#L250-20 is_master_triggered_~__retres1~0#1 := 0; 5840#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5757#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5758#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5686#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5561#L269-18 assume 1 == ~t1_pc~0; 5562#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5638#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5639#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5815#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5816#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5716#L288-18 assume 1 == ~t2_pc~0; 5694#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5527#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5528#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5800#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5692#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5693#L307-18 assume 1 == ~t3_pc~0; 5763#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5658#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5733#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5670#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5671#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5909#L326-18 assume !(1 == ~t4_pc~0); 5910#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 5917#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5776#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5514#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5515#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5961#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5689#L572-5 assume !(1 == ~T1_E~0); 5690#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5715#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6135#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6134#L592-3 assume !(1 == ~E_M~0); 6133#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6132#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6131#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6130#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5701#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5755#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5720#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5736#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 5789#L822 assume !(0 == start_simulation_~tmp~3#1); 5790#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5968#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5833#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5571#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 5546#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5547#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5831#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 5941#L835 assume !(0 != start_simulation_~tmp___0~1#1); 5708#L803-2 [2023-11-19 07:48:06,259 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:06,259 INFO L85 PathProgramCache]: Analyzing trace with hash -516249280, now seen corresponding path program 1 times [2023-11-19 07:48:06,259 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:06,259 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [484231667] [2023-11-19 07:48:06,260 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:06,263 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:06,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:06,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:06,326 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:06,326 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [484231667] [2023-11-19 07:48:06,327 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [484231667] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:06,327 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:06,327 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:48:06,327 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [289854404] [2023-11-19 07:48:06,327 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:06,328 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:06,328 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:06,328 INFO L85 PathProgramCache]: Analyzing trace with hash -1800160059, now seen corresponding path program 1 times [2023-11-19 07:48:06,328 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:06,328 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1743940145] [2023-11-19 07:48:06,329 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:06,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:06,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:06,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:06,373 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:06,373 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1743940145] [2023-11-19 07:48:06,373 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1743940145] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:06,374 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:06,374 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:06,374 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [835183050] [2023-11-19 07:48:06,375 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:06,375 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:06,375 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:06,376 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:06,376 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:06,376 INFO L87 Difference]: Start difference. First operand 719 states and 1057 transitions. cyclomatic complexity: 340 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:06,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:06,483 INFO L93 Difference]: Finished difference Result 1342 states and 1948 transitions. [2023-11-19 07:48:06,483 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1342 states and 1948 transitions. [2023-11-19 07:48:06,494 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1264 [2023-11-19 07:48:06,505 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1342 states to 1342 states and 1948 transitions. [2023-11-19 07:48:06,505 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1342 [2023-11-19 07:48:06,506 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1342 [2023-11-19 07:48:06,506 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1342 states and 1948 transitions. [2023-11-19 07:48:06,508 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:06,509 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1342 states and 1948 transitions. [2023-11-19 07:48:06,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1342 states and 1948 transitions. [2023-11-19 07:48:06,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1342 to 1274. [2023-11-19 07:48:06,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1274 states, 1274 states have (on average 1.4552590266875982) internal successors, (1854), 1273 states have internal predecessors, (1854), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:06,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1274 states to 1274 states and 1854 transitions. [2023-11-19 07:48:06,545 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1274 states and 1854 transitions. [2023-11-19 07:48:06,545 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:06,547 INFO L428 stractBuchiCegarLoop]: Abstraction has 1274 states and 1854 transitions. [2023-11-19 07:48:06,547 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-19 07:48:06,547 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1274 states and 1854 transitions. [2023-11-19 07:48:06,555 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1196 [2023-11-19 07:48:06,555 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:06,556 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:06,557 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:06,558 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:06,558 INFO L748 eck$LassoCheckResult]: Stem: 7818#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 7819#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 7941#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7942#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7720#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 7721#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8041#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7662#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7663#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7809#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7692#L514 assume !(0 == ~M_E~0); 7693#L514-2 assume !(0 == ~T1_E~0); 8079#L519-1 assume !(0 == ~T2_E~0); 7650#L524-1 assume !(0 == ~T3_E~0); 7651#L529-1 assume !(0 == ~T4_E~0); 7782#L534-1 assume !(0 == ~E_M~0); 8002#L539-1 assume !(0 == ~E_1~0); 8003#L544-1 assume !(0 == ~E_2~0); 8039#L549-1 assume !(0 == ~E_3~0); 8040#L554-1 assume !(0 == ~E_4~0); 7645#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7646#L250 assume !(1 == ~m_pc~0); 7890#L250-2 is_master_triggered_~__retres1~0#1 := 0; 8043#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7796#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7797#L637 assume !(0 != activate_threads_~tmp~1#1); 7652#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7653#L269 assume !(1 == ~t1_pc~0); 7590#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7589#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7640#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7641#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7853#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7854#L288 assume 1 == ~t2_pc~0; 7972#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7844#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7947#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7948#L653 assume !(0 != activate_threads_~tmp___1~0#1); 7997#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7879#L307 assume !(1 == ~t3_pc~0); 7799#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7800#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7593#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7594#L661 assume !(0 != activate_threads_~tmp___2~0#1); 7816#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7817#L326 assume 1 == ~t4_pc~0; 8093#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7606#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7696#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7697#L669 assume !(0 != activate_threads_~tmp___3~0#1); 7999#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8000#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 8044#L572-2 assume !(1 == ~T1_E~0); 7658#L577-1 assume !(1 == ~T2_E~0); 7659#L582-1 assume !(1 == ~T3_E~0); 7980#L587-1 assume !(1 == ~T4_E~0); 7989#L592-1 assume !(1 == ~E_M~0); 7597#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7598#L602-1 assume !(1 == ~E_2~0); 7840#L607-1 assume !(1 == ~E_3~0); 7841#L612-1 assume !(1 == ~E_4~0); 8132#L617-1 assume { :end_inline_reset_delta_events } true; 8572#L803-2 [2023-11-19 07:48:06,558 INFO L750 eck$LassoCheckResult]: Loop: 8572#L803-2 assume !false; 8568#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8567#L489-1 assume !false; 8135#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8136#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8168#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8169#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8164#L428 assume !(0 != eval_~tmp~0#1); 7701#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7702#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8059#L514-3 assume !(0 == ~M_E~0); 7862#L514-5 assume !(0 == ~T1_E~0); 7863#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7977#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7978#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7888#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7889#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8817#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8816#L549-3 assume !(0 == ~E_3~0); 8815#L554-3 assume !(0 == ~E_4~0); 8814#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8813#L250-18 assume !(1 == ~m_pc~0); 8810#L250-20 is_master_triggered_~__retres1~0#1 := 0; 8798#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8797#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8796#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8795#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8794#L269-18 assume 1 == ~t1_pc~0; 8791#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8789#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8787#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8785#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8783#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8780#L288-18 assume !(1 == ~t2_pc~0); 8777#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 8775#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8773#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8772#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8771#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8770#L307-18 assume !(1 == ~t3_pc~0); 8768#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 8765#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8763#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8761#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8759#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8756#L326-18 assume !(1 == ~t4_pc~0); 8754#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 8751#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8748#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8746#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8744#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8742#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8740#L572-5 assume !(1 == ~T1_E~0); 8738#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8736#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8734#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8732#L592-3 assume !(1 == ~E_M~0); 8730#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8726#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8072#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8073#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8293#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8214#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8200#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8201#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 7877#L822 assume !(0 == start_simulation_~tmp~3#1); 7878#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8116#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7927#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8590#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 8589#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8587#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8074#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 8075#L835 assume !(0 != start_simulation_~tmp___0~1#1); 8572#L803-2 [2023-11-19 07:48:06,559 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:06,559 INFO L85 PathProgramCache]: Analyzing trace with hash -1001423999, now seen corresponding path program 1 times [2023-11-19 07:48:06,559 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:06,559 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [964411173] [2023-11-19 07:48:06,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:06,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:06,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:06,615 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:06,615 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:06,615 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [964411173] [2023-11-19 07:48:06,616 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [964411173] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:06,616 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:06,616 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:48:06,616 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1013417835] [2023-11-19 07:48:06,616 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:06,617 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:06,617 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:06,617 INFO L85 PathProgramCache]: Analyzing trace with hash -1233885689, now seen corresponding path program 1 times [2023-11-19 07:48:06,617 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:06,618 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [511204168] [2023-11-19 07:48:06,618 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:06,618 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:06,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:06,653 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:06,653 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:06,653 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [511204168] [2023-11-19 07:48:06,653 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [511204168] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:06,654 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:06,654 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:06,654 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1569333485] [2023-11-19 07:48:06,654 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:06,654 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:06,655 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:06,655 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 07:48:06,655 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 07:48:06,655 INFO L87 Difference]: Start difference. First operand 1274 states and 1854 transitions. cyclomatic complexity: 584 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:06,862 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:06,863 INFO L93 Difference]: Finished difference Result 2958 states and 4247 transitions. [2023-11-19 07:48:06,863 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2958 states and 4247 transitions. [2023-11-19 07:48:06,887 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2810 [2023-11-19 07:48:06,911 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2958 states to 2958 states and 4247 transitions. [2023-11-19 07:48:06,911 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2958 [2023-11-19 07:48:06,914 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2958 [2023-11-19 07:48:06,914 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2958 states and 4247 transitions. [2023-11-19 07:48:06,919 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:06,919 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2958 states and 4247 transitions. [2023-11-19 07:48:06,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2958 states and 4247 transitions. [2023-11-19 07:48:06,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2958 to 1343. [2023-11-19 07:48:06,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1343 states, 1343 states have (on average 1.4318689501116904) internal successors, (1923), 1342 states have internal predecessors, (1923), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:06,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1343 states to 1343 states and 1923 transitions. [2023-11-19 07:48:06,964 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1343 states and 1923 transitions. [2023-11-19 07:48:06,964 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-19 07:48:06,965 INFO L428 stractBuchiCegarLoop]: Abstraction has 1343 states and 1923 transitions. [2023-11-19 07:48:06,965 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-19 07:48:06,966 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1343 states and 1923 transitions. [2023-11-19 07:48:06,974 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1262 [2023-11-19 07:48:06,975 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:06,975 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:06,976 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:06,976 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:06,977 INFO L748 eck$LassoCheckResult]: Stem: 12068#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 12069#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 12185#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12186#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11969#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 11970#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12281#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11910#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11911#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12058#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11940#L514 assume !(0 == ~M_E~0); 11941#L514-2 assume !(0 == ~T1_E~0); 12305#L519-1 assume !(0 == ~T2_E~0); 11898#L524-1 assume !(0 == ~T3_E~0); 11899#L529-1 assume !(0 == ~T4_E~0); 12030#L534-1 assume !(0 == ~E_M~0); 12245#L539-1 assume !(0 == ~E_1~0); 12246#L544-1 assume !(0 == ~E_2~0); 12279#L549-1 assume !(0 == ~E_3~0); 12280#L554-1 assume !(0 == ~E_4~0); 11893#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11894#L250 assume !(1 == ~m_pc~0); 12132#L250-2 is_master_triggered_~__retres1~0#1 := 0; 12283#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12047#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12048#L637 assume !(0 != activate_threads_~tmp~1#1); 11900#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11901#L269 assume !(1 == ~t1_pc~0); 11835#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12025#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12142#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12306#L645 assume !(0 != activate_threads_~tmp___0~0#1); 12100#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12101#L288 assume 1 == ~t2_pc~0; 12214#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12093#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12190#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12191#L653 assume !(0 != activate_threads_~tmp___1~0#1); 12239#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12123#L307 assume !(1 == ~t3_pc~0); 12050#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12051#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11838#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11839#L661 assume !(0 != activate_threads_~tmp___2~0#1); 12066#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12067#L326 assume 1 == ~t4_pc~0; 12322#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11853#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11944#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11945#L669 assume !(0 != activate_threads_~tmp___3~0#1); 12242#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12243#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 12284#L572-2 assume !(1 == ~T1_E~0); 12323#L577-1 assume !(1 == ~T2_E~0); 12219#L582-1 assume !(1 == ~T3_E~0); 12220#L587-1 assume !(1 == ~T4_E~0); 12338#L592-1 assume !(1 == ~E_M~0); 12339#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12355#L602-1 assume !(1 == ~E_2~0); 12356#L607-1 assume !(1 == ~E_3~0); 12359#L612-1 assume !(1 == ~E_4~0); 12360#L617-1 assume { :end_inline_reset_delta_events } true; 12706#L803-2 [2023-11-19 07:48:06,977 INFO L750 eck$LassoCheckResult]: Loop: 12706#L803-2 assume !false; 12703#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12702#L489-1 assume !false; 12701#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12700#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12695#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12203#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12204#L428 assume !(0 != eval_~tmp~0#1); 11950#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11951#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12163#L514-3 assume !(0 == ~M_E~0); 12108#L514-5 assume !(0 == ~T1_E~0); 12109#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12218#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11996#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11997#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11831#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11832#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12308#L549-3 assume !(0 == ~E_3~0); 12054#L554-3 assume !(0 == ~E_4~0); 12055#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12161#L250-18 assume !(1 == ~m_pc~0); 12255#L250-20 is_master_triggered_~__retres1~0#1 := 0; 12176#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12084#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12085#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12006#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12007#L269-18 assume 1 == ~t1_pc~0; 13157#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13155#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13153#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13151#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13150#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13149#L288-18 assume 1 == ~t2_pc~0; 12018#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11840#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11841#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13132#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13131#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13130#L307-18 assume 1 == ~t3_pc~0; 13128#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13127#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13126#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13125#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13111#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13110#L326-18 assume !(1 == ~t4_pc~0); 13108#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 13107#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13106#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13105#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12443#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12444#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12438#L572-5 assume !(1 == ~T1_E~0); 12439#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12431#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12432#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12420#L592-3 assume !(1 == ~E_M~0); 12421#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12406#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12407#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12397#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12398#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12389#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12385#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12378#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 12379#L822 assume !(0 == start_simulation_~tmp~3#1); 12752#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12750#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12746#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12744#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 12740#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12738#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12718#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 12711#L835 assume !(0 != start_simulation_~tmp___0~1#1); 12706#L803-2 [2023-11-19 07:48:06,978 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:06,978 INFO L85 PathProgramCache]: Analyzing trace with hash -299824125, now seen corresponding path program 1 times [2023-11-19 07:48:06,978 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:06,978 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [257977192] [2023-11-19 07:48:06,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:06,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:06,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:07,039 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:07,039 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:07,040 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [257977192] [2023-11-19 07:48:07,040 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [257977192] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:07,040 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:07,040 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:07,040 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [167411527] [2023-11-19 07:48:07,041 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:07,041 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:07,041 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:07,042 INFO L85 PathProgramCache]: Analyzing trace with hash -1800160059, now seen corresponding path program 2 times [2023-11-19 07:48:07,042 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:07,042 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1325339960] [2023-11-19 07:48:07,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:07,043 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:07,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:07,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:07,124 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:07,124 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1325339960] [2023-11-19 07:48:07,124 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1325339960] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:07,125 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:07,125 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:07,125 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1074911331] [2023-11-19 07:48:07,125 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:07,125 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:07,126 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:07,126 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:48:07,126 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:48:07,126 INFO L87 Difference]: Start difference. First operand 1343 states and 1923 transitions. cyclomatic complexity: 584 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:07,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:07,296 INFO L93 Difference]: Finished difference Result 3076 states and 4350 transitions. [2023-11-19 07:48:07,296 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3076 states and 4350 transitions. [2023-11-19 07:48:07,322 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2906 [2023-11-19 07:48:07,346 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3076 states to 3076 states and 4350 transitions. [2023-11-19 07:48:07,346 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3076 [2023-11-19 07:48:07,350 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3076 [2023-11-19 07:48:07,350 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3076 states and 4350 transitions. [2023-11-19 07:48:07,354 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:07,354 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3076 states and 4350 transitions. [2023-11-19 07:48:07,358 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3076 states and 4350 transitions. [2023-11-19 07:48:07,402 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3076 to 2418. [2023-11-19 07:48:07,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2418 states, 2418 states have (on average 1.423490488006617) internal successors, (3442), 2417 states have internal predecessors, (3442), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:07,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2418 states to 2418 states and 3442 transitions. [2023-11-19 07:48:07,417 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2418 states and 3442 transitions. [2023-11-19 07:48:07,418 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:48:07,420 INFO L428 stractBuchiCegarLoop]: Abstraction has 2418 states and 3442 transitions. [2023-11-19 07:48:07,420 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-19 07:48:07,420 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2418 states and 3442 transitions. [2023-11-19 07:48:07,436 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2336 [2023-11-19 07:48:07,436 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:07,437 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:07,439 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:07,439 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:07,439 INFO L748 eck$LassoCheckResult]: Stem: 16481#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 16482#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 16583#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16584#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16391#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 16392#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16668#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16336#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16337#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16474#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16362#L514 assume !(0 == ~M_E~0); 16363#L514-2 assume !(0 == ~T1_E~0); 16685#L519-1 assume !(0 == ~T2_E~0); 16324#L524-1 assume !(0 == ~T3_E~0); 16325#L529-1 assume !(0 == ~T4_E~0); 16449#L534-1 assume !(0 == ~E_M~0); 16639#L539-1 assume !(0 == ~E_1~0); 16640#L544-1 assume !(0 == ~E_2~0); 16666#L549-1 assume !(0 == ~E_3~0); 16667#L554-1 assume !(0 == ~E_4~0); 16319#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16320#L250 assume !(1 == ~m_pc~0); 16543#L250-2 is_master_triggered_~__retres1~0#1 := 0; 16670#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16463#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16464#L637 assume !(0 != activate_threads_~tmp~1#1); 16326#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16327#L269 assume !(1 == ~t1_pc~0); 16264#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16444#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16741#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16686#L645 assume !(0 != activate_threads_~tmp___0~0#1); 16510#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16511#L288 assume !(1 == ~t2_pc~0); 16503#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16504#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16590#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16591#L653 assume !(0 != activate_threads_~tmp___1~0#1); 16635#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16534#L307 assume !(1 == ~t3_pc~0); 16466#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16467#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16267#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16268#L661 assume !(0 != activate_threads_~tmp___2~0#1); 16479#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16480#L326 assume 1 == ~t4_pc~0; 16703#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16280#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16366#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16367#L669 assume !(0 != activate_threads_~tmp___3~0#1); 16636#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16637#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 16671#L572-2 assume !(1 == ~T1_E~0); 16332#L577-1 assume !(1 == ~T2_E~0); 16333#L582-1 assume !(1 == ~T3_E~0); 16627#L587-1 assume !(1 == ~T4_E~0); 16628#L592-1 assume !(1 == ~E_M~0); 16271#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 16272#L602-1 assume !(1 == ~E_2~0); 16500#L607-1 assume !(1 == ~E_3~0); 16501#L612-1 assume !(1 == ~E_4~0); 16447#L617-1 assume { :end_inline_reset_delta_events } true; 16448#L803-2 [2023-11-19 07:48:07,440 INFO L750 eck$LassoCheckResult]: Loop: 16448#L803-2 assume !false; 16602#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16560#L489-1 assume !false; 16561#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 16535#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 16377#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 16443#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 16604#L428 assume !(0 != eval_~tmp~0#1); 16372#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16373#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16565#L514-3 assume !(0 == ~M_E~0); 16519#L514-5 assume !(0 == ~T1_E~0); 16520#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16616#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16417#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16418#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16260#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16261#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16688#L549-3 assume !(0 == ~E_3~0); 16470#L554-3 assume !(0 == ~E_4~0); 16471#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16564#L250-18 assume !(1 == ~m_pc~0); 16648#L250-20 is_master_triggered_~__retres1~0#1 := 0; 16575#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16496#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16497#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16427#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16303#L269-18 assume 1 == ~t1_pc~0; 16304#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16566#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18630#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 18629#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16554#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16455#L288-18 assume !(1 == ~t2_pc~0); 16456#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 16269#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16270#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16542#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16433#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16434#L307-18 assume !(1 == ~t3_pc~0); 16400#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 16401#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16473#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16414#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16415#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16649#L326-18 assume !(1 == ~t4_pc~0); 16650#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 16659#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16521#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16256#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16257#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16715#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16430#L572-5 assume !(1 == ~T1_E~0); 16431#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16317#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16318#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16562#L592-3 assume !(1 == ~E_M~0); 16563#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16487#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16488#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16441#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16442#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 16494#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 16460#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 16477#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 16532#L822 assume !(0 == start_simulation_~tmp~3#1); 16533#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 16645#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 16570#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 16313#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 16288#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16289#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16568#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 16681#L835 assume !(0 != start_simulation_~tmp___0~1#1); 16448#L803-2 [2023-11-19 07:48:07,442 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:07,442 INFO L85 PathProgramCache]: Analyzing trace with hash -1271498812, now seen corresponding path program 1 times [2023-11-19 07:48:07,442 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:07,443 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1658030777] [2023-11-19 07:48:07,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:07,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:07,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:07,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:07,493 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:07,494 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1658030777] [2023-11-19 07:48:07,495 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1658030777] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:07,495 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:07,495 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:48:07,495 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1791935025] [2023-11-19 07:48:07,495 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:07,497 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:07,497 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:07,497 INFO L85 PathProgramCache]: Analyzing trace with hash -1233885689, now seen corresponding path program 2 times [2023-11-19 07:48:07,498 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:07,498 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2095231875] [2023-11-19 07:48:07,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:07,498 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:07,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:07,534 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:07,535 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:07,535 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2095231875] [2023-11-19 07:48:07,536 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2095231875] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:07,536 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:07,536 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:07,536 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1372972964] [2023-11-19 07:48:07,536 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:07,537 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:07,537 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:07,537 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:07,537 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:07,538 INFO L87 Difference]: Start difference. First operand 2418 states and 3442 transitions. cyclomatic complexity: 1028 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:07,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:07,624 INFO L93 Difference]: Finished difference Result 4405 states and 6239 transitions. [2023-11-19 07:48:07,624 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4405 states and 6239 transitions. [2023-11-19 07:48:07,654 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4304 [2023-11-19 07:48:07,691 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4405 states to 4405 states and 6239 transitions. [2023-11-19 07:48:07,691 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4405 [2023-11-19 07:48:07,698 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4405 [2023-11-19 07:48:07,698 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4405 states and 6239 transitions. [2023-11-19 07:48:07,704 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:07,705 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4405 states and 6239 transitions. [2023-11-19 07:48:07,710 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4405 states and 6239 transitions. [2023-11-19 07:48:07,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4405 to 4389. [2023-11-19 07:48:07,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4389 states, 4389 states have (on average 1.4178628389154706) internal successors, (6223), 4388 states have internal predecessors, (6223), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:07,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4389 states to 4389 states and 6223 transitions. [2023-11-19 07:48:07,863 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4389 states and 6223 transitions. [2023-11-19 07:48:07,866 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:07,866 INFO L428 stractBuchiCegarLoop]: Abstraction has 4389 states and 6223 transitions. [2023-11-19 07:48:07,867 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-19 07:48:07,867 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4389 states and 6223 transitions. [2023-11-19 07:48:07,884 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4288 [2023-11-19 07:48:07,884 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:07,884 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:07,885 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:07,885 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:07,886 INFO L748 eck$LassoCheckResult]: Stem: 23316#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 23317#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 23425#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23426#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23224#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 23225#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23516#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23169#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23170#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23309#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23195#L514 assume !(0 == ~M_E~0); 23196#L514-2 assume !(0 == ~T1_E~0); 23537#L519-1 assume !(0 == ~T2_E~0); 23155#L524-1 assume !(0 == ~T3_E~0); 23156#L529-1 assume !(0 == ~T4_E~0); 23282#L534-1 assume !(0 == ~E_M~0); 23482#L539-1 assume !(0 == ~E_1~0); 23483#L544-1 assume !(0 == ~E_2~0); 23514#L549-1 assume !(0 == ~E_3~0); 23515#L554-1 assume !(0 == ~E_4~0); 23150#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23151#L250 assume !(1 == ~m_pc~0); 23380#L250-2 is_master_triggered_~__retres1~0#1 := 0; 23518#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23296#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 23297#L637 assume !(0 != activate_threads_~tmp~1#1); 23157#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23158#L269 assume !(1 == ~t1_pc~0); 23094#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23277#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23597#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 23538#L645 assume !(0 != activate_threads_~tmp___0~0#1); 23345#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23346#L288 assume !(1 == ~t2_pc~0); 23340#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23341#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23431#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23432#L653 assume !(0 != activate_threads_~tmp___1~0#1); 23477#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23369#L307 assume !(1 == ~t3_pc~0); 23299#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 23300#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23097#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 23098#L661 assume !(0 != activate_threads_~tmp___2~0#1); 23314#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23315#L326 assume !(1 == ~t4_pc~0); 23109#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 23110#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23199#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 23200#L669 assume !(0 != activate_threads_~tmp___3~0#1); 23478#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23479#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 23519#L572-2 assume !(1 == ~T1_E~0); 23165#L577-1 assume !(1 == ~T2_E~0); 23166#L582-1 assume !(1 == ~T3_E~0); 23461#L587-1 assume !(1 == ~T4_E~0); 23470#L592-1 assume !(1 == ~E_M~0); 23101#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 23102#L602-1 assume !(1 == ~E_2~0); 23337#L607-1 assume !(1 == ~E_3~0); 23338#L612-1 assume !(1 == ~E_4~0); 23280#L617-1 assume { :end_inline_reset_delta_events } true; 23281#L803-2 [2023-11-19 07:48:07,886 INFO L750 eck$LassoCheckResult]: Loop: 23281#L803-2 assume !false; 25429#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25427#L489-1 assume !false; 25425#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 25368#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 25362#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 25359#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 25356#L428 assume !(0 != eval_~tmp~0#1); 25357#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26662#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26661#L514-3 assume !(0 == ~M_E~0); 26660#L514-5 assume !(0 == ~T1_E~0); 26659#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26658#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26657#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26656#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26655#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26653#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26651#L549-3 assume !(0 == ~E_3~0); 26649#L554-3 assume !(0 == ~E_4~0); 26647#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26645#L250-18 assume !(1 == ~m_pc~0); 26643#L250-20 is_master_triggered_~__retres1~0#1 := 0; 26640#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26638#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 26636#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26634#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26632#L269-18 assume !(1 == ~t1_pc~0); 26628#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 26626#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26624#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26622#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 26620#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23288#L288-18 assume !(1 == ~t2_pc~0); 23289#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 26491#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26489#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 26487#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26485#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26483#L307-18 assume 1 == ~t3_pc~0; 26480#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26478#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26476#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 23246#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23247#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23494#L326-18 assume !(1 == ~t4_pc~0); 23495#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 26687#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26685#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 23086#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23087#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23567#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 23262#L572-5 assume !(1 == ~T1_E~0); 23263#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23148#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23149#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23400#L592-3 assume !(1 == ~E_M~0); 23401#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23324#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23325#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23274#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23275#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 23331#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 23293#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 23312#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 23367#L822 assume !(0 == start_simulation_~tmp~3#1); 23368#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 23491#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 23411#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 23143#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 23118#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23119#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23409#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 23536#L835 assume !(0 != start_simulation_~tmp___0~1#1); 23281#L803-2 [2023-11-19 07:48:07,886 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:07,887 INFO L85 PathProgramCache]: Analyzing trace with hash 843496709, now seen corresponding path program 1 times [2023-11-19 07:48:07,887 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:07,887 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1779668363] [2023-11-19 07:48:07,887 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:07,887 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:07,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:07,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:07,935 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:07,935 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1779668363] [2023-11-19 07:48:07,935 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1779668363] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:07,936 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:07,936 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:48:07,936 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1804167884] [2023-11-19 07:48:07,936 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:07,936 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:07,937 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:07,937 INFO L85 PathProgramCache]: Analyzing trace with hash -781202935, now seen corresponding path program 1 times [2023-11-19 07:48:07,937 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:07,937 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1967253631] [2023-11-19 07:48:07,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:07,937 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:07,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:07,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:07,975 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:07,975 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1967253631] [2023-11-19 07:48:07,975 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1967253631] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:07,975 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:07,976 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:07,976 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1547083174] [2023-11-19 07:48:07,976 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:07,976 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:07,976 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:07,977 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:07,977 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:07,978 INFO L87 Difference]: Start difference. First operand 4389 states and 6223 transitions. cyclomatic complexity: 1842 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:08,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:08,048 INFO L93 Difference]: Finished difference Result 6576 states and 9309 transitions. [2023-11-19 07:48:08,049 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6576 states and 9309 transitions. [2023-11-19 07:48:08,090 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6472 [2023-11-19 07:48:08,146 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6576 states to 6576 states and 9309 transitions. [2023-11-19 07:48:08,146 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6576 [2023-11-19 07:48:08,154 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6576 [2023-11-19 07:48:08,155 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6576 states and 9309 transitions. [2023-11-19 07:48:08,165 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:08,165 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6576 states and 9309 transitions. [2023-11-19 07:48:08,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6576 states and 9309 transitions. [2023-11-19 07:48:08,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6576 to 4767. [2023-11-19 07:48:08,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4767 states, 4767 states have (on average 1.4147262429200755) internal successors, (6744), 4766 states have internal predecessors, (6744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:08,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4767 states to 4767 states and 6744 transitions. [2023-11-19 07:48:08,451 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4767 states and 6744 transitions. [2023-11-19 07:48:08,452 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:08,452 INFO L428 stractBuchiCegarLoop]: Abstraction has 4767 states and 6744 transitions. [2023-11-19 07:48:08,453 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-19 07:48:08,453 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4767 states and 6744 transitions. [2023-11-19 07:48:08,481 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4676 [2023-11-19 07:48:08,481 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:08,481 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:08,483 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:08,483 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:08,484 INFO L748 eck$LassoCheckResult]: Stem: 34288#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 34289#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 34394#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34395#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34194#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 34195#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34477#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34138#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34139#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34278#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34167#L514 assume !(0 == ~M_E~0); 34168#L514-2 assume !(0 == ~T1_E~0); 34497#L519-1 assume !(0 == ~T2_E~0); 34126#L524-1 assume !(0 == ~T3_E~0); 34127#L529-1 assume !(0 == ~T4_E~0); 34252#L534-1 assume !(0 == ~E_M~0); 34446#L539-1 assume !(0 == ~E_1~0); 34447#L544-1 assume !(0 == ~E_2~0); 34474#L549-1 assume !(0 == ~E_3~0); 34475#L554-1 assume !(0 == ~E_4~0); 34121#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34122#L250 assume !(1 == ~m_pc~0); 34351#L250-2 is_master_triggered_~__retres1~0#1 := 0; 34478#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34267#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 34268#L637 assume !(0 != activate_threads_~tmp~1#1); 34128#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34129#L269 assume !(1 == ~t1_pc~0); 34066#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34247#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34556#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 34498#L645 assume !(0 != activate_threads_~tmp___0~0#1); 34318#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34319#L288 assume !(1 == ~t2_pc~0); 34312#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34313#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34401#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 34402#L653 assume !(0 != activate_threads_~tmp___1~0#1); 34440#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34341#L307 assume !(1 == ~t3_pc~0); 34270#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34271#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34069#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 34070#L661 assume !(0 != activate_threads_~tmp___2~0#1); 34286#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34287#L326 assume !(1 == ~t4_pc~0); 34081#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 34082#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34169#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 34170#L669 assume !(0 != activate_threads_~tmp___3~0#1); 34443#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34444#L572 assume !(1 == ~M_E~0); 34479#L572-2 assume !(1 == ~T1_E~0); 34134#L577-1 assume !(1 == ~T2_E~0); 34135#L582-1 assume !(1 == ~T3_E~0); 34425#L587-1 assume !(1 == ~T4_E~0); 34434#L592-1 assume !(1 == ~E_M~0); 34075#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 34076#L602-1 assume !(1 == ~E_2~0); 34309#L607-1 assume !(1 == ~E_3~0); 34310#L612-1 assume !(1 == ~E_4~0); 34250#L617-1 assume { :end_inline_reset_delta_events } true; 34251#L803-2 [2023-11-19 07:48:08,484 INFO L750 eck$LassoCheckResult]: Loop: 34251#L803-2 assume !false; 38294#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 38293#L489-1 assume !false; 38291#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 38289#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 38283#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 38281#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 38278#L428 assume !(0 != eval_~tmp~0#1); 38276#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38274#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38272#L514-3 assume !(0 == ~M_E~0); 38270#L514-5 assume !(0 == ~T1_E~0); 38267#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38265#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38263#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38259#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 38255#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 38251#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38244#L549-3 assume !(0 == ~E_3~0); 38240#L554-3 assume !(0 == ~E_4~0); 38236#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38235#L250-18 assume !(1 == ~m_pc~0); 38234#L250-20 is_master_triggered_~__retres1~0#1 := 0; 38233#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38231#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 38229#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38228#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38227#L269-18 assume !(1 == ~t1_pc~0); 38225#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 38223#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38221#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 38220#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 38218#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38216#L288-18 assume !(1 == ~t2_pc~0); 35588#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 38212#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38210#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 38208#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38196#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38190#L307-18 assume 1 == ~t3_pc~0; 38183#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38175#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38174#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 38173#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38170#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38168#L326-18 assume !(1 == ~t4_pc~0); 38166#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 38164#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38162#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 38152#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38143#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38131#L572-3 assume !(1 == ~M_E~0); 35843#L572-5 assume !(1 == ~T1_E~0); 38116#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38109#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38089#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38080#L592-3 assume !(1 == ~E_M~0); 38079#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38078#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38077#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38076#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38075#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 38074#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 38069#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 38068#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 37636#L822 assume !(0 == start_simulation_~tmp~3#1); 37637#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 38309#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 38304#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 38302#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 38301#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38300#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38299#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 38298#L835 assume !(0 != start_simulation_~tmp___0~1#1); 34251#L803-2 [2023-11-19 07:48:08,485 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:08,485 INFO L85 PathProgramCache]: Analyzing trace with hash 1544561287, now seen corresponding path program 1 times [2023-11-19 07:48:08,485 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:08,486 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1240328391] [2023-11-19 07:48:08,486 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:08,488 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:08,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:08,557 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:08,558 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:08,558 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1240328391] [2023-11-19 07:48:08,558 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1240328391] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:08,561 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:08,561 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:08,561 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [329943952] [2023-11-19 07:48:08,561 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:08,562 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:08,562 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:08,562 INFO L85 PathProgramCache]: Analyzing trace with hash 1708326027, now seen corresponding path program 1 times [2023-11-19 07:48:08,562 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:08,562 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387109096] [2023-11-19 07:48:08,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:08,563 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:08,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:08,606 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:08,606 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:08,606 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [387109096] [2023-11-19 07:48:08,606 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [387109096] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:08,606 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:08,607 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:08,607 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [425312917] [2023-11-19 07:48:08,607 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:08,607 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:08,607 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:08,608 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:48:08,608 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:48:08,608 INFO L87 Difference]: Start difference. First operand 4767 states and 6744 transitions. cyclomatic complexity: 1981 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:08,773 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:08,773 INFO L93 Difference]: Finished difference Result 6515 states and 9053 transitions. [2023-11-19 07:48:08,773 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6515 states and 9053 transitions. [2023-11-19 07:48:08,907 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6330 [2023-11-19 07:48:08,949 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6515 states to 6515 states and 9053 transitions. [2023-11-19 07:48:08,950 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6515 [2023-11-19 07:48:08,958 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6515 [2023-11-19 07:48:08,958 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6515 states and 9053 transitions. [2023-11-19 07:48:08,968 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:08,969 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6515 states and 9053 transitions. [2023-11-19 07:48:08,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6515 states and 9053 transitions. [2023-11-19 07:48:09,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6515 to 5354. [2023-11-19 07:48:09,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5354 states, 5354 states have (on average 1.3970862906238326) internal successors, (7480), 5353 states have internal predecessors, (7480), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:09,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5354 states to 5354 states and 7480 transitions. [2023-11-19 07:48:09,106 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5354 states and 7480 transitions. [2023-11-19 07:48:09,106 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:48:09,107 INFO L428 stractBuchiCegarLoop]: Abstraction has 5354 states and 7480 transitions. [2023-11-19 07:48:09,107 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-19 07:48:09,107 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5354 states and 7480 transitions. [2023-11-19 07:48:09,136 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5220 [2023-11-19 07:48:09,136 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:09,136 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:09,138 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:09,138 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:09,139 INFO L748 eck$LassoCheckResult]: Stem: 45587#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 45588#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 45697#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45698#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45491#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 45492#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45787#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45434#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45435#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45578#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45463#L514 assume !(0 == ~M_E~0); 45464#L514-2 assume !(0 == ~T1_E~0); 45815#L519-1 assume !(0 == ~T2_E~0); 45420#L524-1 assume !(0 == ~T3_E~0); 45421#L529-1 assume !(0 == ~T4_E~0); 45550#L534-1 assume !(0 == ~E_M~0); 45755#L539-1 assume 0 == ~E_1~0;~E_1~0 := 1; 45756#L544-1 assume !(0 == ~E_2~0); 45785#L549-1 assume !(0 == ~E_3~0); 45786#L554-1 assume !(0 == ~E_4~0); 45415#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45416#L250 assume !(1 == ~m_pc~0); 45789#L250-2 is_master_triggered_~__retres1~0#1 := 0; 45790#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45921#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 45920#L637 assume !(0 != activate_threads_~tmp~1#1); 45919#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45446#L269 assume !(1 == ~t1_pc~0); 45447#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 45923#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45922#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 45915#L645 assume !(0 != activate_threads_~tmp___0~0#1); 45914#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45913#L288 assume !(1 == ~t2_pc~0); 45912#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 45911#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45910#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 45909#L653 assume !(0 != activate_threads_~tmp___1~0#1); 45908#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45907#L307 assume !(1 == ~t3_pc~0); 45905#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 45904#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45903#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 45902#L661 assume !(0 != activate_threads_~tmp___2~0#1); 45901#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45900#L326 assume !(1 == ~t4_pc~0); 45899#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 45898#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45897#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 45896#L669 assume !(0 != activate_threads_~tmp___3~0#1); 45895#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45894#L572 assume !(1 == ~M_E~0); 45893#L572-2 assume !(1 == ~T1_E~0); 45892#L577-1 assume !(1 == ~T2_E~0); 45891#L582-1 assume !(1 == ~T3_E~0); 45890#L587-1 assume !(1 == ~T4_E~0); 45889#L592-1 assume !(1 == ~E_M~0); 45888#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 45366#L602-1 assume !(1 == ~E_2~0); 45607#L607-1 assume !(1 == ~E_3~0); 45608#L612-1 assume !(1 == ~E_4~0); 45548#L617-1 assume { :end_inline_reset_delta_events } true; 45549#L803-2 [2023-11-19 07:48:09,139 INFO L750 eck$LassoCheckResult]: Loop: 45549#L803-2 assume !false; 50335#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 50332#L489-1 assume !false; 50298#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 50296#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 50289#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 50286#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 50261#L428 assume !(0 != eval_~tmp~0#1); 50262#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50640#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50638#L514-3 assume !(0 == ~M_E~0); 50636#L514-5 assume !(0 == ~T1_E~0); 50630#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50628#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45517#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45518#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45354#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45355#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50683#L549-3 assume !(0 == ~E_3~0); 50682#L554-3 assume !(0 == ~E_4~0); 50681#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50680#L250-18 assume !(1 == ~m_pc~0); 50679#L250-20 is_master_triggered_~__retres1~0#1 := 0; 50678#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50677#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 50676#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50596#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45397#L269-18 assume 1 == ~t1_pc~0; 45398#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50656#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50667#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 50664#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45781#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45559#L288-18 assume !(1 == ~t2_pc~0); 45560#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 45363#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45364#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 50585#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50584#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45804#L307-18 assume 1 == ~t3_pc~0; 45609#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 45501#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45577#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 50580#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50579#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45768#L326-18 assume !(1 == ~t4_pc~0); 45769#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 45776#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45629#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 45630#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45848#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45849#L572-3 assume !(1 == ~M_E~0); 45531#L572-5 assume !(1 == ~T1_E~0); 45532#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 45413#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45414#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50658#L592-3 assume !(1 == ~E_M~0); 50433#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45593#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 45594#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45542#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45543#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 45600#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 45564#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 45581#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 45641#L822 assume !(0 == start_simulation_~tmp~3#1); 45642#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 50687#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 45872#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 45407#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 45408#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50516#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50515#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 50514#L835 assume !(0 != start_simulation_~tmp___0~1#1); 45549#L803-2 [2023-11-19 07:48:09,140 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:09,140 INFO L85 PathProgramCache]: Analyzing trace with hash -383711415, now seen corresponding path program 1 times [2023-11-19 07:48:09,140 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:09,140 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1363813183] [2023-11-19 07:48:09,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:09,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:09,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:09,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:09,192 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:09,192 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1363813183] [2023-11-19 07:48:09,192 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1363813183] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:09,192 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:09,192 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:09,193 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1698467459] [2023-11-19 07:48:09,193 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:09,194 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:09,194 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:09,195 INFO L85 PathProgramCache]: Analyzing trace with hash 204194184, now seen corresponding path program 1 times [2023-11-19 07:48:09,195 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:09,195 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1058869275] [2023-11-19 07:48:09,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:09,195 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:09,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:09,290 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:09,290 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:09,290 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1058869275] [2023-11-19 07:48:09,290 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1058869275] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:09,291 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:09,291 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:09,291 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [683370419] [2023-11-19 07:48:09,291 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:09,291 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:09,292 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:09,292 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:48:09,292 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:48:09,292 INFO L87 Difference]: Start difference. First operand 5354 states and 7480 transitions. cyclomatic complexity: 2130 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:09,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:09,408 INFO L93 Difference]: Finished difference Result 5466 states and 7587 transitions. [2023-11-19 07:48:09,408 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5466 states and 7587 transitions. [2023-11-19 07:48:09,444 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5362 [2023-11-19 07:48:09,471 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5466 states to 5466 states and 7587 transitions. [2023-11-19 07:48:09,471 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5466 [2023-11-19 07:48:09,478 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5466 [2023-11-19 07:48:09,479 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5466 states and 7587 transitions. [2023-11-19 07:48:09,487 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:09,487 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5466 states and 7587 transitions. [2023-11-19 07:48:09,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5466 states and 7587 transitions. [2023-11-19 07:48:09,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5466 to 4548. [2023-11-19 07:48:09,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4548 states, 4548 states have (on average 1.3916007036059808) internal successors, (6329), 4547 states have internal predecessors, (6329), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:09,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4548 states to 4548 states and 6329 transitions. [2023-11-19 07:48:09,595 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4548 states and 6329 transitions. [2023-11-19 07:48:09,596 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:48:09,596 INFO L428 stractBuchiCegarLoop]: Abstraction has 4548 states and 6329 transitions. [2023-11-19 07:48:09,597 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-19 07:48:09,597 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4548 states and 6329 transitions. [2023-11-19 07:48:09,660 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4460 [2023-11-19 07:48:09,660 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:09,660 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:09,661 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:09,662 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:09,662 INFO L748 eck$LassoCheckResult]: Stem: 56406#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 56407#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 56513#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 56514#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 56315#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 56316#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56596#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 56260#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56261#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56397#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 56286#L514 assume !(0 == ~M_E~0); 56287#L514-2 assume !(0 == ~T1_E~0); 56619#L519-1 assume !(0 == ~T2_E~0); 56246#L524-1 assume !(0 == ~T3_E~0); 56247#L529-1 assume !(0 == ~T4_E~0); 56372#L534-1 assume !(0 == ~E_M~0); 56568#L539-1 assume !(0 == ~E_1~0); 56569#L544-1 assume !(0 == ~E_2~0); 56594#L549-1 assume !(0 == ~E_3~0); 56595#L554-1 assume !(0 == ~E_4~0); 56241#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56242#L250 assume !(1 == ~m_pc~0); 56470#L250-2 is_master_triggered_~__retres1~0#1 := 0; 56598#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56386#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 56387#L637 assume !(0 != activate_threads_~tmp~1#1); 56248#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56249#L269 assume !(1 == ~t1_pc~0); 56187#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 56367#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56235#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 56236#L645 assume !(0 != activate_threads_~tmp___0~0#1); 56437#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56438#L288 assume !(1 == ~t2_pc~0); 56430#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 56431#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56520#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 56521#L653 assume !(0 != activate_threads_~tmp___1~0#1); 56563#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56461#L307 assume !(1 == ~t3_pc~0); 56389#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 56390#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56190#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 56191#L661 assume !(0 != activate_threads_~tmp___2~0#1); 56404#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56405#L326 assume !(1 == ~t4_pc~0); 56202#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 56203#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56290#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 56291#L669 assume !(0 != activate_threads_~tmp___3~0#1); 56565#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56566#L572 assume !(1 == ~M_E~0); 56599#L572-2 assume !(1 == ~T1_E~0); 56256#L577-1 assume !(1 == ~T2_E~0); 56257#L582-1 assume !(1 == ~T3_E~0); 56547#L587-1 assume !(1 == ~T4_E~0); 56556#L592-1 assume !(1 == ~E_M~0); 56194#L597-1 assume !(1 == ~E_1~0); 56195#L602-1 assume !(1 == ~E_2~0); 56427#L607-1 assume !(1 == ~E_3~0); 56428#L612-1 assume !(1 == ~E_4~0); 56370#L617-1 assume { :end_inline_reset_delta_events } true; 56371#L803-2 [2023-11-19 07:48:09,662 INFO L750 eck$LassoCheckResult]: Loop: 56371#L803-2 assume !false; 60516#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 56669#L489-1 assume !false; 60514#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 56462#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 56302#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 56366#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 56532#L428 assume !(0 != eval_~tmp~0#1); 56297#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 56298#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 56496#L514-3 assume !(0 == ~M_E~0); 56445#L514-5 assume !(0 == ~T1_E~0); 56446#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 56543#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 56340#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 56341#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 56184#L539-3 assume !(0 == ~E_1~0); 56185#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 56621#L549-3 assume !(0 == ~E_3~0); 56393#L554-3 assume !(0 == ~E_4~0); 56394#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56493#L250-18 assume !(1 == ~m_pc~0); 60661#L250-20 is_master_triggered_~__retres1~0#1 := 0; 56505#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56422#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 56423#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 56350#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56224#L269-18 assume !(1 == ~t1_pc~0); 56226#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 60606#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56646#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 56480#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 56481#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56378#L288-18 assume !(1 == ~t2_pc~0); 56379#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 60603#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60601#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 60599#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 60597#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60595#L307-18 assume 1 == ~t3_pc~0; 60592#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 60591#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60589#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 60587#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60585#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60583#L326-18 assume !(1 == ~t4_pc~0); 60581#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 60579#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60577#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 60575#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60573#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60567#L572-3 assume !(1 == ~M_E~0); 59591#L572-5 assume !(1 == ~T1_E~0); 60565#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 60564#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60563#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 60556#L592-3 assume !(1 == ~E_M~0); 60555#L597-3 assume !(1 == ~E_1~0); 60554#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 60553#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 60552#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 60551#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 60550#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 60545#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 60544#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 59810#L822 assume !(0 == start_simulation_~tmp~3#1); 56564#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 60536#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 60531#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 60529#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 60527#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60524#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60522#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 60520#L835 assume !(0 != start_simulation_~tmp___0~1#1); 56371#L803-2 [2023-11-19 07:48:09,663 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:09,663 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 1 times [2023-11-19 07:48:09,663 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:09,663 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950263451] [2023-11-19 07:48:09,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:09,664 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:09,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:09,677 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:09,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:09,727 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:09,728 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:09,728 INFO L85 PathProgramCache]: Analyzing trace with hash 553707211, now seen corresponding path program 1 times [2023-11-19 07:48:09,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:09,728 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1772035801] [2023-11-19 07:48:09,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:09,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:09,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:09,771 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:09,772 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:09,772 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1772035801] [2023-11-19 07:48:09,772 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1772035801] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:09,772 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:09,772 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:09,773 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [458500160] [2023-11-19 07:48:09,773 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:09,773 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:09,773 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:09,774 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:09,774 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:09,774 INFO L87 Difference]: Start difference. First operand 4548 states and 6329 transitions. cyclomatic complexity: 1785 Second operand has 3 states, 3 states have (on average 24.666666666666668) internal successors, (74), 3 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:09,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:09,885 INFO L93 Difference]: Finished difference Result 6973 states and 9594 transitions. [2023-11-19 07:48:09,886 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6973 states and 9594 transitions. [2023-11-19 07:48:09,932 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6834 [2023-11-19 07:48:10,021 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6973 states to 6973 states and 9594 transitions. [2023-11-19 07:48:10,021 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6973 [2023-11-19 07:48:10,030 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6973 [2023-11-19 07:48:10,030 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6973 states and 9594 transitions. [2023-11-19 07:48:10,055 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:10,056 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6973 states and 9594 transitions. [2023-11-19 07:48:10,083 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6973 states and 9594 transitions. [2023-11-19 07:48:10,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6973 to 6969. [2023-11-19 07:48:10,286 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6969 states, 6969 states have (on average 1.3760941311522457) internal successors, (9590), 6968 states have internal predecessors, (9590), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:10,316 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6969 states to 6969 states and 9590 transitions. [2023-11-19 07:48:10,317 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6969 states and 9590 transitions. [2023-11-19 07:48:10,317 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:10,318 INFO L428 stractBuchiCegarLoop]: Abstraction has 6969 states and 9590 transitions. [2023-11-19 07:48:10,318 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-19 07:48:10,318 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6969 states and 9590 transitions. [2023-11-19 07:48:10,354 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6830 [2023-11-19 07:48:10,354 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:10,354 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:10,356 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:10,356 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:10,357 INFO L748 eck$LassoCheckResult]: Stem: 67933#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 67934#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 68048#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 68049#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 67841#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 67842#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68147#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 67785#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 67786#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 67924#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 67814#L514 assume !(0 == ~M_E~0); 67815#L514-2 assume !(0 == ~T1_E~0); 68174#L519-1 assume !(0 == ~T2_E~0); 67773#L524-1 assume !(0 == ~T3_E~0); 67774#L529-1 assume !(0 == ~T4_E~0); 67898#L534-1 assume 0 == ~E_M~0;~E_M~0 := 1; 68179#L539-1 assume !(0 == ~E_1~0); 68142#L544-1 assume !(0 == ~E_2~0); 68143#L549-1 assume !(0 == ~E_3~0); 68184#L554-1 assume !(0 == ~E_4~0); 68185#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67996#L250 assume !(1 == ~m_pc~0); 67997#L250-2 is_master_triggered_~__retres1~0#1 := 0; 68175#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67912#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 67913#L637 assume !(0 != activate_threads_~tmp~1#1); 67775#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67776#L269 assume !(1 == ~t1_pc~0); 68259#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 68006#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67764#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 67765#L645 assume !(0 != activate_threads_~tmp___0~0#1); 67963#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 67964#L288 assume !(1 == ~t2_pc~0); 68077#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 68256#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68255#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 68254#L653 assume !(0 != activate_threads_~tmp___1~0#1); 68162#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68163#L307 assume !(1 == ~t3_pc~0); 68252#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 68044#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68045#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 68251#L661 assume !(0 != activate_threads_~tmp___2~0#1); 68250#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68249#L326 assume !(1 == ~t4_pc~0); 68248#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 68247#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68246#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 68245#L669 assume !(0 != activate_threads_~tmp___3~0#1); 68244#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68243#L572 assume !(1 == ~M_E~0); 68242#L572-2 assume !(1 == ~T1_E~0); 68241#L577-1 assume !(1 == ~T2_E~0); 68240#L582-1 assume !(1 == ~T3_E~0); 68239#L587-1 assume !(1 == ~T4_E~0); 68210#L592-1 assume 1 == ~E_M~0;~E_M~0 := 2; 67727#L597-1 assume !(1 == ~E_1~0); 67728#L602-1 assume !(1 == ~E_2~0); 67955#L607-1 assume !(1 == ~E_3~0); 67956#L612-1 assume !(1 == ~E_4~0); 67896#L617-1 assume { :end_inline_reset_delta_events } true; 67897#L803-2 [2023-11-19 07:48:10,357 INFO L750 eck$LassoCheckResult]: Loop: 67897#L803-2 assume !false; 69327#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 68671#L489-1 assume !false; 69326#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 69092#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 69086#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 69084#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 69082#L428 assume !(0 != eval_~tmp~0#1); 69083#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 69621#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 69619#L514-3 assume !(0 == ~M_E~0); 69617#L514-5 assume !(0 == ~T1_E~0); 69615#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 69613#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 69611#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 69608#L534-3 assume !(0 == ~E_M~0); 69606#L539-3 assume !(0 == ~E_1~0); 69604#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 69602#L549-3 assume !(0 == ~E_3~0); 69600#L554-3 assume !(0 == ~E_4~0); 69599#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69598#L250-18 assume !(1 == ~m_pc~0); 69597#L250-20 is_master_triggered_~__retres1~0#1 := 0; 69596#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69595#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 69593#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 69591#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69589#L269-18 assume !(1 == ~t1_pc~0); 69586#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 69584#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69582#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 69579#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 69577#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69575#L288-18 assume !(1 == ~t2_pc~0); 69464#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 69572#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69570#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 69568#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 69566#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69564#L307-18 assume 1 == ~t3_pc~0; 69561#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 69559#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69557#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 69554#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69552#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69550#L326-18 assume !(1 == ~t4_pc~0); 69548#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 69546#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69544#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 69542#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 69541#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69539#L572-3 assume !(1 == ~M_E~0); 69535#L572-5 assume !(1 == ~T1_E~0); 69533#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69531#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69529#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69375#L592-3 assume !(1 == ~E_M~0); 69373#L597-3 assume !(1 == ~E_1~0); 69371#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 69369#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69367#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 69365#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 69363#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 69357#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 69355#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 69353#L822 assume !(0 == start_simulation_~tmp~3#1); 69350#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 69344#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 69339#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 69337#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 69335#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69333#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69331#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 69329#L835 assume !(0 != start_simulation_~tmp___0~1#1); 67897#L803-2 [2023-11-19 07:48:10,358 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:10,358 INFO L85 PathProgramCache]: Analyzing trace with hash 1842238409, now seen corresponding path program 1 times [2023-11-19 07:48:10,358 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:10,358 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [113662814] [2023-11-19 07:48:10,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:10,359 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:10,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:10,440 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:10,441 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:10,441 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [113662814] [2023-11-19 07:48:10,441 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [113662814] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:10,441 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:10,441 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:10,442 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [703900890] [2023-11-19 07:48:10,442 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:10,442 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:10,443 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:10,443 INFO L85 PathProgramCache]: Analyzing trace with hash 1114406989, now seen corresponding path program 1 times [2023-11-19 07:48:10,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:10,443 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [50325421] [2023-11-19 07:48:10,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:10,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:10,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:10,519 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:10,520 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:10,520 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [50325421] [2023-11-19 07:48:10,520 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [50325421] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:10,520 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:10,520 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:48:10,521 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1134694063] [2023-11-19 07:48:10,521 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:10,521 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:10,521 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:10,522 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:48:10,522 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:48:10,522 INFO L87 Difference]: Start difference. First operand 6969 states and 9590 transitions. cyclomatic complexity: 2625 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:10,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:10,703 INFO L93 Difference]: Finished difference Result 9388 states and 12909 transitions. [2023-11-19 07:48:10,703 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9388 states and 12909 transitions. [2023-11-19 07:48:10,900 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 9055 [2023-11-19 07:48:10,944 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9388 states to 9388 states and 12909 transitions. [2023-11-19 07:48:10,944 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9388 [2023-11-19 07:48:10,956 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9388 [2023-11-19 07:48:10,957 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9388 states and 12909 transitions. [2023-11-19 07:48:10,968 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:10,968 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9388 states and 12909 transitions. [2023-11-19 07:48:10,982 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9388 states and 12909 transitions. [2023-11-19 07:48:11,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9388 to 6574. [2023-11-19 07:48:11,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6574 states, 6574 states have (on average 1.376635229692729) internal successors, (9050), 6573 states have internal predecessors, (9050), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:11,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6574 states to 6574 states and 9050 transitions. [2023-11-19 07:48:11,137 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6574 states and 9050 transitions. [2023-11-19 07:48:11,137 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:48:11,138 INFO L428 stractBuchiCegarLoop]: Abstraction has 6574 states and 9050 transitions. [2023-11-19 07:48:11,139 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-19 07:48:11,139 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6574 states and 9050 transitions. [2023-11-19 07:48:11,169 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6478 [2023-11-19 07:48:11,169 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:11,170 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:11,172 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:11,172 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:11,172 INFO L748 eck$LassoCheckResult]: Stem: 84304#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 84305#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 84415#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 84416#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 84208#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 84209#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 84505#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 84153#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 84154#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 84294#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 84182#L514 assume !(0 == ~M_E~0); 84183#L514-2 assume !(0 == ~T1_E~0); 84525#L519-1 assume !(0 == ~T2_E~0); 84141#L524-1 assume !(0 == ~T3_E~0); 84142#L529-1 assume !(0 == ~T4_E~0); 84267#L534-1 assume !(0 == ~E_M~0); 84471#L539-1 assume !(0 == ~E_1~0); 84472#L544-1 assume !(0 == ~E_2~0); 84501#L549-1 assume !(0 == ~E_3~0); 84502#L554-1 assume !(0 == ~E_4~0); 84136#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 84137#L250 assume !(1 == ~m_pc~0); 84373#L250-2 is_master_triggered_~__retres1~0#1 := 0; 84506#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84282#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 84283#L637 assume !(0 != activate_threads_~tmp~1#1); 84143#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84144#L269 assume !(1 == ~t1_pc~0); 84083#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 84262#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 84132#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 84133#L645 assume !(0 != activate_threads_~tmp___0~0#1); 84337#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84338#L288 assume !(1 == ~t2_pc~0); 84329#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 84330#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 84421#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 84422#L653 assume !(0 != activate_threads_~tmp___1~0#1); 84465#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 84361#L307 assume !(1 == ~t3_pc~0); 84285#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 84286#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 84086#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 84087#L661 assume !(0 != activate_threads_~tmp___2~0#1); 84302#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 84303#L326 assume !(1 == ~t4_pc~0); 84098#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 84099#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84184#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 84185#L669 assume !(0 != activate_threads_~tmp___3~0#1); 84468#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84469#L572 assume !(1 == ~M_E~0); 84507#L572-2 assume !(1 == ~T1_E~0); 84149#L577-1 assume !(1 == ~T2_E~0); 84150#L582-1 assume !(1 == ~T3_E~0); 84447#L587-1 assume !(1 == ~T4_E~0); 84457#L592-1 assume !(1 == ~E_M~0); 84096#L597-1 assume !(1 == ~E_1~0); 84097#L602-1 assume !(1 == ~E_2~0); 84326#L607-1 assume !(1 == ~E_3~0); 84327#L612-1 assume !(1 == ~E_4~0); 84265#L617-1 assume { :end_inline_reset_delta_events } true; 84266#L803-2 [2023-11-19 07:48:11,173 INFO L750 eck$LassoCheckResult]: Loop: 84266#L803-2 assume !false; 86089#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 86052#L489-1 assume !false; 86086#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 86084#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 86078#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 86076#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 86073#L428 assume !(0 != eval_~tmp~0#1); 86074#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 90268#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 90266#L514-3 assume !(0 == ~M_E~0); 90264#L514-5 assume !(0 == ~T1_E~0); 90261#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 90259#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 90257#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 90255#L534-3 assume !(0 == ~E_M~0); 90253#L539-3 assume !(0 == ~E_1~0); 90251#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 90249#L549-3 assume !(0 == ~E_3~0); 90247#L554-3 assume !(0 == ~E_4~0); 90245#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 90243#L250-18 assume !(1 == ~m_pc~0); 90241#L250-20 is_master_triggered_~__retres1~0#1 := 0; 90239#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 90238#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 90235#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 90234#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 90231#L269-18 assume !(1 == ~t1_pc~0); 90229#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 90227#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 90225#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 90223#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 90221#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86537#L288-18 assume !(1 == ~t2_pc~0); 86534#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 86531#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86528#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 86524#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 86521#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86518#L307-18 assume 1 == ~t3_pc~0; 86513#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 86510#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86112#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 86111#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 86110#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86109#L326-18 assume !(1 == ~t4_pc~0); 86103#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 86101#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86099#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 86097#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 86095#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86093#L572-3 assume !(1 == ~M_E~0); 85890#L572-5 assume !(1 == ~T1_E~0); 86091#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 86090#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 86088#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 86087#L592-3 assume !(1 == ~E_M~0); 86085#L597-3 assume !(1 == ~E_1~0); 86079#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 86077#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 86075#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 86072#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 86068#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 86060#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 86056#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 85624#L822 assume !(0 == start_simulation_~tmp~3#1); 85625#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 86107#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 86102#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 86100#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 86098#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 86096#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 86094#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 86092#L835 assume !(0 != start_simulation_~tmp___0~1#1); 84266#L803-2 [2023-11-19 07:48:11,174 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:11,174 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 2 times [2023-11-19 07:48:11,174 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:11,174 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1125972289] [2023-11-19 07:48:11,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:11,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:11,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:11,188 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:11,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:11,214 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:11,214 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:11,215 INFO L85 PathProgramCache]: Analyzing trace with hash 1114406989, now seen corresponding path program 2 times [2023-11-19 07:48:11,215 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:11,215 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [170533174] [2023-11-19 07:48:11,215 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:11,215 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:11,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:11,278 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:11,279 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:11,279 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [170533174] [2023-11-19 07:48:11,279 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [170533174] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:11,279 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:11,279 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:48:11,280 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [112429688] [2023-11-19 07:48:11,280 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:11,280 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:11,280 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:11,281 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 07:48:11,281 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 07:48:11,282 INFO L87 Difference]: Start difference. First operand 6574 states and 9050 transitions. cyclomatic complexity: 2480 Second operand has 5 states, 5 states have (on average 14.8) internal successors, (74), 5 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:11,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:11,471 INFO L93 Difference]: Finished difference Result 11708 states and 15936 transitions. [2023-11-19 07:48:11,471 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11708 states and 15936 transitions. [2023-11-19 07:48:11,545 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 11580 [2023-11-19 07:48:11,613 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11708 states to 11708 states and 15936 transitions. [2023-11-19 07:48:11,613 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11708 [2023-11-19 07:48:11,630 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11708 [2023-11-19 07:48:11,630 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11708 states and 15936 transitions. [2023-11-19 07:48:11,644 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:11,644 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11708 states and 15936 transitions. [2023-11-19 07:48:11,661 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11708 states and 15936 transitions. [2023-11-19 07:48:11,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11708 to 6646. [2023-11-19 07:48:11,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6646 states, 6646 states have (on average 1.3725549202527836) internal successors, (9122), 6645 states have internal predecessors, (9122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:11,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6646 states to 6646 states and 9122 transitions. [2023-11-19 07:48:11,901 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6646 states and 9122 transitions. [2023-11-19 07:48:11,902 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-19 07:48:11,903 INFO L428 stractBuchiCegarLoop]: Abstraction has 6646 states and 9122 transitions. [2023-11-19 07:48:11,903 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-19 07:48:11,903 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6646 states and 9122 transitions. [2023-11-19 07:48:11,934 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6550 [2023-11-19 07:48:11,935 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:11,935 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:11,936 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:11,937 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:11,937 INFO L748 eck$LassoCheckResult]: Stem: 102600#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 102601#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 102717#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 102718#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 102507#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 102508#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 102802#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 102453#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 102454#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 102592#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 102481#L514 assume !(0 == ~M_E~0); 102482#L514-2 assume !(0 == ~T1_E~0); 102823#L519-1 assume !(0 == ~T2_E~0); 102441#L524-1 assume !(0 == ~T3_E~0); 102442#L529-1 assume !(0 == ~T4_E~0); 102566#L534-1 assume !(0 == ~E_M~0); 102772#L539-1 assume !(0 == ~E_1~0); 102773#L544-1 assume !(0 == ~E_2~0); 102799#L549-1 assume !(0 == ~E_3~0); 102800#L554-1 assume !(0 == ~E_4~0); 102436#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 102437#L250 assume !(1 == ~m_pc~0); 102666#L250-2 is_master_triggered_~__retres1~0#1 := 0; 102803#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 102581#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 102582#L637 assume !(0 != activate_threads_~tmp~1#1); 102443#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 102444#L269 assume !(1 == ~t1_pc~0); 102382#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 102561#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 102432#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 102433#L645 assume !(0 != activate_threads_~tmp___0~0#1); 102630#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 102631#L288 assume !(1 == ~t2_pc~0); 102623#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 102624#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102722#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 102723#L653 assume !(0 != activate_threads_~tmp___1~0#1); 102765#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 102655#L307 assume !(1 == ~t3_pc~0); 102584#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 102585#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 102385#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 102386#L661 assume !(0 != activate_threads_~tmp___2~0#1); 102598#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 102599#L326 assume !(1 == ~t4_pc~0); 102397#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 102398#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 102483#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 102484#L669 assume !(0 != activate_threads_~tmp___3~0#1); 102768#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 102769#L572 assume !(1 == ~M_E~0); 102804#L572-2 assume !(1 == ~T1_E~0); 102449#L577-1 assume !(1 == ~T2_E~0); 102450#L582-1 assume !(1 == ~T3_E~0); 102749#L587-1 assume !(1 == ~T4_E~0); 102759#L592-1 assume !(1 == ~E_M~0); 102395#L597-1 assume !(1 == ~E_1~0); 102396#L602-1 assume !(1 == ~E_2~0); 102620#L607-1 assume !(1 == ~E_3~0); 102621#L612-1 assume !(1 == ~E_4~0); 102564#L617-1 assume { :end_inline_reset_delta_events } true; 102565#L803-2 [2023-11-19 07:48:11,937 INFO L750 eck$LassoCheckResult]: Loop: 102565#L803-2 assume !false; 104521#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 104520#L489-1 assume !false; 104519#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 104518#L386 assume !(0 == ~m_st~0); 104515#L390 assume !(0 == ~t1_st~0); 104516#L394 assume !(0 == ~t2_st~0); 104517#L398 assume !(0 == ~t3_st~0); 104513#L402 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 104514#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 103673#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 103674#L428 assume !(0 != eval_~tmp~0#1); 104510#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 104509#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 104508#L514-3 assume !(0 == ~M_E~0); 104507#L514-5 assume !(0 == ~T1_E~0); 104506#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 104505#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 104504#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 104503#L534-3 assume !(0 == ~E_M~0); 104502#L539-3 assume !(0 == ~E_1~0); 104501#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 104500#L549-3 assume !(0 == ~E_3~0); 104499#L554-3 assume !(0 == ~E_4~0); 104498#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 104497#L250-18 assume !(1 == ~m_pc~0); 104496#L250-20 is_master_triggered_~__retres1~0#1 := 0; 104495#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 104494#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 104493#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 104492#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 104491#L269-18 assume !(1 == ~t1_pc~0); 104489#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 104488#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 104487#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 104486#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 104485#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 104484#L288-18 assume !(1 == ~t2_pc~0); 104219#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 104483#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 104482#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 104481#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 104480#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 104479#L307-18 assume 1 == ~t3_pc~0; 104477#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 104476#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 104475#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 104474#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 104473#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 104472#L326-18 assume !(1 == ~t4_pc~0); 104471#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 104470#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 104469#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 104468#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 104467#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 104466#L572-3 assume !(1 == ~M_E~0); 104340#L572-5 assume !(1 == ~T1_E~0); 104465#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 104464#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 104463#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 104462#L592-3 assume !(1 == ~E_M~0); 104461#L597-3 assume !(1 == ~E_1~0); 104460#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 104459#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 104458#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 104457#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 104456#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 104451#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 104450#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 104448#L822 assume !(0 == start_simulation_~tmp~3#1); 104449#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 104546#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 104541#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 104539#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 104535#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 104533#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 104531#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 104528#L835 assume !(0 != start_simulation_~tmp___0~1#1); 102565#L803-2 [2023-11-19 07:48:11,938 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:11,938 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 3 times [2023-11-19 07:48:11,938 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:11,938 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [255354999] [2023-11-19 07:48:11,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:11,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:11,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:11,951 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:11,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:11,973 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:11,974 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:11,974 INFO L85 PathProgramCache]: Analyzing trace with hash 2571329, now seen corresponding path program 1 times [2023-11-19 07:48:11,975 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:11,975 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1391820415] [2023-11-19 07:48:11,975 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:11,975 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:11,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:12,068 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:12,069 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:12,069 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1391820415] [2023-11-19 07:48:12,069 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1391820415] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:12,069 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:12,069 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:48:12,069 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1972605761] [2023-11-19 07:48:12,070 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:12,070 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:12,070 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:12,070 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 07:48:12,071 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 07:48:12,071 INFO L87 Difference]: Start difference. First operand 6646 states and 9122 transitions. cyclomatic complexity: 2480 Second operand has 5 states, 5 states have (on average 15.6) internal successors, (78), 5 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:12,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:12,438 INFO L93 Difference]: Finished difference Result 10606 states and 14385 transitions. [2023-11-19 07:48:12,438 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10606 states and 14385 transitions. [2023-11-19 07:48:12,505 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10494 [2023-11-19 07:48:12,561 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10606 states to 10606 states and 14385 transitions. [2023-11-19 07:48:12,561 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10606 [2023-11-19 07:48:12,574 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10606 [2023-11-19 07:48:12,574 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10606 states and 14385 transitions. [2023-11-19 07:48:12,588 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:12,588 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10606 states and 14385 transitions. [2023-11-19 07:48:12,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10606 states and 14385 transitions. [2023-11-19 07:48:12,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10606 to 6766. [2023-11-19 07:48:12,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6766 states, 6766 states have (on average 1.3545669524091044) internal successors, (9165), 6765 states have internal predecessors, (9165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:12,785 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6766 states to 6766 states and 9165 transitions. [2023-11-19 07:48:12,785 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6766 states and 9165 transitions. [2023-11-19 07:48:12,786 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-19 07:48:12,786 INFO L428 stractBuchiCegarLoop]: Abstraction has 6766 states and 9165 transitions. [2023-11-19 07:48:12,786 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-19 07:48:12,787 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6766 states and 9165 transitions. [2023-11-19 07:48:12,821 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6670 [2023-11-19 07:48:12,821 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:12,822 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:12,824 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:12,824 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:12,824 INFO L748 eck$LassoCheckResult]: Stem: 119867#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 119868#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 119984#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 119985#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 119772#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 119773#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 120075#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 119717#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 119718#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 119856#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 119745#L514 assume !(0 == ~M_E~0); 119746#L514-2 assume !(0 == ~T1_E~0); 120098#L519-1 assume !(0 == ~T2_E~0); 119705#L524-1 assume !(0 == ~T3_E~0); 119706#L529-1 assume !(0 == ~T4_E~0); 119831#L534-1 assume !(0 == ~E_M~0); 120037#L539-1 assume !(0 == ~E_1~0); 120038#L544-1 assume !(0 == ~E_2~0); 120071#L549-1 assume !(0 == ~E_3~0); 120072#L554-1 assume !(0 == ~E_4~0); 119700#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 119701#L250 assume !(1 == ~m_pc~0); 119935#L250-2 is_master_triggered_~__retres1~0#1 := 0; 120076#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 119845#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 119846#L637 assume !(0 != activate_threads_~tmp~1#1); 119707#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 119708#L269 assume !(1 == ~t1_pc~0); 119646#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 119826#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 119696#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 119697#L645 assume !(0 != activate_threads_~tmp___0~0#1); 119898#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 119899#L288 assume !(1 == ~t2_pc~0); 119892#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 119893#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 119990#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 119991#L653 assume !(0 != activate_threads_~tmp___1~0#1); 120032#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 119923#L307 assume !(1 == ~t3_pc~0); 119848#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 119849#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 119649#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 119650#L661 assume !(0 != activate_threads_~tmp___2~0#1); 119865#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 119866#L326 assume !(1 == ~t4_pc~0); 119661#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 119662#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 119747#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 119748#L669 assume !(0 != activate_threads_~tmp___3~0#1); 120034#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 120035#L572 assume !(1 == ~M_E~0); 120077#L572-2 assume !(1 == ~T1_E~0); 119713#L577-1 assume !(1 == ~T2_E~0); 119714#L582-1 assume !(1 == ~T3_E~0); 120015#L587-1 assume !(1 == ~T4_E~0); 120025#L592-1 assume !(1 == ~E_M~0); 119659#L597-1 assume !(1 == ~E_1~0); 119660#L602-1 assume !(1 == ~E_2~0); 119889#L607-1 assume !(1 == ~E_3~0); 119890#L612-1 assume !(1 == ~E_4~0); 119829#L617-1 assume { :end_inline_reset_delta_events } true; 119830#L803-2 [2023-11-19 07:48:12,825 INFO L750 eck$LassoCheckResult]: Loop: 119830#L803-2 assume !false; 121029#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 121028#L489-1 assume !false; 121027#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 121026#L386 assume !(0 == ~m_st~0); 121023#L390 assume !(0 == ~t1_st~0); 121024#L394 assume !(0 == ~t2_st~0); 121025#L398 assume !(0 == ~t3_st~0); 121021#L402 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 121022#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 121009#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 121010#L428 assume !(0 != eval_~tmp~0#1); 121256#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 121254#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 121252#L514-3 assume !(0 == ~M_E~0); 121250#L514-5 assume !(0 == ~T1_E~0); 121247#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 121244#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 121241#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 121238#L534-3 assume !(0 == ~E_M~0); 121235#L539-3 assume !(0 == ~E_1~0); 121232#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 121229#L549-3 assume !(0 == ~E_3~0); 121226#L554-3 assume !(0 == ~E_4~0); 121223#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 121216#L250-18 assume !(1 == ~m_pc~0); 121213#L250-20 is_master_triggered_~__retres1~0#1 := 0; 121210#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 121206#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 121204#L637-18 assume !(0 != activate_threads_~tmp~1#1); 121201#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 121198#L269-18 assume !(1 == ~t1_pc~0); 121193#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 121190#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 121187#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 121184#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 121180#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 121177#L288-18 assume !(1 == ~t2_pc~0); 120724#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 121173#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 121170#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 121167#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 121164#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 121162#L307-18 assume 1 == ~t3_pc~0; 121157#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 121152#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 121148#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 121144#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 121140#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 121135#L326-18 assume !(1 == ~t4_pc~0); 121130#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 121126#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 121122#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 121118#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 121114#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 121110#L572-3 assume !(1 == ~M_E~0); 121105#L572-5 assume !(1 == ~T1_E~0); 121103#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 121100#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 121097#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 121093#L592-3 assume !(1 == ~E_M~0); 121090#L597-3 assume !(1 == ~E_1~0); 121087#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 121083#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 121080#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 121077#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 121074#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 121067#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 121064#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 121060#L822 assume !(0 == start_simulation_~tmp~3#1); 121057#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 121054#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 121049#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 121047#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 121043#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 121041#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 121039#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 121036#L835 assume !(0 != start_simulation_~tmp___0~1#1); 119830#L803-2 [2023-11-19 07:48:12,825 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:12,826 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 4 times [2023-11-19 07:48:12,826 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:12,826 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1094433238] [2023-11-19 07:48:12,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:12,827 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:12,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:12,842 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:12,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:12,877 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:12,878 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:12,878 INFO L85 PathProgramCache]: Analyzing trace with hash -12947389, now seen corresponding path program 1 times [2023-11-19 07:48:12,878 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:12,878 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1472847934] [2023-11-19 07:48:12,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:12,879 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:12,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:12,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:12,937 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:12,937 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1472847934] [2023-11-19 07:48:12,937 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1472847934] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:12,937 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:12,937 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:12,938 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1345552826] [2023-11-19 07:48:12,938 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:12,939 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:12,939 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:12,939 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:12,940 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:12,940 INFO L87 Difference]: Start difference. First operand 6766 states and 9165 transitions. cyclomatic complexity: 2403 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:13,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:13,118 INFO L93 Difference]: Finished difference Result 10648 states and 14247 transitions. [2023-11-19 07:48:13,118 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10648 states and 14247 transitions. [2023-11-19 07:48:13,170 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 10534 [2023-11-19 07:48:13,213 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10648 states to 10648 states and 14247 transitions. [2023-11-19 07:48:13,213 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10648 [2023-11-19 07:48:13,221 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10648 [2023-11-19 07:48:13,221 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10648 states and 14247 transitions. [2023-11-19 07:48:13,231 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:13,231 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10648 states and 14247 transitions. [2023-11-19 07:48:13,241 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10648 states and 14247 transitions. [2023-11-19 07:48:13,367 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10648 to 10392. [2023-11-19 07:48:13,387 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10392 states, 10392 states have (on average 1.3386258660508084) internal successors, (13911), 10391 states have internal predecessors, (13911), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:13,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10392 states to 10392 states and 13911 transitions. [2023-11-19 07:48:13,420 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10392 states and 13911 transitions. [2023-11-19 07:48:13,421 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:13,421 INFO L428 stractBuchiCegarLoop]: Abstraction has 10392 states and 13911 transitions. [2023-11-19 07:48:13,421 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-19 07:48:13,422 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10392 states and 13911 transitions. [2023-11-19 07:48:13,468 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 10278 [2023-11-19 07:48:13,468 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:13,468 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:13,469 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:13,469 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:13,470 INFO L748 eck$LassoCheckResult]: Stem: 137287#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 137288#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 137397#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 137398#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 137191#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 137192#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 137492#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 137137#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 137138#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 137276#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 137165#L514 assume !(0 == ~M_E~0); 137166#L514-2 assume !(0 == ~T1_E~0); 137511#L519-1 assume !(0 == ~T2_E~0); 137125#L524-1 assume !(0 == ~T3_E~0); 137126#L529-1 assume !(0 == ~T4_E~0); 137249#L534-1 assume !(0 == ~E_M~0); 137458#L539-1 assume !(0 == ~E_1~0); 137459#L544-1 assume !(0 == ~E_2~0); 137489#L549-1 assume !(0 == ~E_3~0); 137490#L554-1 assume !(0 == ~E_4~0); 137120#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 137121#L250 assume !(1 == ~m_pc~0); 137351#L250-2 is_master_triggered_~__retres1~0#1 := 0; 137493#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 137265#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 137266#L637 assume !(0 != activate_threads_~tmp~1#1); 137127#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 137128#L269 assume !(1 == ~t1_pc~0); 137066#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 137244#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 137116#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 137117#L645 assume !(0 != activate_threads_~tmp___0~0#1); 137316#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 137317#L288 assume !(1 == ~t2_pc~0); 137310#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 137311#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 137403#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 137404#L653 assume !(0 != activate_threads_~tmp___1~0#1); 137453#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 137339#L307 assume !(1 == ~t3_pc~0); 137268#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 137269#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 137069#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 137070#L661 assume !(0 != activate_threads_~tmp___2~0#1); 137285#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 137286#L326 assume !(1 == ~t4_pc~0); 137081#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 137082#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 137167#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 137168#L669 assume !(0 != activate_threads_~tmp___3~0#1); 137455#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 137456#L572 assume !(1 == ~M_E~0); 137494#L572-2 assume !(1 == ~T1_E~0); 137133#L577-1 assume !(1 == ~T2_E~0); 137134#L582-1 assume !(1 == ~T3_E~0); 137435#L587-1 assume !(1 == ~T4_E~0); 137445#L592-1 assume !(1 == ~E_M~0); 137079#L597-1 assume !(1 == ~E_1~0); 137080#L602-1 assume !(1 == ~E_2~0); 137307#L607-1 assume !(1 == ~E_3~0); 137308#L612-1 assume !(1 == ~E_4~0); 137247#L617-1 assume { :end_inline_reset_delta_events } true; 137248#L803-2 assume !false; 139112#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 139080#L489-1 [2023-11-19 07:48:13,470 INFO L750 eck$LassoCheckResult]: Loop: 139080#L489-1 assume !false; 139081#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 139375#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 139373#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 139370#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 139368#L428 assume 0 != eval_~tmp~0#1; 139366#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 139363#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 139361#L436-2 havoc eval_~tmp_ndt_1~0#1; 139351#L433-1 assume !(0 == ~t1_st~0); 139274#L447-1 assume !(0 == ~t2_st~0); 139270#L461-1 assume !(0 == ~t3_st~0); 139228#L475-1 assume !(0 == ~t4_st~0); 139080#L489-1 [2023-11-19 07:48:13,474 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:13,474 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 1 times [2023-11-19 07:48:13,474 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:13,475 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [710044993] [2023-11-19 07:48:13,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:13,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:13,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:13,488 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:13,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:13,518 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:13,519 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:13,519 INFO L85 PathProgramCache]: Analyzing trace with hash 1561748980, now seen corresponding path program 1 times [2023-11-19 07:48:13,520 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:13,520 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [327704022] [2023-11-19 07:48:13,520 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:13,520 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:13,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:13,526 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:13,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:13,531 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:13,534 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:13,534 INFO L85 PathProgramCache]: Analyzing trace with hash 1479320330, now seen corresponding path program 1 times [2023-11-19 07:48:13,534 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:13,535 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [38834924] [2023-11-19 07:48:13,535 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:13,535 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:13,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:13,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:13,584 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:13,584 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [38834924] [2023-11-19 07:48:13,584 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [38834924] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:13,585 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:13,585 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:13,585 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1170711650] [2023-11-19 07:48:13,585 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:13,699 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:13,699 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:13,699 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:13,699 INFO L87 Difference]: Start difference. First operand 10392 states and 13911 transitions. cyclomatic complexity: 3525 Second operand has 3 states, 3 states have (on average 25.666666666666668) internal successors, (77), 3 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:13,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:13,908 INFO L93 Difference]: Finished difference Result 16714 states and 22195 transitions. [2023-11-19 07:48:13,908 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16714 states and 22195 transitions. [2023-11-19 07:48:14,007 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 16492 [2023-11-19 07:48:14,086 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16714 states to 16714 states and 22195 transitions. [2023-11-19 07:48:14,087 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16714 [2023-11-19 07:48:14,099 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16714 [2023-11-19 07:48:14,100 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16714 states and 22195 transitions. [2023-11-19 07:48:14,116 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:14,116 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16714 states and 22195 transitions. [2023-11-19 07:48:14,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16714 states and 22195 transitions. [2023-11-19 07:48:14,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16714 to 16714. [2023-11-19 07:48:14,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16714 states, 16714 states have (on average 1.327928682541582) internal successors, (22195), 16713 states have internal predecessors, (22195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:14,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16714 states to 16714 states and 22195 transitions. [2023-11-19 07:48:14,385 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16714 states and 22195 transitions. [2023-11-19 07:48:14,386 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:14,386 INFO L428 stractBuchiCegarLoop]: Abstraction has 16714 states and 22195 transitions. [2023-11-19 07:48:14,386 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-19 07:48:14,386 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16714 states and 22195 transitions. [2023-11-19 07:48:14,553 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 16492 [2023-11-19 07:48:14,553 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:14,553 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:14,554 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:14,554 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:14,554 INFO L748 eck$LassoCheckResult]: Stem: 164403#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 164404#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 164515#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 164516#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 164305#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 164306#L353-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 164603#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 164251#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 164252#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 164686#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 165551#L514 assume !(0 == ~M_E~0); 165549#L514-2 assume !(0 == ~T1_E~0); 165547#L519-1 assume !(0 == ~T2_E~0); 165545#L524-1 assume !(0 == ~T3_E~0); 165543#L529-1 assume !(0 == ~T4_E~0); 164632#L534-1 assume !(0 == ~E_M~0); 164574#L539-1 assume !(0 == ~E_1~0); 164575#L544-1 assume !(0 == ~E_2~0); 164601#L549-1 assume !(0 == ~E_3~0); 164602#L554-1 assume !(0 == ~E_4~0); 165445#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 164470#L250 assume !(1 == ~m_pc~0); 164471#L250-2 is_master_triggered_~__retres1~0#1 := 0; 165424#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 165422#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 164606#L637 assume !(0 != activate_threads_~tmp~1#1); 164241#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 164242#L269 assume !(1 == ~t1_pc~0); 164180#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 164360#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 164228#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 164229#L645 assume !(0 != activate_threads_~tmp___0~0#1); 164435#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 164436#L288 assume !(1 == ~t2_pc~0); 164427#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 164428#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 164556#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 165407#L653 assume !(0 != activate_threads_~tmp___1~0#1); 165402#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 164457#L307 assume !(1 == ~t3_pc~0); 164458#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 165396#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 165395#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 165394#L661 assume !(0 != activate_threads_~tmp___2~0#1); 165393#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 165392#L326 assume !(1 == ~t4_pc~0); 165391#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 165390#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 165389#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 165388#L669 assume !(0 != activate_threads_~tmp___3~0#1); 165387#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 165386#L572 assume !(1 == ~M_E~0); 165385#L572-2 assume !(1 == ~T1_E~0); 165384#L577-1 assume !(1 == ~T2_E~0); 165383#L582-1 assume !(1 == ~T3_E~0); 165382#L587-1 assume !(1 == ~T4_E~0); 165381#L592-1 assume !(1 == ~E_M~0); 165380#L597-1 assume !(1 == ~E_1~0); 165379#L602-1 assume !(1 == ~E_2~0); 165378#L607-1 assume !(1 == ~E_3~0); 165377#L612-1 assume !(1 == ~E_4~0); 165376#L617-1 assume { :end_inline_reset_delta_events } true; 165375#L803-2 assume !false; 165373#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 165338#L489-1 [2023-11-19 07:48:14,555 INFO L750 eck$LassoCheckResult]: Loop: 165338#L489-1 assume !false; 165370#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 165367#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 165365#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 165363#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 165358#L428 assume 0 != eval_~tmp~0#1; 165355#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 165352#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 165350#L436-2 havoc eval_~tmp_ndt_1~0#1; 165348#L433-1 assume !(0 == ~t1_st~0); 165345#L447-1 assume !(0 == ~t2_st~0); 165341#L461-1 assume !(0 == ~t3_st~0); 165337#L475-1 assume !(0 == ~t4_st~0); 165338#L489-1 [2023-11-19 07:48:14,555 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:14,555 INFO L85 PathProgramCache]: Analyzing trace with hash 600428717, now seen corresponding path program 1 times [2023-11-19 07:48:14,555 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:14,555 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1999775913] [2023-11-19 07:48:14,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:14,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:14,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:14,585 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:14,585 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:14,585 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1999775913] [2023-11-19 07:48:14,586 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1999775913] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:14,586 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:14,586 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:14,586 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1629885713] [2023-11-19 07:48:14,586 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:14,586 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:14,587 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:14,587 INFO L85 PathProgramCache]: Analyzing trace with hash 1561748980, now seen corresponding path program 2 times [2023-11-19 07:48:14,587 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:14,587 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1648501056] [2023-11-19 07:48:14,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:14,588 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:14,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:14,593 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:14,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:14,598 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:14,706 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:14,707 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:14,707 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:14,707 INFO L87 Difference]: Start difference. First operand 16714 states and 22195 transitions. cyclomatic complexity: 5487 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:14,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:14,797 INFO L93 Difference]: Finished difference Result 16654 states and 22116 transitions. [2023-11-19 07:48:14,797 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16654 states and 22116 transitions. [2023-11-19 07:48:14,894 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 16492 [2023-11-19 07:48:14,971 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16654 states to 16654 states and 22116 transitions. [2023-11-19 07:48:14,972 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16654 [2023-11-19 07:48:14,985 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16654 [2023-11-19 07:48:14,986 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16654 states and 22116 transitions. [2023-11-19 07:48:15,002 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:15,003 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16654 states and 22116 transitions. [2023-11-19 07:48:15,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16654 states and 22116 transitions. [2023-11-19 07:48:15,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16654 to 16654. [2023-11-19 07:48:15,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16654 states, 16654 states have (on average 1.3279692566350427) internal successors, (22116), 16653 states have internal predecessors, (22116), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:15,460 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16654 states to 16654 states and 22116 transitions. [2023-11-19 07:48:15,463 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16654 states and 22116 transitions. [2023-11-19 07:48:15,463 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:15,464 INFO L428 stractBuchiCegarLoop]: Abstraction has 16654 states and 22116 transitions. [2023-11-19 07:48:15,464 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-19 07:48:15,464 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16654 states and 22116 transitions. [2023-11-19 07:48:15,533 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 16492 [2023-11-19 07:48:15,533 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:15,533 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:15,534 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:15,535 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:15,535 INFO L748 eck$LassoCheckResult]: Stem: 197777#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 197778#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 197887#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 197888#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 197683#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 197684#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 197973#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 197626#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 197627#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 197768#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 197652#L514 assume !(0 == ~M_E~0); 197653#L514-2 assume !(0 == ~T1_E~0); 197993#L519-1 assume !(0 == ~T2_E~0); 197614#L524-1 assume !(0 == ~T3_E~0); 197615#L529-1 assume !(0 == ~T4_E~0); 197741#L534-1 assume !(0 == ~E_M~0); 197944#L539-1 assume !(0 == ~E_1~0); 197945#L544-1 assume !(0 == ~E_2~0); 197971#L549-1 assume !(0 == ~E_3~0); 197972#L554-1 assume !(0 == ~E_4~0); 197609#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 197610#L250 assume !(1 == ~m_pc~0); 197843#L250-2 is_master_triggered_~__retres1~0#1 := 0; 197976#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 197756#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 197757#L637 assume !(0 != activate_threads_~tmp~1#1); 197616#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 197617#L269 assume !(1 == ~t1_pc~0); 197554#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 197736#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 197603#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 197604#L645 assume !(0 != activate_threads_~tmp___0~0#1); 197806#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 197807#L288 assume !(1 == ~t2_pc~0); 197800#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 197801#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 197893#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 197894#L653 assume !(0 != activate_threads_~tmp___1~0#1); 197939#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 197829#L307 assume !(1 == ~t3_pc~0); 197759#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 197760#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 197557#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 197558#L661 assume !(0 != activate_threads_~tmp___2~0#1); 197775#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 197776#L326 assume !(1 == ~t4_pc~0); 197569#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 197570#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 197656#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 197657#L669 assume !(0 != activate_threads_~tmp___3~0#1); 197941#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 197942#L572 assume !(1 == ~M_E~0); 197977#L572-2 assume !(1 == ~T1_E~0); 197622#L577-1 assume !(1 == ~T2_E~0); 197623#L582-1 assume !(1 == ~T3_E~0); 197923#L587-1 assume !(1 == ~T4_E~0); 197933#L592-1 assume !(1 == ~E_M~0); 197563#L597-1 assume !(1 == ~E_1~0); 197564#L602-1 assume !(1 == ~E_2~0); 197797#L607-1 assume !(1 == ~E_3~0); 197798#L612-1 assume !(1 == ~E_4~0); 197739#L617-1 assume { :end_inline_reset_delta_events } true; 197740#L803-2 assume !false; 198940#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 198935#L489-1 [2023-11-19 07:48:15,535 INFO L750 eck$LassoCheckResult]: Loop: 198935#L489-1 assume !false; 198930#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 198924#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 198918#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 198911#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 198904#L428 assume 0 != eval_~tmp~0#1; 198896#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 198891#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 198886#L436-2 havoc eval_~tmp_ndt_1~0#1; 198881#L433-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 198688#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 198872#L450-2 havoc eval_~tmp_ndt_2~0#1; 198864#L447-1 assume !(0 == ~t2_st~0); 198865#L461-1 assume !(0 == ~t3_st~0); 198942#L475-1 assume !(0 == ~t4_st~0); 198935#L489-1 [2023-11-19 07:48:15,536 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:15,536 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 2 times [2023-11-19 07:48:15,536 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:15,536 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1020305134] [2023-11-19 07:48:15,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:15,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:15,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:15,558 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:15,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:15,584 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:15,585 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:15,585 INFO L85 PathProgramCache]: Analyzing trace with hash 1594291277, now seen corresponding path program 1 times [2023-11-19 07:48:15,586 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:15,586 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [530201644] [2023-11-19 07:48:15,586 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:15,587 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:15,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:15,592 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:15,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:15,598 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:15,599 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:15,599 INFO L85 PathProgramCache]: Analyzing trace with hash -310230045, now seen corresponding path program 1 times [2023-11-19 07:48:15,599 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:15,599 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1887995085] [2023-11-19 07:48:15,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:15,600 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:15,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:15,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:15,668 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:15,668 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1887995085] [2023-11-19 07:48:15,669 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1887995085] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:15,669 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:15,669 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:15,669 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1873660799] [2023-11-19 07:48:15,670 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:15,769 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:15,770 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:15,770 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:15,771 INFO L87 Difference]: Start difference. First operand 16654 states and 22116 transitions. cyclomatic complexity: 5468 Second operand has 3 states, 3 states have (on average 26.333333333333332) internal successors, (79), 3 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:16,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:16,012 INFO L93 Difference]: Finished difference Result 30842 states and 40748 transitions. [2023-11-19 07:48:16,012 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30842 states and 40748 transitions. [2023-11-19 07:48:16,357 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 30584 [2023-11-19 07:48:16,500 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30842 states to 30842 states and 40748 transitions. [2023-11-19 07:48:16,500 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30842 [2023-11-19 07:48:16,521 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30842 [2023-11-19 07:48:16,521 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30842 states and 40748 transitions. [2023-11-19 07:48:16,546 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:16,546 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30842 states and 40748 transitions. [2023-11-19 07:48:16,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30842 states and 40748 transitions. [2023-11-19 07:48:16,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30842 to 30072. [2023-11-19 07:48:16,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30072 states, 30072 states have (on average 1.322093641926044) internal successors, (39758), 30071 states have internal predecessors, (39758), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:17,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30072 states to 30072 states and 39758 transitions. [2023-11-19 07:48:17,051 INFO L240 hiAutomatonCegarLoop]: Abstraction has 30072 states and 39758 transitions. [2023-11-19 07:48:17,052 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:17,052 INFO L428 stractBuchiCegarLoop]: Abstraction has 30072 states and 39758 transitions. [2023-11-19 07:48:17,052 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-19 07:48:17,052 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30072 states and 39758 transitions. [2023-11-19 07:48:17,335 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 29814 [2023-11-19 07:48:17,336 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:17,336 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:17,337 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:17,337 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:17,338 INFO L748 eck$LassoCheckResult]: Stem: 245284#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 245285#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 245396#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 245397#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 245186#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 245187#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 245486#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 245131#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 245132#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 245273#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 245157#L514 assume !(0 == ~M_E~0); 245158#L514-2 assume !(0 == ~T1_E~0); 245509#L519-1 assume !(0 == ~T2_E~0); 245117#L524-1 assume !(0 == ~T3_E~0); 245118#L529-1 assume !(0 == ~T4_E~0); 245246#L534-1 assume !(0 == ~E_M~0); 245454#L539-1 assume !(0 == ~E_1~0); 245455#L544-1 assume !(0 == ~E_2~0); 245484#L549-1 assume !(0 == ~E_3~0); 245485#L554-1 assume !(0 == ~E_4~0); 245112#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 245113#L250 assume !(1 == ~m_pc~0); 245349#L250-2 is_master_triggered_~__retres1~0#1 := 0; 245488#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 245261#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 245262#L637 assume !(0 != activate_threads_~tmp~1#1); 245119#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 245120#L269 assume !(1 == ~t1_pc~0); 245058#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 245241#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 245106#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 245107#L645 assume !(0 != activate_threads_~tmp___0~0#1); 245314#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 245315#L288 assume !(1 == ~t2_pc~0); 245306#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 245307#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 245402#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 245403#L653 assume !(0 != activate_threads_~tmp___1~0#1); 245447#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 245339#L307 assume !(1 == ~t3_pc~0); 245264#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 245265#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 245061#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 245062#L661 assume !(0 != activate_threads_~tmp___2~0#1); 245282#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 245283#L326 assume !(1 == ~t4_pc~0); 245073#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 245074#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 245161#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 245162#L669 assume !(0 != activate_threads_~tmp___3~0#1); 245450#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 245451#L572 assume !(1 == ~M_E~0); 245489#L572-2 assume !(1 == ~T1_E~0); 245127#L577-1 assume !(1 == ~T2_E~0); 245128#L582-1 assume !(1 == ~T3_E~0); 245431#L587-1 assume !(1 == ~T4_E~0); 245440#L592-1 assume !(1 == ~E_M~0); 245065#L597-1 assume !(1 == ~E_1~0); 245066#L602-1 assume !(1 == ~E_2~0); 245303#L607-1 assume !(1 == ~E_3~0); 245304#L612-1 assume !(1 == ~E_4~0); 245244#L617-1 assume { :end_inline_reset_delta_events } true; 245245#L803-2 assume !false; 260354#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 260353#L489-1 [2023-11-19 07:48:17,338 INFO L750 eck$LassoCheckResult]: Loop: 260353#L489-1 assume !false; 260352#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 260347#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 260345#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 260343#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 260341#L428 assume 0 != eval_~tmp~0#1; 260338#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 260335#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 260332#L436-2 havoc eval_~tmp_ndt_1~0#1; 260330#L433-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 259969#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 260328#L450-2 havoc eval_~tmp_ndt_2~0#1; 260367#L447-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 260363#L464 assume !(0 != eval_~tmp_ndt_3~0#1); 260362#L464-2 havoc eval_~tmp_ndt_3~0#1; 260359#L461-1 assume !(0 == ~t3_st~0); 260356#L475-1 assume !(0 == ~t4_st~0); 260353#L489-1 [2023-11-19 07:48:17,338 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:17,338 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 3 times [2023-11-19 07:48:17,338 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:17,339 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1138759792] [2023-11-19 07:48:17,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:17,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:17,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:17,351 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:17,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:17,367 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:17,367 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:17,367 INFO L85 PathProgramCache]: Analyzing trace with hash -1337685132, now seen corresponding path program 1 times [2023-11-19 07:48:17,367 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:17,368 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [372957531] [2023-11-19 07:48:17,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:17,368 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:17,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:17,372 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:17,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:17,376 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:17,377 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:17,377 INFO L85 PathProgramCache]: Analyzing trace with hash -1926607478, now seen corresponding path program 1 times [2023-11-19 07:48:17,377 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:17,377 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1355960940] [2023-11-19 07:48:17,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:17,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:17,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:17,420 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:17,420 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:17,421 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1355960940] [2023-11-19 07:48:17,421 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1355960940] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:17,421 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:17,421 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:17,421 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [446491493] [2023-11-19 07:48:17,421 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:17,509 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:17,510 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:17,510 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:17,510 INFO L87 Difference]: Start difference. First operand 30072 states and 39758 transitions. cyclomatic complexity: 9692 Second operand has 3 states, 3 states have (on average 27.0) internal successors, (81), 3 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:17,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:17,911 INFO L93 Difference]: Finished difference Result 52910 states and 69660 transitions. [2023-11-19 07:48:17,911 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52910 states and 69660 transitions. [2023-11-19 07:48:18,202 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 52460 [2023-11-19 07:48:18,429 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52910 states to 52910 states and 69660 transitions. [2023-11-19 07:48:18,429 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 52910 [2023-11-19 07:48:18,466 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 52910 [2023-11-19 07:48:18,466 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52910 states and 69660 transitions. [2023-11-19 07:48:18,537 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:18,537 INFO L218 hiAutomatonCegarLoop]: Abstraction has 52910 states and 69660 transitions. [2023-11-19 07:48:18,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52910 states and 69660 transitions. [2023-11-19 07:48:19,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52910 to 51062. [2023-11-19 07:48:19,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51062 states, 51062 states have (on average 1.3211390074811014) internal successors, (67460), 51061 states have internal predecessors, (67460), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:19,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51062 states to 51062 states and 67460 transitions. [2023-11-19 07:48:19,896 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51062 states and 67460 transitions. [2023-11-19 07:48:19,896 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:19,897 INFO L428 stractBuchiCegarLoop]: Abstraction has 51062 states and 67460 transitions. [2023-11-19 07:48:19,897 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-19 07:48:19,897 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51062 states and 67460 transitions. [2023-11-19 07:48:20,021 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 50612 [2023-11-19 07:48:20,021 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:20,021 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:20,022 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:20,022 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:20,023 INFO L748 eck$LassoCheckResult]: Stem: 328271#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 328272#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 328386#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 328387#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 328176#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 328177#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 328479#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 328120#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 328121#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 328262#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 328146#L514 assume !(0 == ~M_E~0); 328147#L514-2 assume !(0 == ~T1_E~0); 328505#L519-1 assume !(0 == ~T2_E~0); 328108#L524-1 assume !(0 == ~T3_E~0); 328109#L529-1 assume !(0 == ~T4_E~0); 328235#L534-1 assume !(0 == ~E_M~0); 328445#L539-1 assume !(0 == ~E_1~0); 328446#L544-1 assume !(0 == ~E_2~0); 328477#L549-1 assume !(0 == ~E_3~0); 328478#L554-1 assume !(0 == ~E_4~0); 328103#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 328104#L250 assume !(1 == ~m_pc~0); 328336#L250-2 is_master_triggered_~__retres1~0#1 := 0; 328482#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 328251#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 328252#L637 assume !(0 != activate_threads_~tmp~1#1); 328110#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 328111#L269 assume !(1 == ~t1_pc~0); 328048#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 328230#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 328097#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 328098#L645 assume !(0 != activate_threads_~tmp___0~0#1); 328302#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 328303#L288 assume !(1 == ~t2_pc~0); 328296#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 328297#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 328393#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 328394#L653 assume !(0 != activate_threads_~tmp___1~0#1); 328440#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 328324#L307 assume !(1 == ~t3_pc~0); 328254#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 328255#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 328051#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 328052#L661 assume !(0 != activate_threads_~tmp___2~0#1); 328269#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 328270#L326 assume !(1 == ~t4_pc~0); 328063#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 328064#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 328150#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 328151#L669 assume !(0 != activate_threads_~tmp___3~0#1); 328442#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 328443#L572 assume !(1 == ~M_E~0); 328483#L572-2 assume !(1 == ~T1_E~0); 328116#L577-1 assume !(1 == ~T2_E~0); 328117#L582-1 assume !(1 == ~T3_E~0); 328423#L587-1 assume !(1 == ~T4_E~0); 328433#L592-1 assume !(1 == ~E_M~0); 328055#L597-1 assume !(1 == ~E_1~0); 328056#L602-1 assume !(1 == ~E_2~0); 328293#L607-1 assume !(1 == ~E_3~0); 328294#L612-1 assume !(1 == ~E_4~0); 328233#L617-1 assume { :end_inline_reset_delta_events } true; 328234#L803-2 assume !false; 335924#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 335918#L489-1 [2023-11-19 07:48:20,023 INFO L750 eck$LassoCheckResult]: Loop: 335918#L489-1 assume !false; 335912#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 335907#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 335904#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 335896#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 335895#L428 assume 0 != eval_~tmp~0#1; 335894#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 335891#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 335889#L436-2 havoc eval_~tmp_ndt_1~0#1; 335887#L433-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 335703#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 335884#L450-2 havoc eval_~tmp_ndt_2~0#1; 334995#L447-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 334993#L464 assume !(0 != eval_~tmp_ndt_3~0#1); 334994#L464-2 havoc eval_~tmp_ndt_3~0#1; 335933#L461-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 335930#L478 assume !(0 != eval_~tmp_ndt_4~0#1); 335928#L478-2 havoc eval_~tmp_ndt_4~0#1; 335926#L475-1 assume !(0 == ~t4_st~0); 335918#L489-1 [2023-11-19 07:48:20,023 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:20,024 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 4 times [2023-11-19 07:48:20,024 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:20,024 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1861512061] [2023-11-19 07:48:20,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:20,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:20,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:20,036 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:20,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:20,064 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:20,065 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:20,065 INFO L85 PathProgramCache]: Analyzing trace with hash -1324933107, now seen corresponding path program 1 times [2023-11-19 07:48:20,065 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:20,067 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [99158340] [2023-11-19 07:48:20,067 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:20,068 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:20,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:20,072 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:20,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:20,076 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:20,077 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:20,077 INFO L85 PathProgramCache]: Analyzing trace with hash -343624541, now seen corresponding path program 1 times [2023-11-19 07:48:20,077 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:20,079 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1081404350] [2023-11-19 07:48:20,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:20,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:20,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:20,121 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:20,122 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:20,122 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1081404350] [2023-11-19 07:48:20,122 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1081404350] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:20,122 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:20,122 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:48:20,122 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [611387655] [2023-11-19 07:48:20,123 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:20,213 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:20,214 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:20,214 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:20,214 INFO L87 Difference]: Start difference. First operand 51062 states and 67460 transitions. cyclomatic complexity: 16404 Second operand has 3 states, 2 states have (on average 41.5) internal successors, (83), 3 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:20,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:20,437 INFO L93 Difference]: Finished difference Result 57552 states and 75754 transitions. [2023-11-19 07:48:20,437 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57552 states and 75754 transitions. [2023-11-19 07:48:20,926 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 56630 [2023-11-19 07:48:21,094 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57552 states to 57552 states and 75754 transitions. [2023-11-19 07:48:21,094 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 57552 [2023-11-19 07:48:21,130 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 57552 [2023-11-19 07:48:21,130 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57552 states and 75754 transitions. [2023-11-19 07:48:21,185 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:21,186 INFO L218 hiAutomatonCegarLoop]: Abstraction has 57552 states and 75754 transitions. [2023-11-19 07:48:21,220 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57552 states and 75754 transitions. [2023-11-19 07:48:21,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57552 to 57104. [2023-11-19 07:48:22,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57104 states, 57104 states have (on average 1.3187517511908098) internal successors, (75306), 57103 states have internal predecessors, (75306), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:22,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57104 states to 57104 states and 75306 transitions. [2023-11-19 07:48:22,196 INFO L240 hiAutomatonCegarLoop]: Abstraction has 57104 states and 75306 transitions. [2023-11-19 07:48:22,197 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:22,197 INFO L428 stractBuchiCegarLoop]: Abstraction has 57104 states and 75306 transitions. [2023-11-19 07:48:22,197 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-19 07:48:22,198 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 57104 states and 75306 transitions. [2023-11-19 07:48:22,415 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 56182 [2023-11-19 07:48:22,415 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:22,415 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:22,416 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:22,416 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:22,417 INFO L748 eck$LassoCheckResult]: Stem: 436897#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 436898#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 437017#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 437018#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 436798#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 436799#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 437120#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 436743#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 436744#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 436886#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 436771#L514 assume !(0 == ~M_E~0); 436772#L514-2 assume !(0 == ~T1_E~0); 437147#L519-1 assume !(0 == ~T2_E~0); 436731#L524-1 assume !(0 == ~T3_E~0); 436732#L529-1 assume !(0 == ~T4_E~0); 436859#L534-1 assume !(0 == ~E_M~0); 437082#L539-1 assume !(0 == ~E_1~0); 437083#L544-1 assume !(0 == ~E_2~0); 437117#L549-1 assume !(0 == ~E_3~0); 437118#L554-1 assume !(0 == ~E_4~0); 436726#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 436727#L250 assume !(1 == ~m_pc~0); 436971#L250-2 is_master_triggered_~__retres1~0#1 := 0; 437121#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 436874#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 436875#L637 assume !(0 != activate_threads_~tmp~1#1); 436733#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 436734#L269 assume !(1 == ~t1_pc~0); 436671#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 436854#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 436722#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 436723#L645 assume !(0 != activate_threads_~tmp___0~0#1); 436930#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 436931#L288 assume !(1 == ~t2_pc~0); 436922#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 436923#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 437024#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 437025#L653 assume !(0 != activate_threads_~tmp___1~0#1); 437075#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 436953#L307 assume !(1 == ~t3_pc~0); 436877#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 436878#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 436674#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 436675#L661 assume !(0 != activate_threads_~tmp___2~0#1); 436895#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 436896#L326 assume !(1 == ~t4_pc~0); 436686#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 436687#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 436773#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 436774#L669 assume !(0 != activate_threads_~tmp___3~0#1); 437078#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 437079#L572 assume !(1 == ~M_E~0); 437122#L572-2 assume !(1 == ~T1_E~0); 436739#L577-1 assume !(1 == ~T2_E~0); 436740#L582-1 assume !(1 == ~T3_E~0); 437058#L587-1 assume !(1 == ~T4_E~0); 437068#L592-1 assume !(1 == ~E_M~0); 436684#L597-1 assume !(1 == ~E_1~0); 436685#L602-1 assume !(1 == ~E_2~0); 436919#L607-1 assume !(1 == ~E_3~0); 436920#L612-1 assume !(1 == ~E_4~0); 436857#L617-1 assume { :end_inline_reset_delta_events } true; 436858#L803-2 assume !false; 446425#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 446420#L489-1 [2023-11-19 07:48:22,417 INFO L750 eck$LassoCheckResult]: Loop: 446420#L489-1 assume !false; 446416#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 446412#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 446406#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 446402#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 446398#L428 assume 0 != eval_~tmp~0#1; 446391#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 446386#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 446382#L436-2 havoc eval_~tmp_ndt_1~0#1; 446327#L433-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 446212#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 446326#L450-2 havoc eval_~tmp_ndt_2~0#1; 446450#L447-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 443426#L464 assume !(0 != eval_~tmp_ndt_3~0#1); 446443#L464-2 havoc eval_~tmp_ndt_3~0#1; 446440#L461-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 446310#L478 assume !(0 != eval_~tmp_ndt_4~0#1); 446435#L478-2 havoc eval_~tmp_ndt_4~0#1; 446432#L475-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 446429#L492 assume !(0 != eval_~tmp_ndt_5~0#1); 446426#L492-2 havoc eval_~tmp_ndt_5~0#1; 446420#L489-1 [2023-11-19 07:48:22,418 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:22,418 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 5 times [2023-11-19 07:48:22,418 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:22,418 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1141731089] [2023-11-19 07:48:22,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:22,419 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:22,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:22,431 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:22,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:22,450 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:22,451 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:22,451 INFO L85 PathProgramCache]: Analyzing trace with hash -1950508812, now seen corresponding path program 1 times [2023-11-19 07:48:22,451 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:22,451 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1104841478] [2023-11-19 07:48:22,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:22,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:22,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:22,456 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:22,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:22,461 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:22,461 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:22,461 INFO L85 PathProgramCache]: Analyzing trace with hash 489185290, now seen corresponding path program 1 times [2023-11-19 07:48:22,462 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:22,462 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [753035327] [2023-11-19 07:48:22,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:22,462 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:22,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:22,474 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:22,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:22,499 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:24,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:24,342 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:24,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:24,561 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 19.11 07:48:24 BoogieIcfgContainer [2023-11-19 07:48:24,562 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-19 07:48:24,562 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-19 07:48:24,562 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-19 07:48:24,563 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-19 07:48:24,563 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:48:03" (3/4) ... [2023-11-19 07:48:24,566 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-19 07:48:24,659 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a7be7761-ee72-4f7f-80ea-03dd6347eac3/bin/uautomizer-verify-uCwYo4JHxu/witness.graphml [2023-11-19 07:48:24,659 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-19 07:48:24,660 INFO L158 Benchmark]: Toolchain (without parser) took 22796.12ms. Allocated memory was 146.8MB in the beginning and 9.3GB in the end (delta: 9.2GB). Free memory was 117.2MB in the beginning and 8.5GB in the end (delta: -8.3GB). Peak memory consumption was 829.9MB. Max. memory is 16.1GB. [2023-11-19 07:48:24,660 INFO L158 Benchmark]: CDTParser took 0.72ms. Allocated memory is still 115.3MB. Free memory is still 74.7MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-19 07:48:24,660 INFO L158 Benchmark]: CACSL2BoogieTranslator took 400.63ms. Allocated memory is still 146.8MB. Free memory was 117.0MB in the beginning and 101.2MB in the end (delta: 15.7MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2023-11-19 07:48:24,661 INFO L158 Benchmark]: Boogie Procedure Inliner took 90.18ms. Allocated memory is still 146.8MB. Free memory was 101.2MB in the beginning and 97.0MB in the end (delta: 4.3MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-19 07:48:24,661 INFO L158 Benchmark]: Boogie Preprocessor took 114.39ms. Allocated memory is still 146.8MB. Free memory was 97.0MB in the beginning and 92.8MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-19 07:48:24,661 INFO L158 Benchmark]: RCFGBuilder took 1476.79ms. Allocated memory is still 146.8MB. Free memory was 92.8MB in the beginning and 95.0MB in the end (delta: -2.2MB). Peak memory consumption was 35.7MB. Max. memory is 16.1GB. [2023-11-19 07:48:24,662 INFO L158 Benchmark]: BuchiAutomizer took 20611.70ms. Allocated memory was 146.8MB in the beginning and 9.3GB in the end (delta: 9.2GB). Free memory was 94.4MB in the beginning and 8.5GB in the end (delta: -8.4GB). Peak memory consumption was 797.2MB. Max. memory is 16.1GB. [2023-11-19 07:48:24,662 INFO L158 Benchmark]: Witness Printer took 96.73ms. Allocated memory is still 9.3GB. Free memory was 8.5GB in the beginning and 8.5GB in the end (delta: 8.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2023-11-19 07:48:24,664 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.72ms. Allocated memory is still 115.3MB. Free memory is still 74.7MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 400.63ms. Allocated memory is still 146.8MB. Free memory was 117.0MB in the beginning and 101.2MB in the end (delta: 15.7MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 90.18ms. Allocated memory is still 146.8MB. Free memory was 101.2MB in the beginning and 97.0MB in the end (delta: 4.3MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 114.39ms. Allocated memory is still 146.8MB. Free memory was 97.0MB in the beginning and 92.8MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1476.79ms. Allocated memory is still 146.8MB. Free memory was 92.8MB in the beginning and 95.0MB in the end (delta: -2.2MB). Peak memory consumption was 35.7MB. Max. memory is 16.1GB. * BuchiAutomizer took 20611.70ms. Allocated memory was 146.8MB in the beginning and 9.3GB in the end (delta: 9.2GB). Free memory was 94.4MB in the beginning and 8.5GB in the end (delta: -8.4GB). Peak memory consumption was 797.2MB. Max. memory is 16.1GB. * Witness Printer took 96.73ms. Allocated memory is still 9.3GB. Free memory was 8.5GB in the beginning and 8.5GB in the end (delta: 8.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 23 terminating modules (23 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.23 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 57104 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 20.3s and 24 iterations. TraceHistogramMax:1. Analysis of lassos took 5.7s. Construction of modules took 0.9s. Büchi inclusion checks took 12.1s. Highest rank in rank-based complementation 0. Minimization of det autom 23. Minimization of nondet autom 0. Automata minimization 5.7s AutomataMinimizationTime, 23 MinimizatonAttempts, 21288 StatesRemovedByMinimization, 16 NontrivialMinimizations. Non-live state removal took 3.3s Buchi closure took 0.2s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 16644 SdHoareTripleChecker+Valid, 1.2s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 16644 mSDsluCounter, 30707 SdHoareTripleChecker+Invalid, 1.0s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 14338 mSDsCounter, 273 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 823 IncrementalHoareTripleChecker+Invalid, 1096 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 273 mSolverCounterUnsat, 16369 mSDtfsCounter, 823 mSolverCounterSat, 0.3s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc4 concLT0 SILN1 SILU0 SILI14 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 423]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, token=0] [L848] int __retres1 ; [L852] CALL init_model() [L760] m_i = 1 [L761] t1_i = 1 [L762] t2_i = 1 [L763] t3_i = 1 [L764] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L852] RET init_model() [L853] CALL start_simulation() [L789] int kernel_st ; [L790] int tmp ; [L791] int tmp___0 ; [L795] kernel_st = 0 [L796] FCALL update_channels() [L797] CALL init_threads() [L353] COND TRUE m_i == 1 [L354] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L358] COND TRUE t1_i == 1 [L359] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L363] COND TRUE t2_i == 1 [L364] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L368] COND TRUE t3_i == 1 [L369] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L373] COND TRUE t4_i == 1 [L374] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L797] RET init_threads() [L798] CALL fire_delta_events() [L514] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L519] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L524] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L529] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L534] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L539] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L544] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L549] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L554] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L559] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L798] RET fire_delta_events() [L799] CALL activate_threads() [L627] int tmp ; [L628] int tmp___0 ; [L629] int tmp___1 ; [L630] int tmp___2 ; [L631] int tmp___3 ; [L635] CALL, EXPR is_master_triggered() [L247] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L250] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L260] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L635] RET, EXPR is_master_triggered() [L635] tmp = is_master_triggered() [L637] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, token=0] [L643] CALL, EXPR is_transmit1_triggered() [L266] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L269] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L279] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L643] RET, EXPR is_transmit1_triggered() [L643] tmp___0 = is_transmit1_triggered() [L645] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, token=0] [L651] CALL, EXPR is_transmit2_triggered() [L285] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L288] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L298] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L651] RET, EXPR is_transmit2_triggered() [L651] tmp___1 = is_transmit2_triggered() [L653] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L659] CALL, EXPR is_transmit3_triggered() [L304] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L307] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L317] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L659] RET, EXPR is_transmit3_triggered() [L659] tmp___2 = is_transmit3_triggered() [L661] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L667] CALL, EXPR is_transmit4_triggered() [L323] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L326] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L336] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L667] RET, EXPR is_transmit4_triggered() [L667] tmp___3 = is_transmit4_triggered() [L669] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L799] RET activate_threads() [L800] CALL reset_delta_events() [L572] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L577] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L582] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L587] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L592] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L597] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L602] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L607] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L612] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L617] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L800] RET reset_delta_events() [L803] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, kernel_st=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L806] kernel_st = 1 [L807] CALL eval() [L419] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L423] COND TRUE 1 [L426] CALL, EXPR exists_runnable_thread() [L383] int __retres1 ; [L386] COND TRUE m_st == 0 [L387] __retres1 = 1 [L414] return (__retres1); [L426] RET, EXPR exists_runnable_thread() [L426] tmp = exists_runnable_thread() [L428] COND TRUE \read(tmp) [L433] COND TRUE m_st == 0 [L434] int tmp_ndt_1; [L435] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L436] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L433-L444] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L447] COND TRUE t1_st == 0 [L448] int tmp_ndt_2; [L449] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L450] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L447-L458] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L461] COND TRUE t2_st == 0 [L462] int tmp_ndt_3; [L463] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L464] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L461-L472] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L475] COND TRUE t3_st == 0 [L476] int tmp_ndt_4; [L477] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L478] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L475-L486] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L489] COND TRUE t4_st == 0 [L490] int tmp_ndt_5; [L491] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L492] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L489-L500] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 423]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, token=0] [L848] int __retres1 ; [L852] CALL init_model() [L760] m_i = 1 [L761] t1_i = 1 [L762] t2_i = 1 [L763] t3_i = 1 [L764] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L852] RET init_model() [L853] CALL start_simulation() [L789] int kernel_st ; [L790] int tmp ; [L791] int tmp___0 ; [L795] kernel_st = 0 [L796] FCALL update_channels() [L797] CALL init_threads() [L353] COND TRUE m_i == 1 [L354] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L358] COND TRUE t1_i == 1 [L359] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L363] COND TRUE t2_i == 1 [L364] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L368] COND TRUE t3_i == 1 [L369] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L373] COND TRUE t4_i == 1 [L374] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L797] RET init_threads() [L798] CALL fire_delta_events() [L514] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L519] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L524] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L529] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L534] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L539] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L544] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L549] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L554] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L559] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L798] RET fire_delta_events() [L799] CALL activate_threads() [L627] int tmp ; [L628] int tmp___0 ; [L629] int tmp___1 ; [L630] int tmp___2 ; [L631] int tmp___3 ; [L635] CALL, EXPR is_master_triggered() [L247] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L250] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L260] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L635] RET, EXPR is_master_triggered() [L635] tmp = is_master_triggered() [L637] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, token=0] [L643] CALL, EXPR is_transmit1_triggered() [L266] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L269] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L279] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L643] RET, EXPR is_transmit1_triggered() [L643] tmp___0 = is_transmit1_triggered() [L645] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, token=0] [L651] CALL, EXPR is_transmit2_triggered() [L285] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L288] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L298] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L651] RET, EXPR is_transmit2_triggered() [L651] tmp___1 = is_transmit2_triggered() [L653] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L659] CALL, EXPR is_transmit3_triggered() [L304] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L307] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L317] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L659] RET, EXPR is_transmit3_triggered() [L659] tmp___2 = is_transmit3_triggered() [L661] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L667] CALL, EXPR is_transmit4_triggered() [L323] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L326] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L336] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L667] RET, EXPR is_transmit4_triggered() [L667] tmp___3 = is_transmit4_triggered() [L669] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L799] RET activate_threads() [L800] CALL reset_delta_events() [L572] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L577] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L582] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L587] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L592] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L597] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L602] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L607] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L612] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L617] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L800] RET reset_delta_events() [L803] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, kernel_st=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L806] kernel_st = 1 [L807] CALL eval() [L419] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L423] COND TRUE 1 [L426] CALL, EXPR exists_runnable_thread() [L383] int __retres1 ; [L386] COND TRUE m_st == 0 [L387] __retres1 = 1 [L414] return (__retres1); [L426] RET, EXPR exists_runnable_thread() [L426] tmp = exists_runnable_thread() [L428] COND TRUE \read(tmp) [L433] COND TRUE m_st == 0 [L434] int tmp_ndt_1; [L435] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L436] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L433-L444] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L447] COND TRUE t1_st == 0 [L448] int tmp_ndt_2; [L449] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L450] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L447-L458] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L461] COND TRUE t2_st == 0 [L462] int tmp_ndt_3; [L463] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L464] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L461-L472] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L475] COND TRUE t3_st == 0 [L476] int tmp_ndt_4; [L477] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L478] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L475-L486] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L489] COND TRUE t4_st == 0 [L490] int tmp_ndt_5; [L491] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L492] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L489-L500] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-19 07:48:24,879 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a7be7761-ee72-4f7f-80ea-03dd6347eac3/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)