./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 9bd2c7ff Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_29fd8cb5-ea16-406b-9e9c-449480d3a906/bin/uautomizer-verify-uCwYo4JHxu/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_29fd8cb5-ea16-406b-9e9c-449480d3a906/bin/uautomizer-verify-uCwYo4JHxu/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_29fd8cb5-ea16-406b-9e9c-449480d3a906/bin/uautomizer-verify-uCwYo4JHxu/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_29fd8cb5-ea16-406b-9e9c-449480d3a906/bin/uautomizer-verify-uCwYo4JHxu/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_29fd8cb5-ea16-406b-9e9c-449480d3a906/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_29fd8cb5-ea16-406b-9e9c-449480d3a906/bin/uautomizer-verify-uCwYo4JHxu --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 16e147b68a860b93a665f8bd36a316225675cf186d50a72fc3242bc6ec552f78 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-9bd2c7f [2023-11-19 08:06:43,738 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-19 08:06:43,880 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_29fd8cb5-ea16-406b-9e9c-449480d3a906/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-19 08:06:43,885 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-19 08:06:43,886 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-19 08:06:43,927 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-19 08:06:43,929 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-19 08:06:43,930 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-19 08:06:43,932 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-19 08:06:43,937 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-19 08:06:43,939 INFO L153 SettingsManager]: * Use SBE=true [2023-11-19 08:06:43,939 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-19 08:06:43,940 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-19 08:06:43,942 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-19 08:06:43,942 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-19 08:06:43,943 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-19 08:06:43,943 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-19 08:06:43,944 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-19 08:06:43,946 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-19 08:06:43,947 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-19 08:06:43,947 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-19 08:06:43,948 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-19 08:06:43,948 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-19 08:06:43,948 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-19 08:06:43,949 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-19 08:06:43,949 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-19 08:06:43,950 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-19 08:06:43,950 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-19 08:06:43,950 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-19 08:06:43,951 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-19 08:06:43,952 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-19 08:06:43,953 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-19 08:06:43,953 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-19 08:06:43,953 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-19 08:06:43,953 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-19 08:06:43,954 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-19 08:06:43,954 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_29fd8cb5-ea16-406b-9e9c-449480d3a906/bin/uautomizer-verify-uCwYo4JHxu/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_29fd8cb5-ea16-406b-9e9c-449480d3a906/bin/uautomizer-verify-uCwYo4JHxu Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 16e147b68a860b93a665f8bd36a316225675cf186d50a72fc3242bc6ec552f78 [2023-11-19 08:06:44,331 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-19 08:06:44,368 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-19 08:06:44,371 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-19 08:06:44,372 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-19 08:06:44,373 INFO L274 PluginConnector]: CDTParser initialized [2023-11-19 08:06:44,374 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_29fd8cb5-ea16-406b-9e9c-449480d3a906/bin/uautomizer-verify-uCwYo4JHxu/../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c [2023-11-19 08:06:47,571 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-19 08:06:47,813 INFO L384 CDTParser]: Found 1 translation units. [2023-11-19 08:06:47,814 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_29fd8cb5-ea16-406b-9e9c-449480d3a906/sv-benchmarks/c/systemc/token_ring.05.cil-2.c [2023-11-19 08:06:47,832 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_29fd8cb5-ea16-406b-9e9c-449480d3a906/bin/uautomizer-verify-uCwYo4JHxu/data/8941a2174/320771fafec14f73a1f95fbc8822a130/FLAGc41fd908c [2023-11-19 08:06:47,847 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_29fd8cb5-ea16-406b-9e9c-449480d3a906/bin/uautomizer-verify-uCwYo4JHxu/data/8941a2174/320771fafec14f73a1f95fbc8822a130 [2023-11-19 08:06:47,850 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-19 08:06:47,852 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-19 08:06:47,854 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-19 08:06:47,854 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-19 08:06:47,860 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-19 08:06:47,860 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 08:06:47" (1/1) ... [2023-11-19 08:06:47,862 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@60469145 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:06:47, skipping insertion in model container [2023-11-19 08:06:47,862 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 08:06:47" (1/1) ... [2023-11-19 08:06:47,908 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-19 08:06:48,183 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 08:06:48,204 INFO L202 MainTranslator]: Completed pre-run [2023-11-19 08:06:48,264 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 08:06:48,284 INFO L206 MainTranslator]: Completed translation [2023-11-19 08:06:48,284 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:06:48 WrapperNode [2023-11-19 08:06:48,285 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-19 08:06:48,286 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-19 08:06:48,286 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-19 08:06:48,286 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-19 08:06:48,294 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:06:48" (1/1) ... [2023-11-19 08:06:48,307 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:06:48" (1/1) ... [2023-11-19 08:06:48,389 INFO L138 Inliner]: procedures = 38, calls = 48, calls flagged for inlining = 43, calls inlined = 97, statements flattened = 1368 [2023-11-19 08:06:48,389 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-19 08:06:48,390 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-19 08:06:48,391 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-19 08:06:48,391 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-19 08:06:48,401 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:06:48" (1/1) ... [2023-11-19 08:06:48,402 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:06:48" (1/1) ... [2023-11-19 08:06:48,408 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:06:48" (1/1) ... [2023-11-19 08:06:48,409 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:06:48" (1/1) ... [2023-11-19 08:06:48,434 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:06:48" (1/1) ... [2023-11-19 08:06:48,451 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:06:48" (1/1) ... [2023-11-19 08:06:48,456 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:06:48" (1/1) ... [2023-11-19 08:06:48,462 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:06:48" (1/1) ... [2023-11-19 08:06:48,471 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-19 08:06:48,472 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-19 08:06:48,472 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-19 08:06:48,472 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-19 08:06:48,473 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:06:48" (1/1) ... [2023-11-19 08:06:48,480 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 08:06:48,516 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_29fd8cb5-ea16-406b-9e9c-449480d3a906/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 08:06:48,542 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_29fd8cb5-ea16-406b-9e9c-449480d3a906/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 08:06:48,586 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_29fd8cb5-ea16-406b-9e9c-449480d3a906/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-19 08:06:48,616 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-19 08:06:48,617 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-19 08:06:48,617 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-19 08:06:48,617 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-19 08:06:48,773 INFO L236 CfgBuilder]: Building ICFG [2023-11-19 08:06:48,776 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-19 08:06:50,088 INFO L277 CfgBuilder]: Performing block encoding [2023-11-19 08:06:50,107 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-19 08:06:50,108 INFO L302 CfgBuilder]: Removed 8 assume(true) statements. [2023-11-19 08:06:50,118 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 08:06:50 BoogieIcfgContainer [2023-11-19 08:06:50,118 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-19 08:06:50,120 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-19 08:06:50,120 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-19 08:06:50,125 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-19 08:06:50,126 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 08:06:50,126 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 08:06:47" (1/3) ... [2023-11-19 08:06:50,127 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5f78c1b9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 08:06:50, skipping insertion in model container [2023-11-19 08:06:50,128 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 08:06:50,128 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:06:48" (2/3) ... [2023-11-19 08:06:50,128 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5f78c1b9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 08:06:50, skipping insertion in model container [2023-11-19 08:06:50,129 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 08:06:50,129 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 08:06:50" (3/3) ... [2023-11-19 08:06:50,131 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-2.c [2023-11-19 08:06:50,209 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-19 08:06:50,209 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-19 08:06:50,209 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-19 08:06:50,209 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-19 08:06:50,210 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-19 08:06:50,210 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-19 08:06:50,210 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-19 08:06:50,210 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-19 08:06:50,219 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 567 states, 566 states have (on average 1.5229681978798586) internal successors, (862), 566 states have internal predecessors, (862), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:50,284 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 484 [2023-11-19 08:06:50,284 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:06:50,284 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:06:50,299 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:50,299 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:50,299 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-19 08:06:50,302 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 567 states, 566 states have (on average 1.5229681978798586) internal successors, (862), 566 states have internal predecessors, (862), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:50,321 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 484 [2023-11-19 08:06:50,321 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:06:50,322 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:06:50,327 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:50,328 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:50,339 INFO L748 eck$LassoCheckResult]: Stem: 192#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 472#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 279#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 469#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 265#L426true assume !(1 == ~m_i~0);~m_st~0 := 2; 328#L426-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 153#L431-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 323#L436-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 138#L441-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 507#L446-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 364#L451-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 209#L611true assume 0 == ~M_E~0;~M_E~0 := 1; 385#L611-2true assume !(0 == ~T1_E~0); 382#L616-1true assume !(0 == ~T2_E~0); 390#L621-1true assume !(0 == ~T3_E~0); 65#L626-1true assume !(0 == ~T4_E~0); 354#L631-1true assume !(0 == ~T5_E~0); 177#L636-1true assume !(0 == ~E_M~0); 91#L641-1true assume !(0 == ~E_1~0); 188#L646-1true assume 0 == ~E_2~0;~E_2~0 := 1; 498#L651-1true assume !(0 == ~E_3~0); 444#L656-1true assume !(0 == ~E_4~0); 362#L661-1true assume !(0 == ~E_5~0); 407#L666-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 530#L304true assume !(1 == ~m_pc~0); 104#L304-2true is_master_triggered_~__retres1~0#1 := 0; 52#L315true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 156#is_master_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 27#L755true assume !(0 != activate_threads_~tmp~1#1); 553#L755-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6#L323true assume 1 == ~t1_pc~0; 309#L324true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35#L334true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 499#L763true assume !(0 != activate_threads_~tmp___0~0#1); 510#L763-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37#L342true assume 1 == ~t2_pc~0; 524#L343true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 110#L353true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 281#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 532#L771true assume !(0 != activate_threads_~tmp___1~0#1); 355#L771-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 238#L361true assume !(1 == ~t3_pc~0); 256#L361-2true is_transmit3_triggered_~__retres1~3#1 := 0; 463#L372true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 435#L779true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45#L779-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 237#L380true assume 1 == ~t4_pc~0; 77#L381true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 375#L391true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 270#L787true assume !(0 != activate_threads_~tmp___3~0#1); 522#L787-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78#L399true assume !(1 == ~t5_pc~0); 159#L399-2true is_transmit5_triggered_~__retres1~5#1 := 0; 387#L410true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 164#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 154#L795true assume !(0 != activate_threads_~tmp___4~0#1); 458#L795-2true havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 533#L679true assume !(1 == ~M_E~0); 206#L679-2true assume !(1 == ~T1_E~0); 117#L684-1true assume !(1 == ~T2_E~0); 244#L689-1true assume !(1 == ~T3_E~0); 544#L694-1true assume !(1 == ~T4_E~0); 243#L699-1true assume !(1 == ~T5_E~0); 363#L704-1true assume !(1 == ~E_M~0); 224#L709-1true assume 1 == ~E_1~0;~E_1~0 := 2; 180#L714-1true assume !(1 == ~E_2~0); 344#L719-1true assume !(1 == ~E_3~0); 483#L724-1true assume !(1 == ~E_4~0); 59#L729-1true assume !(1 == ~E_5~0); 465#L734-1true assume { :end_inline_reset_delta_events } true; 333#L940-2true [2023-11-19 08:06:50,342 INFO L750 eck$LassoCheckResult]: Loop: 333#L940-2true assume !false; 402#L941true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 447#L586-1true assume false; 96#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 412#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 303#L611-3true assume 0 == ~M_E~0;~M_E~0 := 1; 60#L611-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 319#L616-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 57#L621-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 30#L626-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 563#L631-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 31#L636-3true assume 0 == ~E_M~0;~E_M~0 := 1; 66#L641-3true assume !(0 == ~E_1~0); 240#L646-3true assume 0 == ~E_2~0;~E_2~0 := 1; 72#L651-3true assume 0 == ~E_3~0;~E_3~0 := 1; 218#L656-3true assume 0 == ~E_4~0;~E_4~0 := 1; 500#L661-3true assume 0 == ~E_5~0;~E_5~0 := 1; 512#L666-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 157#L304-21true assume 1 == ~m_pc~0; 519#L305-7true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 267#L315-7true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 114#is_master_triggered_returnLabel#8true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 197#L755-21true assume !(0 != activate_threads_~tmp~1#1); 220#L755-23true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 495#L323-21true assume !(1 == ~t1_pc~0); 372#L323-23true is_transmit1_triggered_~__retres1~1#1 := 0; 408#L334-7true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82#is_transmit1_triggered_returnLabel#8true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 403#L763-21true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 423#L763-23true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 560#L342-21true assume 1 == ~t2_pc~0; 25#L343-7true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 261#L353-7true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 205#is_transmit2_triggered_returnLabel#8true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 357#L771-21true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 79#L771-23true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 478#L361-21true assume !(1 == ~t3_pc~0); 460#L361-23true is_transmit3_triggered_~__retres1~3#1 := 0; 482#L372-7true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 484#is_transmit3_triggered_returnLabel#8true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 178#L779-21true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29#L779-23true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 518#L380-21true assume 1 == ~t4_pc~0; 432#L381-7true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 99#L391-7true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 454#is_transmit4_triggered_returnLabel#8true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 343#L787-21true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 271#L787-23true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 144#L399-21true assume 1 == ~t5_pc~0; 129#L400-7true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 286#L410-7true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 255#is_transmit5_triggered_returnLabel#8true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 505#L795-21true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 451#L795-23true havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26#L679-3true assume 1 == ~M_E~0;~M_E~0 := 2; 185#L679-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 230#L684-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 2#L689-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 168#L694-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 21#L699-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 307#L704-3true assume !(1 == ~E_M~0); 400#L709-3true assume 1 == ~E_1~0;~E_1~0 := 2; 291#L714-3true assume 1 == ~E_2~0;~E_2~0 := 2; 162#L719-3true assume 1 == ~E_3~0;~E_3~0 := 2; 20#L724-3true assume 1 == ~E_4~0;~E_4~0 := 2; 276#L729-3true assume 1 == ~E_5~0;~E_5~0 := 2; 326#L734-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 34#L464-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 219#L496-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 250#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 253#L959true assume !(0 == start_simulation_~tmp~3#1); 517#L959-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 182#L464-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 384#L496-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 42#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 373#L914true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 128#L921true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 422#stop_simulation_returnLabel#1true start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 308#L972true assume !(0 != start_simulation_~tmp___0~1#1); 333#L940-2true [2023-11-19 08:06:50,351 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:50,351 INFO L85 PathProgramCache]: Analyzing trace with hash 907431560, now seen corresponding path program 1 times [2023-11-19 08:06:50,364 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:50,365 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [360489126] [2023-11-19 08:06:50,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:50,366 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:50,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:50,743 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:50,743 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:50,746 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [360489126] [2023-11-19 08:06:50,747 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [360489126] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:50,747 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:50,747 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:06:50,749 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1557051977] [2023-11-19 08:06:50,750 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:50,758 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:06:50,760 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:50,761 INFO L85 PathProgramCache]: Analyzing trace with hash -2069699191, now seen corresponding path program 1 times [2023-11-19 08:06:50,762 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:50,762 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [497580222] [2023-11-19 08:06:50,762 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:50,763 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:50,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:50,880 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:50,892 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:50,893 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [497580222] [2023-11-19 08:06:50,893 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [497580222] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:50,893 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:50,894 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 08:06:50,894 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [345671010] [2023-11-19 08:06:50,894 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:50,896 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:06:50,898 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:06:50,952 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:06:50,953 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:06:50,957 INFO L87 Difference]: Start difference. First operand has 567 states, 566 states have (on average 1.5229681978798586) internal successors, (862), 566 states have internal predecessors, (862), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:51,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:06:51,038 INFO L93 Difference]: Finished difference Result 563 states and 839 transitions. [2023-11-19 08:06:51,040 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 563 states and 839 transitions. [2023-11-19 08:06:51,048 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2023-11-19 08:06:51,061 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 563 states to 557 states and 833 transitions. [2023-11-19 08:06:51,062 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 557 [2023-11-19 08:06:51,065 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 557 [2023-11-19 08:06:51,066 INFO L73 IsDeterministic]: Start isDeterministic. Operand 557 states and 833 transitions. [2023-11-19 08:06:51,071 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:06:51,071 INFO L218 hiAutomatonCegarLoop]: Abstraction has 557 states and 833 transitions. [2023-11-19 08:06:51,098 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states and 833 transitions. [2023-11-19 08:06:51,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 557. [2023-11-19 08:06:51,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 557 states, 557 states have (on average 1.4955116696588868) internal successors, (833), 556 states have internal predecessors, (833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:51,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 557 states and 833 transitions. [2023-11-19 08:06:51,151 INFO L240 hiAutomatonCegarLoop]: Abstraction has 557 states and 833 transitions. [2023-11-19 08:06:51,153 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:06:51,157 INFO L428 stractBuchiCegarLoop]: Abstraction has 557 states and 833 transitions. [2023-11-19 08:06:51,158 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-19 08:06:51,158 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 557 states and 833 transitions. [2023-11-19 08:06:51,163 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2023-11-19 08:06:51,163 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:06:51,164 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:06:51,169 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:51,169 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:51,169 INFO L748 eck$LassoCheckResult]: Stem: 1478#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1479#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1578#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1579#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1564#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 1565#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1421#L431-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1422#L436-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1399#L441-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1400#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1630#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1502#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 1503#L611-2 assume !(0 == ~T1_E~0); 1642#L616-1 assume !(0 == ~T2_E~0); 1643#L621-1 assume !(0 == ~T3_E~0); 1267#L626-1 assume !(0 == ~T4_E~0); 1268#L631-1 assume !(0 == ~T5_E~0); 1459#L636-1 assume !(0 == ~E_M~0); 1319#L641-1 assume !(0 == ~E_1~0); 1320#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 1476#L651-1 assume !(0 == ~E_3~0); 1671#L656-1 assume !(0 == ~E_4~0); 1628#L661-1 assume !(0 == ~E_5~0); 1629#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1655#L304 assume !(1 == ~m_pc~0); 1345#L304-2 is_master_triggered_~__retres1~0#1 := 0; 1242#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1243#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1193#L755 assume !(0 != activate_threads_~tmp~1#1); 1194#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1149#L323 assume 1 == ~t1_pc~0; 1150#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1212#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1213#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1228#L763 assume !(0 != activate_threads_~tmp___0~0#1); 1691#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1215#L342 assume 1 == ~t2_pc~0; 1216#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1351#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1352#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1580#L771 assume !(0 != activate_threads_~tmp___1~0#1); 1625#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1535#L361 assume !(1 == ~t3_pc~0); 1536#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1560#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1165#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1166#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1233#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1234#L380 assume 1 == ~t4_pc~0; 1289#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1290#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1314#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1315#L787 assume !(0 != activate_threads_~tmp___3~0#1); 1567#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1292#L399 assume !(1 == ~t5_pc~0); 1293#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1431#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1436#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1423#L795 assume !(0 != activate_threads_~tmp___4~0#1); 1424#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1680#L679 assume !(1 == ~M_E~0); 1500#L679-2 assume !(1 == ~T1_E~0); 1364#L684-1 assume !(1 == ~T2_E~0); 1365#L689-1 assume !(1 == ~T3_E~0); 1543#L694-1 assume !(1 == ~T4_E~0); 1541#L699-1 assume !(1 == ~T5_E~0); 1542#L704-1 assume !(1 == ~E_M~0); 1525#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1466#L714-1 assume !(1 == ~E_2~0); 1467#L719-1 assume !(1 == ~E_3~0); 1621#L724-1 assume !(1 == ~E_4~0); 1253#L729-1 assume !(1 == ~E_5~0); 1254#L734-1 assume { :end_inline_reset_delta_events } true; 1597#L940-2 [2023-11-19 08:06:51,170 INFO L750 eck$LassoCheckResult]: Loop: 1597#L940-2 assume !false; 1611#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1327#L586-1 assume !false; 1674#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1677#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1538#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1539#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1534#L511 assume !(0 != eval_~tmp~0#1); 1330#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1331#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1591#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1255#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1256#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1251#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1200#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1201#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1202#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1203#L641-3 assume !(0 == ~E_1~0); 1269#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1279#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1280#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1519#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1692#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1428#L304-21 assume !(1 == ~m_pc~0); 1282#L304-23 is_master_triggered_~__retres1~0#1 := 0; 1283#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1358#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1359#L755-21 assume !(0 != activate_threads_~tmp~1#1); 1487#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1521#L323-21 assume 1 == ~t1_pc~0; 1162#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1163#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1301#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1302#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1653#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1664#L342-21 assume 1 == ~t2_pc~0; 1188#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1189#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1498#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1499#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1295#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1296#L361-21 assume !(1 == ~t3_pc~0); 1681#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 1682#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1686#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1462#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1198#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1199#L380-21 assume 1 == ~t4_pc~0; 1670#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1262#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1337#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1618#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1568#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1409#L399-21 assume !(1 == ~t5_pc~0); 1265#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 1266#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1558#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1559#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1676#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1191#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1192#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1472#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1139#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1140#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1180#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1181#L704-3 assume !(1 == ~E_M~0); 1595#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1586#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1433#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1178#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1179#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1574#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1209#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1210#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1520#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 1553#L959 assume !(0 == start_simulation_~tmp~3#1); 1557#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1463#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1464#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1224#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 1225#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1383#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1384#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1596#L972 assume !(0 != start_simulation_~tmp___0~1#1); 1597#L940-2 [2023-11-19 08:06:51,172 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:51,172 INFO L85 PathProgramCache]: Analyzing trace with hash 1400057734, now seen corresponding path program 1 times [2023-11-19 08:06:51,173 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:51,173 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1454455185] [2023-11-19 08:06:51,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:51,173 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:51,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:51,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:51,320 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:51,321 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1454455185] [2023-11-19 08:06:51,321 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1454455185] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:51,322 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:51,322 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:06:51,323 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [164981482] [2023-11-19 08:06:51,323 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:51,324 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:06:51,325 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:51,325 INFO L85 PathProgramCache]: Analyzing trace with hash -803035657, now seen corresponding path program 1 times [2023-11-19 08:06:51,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:51,326 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1821603185] [2023-11-19 08:06:51,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:51,328 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:51,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:51,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:51,501 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:51,501 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1821603185] [2023-11-19 08:06:51,502 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1821603185] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:51,502 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:51,503 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:06:51,503 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1481316893] [2023-11-19 08:06:51,503 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:51,505 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:06:51,507 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:06:51,508 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:06:51,508 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:06:51,509 INFO L87 Difference]: Start difference. First operand 557 states and 833 transitions. cyclomatic complexity: 277 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:51,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:06:51,542 INFO L93 Difference]: Finished difference Result 557 states and 832 transitions. [2023-11-19 08:06:51,543 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 832 transitions. [2023-11-19 08:06:51,552 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2023-11-19 08:06:51,559 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 557 states and 832 transitions. [2023-11-19 08:06:51,560 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 557 [2023-11-19 08:06:51,562 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 557 [2023-11-19 08:06:51,562 INFO L73 IsDeterministic]: Start isDeterministic. Operand 557 states and 832 transitions. [2023-11-19 08:06:51,573 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:06:51,573 INFO L218 hiAutomatonCegarLoop]: Abstraction has 557 states and 832 transitions. [2023-11-19 08:06:51,575 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states and 832 transitions. [2023-11-19 08:06:51,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 557. [2023-11-19 08:06:51,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 557 states, 557 states have (on average 1.4937163375224416) internal successors, (832), 556 states have internal predecessors, (832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:51,621 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 557 states and 832 transitions. [2023-11-19 08:06:51,622 INFO L240 hiAutomatonCegarLoop]: Abstraction has 557 states and 832 transitions. [2023-11-19 08:06:51,624 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:06:51,625 INFO L428 stractBuchiCegarLoop]: Abstraction has 557 states and 832 transitions. [2023-11-19 08:06:51,625 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-19 08:06:51,625 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 557 states and 832 transitions. [2023-11-19 08:06:51,630 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2023-11-19 08:06:51,631 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:06:51,632 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:06:51,634 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:51,639 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:51,640 INFO L748 eck$LassoCheckResult]: Stem: 2599#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2600#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2699#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2700#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2685#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 2686#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2542#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2543#L436-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2520#L441-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2521#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2751#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2623#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 2624#L611-2 assume !(0 == ~T1_E~0); 2763#L616-1 assume !(0 == ~T2_E~0); 2764#L621-1 assume !(0 == ~T3_E~0); 2388#L626-1 assume !(0 == ~T4_E~0); 2389#L631-1 assume !(0 == ~T5_E~0); 2583#L636-1 assume !(0 == ~E_M~0); 2440#L641-1 assume !(0 == ~E_1~0); 2441#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 2597#L651-1 assume !(0 == ~E_3~0); 2792#L656-1 assume !(0 == ~E_4~0); 2749#L661-1 assume !(0 == ~E_5~0); 2750#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2776#L304 assume !(1 == ~m_pc~0); 2467#L304-2 is_master_triggered_~__retres1~0#1 := 0; 2363#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2364#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2316#L755 assume !(0 != activate_threads_~tmp~1#1); 2317#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2270#L323 assume 1 == ~t1_pc~0; 2271#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2333#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2334#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2349#L763 assume !(0 != activate_threads_~tmp___0~0#1); 2812#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2340#L342 assume 1 == ~t2_pc~0; 2341#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2472#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2473#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2701#L771 assume !(0 != activate_threads_~tmp___1~0#1); 2746#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2656#L361 assume !(1 == ~t3_pc~0); 2657#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2681#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2286#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2287#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2354#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2355#L380 assume 1 == ~t4_pc~0; 2410#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2411#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2436#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2437#L787 assume !(0 != activate_threads_~tmp___3~0#1); 2688#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2413#L399 assume !(1 == ~t5_pc~0); 2414#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2552#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2557#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2544#L795 assume !(0 != activate_threads_~tmp___4~0#1); 2545#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2801#L679 assume !(1 == ~M_E~0); 2621#L679-2 assume !(1 == ~T1_E~0); 2485#L684-1 assume !(1 == ~T2_E~0); 2486#L689-1 assume !(1 == ~T3_E~0); 2664#L694-1 assume !(1 == ~T4_E~0); 2662#L699-1 assume !(1 == ~T5_E~0); 2663#L704-1 assume !(1 == ~E_M~0); 2646#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2587#L714-1 assume !(1 == ~E_2~0); 2588#L719-1 assume !(1 == ~E_3~0); 2742#L724-1 assume !(1 == ~E_4~0); 2374#L729-1 assume !(1 == ~E_5~0); 2375#L734-1 assume { :end_inline_reset_delta_events } true; 2718#L940-2 [2023-11-19 08:06:51,640 INFO L750 eck$LassoCheckResult]: Loop: 2718#L940-2 assume !false; 2732#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2448#L586-1 assume !false; 2795#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2798#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2659#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2660#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2655#L511 assume !(0 != eval_~tmp~0#1); 2451#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2452#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2712#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2376#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2377#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2373#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2321#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2322#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2323#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2324#L641-3 assume !(0 == ~E_1~0); 2390#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2400#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2401#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2640#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2813#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2549#L304-21 assume !(1 == ~m_pc~0); 2403#L304-23 is_master_triggered_~__retres1~0#1 := 0; 2404#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2479#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2480#L755-21 assume !(0 != activate_threads_~tmp~1#1); 2608#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2642#L323-21 assume 1 == ~t1_pc~0; 2283#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2284#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2422#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2423#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2774#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2785#L342-21 assume 1 == ~t2_pc~0; 2309#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2310#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2617#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2618#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2416#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2417#L361-21 assume !(1 == ~t3_pc~0); 2802#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 2803#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2807#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2582#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2314#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2315#L380-21 assume 1 == ~t4_pc~0; 2791#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2381#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2456#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2739#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2689#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2530#L399-21 assume !(1 == ~t5_pc~0); 2386#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 2387#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2679#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2680#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2797#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2312#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2313#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2593#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2260#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2261#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2301#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2302#L704-3 assume !(1 == ~E_M~0); 2716#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2707#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2554#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2299#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2300#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2695#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2330#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2331#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2641#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 2674#L959 assume !(0 == start_simulation_~tmp~3#1); 2678#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2584#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2585#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2345#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 2346#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2504#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2505#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 2717#L972 assume !(0 != start_simulation_~tmp___0~1#1); 2718#L940-2 [2023-11-19 08:06:51,641 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:51,642 INFO L85 PathProgramCache]: Analyzing trace with hash -1678755836, now seen corresponding path program 1 times [2023-11-19 08:06:51,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:51,648 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [808476395] [2023-11-19 08:06:51,648 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:51,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:51,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:51,735 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:51,735 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:51,736 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [808476395] [2023-11-19 08:06:51,736 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [808476395] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:51,736 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:51,736 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:06:51,736 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1496571869] [2023-11-19 08:06:51,737 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:51,737 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:06:51,737 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:51,738 INFO L85 PathProgramCache]: Analyzing trace with hash -803035657, now seen corresponding path program 2 times [2023-11-19 08:06:51,738 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:51,738 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1991041597] [2023-11-19 08:06:51,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:51,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:51,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:51,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:51,837 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:51,837 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1991041597] [2023-11-19 08:06:51,837 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1991041597] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:51,837 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:51,838 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:06:51,838 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [985194373] [2023-11-19 08:06:51,838 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:51,838 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:06:51,839 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:06:51,839 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:06:51,839 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:06:51,840 INFO L87 Difference]: Start difference. First operand 557 states and 832 transitions. cyclomatic complexity: 276 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:51,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:06:51,858 INFO L93 Difference]: Finished difference Result 557 states and 831 transitions. [2023-11-19 08:06:51,858 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 831 transitions. [2023-11-19 08:06:51,863 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2023-11-19 08:06:51,869 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 557 states and 831 transitions. [2023-11-19 08:06:51,869 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 557 [2023-11-19 08:06:51,870 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 557 [2023-11-19 08:06:51,870 INFO L73 IsDeterministic]: Start isDeterministic. Operand 557 states and 831 transitions. [2023-11-19 08:06:51,871 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:06:51,871 INFO L218 hiAutomatonCegarLoop]: Abstraction has 557 states and 831 transitions. [2023-11-19 08:06:51,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states and 831 transitions. [2023-11-19 08:06:51,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 557. [2023-11-19 08:06:51,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 557 states, 557 states have (on average 1.4919210053859964) internal successors, (831), 556 states have internal predecessors, (831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:51,886 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 557 states and 831 transitions. [2023-11-19 08:06:51,886 INFO L240 hiAutomatonCegarLoop]: Abstraction has 557 states and 831 transitions. [2023-11-19 08:06:51,887 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:06:51,888 INFO L428 stractBuchiCegarLoop]: Abstraction has 557 states and 831 transitions. [2023-11-19 08:06:51,888 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-19 08:06:51,888 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 557 states and 831 transitions. [2023-11-19 08:06:51,892 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2023-11-19 08:06:51,892 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:06:51,892 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:06:51,894 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:51,894 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:51,895 INFO L748 eck$LassoCheckResult]: Stem: 3720#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3721#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3820#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3821#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3806#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 3807#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3663#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3664#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3641#L441-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3642#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3872#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3744#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 3745#L611-2 assume !(0 == ~T1_E~0); 3885#L616-1 assume !(0 == ~T2_E~0); 3886#L621-1 assume !(0 == ~T3_E~0); 3509#L626-1 assume !(0 == ~T4_E~0); 3510#L631-1 assume !(0 == ~T5_E~0); 3704#L636-1 assume !(0 == ~E_M~0); 3561#L641-1 assume !(0 == ~E_1~0); 3562#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 3718#L651-1 assume !(0 == ~E_3~0); 3913#L656-1 assume !(0 == ~E_4~0); 3870#L661-1 assume !(0 == ~E_5~0); 3871#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3897#L304 assume !(1 == ~m_pc~0); 3590#L304-2 is_master_triggered_~__retres1~0#1 := 0; 3484#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3485#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3437#L755 assume !(0 != activate_threads_~tmp~1#1); 3438#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3391#L323 assume 1 == ~t1_pc~0; 3392#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3454#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3455#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3470#L763 assume !(0 != activate_threads_~tmp___0~0#1); 3933#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3461#L342 assume 1 == ~t2_pc~0; 3462#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3593#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3594#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3822#L771 assume !(0 != activate_threads_~tmp___1~0#1); 3867#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3777#L361 assume !(1 == ~t3_pc~0); 3778#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3802#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3407#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3408#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3475#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3476#L380 assume 1 == ~t4_pc~0; 3531#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3532#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3557#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3558#L787 assume !(0 != activate_threads_~tmp___3~0#1); 3809#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3534#L399 assume !(1 == ~t5_pc~0); 3535#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3674#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3678#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3665#L795 assume !(0 != activate_threads_~tmp___4~0#1); 3666#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3922#L679 assume !(1 == ~M_E~0); 3743#L679-2 assume !(1 == ~T1_E~0); 3606#L684-1 assume !(1 == ~T2_E~0); 3607#L689-1 assume !(1 == ~T3_E~0); 3785#L694-1 assume !(1 == ~T4_E~0); 3783#L699-1 assume !(1 == ~T5_E~0); 3784#L704-1 assume !(1 == ~E_M~0); 3767#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3708#L714-1 assume !(1 == ~E_2~0); 3709#L719-1 assume !(1 == ~E_3~0); 3863#L724-1 assume !(1 == ~E_4~0); 3495#L729-1 assume !(1 == ~E_5~0); 3496#L734-1 assume { :end_inline_reset_delta_events } true; 3839#L940-2 [2023-11-19 08:06:51,895 INFO L750 eck$LassoCheckResult]: Loop: 3839#L940-2 assume !false; 3853#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3569#L586-1 assume !false; 3916#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3919#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3780#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3781#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3776#L511 assume !(0 != eval_~tmp~0#1); 3572#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3573#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3833#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3497#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3498#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3494#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3442#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3443#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3444#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3445#L641-3 assume !(0 == ~E_1~0); 3511#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3521#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3522#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3761#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3934#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3670#L304-21 assume !(1 == ~m_pc~0); 3524#L304-23 is_master_triggered_~__retres1~0#1 := 0; 3525#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3600#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3601#L755-21 assume !(0 != activate_threads_~tmp~1#1); 3729#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3763#L323-21 assume 1 == ~t1_pc~0; 3404#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3405#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3543#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3544#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3895#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3906#L342-21 assume 1 == ~t2_pc~0; 3430#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3431#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3738#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3739#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3537#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3538#L361-21 assume !(1 == ~t3_pc~0); 3923#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 3924#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3928#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3703#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3435#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3436#L380-21 assume 1 == ~t4_pc~0; 3912#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3504#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3577#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3861#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3810#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3651#L399-21 assume !(1 == ~t5_pc~0); 3507#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 3508#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3800#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3801#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3918#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3433#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3434#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3714#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3381#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3382#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3422#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3423#L704-3 assume !(1 == ~E_M~0); 3837#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3828#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3675#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3420#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3421#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3818#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3451#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3452#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3762#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 3795#L959 assume !(0 == start_simulation_~tmp~3#1); 3799#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3705#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3706#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3466#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 3467#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3625#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3626#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 3838#L972 assume !(0 != start_simulation_~tmp___0~1#1); 3839#L940-2 [2023-11-19 08:06:51,896 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:51,896 INFO L85 PathProgramCache]: Analyzing trace with hash -946788410, now seen corresponding path program 1 times [2023-11-19 08:06:51,896 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:51,897 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [182610850] [2023-11-19 08:06:51,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:51,897 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:51,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:51,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:51,934 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:51,934 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [182610850] [2023-11-19 08:06:51,935 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [182610850] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:51,935 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:51,935 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:06:51,935 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1518769217] [2023-11-19 08:06:51,935 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:51,936 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:06:51,936 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:51,936 INFO L85 PathProgramCache]: Analyzing trace with hash -803035657, now seen corresponding path program 3 times [2023-11-19 08:06:51,937 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:51,937 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1578316739] [2023-11-19 08:06:51,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:51,937 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:51,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:51,992 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:51,994 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:51,994 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1578316739] [2023-11-19 08:06:51,995 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1578316739] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:51,995 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:51,995 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:06:51,995 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [202176023] [2023-11-19 08:06:51,996 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:51,996 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:06:51,997 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:06:51,997 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:06:51,997 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:06:51,998 INFO L87 Difference]: Start difference. First operand 557 states and 831 transitions. cyclomatic complexity: 275 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:52,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:06:52,017 INFO L93 Difference]: Finished difference Result 557 states and 830 transitions. [2023-11-19 08:06:52,017 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 830 transitions. [2023-11-19 08:06:52,023 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2023-11-19 08:06:52,048 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 557 states and 830 transitions. [2023-11-19 08:06:52,048 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 557 [2023-11-19 08:06:52,049 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 557 [2023-11-19 08:06:52,049 INFO L73 IsDeterministic]: Start isDeterministic. Operand 557 states and 830 transitions. [2023-11-19 08:06:52,050 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:06:52,050 INFO L218 hiAutomatonCegarLoop]: Abstraction has 557 states and 830 transitions. [2023-11-19 08:06:52,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states and 830 transitions. [2023-11-19 08:06:52,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 557. [2023-11-19 08:06:52,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 557 states, 557 states have (on average 1.4901256732495511) internal successors, (830), 556 states have internal predecessors, (830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:52,064 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 557 states and 830 transitions. [2023-11-19 08:06:52,064 INFO L240 hiAutomatonCegarLoop]: Abstraction has 557 states and 830 transitions. [2023-11-19 08:06:52,065 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:06:52,065 INFO L428 stractBuchiCegarLoop]: Abstraction has 557 states and 830 transitions. [2023-11-19 08:06:52,066 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-19 08:06:52,066 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 557 states and 830 transitions. [2023-11-19 08:06:52,069 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2023-11-19 08:06:52,070 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:06:52,070 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:06:52,072 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:52,072 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:52,072 INFO L748 eck$LassoCheckResult]: Stem: 4841#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4842#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4941#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4942#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4927#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 4928#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4784#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4785#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4762#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4763#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4993#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4865#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 4866#L611-2 assume !(0 == ~T1_E~0); 5006#L616-1 assume !(0 == ~T2_E~0); 5007#L621-1 assume !(0 == ~T3_E~0); 4634#L626-1 assume !(0 == ~T4_E~0); 4635#L631-1 assume !(0 == ~T5_E~0); 4825#L636-1 assume !(0 == ~E_M~0); 4685#L641-1 assume !(0 == ~E_1~0); 4686#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 4839#L651-1 assume !(0 == ~E_3~0); 5034#L656-1 assume !(0 == ~E_4~0); 4991#L661-1 assume !(0 == ~E_5~0); 4992#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5018#L304 assume !(1 == ~m_pc~0); 4712#L304-2 is_master_triggered_~__retres1~0#1 := 0; 4605#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4606#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4558#L755 assume !(0 != activate_threads_~tmp~1#1); 4559#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4514#L323 assume 1 == ~t1_pc~0; 4515#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4575#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4576#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4591#L763 assume !(0 != activate_threads_~tmp___0~0#1); 5054#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4584#L342 assume 1 == ~t2_pc~0; 4585#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4714#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4715#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4943#L771 assume !(0 != activate_threads_~tmp___1~0#1); 4988#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4898#L361 assume !(1 == ~t3_pc~0); 4899#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4923#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4528#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4529#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4596#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4597#L380 assume 1 == ~t4_pc~0; 4652#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4653#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4680#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4681#L787 assume !(0 != activate_threads_~tmp___3~0#1); 4930#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4655#L399 assume !(1 == ~t5_pc~0); 4656#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4795#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4799#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4786#L795 assume !(0 != activate_threads_~tmp___4~0#1); 4787#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5043#L679 assume !(1 == ~M_E~0); 4864#L679-2 assume !(1 == ~T1_E~0); 4727#L684-1 assume !(1 == ~T2_E~0); 4728#L689-1 assume !(1 == ~T3_E~0); 4906#L694-1 assume !(1 == ~T4_E~0); 4904#L699-1 assume !(1 == ~T5_E~0); 4905#L704-1 assume !(1 == ~E_M~0); 4888#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4830#L714-1 assume !(1 == ~E_2~0); 4831#L719-1 assume !(1 == ~E_3~0); 4984#L724-1 assume !(1 == ~E_4~0); 4616#L729-1 assume !(1 == ~E_5~0); 4617#L734-1 assume { :end_inline_reset_delta_events } true; 4961#L940-2 [2023-11-19 08:06:52,073 INFO L750 eck$LassoCheckResult]: Loop: 4961#L940-2 assume !false; 4974#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4690#L586-1 assume !false; 5037#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5040#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4901#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4902#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4897#L511 assume !(0 != eval_~tmp~0#1); 4693#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4694#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4954#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4618#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4619#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4615#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4563#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4564#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4565#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4566#L641-3 assume !(0 == ~E_1~0); 4628#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4642#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4643#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4881#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5055#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4791#L304-21 assume !(1 == ~m_pc~0); 4645#L304-23 is_master_triggered_~__retres1~0#1 := 0; 4646#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4721#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4722#L755-21 assume !(0 != activate_threads_~tmp~1#1); 4850#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4884#L323-21 assume 1 == ~t1_pc~0; 4525#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4526#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4664#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4665#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5016#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5027#L342-21 assume 1 == ~t2_pc~0; 4551#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4552#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4861#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4862#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4658#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4659#L361-21 assume !(1 == ~t3_pc~0); 5044#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 5045#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5049#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4824#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4556#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4557#L380-21 assume !(1 == ~t4_pc~0); 4624#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 4625#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4698#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4982#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4931#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4772#L399-21 assume !(1 == ~t5_pc~0); 4632#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 4633#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4921#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4922#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5039#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4554#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4555#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4835#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4502#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4503#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4543#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4544#L704-3 assume !(1 == ~E_M~0); 4959#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4949#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4796#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4541#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4542#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4939#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4572#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4573#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4883#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 4916#L959 assume !(0 == start_simulation_~tmp~3#1); 4920#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4827#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4828#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4589#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 4590#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4746#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4747#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 4960#L972 assume !(0 != start_simulation_~tmp___0~1#1); 4961#L940-2 [2023-11-19 08:06:52,074 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:52,074 INFO L85 PathProgramCache]: Analyzing trace with hash 739391428, now seen corresponding path program 1 times [2023-11-19 08:06:52,074 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:52,074 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [420121897] [2023-11-19 08:06:52,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:52,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:52,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:52,110 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:52,110 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:52,110 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [420121897] [2023-11-19 08:06:52,110 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [420121897] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:52,111 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:52,111 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:06:52,111 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [131289111] [2023-11-19 08:06:52,111 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:52,112 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:06:52,112 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:52,112 INFO L85 PathProgramCache]: Analyzing trace with hash 322224312, now seen corresponding path program 1 times [2023-11-19 08:06:52,113 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:52,113 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1043529266] [2023-11-19 08:06:52,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:52,113 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:52,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:52,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:52,158 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:52,158 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1043529266] [2023-11-19 08:06:52,158 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1043529266] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:52,159 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:52,159 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:06:52,159 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1692522591] [2023-11-19 08:06:52,159 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:52,160 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:06:52,160 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:06:52,161 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:06:52,161 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:06:52,161 INFO L87 Difference]: Start difference. First operand 557 states and 830 transitions. cyclomatic complexity: 274 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:52,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:06:52,180 INFO L93 Difference]: Finished difference Result 557 states and 829 transitions. [2023-11-19 08:06:52,180 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 829 transitions. [2023-11-19 08:06:52,185 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2023-11-19 08:06:52,190 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 557 states and 829 transitions. [2023-11-19 08:06:52,191 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 557 [2023-11-19 08:06:52,192 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 557 [2023-11-19 08:06:52,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 557 states and 829 transitions. [2023-11-19 08:06:52,193 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:06:52,193 INFO L218 hiAutomatonCegarLoop]: Abstraction has 557 states and 829 transitions. [2023-11-19 08:06:52,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states and 829 transitions. [2023-11-19 08:06:52,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 557. [2023-11-19 08:06:52,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 557 states, 557 states have (on average 1.488330341113106) internal successors, (829), 556 states have internal predecessors, (829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:52,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 557 states and 829 transitions. [2023-11-19 08:06:52,208 INFO L240 hiAutomatonCegarLoop]: Abstraction has 557 states and 829 transitions. [2023-11-19 08:06:52,209 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:06:52,210 INFO L428 stractBuchiCegarLoop]: Abstraction has 557 states and 829 transitions. [2023-11-19 08:06:52,210 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-19 08:06:52,210 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 557 states and 829 transitions. [2023-11-19 08:06:52,213 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2023-11-19 08:06:52,214 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:06:52,214 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:06:52,215 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:52,216 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:52,216 INFO L748 eck$LassoCheckResult]: Stem: 5962#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 5963#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 6062#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6063#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6048#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 6049#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5905#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5906#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5883#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5884#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6114#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5986#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 5987#L611-2 assume !(0 == ~T1_E~0); 6127#L616-1 assume !(0 == ~T2_E~0); 6128#L621-1 assume !(0 == ~T3_E~0); 5755#L626-1 assume !(0 == ~T4_E~0); 5756#L631-1 assume !(0 == ~T5_E~0); 5946#L636-1 assume !(0 == ~E_M~0); 5806#L641-1 assume !(0 == ~E_1~0); 5807#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5960#L651-1 assume !(0 == ~E_3~0); 6155#L656-1 assume !(0 == ~E_4~0); 6112#L661-1 assume !(0 == ~E_5~0); 6113#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6139#L304 assume !(1 == ~m_pc~0); 5833#L304-2 is_master_triggered_~__retres1~0#1 := 0; 5726#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5727#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5682#L755 assume !(0 != activate_threads_~tmp~1#1); 5683#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5635#L323 assume 1 == ~t1_pc~0; 5636#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5696#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5697#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5712#L763 assume !(0 != activate_threads_~tmp___0~0#1); 6175#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5705#L342 assume 1 == ~t2_pc~0; 5706#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5835#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5836#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6064#L771 assume !(0 != activate_threads_~tmp___1~0#1); 6109#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6019#L361 assume !(1 == ~t3_pc~0); 6020#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6044#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5649#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5650#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5717#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5718#L380 assume 1 == ~t4_pc~0; 5776#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5777#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5798#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5799#L787 assume !(0 != activate_threads_~tmp___3~0#1); 6051#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5773#L399 assume !(1 == ~t5_pc~0); 5774#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5915#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5920#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5907#L795 assume !(0 != activate_threads_~tmp___4~0#1); 5908#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6164#L679 assume !(1 == ~M_E~0); 5984#L679-2 assume !(1 == ~T1_E~0); 5848#L684-1 assume !(1 == ~T2_E~0); 5849#L689-1 assume !(1 == ~T3_E~0); 6027#L694-1 assume !(1 == ~T4_E~0); 6025#L699-1 assume !(1 == ~T5_E~0); 6026#L704-1 assume !(1 == ~E_M~0); 6009#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5947#L714-1 assume !(1 == ~E_2~0); 5948#L719-1 assume !(1 == ~E_3~0); 6105#L724-1 assume !(1 == ~E_4~0); 5737#L729-1 assume !(1 == ~E_5~0); 5738#L734-1 assume { :end_inline_reset_delta_events } true; 6082#L940-2 [2023-11-19 08:06:52,217 INFO L750 eck$LassoCheckResult]: Loop: 6082#L940-2 assume !false; 6095#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5811#L586-1 assume !false; 6157#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6161#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6022#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6023#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6018#L511 assume !(0 != eval_~tmp~0#1); 5814#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5815#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6075#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5739#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5740#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5735#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5684#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5685#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5686#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5687#L641-3 assume !(0 == ~E_1~0); 5749#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5763#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5764#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6003#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6176#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5912#L304-21 assume !(1 == ~m_pc~0); 5766#L304-23 is_master_triggered_~__retres1~0#1 := 0; 5767#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5842#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5843#L755-21 assume !(0 != activate_threads_~tmp~1#1); 5971#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6005#L323-21 assume !(1 == ~t1_pc~0); 5648#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 5647#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5785#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5786#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6137#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6148#L342-21 assume 1 == ~t2_pc~0; 5672#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5673#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5982#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5983#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5779#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5780#L361-21 assume !(1 == ~t3_pc~0); 6165#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 6166#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6170#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5945#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5680#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5681#L380-21 assume !(1 == ~t4_pc~0); 5745#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 5746#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5819#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6104#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6052#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5893#L399-21 assume !(1 == ~t5_pc~0); 5753#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 5754#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6042#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6043#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6160#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5675#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5676#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5956#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5623#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5624#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5664#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5665#L704-3 assume !(1 == ~E_M~0); 6080#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6070#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5917#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5662#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5663#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6060#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5693#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5694#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6004#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 6037#L959 assume !(0 == start_simulation_~tmp~3#1); 6041#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5950#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5951#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5710#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 5711#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5867#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5868#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 6081#L972 assume !(0 != start_simulation_~tmp___0~1#1); 6082#L940-2 [2023-11-19 08:06:52,217 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:52,218 INFO L85 PathProgramCache]: Analyzing trace with hash 793784326, now seen corresponding path program 1 times [2023-11-19 08:06:52,218 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:52,218 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [992988184] [2023-11-19 08:06:52,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:52,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:52,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:52,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:52,276 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:52,276 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [992988184] [2023-11-19 08:06:52,276 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [992988184] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:52,277 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:52,277 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 08:06:52,277 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1164051001] [2023-11-19 08:06:52,277 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:52,278 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:06:52,278 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:52,278 INFO L85 PathProgramCache]: Analyzing trace with hash -785904327, now seen corresponding path program 1 times [2023-11-19 08:06:52,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:52,279 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [467538972] [2023-11-19 08:06:52,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:52,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:52,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:52,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:52,322 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:52,322 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [467538972] [2023-11-19 08:06:52,323 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [467538972] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:52,323 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:52,323 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:06:52,323 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1026338690] [2023-11-19 08:06:52,324 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:52,324 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:06:52,324 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:06:52,325 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:06:52,325 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:06:52,325 INFO L87 Difference]: Start difference. First operand 557 states and 829 transitions. cyclomatic complexity: 273 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:52,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:06:52,375 INFO L93 Difference]: Finished difference Result 991 states and 1469 transitions. [2023-11-19 08:06:52,375 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 991 states and 1469 transitions. [2023-11-19 08:06:52,384 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 912 [2023-11-19 08:06:52,392 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 991 states to 991 states and 1469 transitions. [2023-11-19 08:06:52,393 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 991 [2023-11-19 08:06:52,394 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 991 [2023-11-19 08:06:52,394 INFO L73 IsDeterministic]: Start isDeterministic. Operand 991 states and 1469 transitions. [2023-11-19 08:06:52,396 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:06:52,396 INFO L218 hiAutomatonCegarLoop]: Abstraction has 991 states and 1469 transitions. [2023-11-19 08:06:52,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 991 states and 1469 transitions. [2023-11-19 08:06:52,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 991 to 991. [2023-11-19 08:06:52,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 991 states, 991 states have (on average 1.4823410696266397) internal successors, (1469), 990 states have internal predecessors, (1469), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:52,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 991 states to 991 states and 1469 transitions. [2023-11-19 08:06:52,425 INFO L240 hiAutomatonCegarLoop]: Abstraction has 991 states and 1469 transitions. [2023-11-19 08:06:52,425 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:06:52,426 INFO L428 stractBuchiCegarLoop]: Abstraction has 991 states and 1469 transitions. [2023-11-19 08:06:52,426 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-19 08:06:52,427 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 991 states and 1469 transitions. [2023-11-19 08:06:52,433 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 912 [2023-11-19 08:06:52,433 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:06:52,433 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:06:52,435 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:52,435 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:52,435 INFO L748 eck$LassoCheckResult]: Stem: 7520#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7521#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7623#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7624#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7609#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 7610#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7461#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7462#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7439#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7440#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7688#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7544#L611 assume !(0 == ~M_E~0); 7545#L611-2 assume !(0 == ~T1_E~0); 7701#L616-1 assume !(0 == ~T2_E~0); 7702#L621-1 assume !(0 == ~T3_E~0); 7304#L626-1 assume !(0 == ~T4_E~0); 7305#L631-1 assume !(0 == ~T5_E~0); 7500#L636-1 assume !(0 == ~E_M~0); 7359#L641-1 assume !(0 == ~E_1~0); 7360#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7518#L651-1 assume !(0 == ~E_3~0); 7739#L656-1 assume !(0 == ~E_4~0); 7686#L661-1 assume !(0 == ~E_5~0); 7687#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7718#L304 assume !(1 == ~m_pc~0); 7385#L304-2 is_master_triggered_~__retres1~0#1 := 0; 7281#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7282#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7232#L755 assume !(0 != activate_threads_~tmp~1#1); 7233#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7186#L323 assume 1 == ~t1_pc~0; 7187#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7251#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7252#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7267#L763 assume !(0 != activate_threads_~tmp___0~0#1); 7766#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7254#L342 assume 1 == ~t2_pc~0; 7255#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7391#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7392#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7625#L771 assume !(0 != activate_threads_~tmp___1~0#1); 7681#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7579#L361 assume !(1 == ~t3_pc~0); 7580#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7604#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7204#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7205#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7270#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7271#L380 assume 1 == ~t4_pc~0; 7328#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7329#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7354#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7355#L787 assume !(0 != activate_threads_~tmp___3~0#1); 7612#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7331#L399 assume !(1 == ~t5_pc~0); 7332#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7471#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7476#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7463#L795 assume !(0 != activate_threads_~tmp___4~0#1); 7464#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7751#L679 assume !(1 == ~M_E~0); 7542#L679-2 assume !(1 == ~T1_E~0); 7404#L684-1 assume !(1 == ~T2_E~0); 7405#L689-1 assume !(1 == ~T3_E~0); 7587#L694-1 assume !(1 == ~T4_E~0); 7585#L699-1 assume !(1 == ~T5_E~0); 7586#L704-1 assume !(1 == ~E_M~0); 7568#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7504#L714-1 assume !(1 == ~E_2~0); 7505#L719-1 assume !(1 == ~E_3~0); 7676#L724-1 assume !(1 == ~E_4~0); 7292#L729-1 assume !(1 == ~E_5~0); 7293#L734-1 assume { :end_inline_reset_delta_events } true; 7647#L940-2 [2023-11-19 08:06:52,436 INFO L750 eck$LassoCheckResult]: Loop: 7647#L940-2 assume !false; 7715#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7367#L586-1 assume !false; 7784#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7780#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7777#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7638#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7577#L511 assume !(0 != eval_~tmp~0#1); 7370#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7371#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7640#L611-3 assume !(0 == ~M_E~0); 7294#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7295#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7290#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7239#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7240#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7241#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7242#L641-3 assume !(0 == ~E_1~0); 7306#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7318#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7319#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7562#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7767#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7468#L304-21 assume !(1 == ~m_pc~0); 7321#L304-23 is_master_triggered_~__retres1~0#1 := 0; 7322#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7398#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7399#L755-21 assume !(0 != activate_threads_~tmp~1#1); 7529#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7564#L323-21 assume 1 == ~t1_pc~0; 7201#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7202#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7341#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7342#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7716#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7731#L342-21 assume 1 == ~t2_pc~0; 7227#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7228#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7540#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7541#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7334#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7335#L361-21 assume !(1 == ~t3_pc~0); 7752#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 7753#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7760#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7503#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7237#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7238#L380-21 assume !(1 == ~t4_pc~0); 7300#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 7301#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7375#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7675#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7613#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7449#L399-21 assume 1 == ~t5_pc~0; 7425#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7311#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7602#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7603#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7745#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7230#L679-3 assume !(1 == ~M_E~0); 7231#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8141#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8140#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8139#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8138#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8137#L704-3 assume !(1 == ~E_M~0); 8136#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8135#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8134#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8133#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8132#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8131#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 8118#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 8114#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 8113#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 8112#L959 assume !(0 == start_simulation_~tmp~3#1); 8110#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 8106#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 8103#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7265#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 7266#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7423#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7424#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 7646#L972 assume !(0 != start_simulation_~tmp___0~1#1); 7647#L940-2 [2023-11-19 08:06:52,437 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:52,437 INFO L85 PathProgramCache]: Analyzing trace with hash 1473056580, now seen corresponding path program 1 times [2023-11-19 08:06:52,437 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:52,437 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [37806753] [2023-11-19 08:06:52,437 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:52,438 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:52,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:52,481 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:52,481 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:52,482 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [37806753] [2023-11-19 08:06:52,482 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [37806753] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:52,482 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:52,482 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 08:06:52,482 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [78447021] [2023-11-19 08:06:52,483 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:52,483 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:06:52,483 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:52,483 INFO L85 PathProgramCache]: Analyzing trace with hash -1173500553, now seen corresponding path program 1 times [2023-11-19 08:06:52,484 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:52,484 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2039077913] [2023-11-19 08:06:52,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:52,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:52,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:52,556 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:52,556 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:52,557 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2039077913] [2023-11-19 08:06:52,557 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2039077913] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:52,557 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:52,557 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:06:52,557 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1600161400] [2023-11-19 08:06:52,558 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:52,558 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:06:52,558 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:06:52,559 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:06:52,559 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:06:52,559 INFO L87 Difference]: Start difference. First operand 991 states and 1469 transitions. cyclomatic complexity: 479 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:52,618 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:06:52,618 INFO L93 Difference]: Finished difference Result 991 states and 1447 transitions. [2023-11-19 08:06:52,619 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 991 states and 1447 transitions. [2023-11-19 08:06:52,627 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 912 [2023-11-19 08:06:52,635 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 991 states to 991 states and 1447 transitions. [2023-11-19 08:06:52,635 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 991 [2023-11-19 08:06:52,637 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 991 [2023-11-19 08:06:52,637 INFO L73 IsDeterministic]: Start isDeterministic. Operand 991 states and 1447 transitions. [2023-11-19 08:06:52,639 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:06:52,639 INFO L218 hiAutomatonCegarLoop]: Abstraction has 991 states and 1447 transitions. [2023-11-19 08:06:52,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 991 states and 1447 transitions. [2023-11-19 08:06:52,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 991 to 991. [2023-11-19 08:06:52,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 991 states, 991 states have (on average 1.4601412714429869) internal successors, (1447), 990 states have internal predecessors, (1447), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:52,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 991 states to 991 states and 1447 transitions. [2023-11-19 08:06:52,666 INFO L240 hiAutomatonCegarLoop]: Abstraction has 991 states and 1447 transitions. [2023-11-19 08:06:52,666 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:06:52,667 INFO L428 stractBuchiCegarLoop]: Abstraction has 991 states and 1447 transitions. [2023-11-19 08:06:52,667 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-19 08:06:52,667 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 991 states and 1447 transitions. [2023-11-19 08:06:52,673 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 912 [2023-11-19 08:06:52,674 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:06:52,674 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:06:52,675 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:52,675 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:52,676 INFO L748 eck$LassoCheckResult]: Stem: 9508#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 9509#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9612#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9613#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9598#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 9599#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9449#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9450#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9427#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9428#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9677#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9532#L611 assume !(0 == ~M_E~0); 9533#L611-2 assume !(0 == ~T1_E~0); 9691#L616-1 assume !(0 == ~T2_E~0); 9692#L621-1 assume !(0 == ~T3_E~0); 9298#L626-1 assume !(0 == ~T4_E~0); 9299#L631-1 assume !(0 == ~T5_E~0); 9488#L636-1 assume !(0 == ~E_M~0); 9347#L641-1 assume !(0 == ~E_1~0); 9348#L646-1 assume !(0 == ~E_2~0); 9506#L651-1 assume !(0 == ~E_3~0); 9730#L656-1 assume !(0 == ~E_4~0); 9675#L661-1 assume !(0 == ~E_5~0); 9676#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9709#L304 assume !(1 == ~m_pc~0); 9373#L304-2 is_master_triggered_~__retres1~0#1 := 0; 9269#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9270#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9220#L755 assume !(0 != activate_threads_~tmp~1#1); 9221#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9175#L323 assume 1 == ~t1_pc~0; 9176#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9239#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9240#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9255#L763 assume !(0 != activate_threads_~tmp___0~0#1); 9756#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9242#L342 assume !(1 == ~t2_pc~0); 9244#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9379#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9380#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9614#L771 assume !(0 != activate_threads_~tmp___1~0#1); 9671#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9567#L361 assume !(1 == ~t3_pc~0); 9568#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9592#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9193#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9194#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9258#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9259#L380 assume 1 == ~t4_pc~0; 9316#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9317#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9342#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9343#L787 assume !(0 != activate_threads_~tmp___3~0#1); 9601#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9319#L399 assume !(1 == ~t5_pc~0); 9320#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9459#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9464#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9451#L795 assume !(0 != activate_threads_~tmp___4~0#1); 9452#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9741#L679 assume !(1 == ~M_E~0); 9530#L679-2 assume !(1 == ~T1_E~0); 9392#L684-1 assume !(1 == ~T2_E~0); 9393#L689-1 assume !(1 == ~T3_E~0); 9575#L694-1 assume !(1 == ~T4_E~0); 9573#L699-1 assume !(1 == ~T5_E~0); 9574#L704-1 assume !(1 == ~E_M~0); 9556#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9492#L714-1 assume !(1 == ~E_2~0); 9493#L719-1 assume !(1 == ~E_3~0); 9665#L724-1 assume !(1 == ~E_4~0); 9280#L729-1 assume !(1 == ~E_5~0); 9281#L734-1 assume { :end_inline_reset_delta_events } true; 9635#L940-2 [2023-11-19 08:06:52,676 INFO L750 eck$LassoCheckResult]: Loop: 9635#L940-2 assume !false; 9704#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9355#L586-1 assume !false; 9732#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9736#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9570#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9571#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9766#L511 assume !(0 != eval_~tmp~0#1); 9358#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9359#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9628#L611-3 assume !(0 == ~M_E~0); 9282#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9283#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9278#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9227#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9228#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9229#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9230#L641-3 assume !(0 == ~E_1~0); 9292#L646-3 assume !(0 == ~E_2~0); 9306#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9307#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9550#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9757#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9456#L304-21 assume 1 == ~m_pc~0; 9457#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9310#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9386#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9387#L755-21 assume !(0 != activate_threads_~tmp~1#1); 9517#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9552#L323-21 assume 1 == ~t1_pc~0; 9190#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9191#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9329#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9330#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9705#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9722#L342-21 assume !(1 == ~t2_pc~0); 9217#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 9596#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9528#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9529#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9322#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9323#L361-21 assume 1 == ~t3_pc~0; 9748#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9743#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9749#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9491#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9225#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9226#L380-21 assume 1 == ~t4_pc~0; 9728#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9289#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9363#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9664#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9602#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9437#L399-21 assume !(1 == ~t5_pc~0); 9296#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 9297#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9618#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10041#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9735#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9218#L679-3 assume !(1 == ~M_E~0); 9219#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10080#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10079#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10078#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10077#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10076#L704-3 assume !(1 == ~E_M~0); 10075#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10074#L714-3 assume !(1 == ~E_2~0); 10073#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10072#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10071#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10070#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 10057#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 10053#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 10052#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 10051#L959 assume !(0 == start_simulation_~tmp~3#1); 10049#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 10045#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 10042#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9253#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 9254#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9411#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9412#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 9634#L972 assume !(0 != start_simulation_~tmp___0~1#1); 9635#L940-2 [2023-11-19 08:06:52,677 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:52,677 INFO L85 PathProgramCache]: Analyzing trace with hash -820631741, now seen corresponding path program 1 times [2023-11-19 08:06:52,678 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:52,678 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [836700] [2023-11-19 08:06:52,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:52,678 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:52,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:52,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:52,738 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:52,738 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [836700] [2023-11-19 08:06:52,739 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [836700] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:52,739 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:52,739 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:06:52,739 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1025388593] [2023-11-19 08:06:52,739 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:52,740 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:06:52,740 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:52,740 INFO L85 PathProgramCache]: Analyzing trace with hash 740528630, now seen corresponding path program 1 times [2023-11-19 08:06:52,741 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:52,741 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [277214982] [2023-11-19 08:06:52,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:52,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:52,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:52,782 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:52,782 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:52,783 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [277214982] [2023-11-19 08:06:52,783 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [277214982] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:52,783 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:52,783 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:06:52,783 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [466819021] [2023-11-19 08:06:52,784 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:52,784 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:06:52,784 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:06:52,785 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 08:06:52,785 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 08:06:52,785 INFO L87 Difference]: Start difference. First operand 991 states and 1447 transitions. cyclomatic complexity: 457 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:52,997 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:06:52,997 INFO L93 Difference]: Finished difference Result 2648 states and 3798 transitions. [2023-11-19 08:06:52,997 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2648 states and 3798 transitions. [2023-11-19 08:06:53,019 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2473 [2023-11-19 08:06:53,042 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2648 states to 2648 states and 3798 transitions. [2023-11-19 08:06:53,043 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2648 [2023-11-19 08:06:53,046 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2648 [2023-11-19 08:06:53,046 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2648 states and 3798 transitions. [2023-11-19 08:06:53,050 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:06:53,050 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2648 states and 3798 transitions. [2023-11-19 08:06:53,054 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2648 states and 3798 transitions. [2023-11-19 08:06:53,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2648 to 2488. [2023-11-19 08:06:53,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2488 states, 2488 states have (on average 1.4405144694533762) internal successors, (3584), 2487 states have internal predecessors, (3584), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:53,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2488 states to 2488 states and 3584 transitions. [2023-11-19 08:06:53,112 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2488 states and 3584 transitions. [2023-11-19 08:06:53,113 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 08:06:53,114 INFO L428 stractBuchiCegarLoop]: Abstraction has 2488 states and 3584 transitions. [2023-11-19 08:06:53,114 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-19 08:06:53,114 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2488 states and 3584 transitions. [2023-11-19 08:06:53,129 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2401 [2023-11-19 08:06:53,129 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:06:53,129 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:06:53,131 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:53,131 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:53,131 INFO L748 eck$LassoCheckResult]: Stem: 13162#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 13163#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 13270#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13271#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13254#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 13255#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13103#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13104#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13080#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13081#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13340#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13188#L611 assume !(0 == ~M_E~0); 13189#L611-2 assume !(0 == ~T1_E~0); 13357#L616-1 assume !(0 == ~T2_E~0); 13358#L621-1 assume !(0 == ~T3_E~0); 12945#L626-1 assume !(0 == ~T4_E~0); 12946#L631-1 assume !(0 == ~T5_E~0); 13145#L636-1 assume !(0 == ~E_M~0); 12997#L641-1 assume !(0 == ~E_1~0); 12998#L646-1 assume !(0 == ~E_2~0); 13160#L651-1 assume !(0 == ~E_3~0); 13404#L656-1 assume !(0 == ~E_4~0); 13338#L661-1 assume !(0 == ~E_5~0); 13339#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13380#L304 assume !(1 == ~m_pc~0); 13025#L304-2 is_master_triggered_~__retres1~0#1 := 0; 12919#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12920#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12870#L755 assume !(0 != activate_threads_~tmp~1#1); 12871#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12824#L323 assume !(1 == ~t1_pc~0); 12825#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12887#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12888#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12902#L763 assume !(0 != activate_threads_~tmp___0~0#1); 13438#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12894#L342 assume !(1 == ~t2_pc~0); 12896#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13029#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13030#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13273#L771 assume !(0 != activate_threads_~tmp___1~0#1); 13335#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13221#L361 assume !(1 == ~t3_pc~0); 13222#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13249#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12841#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12842#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12907#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12908#L380 assume 1 == ~t4_pc~0; 12967#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12968#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12993#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12994#L787 assume !(0 != activate_threads_~tmp___3~0#1); 13258#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12970#L399 assume !(1 == ~t5_pc~0); 12971#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13113#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13119#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13105#L795 assume !(0 != activate_threads_~tmp___4~0#1); 13106#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13419#L679 assume !(1 == ~M_E~0); 13186#L679-2 assume !(1 == ~T1_E~0); 13044#L684-1 assume !(1 == ~T2_E~0); 13045#L689-1 assume !(1 == ~T3_E~0); 13230#L694-1 assume !(1 == ~T4_E~0); 13228#L699-1 assume !(1 == ~T5_E~0); 13229#L704-1 assume !(1 == ~E_M~0); 13210#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 13147#L714-1 assume !(1 == ~E_2~0); 13148#L719-1 assume !(1 == ~E_3~0); 13330#L724-1 assume !(1 == ~E_4~0); 12931#L729-1 assume !(1 == ~E_5~0); 12932#L734-1 assume { :end_inline_reset_delta_events } true; 13297#L940-2 [2023-11-19 08:06:53,132 INFO L750 eck$LassoCheckResult]: Loop: 13297#L940-2 assume !false; 13377#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13004#L586-1 assume !false; 13409#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 13413#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 13322#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 13288#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 13218#L511 assume !(0 != eval_~tmp~0#1); 13220#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14955#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13289#L611-3 assume !(0 == ~M_E~0); 12933#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12934#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12930#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12875#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12876#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12877#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12878#L641-3 assume !(0 == ~E_1~0); 12947#L646-3 assume !(0 == ~E_2~0); 12957#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12958#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13204#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13440#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13110#L304-21 assume !(1 == ~m_pc~0); 12960#L304-23 is_master_triggered_~__retres1~0#1 := 0; 12961#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13256#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15169#L755-21 assume !(0 != activate_threads_~tmp~1#1); 15167#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15166#L323-21 assume !(1 == ~t1_pc~0); 15165#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 15164#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15163#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15162#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15161#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15160#L342-21 assume !(1 == ~t2_pc~0); 15158#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 15157#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15156#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15155#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15153#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15152#L361-21 assume 1 == ~t3_pc~0; 15150#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15149#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15148#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15147#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15145#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15143#L380-21 assume !(1 == ~t4_pc~0); 15140#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 15139#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15138#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15137#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15136#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15134#L399-21 assume 1 == ~t5_pc~0; 15131#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15129#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15127#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13441#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13412#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12866#L679-3 assume !(1 == ~M_E~0); 12867#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15118#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15117#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15116#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15115#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15114#L704-3 assume !(1 == ~E_M~0); 15113#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15112#L714-3 assume !(1 == ~E_2~0); 15111#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15110#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15108#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15106#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 12884#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 12885#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 13205#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 15093#L959 assume !(0 == start_simulation_~tmp~3#1); 13446#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 13447#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 14976#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 12900#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 12901#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13063#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13064#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 13296#L972 assume !(0 != start_simulation_~tmp___0~1#1); 13297#L940-2 [2023-11-19 08:06:53,133 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:53,133 INFO L85 PathProgramCache]: Analyzing trace with hash 1077898564, now seen corresponding path program 1 times [2023-11-19 08:06:53,133 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:53,133 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1760533440] [2023-11-19 08:06:53,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:53,158 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:53,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:53,247 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:53,248 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:53,248 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1760533440] [2023-11-19 08:06:53,248 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1760533440] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:53,248 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:53,249 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 08:06:53,249 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1499552721] [2023-11-19 08:06:53,249 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:53,250 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:06:53,250 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:53,250 INFO L85 PathProgramCache]: Analyzing trace with hash -737304200, now seen corresponding path program 1 times [2023-11-19 08:06:53,250 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:53,251 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1565231805] [2023-11-19 08:06:53,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:53,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:53,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:53,297 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:53,297 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:53,297 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1565231805] [2023-11-19 08:06:53,297 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1565231805] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:53,298 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:53,298 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:06:53,298 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [349585366] [2023-11-19 08:06:53,298 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:53,299 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:06:53,299 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:06:53,299 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 08:06:53,300 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 08:06:53,300 INFO L87 Difference]: Start difference. First operand 2488 states and 3584 transitions. cyclomatic complexity: 1098 Second operand has 5 states, 5 states have (on average 14.6) internal successors, (73), 5 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:53,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:06:53,585 INFO L93 Difference]: Finished difference Result 5413 states and 7710 transitions. [2023-11-19 08:06:53,586 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5413 states and 7710 transitions. [2023-11-19 08:06:53,628 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5270 [2023-11-19 08:06:53,674 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5413 states to 5413 states and 7710 transitions. [2023-11-19 08:06:53,674 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5413 [2023-11-19 08:06:53,680 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5413 [2023-11-19 08:06:53,680 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5413 states and 7710 transitions. [2023-11-19 08:06:53,688 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:06:53,688 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5413 states and 7710 transitions. [2023-11-19 08:06:53,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5413 states and 7710 transitions. [2023-11-19 08:06:53,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5413 to 2608. [2023-11-19 08:06:53,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2608 states, 2608 states have (on average 1.4202453987730062) internal successors, (3704), 2607 states have internal predecessors, (3704), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:53,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2608 states to 2608 states and 3704 transitions. [2023-11-19 08:06:53,764 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2608 states and 3704 transitions. [2023-11-19 08:06:53,765 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-19 08:06:53,765 INFO L428 stractBuchiCegarLoop]: Abstraction has 2608 states and 3704 transitions. [2023-11-19 08:06:53,766 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-19 08:06:53,766 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2608 states and 3704 transitions. [2023-11-19 08:06:53,777 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2518 [2023-11-19 08:06:53,777 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:06:53,777 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:06:53,778 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:53,779 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:53,779 INFO L748 eck$LassoCheckResult]: Stem: 21075#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 21076#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 21188#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21189#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21173#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 21174#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21015#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21016#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20991#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20992#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21254#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21101#L611 assume !(0 == ~M_E~0); 21102#L611-2 assume !(0 == ~T1_E~0); 21270#L616-1 assume !(0 == ~T2_E~0); 21271#L621-1 assume !(0 == ~T3_E~0); 20862#L626-1 assume !(0 == ~T4_E~0); 20863#L631-1 assume !(0 == ~T5_E~0); 21056#L636-1 assume !(0 == ~E_M~0); 20911#L641-1 assume !(0 == ~E_1~0); 20912#L646-1 assume !(0 == ~E_2~0); 21073#L651-1 assume !(0 == ~E_3~0); 21323#L656-1 assume !(0 == ~E_4~0); 21252#L661-1 assume !(0 == ~E_5~0); 21253#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21291#L304 assume !(1 == ~m_pc~0); 20940#L304-2 is_master_triggered_~__retres1~0#1 := 0; 20833#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20834#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20787#L755 assume !(0 != activate_threads_~tmp~1#1); 20788#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20742#L323 assume !(1 == ~t1_pc~0); 20743#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20801#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20802#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20816#L763 assume !(0 != activate_threads_~tmp___0~0#1); 21364#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20810#L342 assume !(1 == ~t2_pc~0); 20812#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20942#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20943#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21190#L771 assume !(0 != activate_threads_~tmp___1~0#1); 21246#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21136#L361 assume !(1 == ~t3_pc~0); 21137#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21165#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21342#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21321#L779 assume !(0 != activate_threads_~tmp___2~0#1); 20821#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20822#L380 assume 1 == ~t4_pc~0; 20880#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20881#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20907#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20908#L787 assume !(0 != activate_threads_~tmp___3~0#1); 21176#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20883#L399 assume !(1 == ~t5_pc~0); 20884#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21025#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21030#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21017#L795 assume !(0 != activate_threads_~tmp___4~0#1); 21018#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21337#L679 assume !(1 == ~M_E~0); 21100#L679-2 assume !(1 == ~T1_E~0); 20955#L684-1 assume !(1 == ~T2_E~0); 20956#L689-1 assume !(1 == ~T3_E~0); 21145#L694-1 assume !(1 == ~T4_E~0); 21143#L699-1 assume !(1 == ~T5_E~0); 21144#L704-1 assume !(1 == ~E_M~0); 21126#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 21063#L714-1 assume !(1 == ~E_2~0); 21064#L719-1 assume !(1 == ~E_3~0); 21240#L724-1 assume !(1 == ~E_4~0); 20844#L729-1 assume !(1 == ~E_5~0); 20845#L734-1 assume { :end_inline_reset_delta_events } true; 21343#L940-2 [2023-11-19 08:06:53,780 INFO L750 eck$LassoCheckResult]: Loop: 21343#L940-2 assume !false; 22581#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22577#L586-1 assume !false; 22575#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 22560#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 22554#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 22551#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22542#L511 assume !(0 != eval_~tmp~0#1); 22543#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23310#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23309#L611-3 assume !(0 == ~M_E~0); 23308#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23307#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23306#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23305#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21395#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20791#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20792#L641-3 assume !(0 == ~E_1~0); 20861#L646-3 assume !(0 == ~E_2~0); 20870#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20871#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21118#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21365#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21022#L304-21 assume !(1 == ~m_pc~0); 20873#L304-23 is_master_triggered_~__retres1~0#1 := 0; 20874#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20949#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20950#L755-21 assume !(0 != activate_threads_~tmp~1#1); 21083#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21121#L323-21 assume !(1 == ~t1_pc~0); 21260#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 21261#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20892#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20893#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21289#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21304#L342-21 assume !(1 == ~t2_pc~0); 20779#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 21170#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21092#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21093#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20886#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20887#L361-21 assume 1 == ~t3_pc~0; 21367#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21368#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23227#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23226#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20782#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20783#L380-21 assume !(1 == ~t4_pc~0); 20850#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 20851#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20925#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21237#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21177#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21000#L399-21 assume 1 == ~t5_pc~0; 20976#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20857#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21163#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21164#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21331#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20780#L679-3 assume !(1 == ~M_E~0); 20781#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21068#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20730#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20731#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20770#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20771#L704-3 assume !(1 == ~E_M~0); 21207#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21196#L714-3 assume !(1 == ~E_2~0); 21026#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21027#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21183#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21184#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 20798#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 20799#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 21155#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 21156#L959 assume !(0 == start_simulation_~tmp~3#1); 22650#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 22644#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 22640#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 22638#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 22634#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22608#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22600#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 22592#L972 assume !(0 != start_simulation_~tmp___0~1#1); 21343#L940-2 [2023-11-19 08:06:53,780 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:53,781 INFO L85 PathProgramCache]: Analyzing trace with hash -1293840698, now seen corresponding path program 1 times [2023-11-19 08:06:53,781 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:53,781 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [797010244] [2023-11-19 08:06:53,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:53,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:53,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:53,825 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:53,826 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:53,826 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [797010244] [2023-11-19 08:06:53,826 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [797010244] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:53,826 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:53,826 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 08:06:53,827 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1308605653] [2023-11-19 08:06:53,827 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:53,827 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:06:53,828 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:53,828 INFO L85 PathProgramCache]: Analyzing trace with hash -737304200, now seen corresponding path program 2 times [2023-11-19 08:06:53,828 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:53,828 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1486643167] [2023-11-19 08:06:53,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:53,829 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:53,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:53,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:53,867 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:53,867 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1486643167] [2023-11-19 08:06:53,867 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1486643167] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:53,867 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:53,867 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:06:53,868 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1894319228] [2023-11-19 08:06:53,868 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:53,868 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:06:53,868 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:06:53,869 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:06:53,869 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:06:53,869 INFO L87 Difference]: Start difference. First operand 2608 states and 3704 transitions. cyclomatic complexity: 1098 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:54,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:06:54,000 INFO L93 Difference]: Finished difference Result 4820 states and 6814 transitions. [2023-11-19 08:06:54,001 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4820 states and 6814 transitions. [2023-11-19 08:06:54,031 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4709 [2023-11-19 08:06:54,068 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4820 states to 4820 states and 6814 transitions. [2023-11-19 08:06:54,068 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4820 [2023-11-19 08:06:54,073 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4820 [2023-11-19 08:06:54,074 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4820 states and 6814 transitions. [2023-11-19 08:06:54,081 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:06:54,081 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4820 states and 6814 transitions. [2023-11-19 08:06:54,087 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4820 states and 6814 transitions. [2023-11-19 08:06:54,161 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4820 to 4808. [2023-11-19 08:06:54,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4808 states, 4808 states have (on average 1.4147254575707155) internal successors, (6802), 4807 states have internal predecessors, (6802), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:54,188 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4808 states to 4808 states and 6802 transitions. [2023-11-19 08:06:54,189 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4808 states and 6802 transitions. [2023-11-19 08:06:54,189 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:06:54,190 INFO L428 stractBuchiCegarLoop]: Abstraction has 4808 states and 6802 transitions. [2023-11-19 08:06:54,190 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-19 08:06:54,190 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4808 states and 6802 transitions. [2023-11-19 08:06:54,210 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4697 [2023-11-19 08:06:54,211 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:06:54,211 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:06:54,212 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:54,212 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:54,213 INFO L748 eck$LassoCheckResult]: Stem: 28510#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 28511#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 28622#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28623#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28607#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 28608#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28452#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28453#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28430#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28431#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28689#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28535#L611 assume !(0 == ~M_E~0); 28536#L611-2 assume !(0 == ~T1_E~0); 28705#L616-1 assume !(0 == ~T2_E~0); 28706#L621-1 assume !(0 == ~T3_E~0); 28300#L626-1 assume !(0 == ~T4_E~0); 28301#L631-1 assume !(0 == ~T5_E~0); 28493#L636-1 assume !(0 == ~E_M~0); 28349#L641-1 assume !(0 == ~E_1~0); 28350#L646-1 assume !(0 == ~E_2~0); 28508#L651-1 assume !(0 == ~E_3~0); 28753#L656-1 assume !(0 == ~E_4~0); 28687#L661-1 assume !(0 == ~E_5~0); 28688#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28721#L304 assume !(1 == ~m_pc~0); 28378#L304-2 is_master_triggered_~__retres1~0#1 := 0; 28269#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28270#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 28222#L755 assume !(0 != activate_threads_~tmp~1#1); 28223#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28177#L323 assume !(1 == ~t1_pc~0); 28178#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28236#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28237#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 28252#L763 assume !(0 != activate_threads_~tmp___0~0#1); 28784#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28246#L342 assume !(1 == ~t2_pc~0); 28248#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28380#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28381#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 28624#L771 assume !(0 != activate_threads_~tmp___1~0#1); 28684#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28573#L361 assume !(1 == ~t3_pc~0); 28574#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 28601#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28190#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28191#L779 assume !(0 != activate_threads_~tmp___2~0#1); 28257#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28258#L380 assume !(1 == ~t4_pc~0); 28572#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28698#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28344#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28345#L787 assume !(0 != activate_threads_~tmp___3~0#1); 28610#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28319#L399 assume !(1 == ~t5_pc~0); 28320#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28463#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28467#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28454#L795 assume !(0 != activate_threads_~tmp___4~0#1); 28455#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28763#L679 assume !(1 == ~M_E~0); 28534#L679-2 assume !(1 == ~T1_E~0); 28393#L684-1 assume !(1 == ~T2_E~0); 28394#L689-1 assume !(1 == ~T3_E~0); 28582#L694-1 assume !(1 == ~T4_E~0); 28580#L699-1 assume !(1 == ~T5_E~0); 28581#L704-1 assume !(1 == ~E_M~0); 28560#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 28498#L714-1 assume !(1 == ~E_2~0); 28499#L719-1 assume !(1 == ~E_3~0); 28679#L724-1 assume !(1 == ~E_4~0); 28281#L729-1 assume !(1 == ~E_5~0); 28282#L734-1 assume { :end_inline_reset_delta_events } true; 28766#L940-2 [2023-11-19 08:06:54,213 INFO L750 eck$LassoCheckResult]: Loop: 28766#L940-2 assume !false; 30862#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30855#L586-1 assume !false; 30850#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 30844#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 30835#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 30833#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 30830#L511 assume !(0 != eval_~tmp~0#1); 30827#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30825#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30823#L611-3 assume !(0 == ~M_E~0); 30821#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30819#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30817#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30815#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30813#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30811#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 30809#L641-3 assume !(0 == ~E_1~0); 30807#L646-3 assume !(0 == ~E_2~0); 30805#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30803#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30801#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30799#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30797#L304-21 assume !(1 == ~m_pc~0); 30795#L304-23 is_master_triggered_~__retres1~0#1 := 0; 30793#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30791#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30789#L755-21 assume !(0 != activate_threads_~tmp~1#1); 30787#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30785#L323-21 assume !(1 == ~t1_pc~0); 30783#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 30781#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30779#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30777#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30775#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30773#L342-21 assume !(1 == ~t2_pc~0); 30769#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 30767#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30765#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30763#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30761#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30759#L361-21 assume 1 == ~t3_pc~0; 30756#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30752#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30748#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30744#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30741#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30739#L380-21 assume !(1 == ~t4_pc~0); 30737#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 30735#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30733#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30731#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30729#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30727#L399-21 assume 1 == ~t5_pc~0; 30724#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30721#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30719#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30717#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30715#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30713#L679-3 assume !(1 == ~M_E~0); 30710#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30709#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30707#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30704#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30697#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30690#L704-3 assume !(1 == ~E_M~0); 30662#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30655#L714-3 assume !(1 == ~E_2~0); 30654#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30653#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30652#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30650#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 30651#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 30636#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 30103#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 30081#L959 assume !(0 == start_simulation_~tmp~3#1); 30082#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 31072#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 30908#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 30904#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 30902#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30900#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30896#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 30894#L972 assume !(0 != start_simulation_~tmp___0~1#1); 28766#L940-2 [2023-11-19 08:06:54,214 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:54,215 INFO L85 PathProgramCache]: Analyzing trace with hash 943522567, now seen corresponding path program 1 times [2023-11-19 08:06:54,215 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:54,215 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [258594400] [2023-11-19 08:06:54,215 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:54,215 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:54,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:54,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:54,276 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:54,276 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [258594400] [2023-11-19 08:06:54,276 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [258594400] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:54,276 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:54,276 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:06:54,277 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [336572206] [2023-11-19 08:06:54,277 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:54,277 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:06:54,277 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:54,278 INFO L85 PathProgramCache]: Analyzing trace with hash -737304200, now seen corresponding path program 3 times [2023-11-19 08:06:54,278 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:54,278 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1349297549] [2023-11-19 08:06:54,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:54,278 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:54,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:54,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:54,317 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:54,318 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1349297549] [2023-11-19 08:06:54,318 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1349297549] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:54,318 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:54,318 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:06:54,318 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [650595204] [2023-11-19 08:06:54,318 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:54,319 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:06:54,319 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:06:54,319 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 08:06:54,320 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 08:06:54,320 INFO L87 Difference]: Start difference. First operand 4808 states and 6802 transitions. cyclomatic complexity: 1998 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:54,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:06:54,478 INFO L93 Difference]: Finished difference Result 7654 states and 10754 transitions. [2023-11-19 08:06:54,479 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7654 states and 10754 transitions. [2023-11-19 08:06:54,575 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7429 [2023-11-19 08:06:54,621 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7654 states to 7654 states and 10754 transitions. [2023-11-19 08:06:54,622 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7654 [2023-11-19 08:06:54,630 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7654 [2023-11-19 08:06:54,631 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7654 states and 10754 transitions. [2023-11-19 08:06:54,643 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:06:54,643 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7654 states and 10754 transitions. [2023-11-19 08:06:54,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7654 states and 10754 transitions. [2023-11-19 08:06:54,767 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7654 to 5537. [2023-11-19 08:06:54,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5537 states, 5537 states have (on average 1.4081632653061225) internal successors, (7797), 5536 states have internal predecessors, (7797), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:54,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5537 states to 5537 states and 7797 transitions. [2023-11-19 08:06:54,801 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5537 states and 7797 transitions. [2023-11-19 08:06:54,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 08:06:54,802 INFO L428 stractBuchiCegarLoop]: Abstraction has 5537 states and 7797 transitions. [2023-11-19 08:06:54,802 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-19 08:06:54,802 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5537 states and 7797 transitions. [2023-11-19 08:06:54,831 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5371 [2023-11-19 08:06:54,831 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:06:54,831 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:06:54,833 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:54,833 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:54,834 INFO L748 eck$LassoCheckResult]: Stem: 40989#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 40990#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 41096#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41097#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41079#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 41080#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40924#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40925#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40899#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40900#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41161#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41013#L611 assume !(0 == ~M_E~0); 41014#L611-2 assume !(0 == ~T1_E~0); 41178#L616-1 assume !(0 == ~T2_E~0); 41179#L621-1 assume !(0 == ~T3_E~0); 40761#L626-1 assume !(0 == ~T4_E~0); 40762#L631-1 assume !(0 == ~T5_E~0); 40965#L636-1 assume !(0 == ~E_M~0); 40815#L641-1 assume 0 == ~E_1~0;~E_1~0 := 1; 40816#L646-1 assume !(0 == ~E_2~0); 41259#L651-1 assume !(0 == ~E_3~0); 41260#L656-1 assume !(0 == ~E_4~0); 41338#L661-1 assume !(0 == ~E_5~0); 41337#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41336#L304 assume !(1 == ~m_pc~0); 41335#L304-2 is_master_triggered_~__retres1~0#1 := 0; 41334#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40931#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 40688#L755 assume !(0 != activate_threads_~tmp~1#1); 40689#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40645#L323 assume !(1 == ~t1_pc~0); 40646#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41038#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41331#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 41330#L763 assume !(0 != activate_threads_~tmp___0~0#1); 41329#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40710#L342 assume !(1 == ~t2_pc~0); 40712#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41324#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41098#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 41099#L771 assume !(0 != activate_threads_~tmp___1~0#1); 41155#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41048#L361 assume !(1 == ~t3_pc~0); 41049#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41073#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40661#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 40662#L779 assume !(0 != activate_threads_~tmp___2~0#1); 40725#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40726#L380 assume !(1 == ~t4_pc~0); 41047#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41308#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40808#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 40809#L787 assume !(0 != activate_threads_~tmp___3~0#1); 41307#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40786#L399 assume !(1 == ~t5_pc~0); 40787#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 41306#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40940#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 40941#L795 assume !(0 != activate_threads_~tmp___4~0#1); 41305#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41278#L679 assume !(1 == ~M_E~0); 41011#L679-2 assume !(1 == ~T1_E~0); 40861#L684-1 assume !(1 == ~T2_E~0); 40862#L689-1 assume !(1 == ~T3_E~0); 41056#L694-1 assume !(1 == ~T4_E~0); 41301#L699-1 assume !(1 == ~T5_E~0); 41300#L704-1 assume !(1 == ~E_M~0); 41299#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 40971#L714-1 assume !(1 == ~E_2~0); 40972#L719-1 assume !(1 == ~E_3~0); 41151#L724-1 assume !(1 == ~E_4~0); 40749#L729-1 assume !(1 == ~E_5~0); 40750#L734-1 assume { :end_inline_reset_delta_events } true; 41243#L940-2 [2023-11-19 08:06:54,835 INFO L750 eck$LassoCheckResult]: Loop: 41243#L940-2 assume !false; 45454#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45452#L586-1 assume !false; 45436#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 45381#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 45377#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 45375#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 45367#L511 assume !(0 != eval_~tmp~0#1); 45368#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41207#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41112#L611-3 assume !(0 == ~M_E~0); 40751#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40752#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 40747#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40695#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40696#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40697#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 40698#L641-3 assume !(0 == ~E_1~0); 40763#L646-3 assume !(0 == ~E_2~0); 40776#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40777#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 41030#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 41262#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40932#L304-21 assume !(1 == ~m_pc~0); 40779#L304-23 is_master_triggered_~__retres1~0#1 := 0; 40780#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46112#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 46111#L755-21 assume !(0 != activate_threads_~tmp~1#1); 46008#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46007#L323-21 assume !(1 == ~t1_pc~0); 46004#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 46003#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46002#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 46001#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46000#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45999#L342-21 assume !(1 == ~t2_pc~0); 45997#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 45996#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45995#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 45994#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45992#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45993#L361-21 assume !(1 == ~t3_pc~0); 46083#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 46081#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46079#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 46077#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 46074#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46072#L380-21 assume !(1 == ~t4_pc~0); 46070#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 46068#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46066#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 46064#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46062#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46059#L399-21 assume !(1 == ~t5_pc~0); 40768#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 40769#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41071#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41072#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41233#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40686#L679-3 assume !(1 == ~M_E~0); 40687#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40981#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40637#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40638#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46047#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 46046#L704-3 assume !(1 == ~E_M~0); 41197#L709-3 assume !(1 == ~E_1~0); 41198#L714-3 assume !(1 == ~E_2~0); 45774#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45773#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44869#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43539#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 40703#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 40704#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 41031#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 41066#L959 assume !(0 == start_simulation_~tmp~3#1); 41070#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 45484#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 45480#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 45478#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 45475#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 45473#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 45471#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 45469#L972 assume !(0 != start_simulation_~tmp___0~1#1); 41243#L940-2 [2023-11-19 08:06:54,836 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:54,836 INFO L85 PathProgramCache]: Analyzing trace with hash -443262843, now seen corresponding path program 1 times [2023-11-19 08:06:54,836 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:54,837 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [57171064] [2023-11-19 08:06:54,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:54,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:54,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:54,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:54,899 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:54,899 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [57171064] [2023-11-19 08:06:54,899 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [57171064] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:54,899 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:54,900 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:06:54,900 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [928027496] [2023-11-19 08:06:54,900 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:54,901 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:06:54,901 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:54,901 INFO L85 PathProgramCache]: Analyzing trace with hash -154789446, now seen corresponding path program 1 times [2023-11-19 08:06:54,902 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:54,902 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1636045644] [2023-11-19 08:06:54,902 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:54,902 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:54,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:54,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:54,948 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:54,949 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1636045644] [2023-11-19 08:06:54,949 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1636045644] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:54,949 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:54,949 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:06:54,950 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1494639699] [2023-11-19 08:06:54,950 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:54,950 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:06:54,951 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:06:54,951 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 08:06:54,951 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 08:06:54,951 INFO L87 Difference]: Start difference. First operand 5537 states and 7797 transitions. cyclomatic complexity: 2264 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:55,094 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:06:55,094 INFO L93 Difference]: Finished difference Result 6778 states and 9497 transitions. [2023-11-19 08:06:55,094 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6778 states and 9497 transitions. [2023-11-19 08:06:55,260 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6613 [2023-11-19 08:06:55,300 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6778 states to 6778 states and 9497 transitions. [2023-11-19 08:06:55,300 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6778 [2023-11-19 08:06:55,308 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6778 [2023-11-19 08:06:55,308 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6778 states and 9497 transitions. [2023-11-19 08:06:55,319 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:06:55,319 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6778 states and 9497 transitions. [2023-11-19 08:06:55,328 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6778 states and 9497 transitions. [2023-11-19 08:06:55,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6778 to 4808. [2023-11-19 08:06:55,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4808 states, 4808 states have (on average 1.401830282861897) internal successors, (6740), 4807 states have internal predecessors, (6740), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:55,450 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4808 states to 4808 states and 6740 transitions. [2023-11-19 08:06:55,451 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4808 states and 6740 transitions. [2023-11-19 08:06:55,451 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 08:06:55,453 INFO L428 stractBuchiCegarLoop]: Abstraction has 4808 states and 6740 transitions. [2023-11-19 08:06:55,454 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-19 08:06:55,454 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4808 states and 6740 transitions. [2023-11-19 08:06:55,476 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4697 [2023-11-19 08:06:55,476 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:06:55,476 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:06:55,478 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:55,478 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:55,478 INFO L748 eck$LassoCheckResult]: Stem: 53304#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 53305#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 53416#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53417#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53399#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 53400#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53244#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53245#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53223#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53224#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53486#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53330#L611 assume !(0 == ~M_E~0); 53331#L611-2 assume !(0 == ~T1_E~0); 53504#L616-1 assume !(0 == ~T2_E~0); 53505#L621-1 assume !(0 == ~T3_E~0); 53092#L626-1 assume !(0 == ~T4_E~0); 53093#L631-1 assume !(0 == ~T5_E~0); 53285#L636-1 assume !(0 == ~E_M~0); 53142#L641-1 assume !(0 == ~E_1~0); 53143#L646-1 assume !(0 == ~E_2~0); 53301#L651-1 assume !(0 == ~E_3~0); 53547#L656-1 assume !(0 == ~E_4~0); 53484#L661-1 assume !(0 == ~E_5~0); 53485#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53520#L304 assume !(1 == ~m_pc~0); 53170#L304-2 is_master_triggered_~__retres1~0#1 := 0; 53063#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53064#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 53018#L755 assume !(0 != activate_threads_~tmp~1#1); 53019#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52974#L323 assume !(1 == ~t1_pc~0); 52975#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 53031#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53032#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 53047#L763 assume !(0 != activate_threads_~tmp___0~0#1); 53584#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53041#L342 assume !(1 == ~t2_pc~0); 53043#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 53172#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53173#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 53420#L771 assume !(0 != activate_threads_~tmp___1~0#1); 53479#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53365#L361 assume !(1 == ~t3_pc~0); 53366#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53392#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52986#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 52987#L779 assume !(0 != activate_threads_~tmp___2~0#1); 53052#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53053#L380 assume !(1 == ~t4_pc~0); 53364#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 53497#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53137#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 53138#L787 assume !(0 != activate_threads_~tmp___3~0#1); 53404#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53111#L399 assume !(1 == ~t5_pc~0); 53112#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 53254#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53258#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 53246#L795 assume !(0 != activate_threads_~tmp___4~0#1); 53247#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53559#L679 assume !(1 == ~M_E~0); 53329#L679-2 assume !(1 == ~T1_E~0); 53186#L684-1 assume !(1 == ~T2_E~0); 53187#L689-1 assume !(1 == ~T3_E~0); 53374#L694-1 assume !(1 == ~T4_E~0); 53372#L699-1 assume !(1 == ~T5_E~0); 53373#L704-1 assume !(1 == ~E_M~0); 53353#L709-1 assume !(1 == ~E_1~0); 53290#L714-1 assume !(1 == ~E_2~0); 53291#L719-1 assume !(1 == ~E_3~0); 53473#L724-1 assume !(1 == ~E_4~0); 53074#L729-1 assume !(1 == ~E_5~0); 53075#L734-1 assume { :end_inline_reset_delta_events } true; 53563#L940-2 [2023-11-19 08:06:55,479 INFO L750 eck$LassoCheckResult]: Loop: 53563#L940-2 assume !false; 57309#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53147#L586-1 assume !false; 57306#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 53602#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 53368#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 53369#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 53362#L511 assume !(0 != eval_~tmp~0#1); 53363#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 57769#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 57768#L611-3 assume !(0 == ~M_E~0); 57767#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 57766#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 57765#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 57764#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 57763#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 57762#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 57761#L641-3 assume !(0 == ~E_1~0); 57760#L646-3 assume !(0 == ~E_2~0); 57759#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 57758#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 57757#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 57756#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57749#L304-21 assume !(1 == ~m_pc~0); 57748#L304-23 is_master_triggered_~__retres1~0#1 := 0; 53401#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53180#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 53181#L755-21 assume !(0 != activate_threads_~tmp~1#1); 53313#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53348#L323-21 assume !(1 == ~t1_pc~0); 53582#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 57755#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57754#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 57753#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 57752#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57636#L342-21 assume !(1 == ~t2_pc~0); 57633#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 57631#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 57629#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 57626#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 57625#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 57624#L361-21 assume !(1 == ~t3_pc~0); 57622#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 57620#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 57618#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 57617#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 57615#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57614#L380-21 assume !(1 == ~t4_pc~0); 57613#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 57612#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57611#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 53470#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53405#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53232#L399-21 assume 1 == ~t5_pc~0; 53208#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53087#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53390#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 53391#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 53587#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57546#L679-3 assume !(1 == ~M_E~0); 56021#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 57545#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 57544#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 57543#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 57541#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 57540#L704-3 assume !(1 == ~E_M~0); 57539#L709-3 assume !(1 == ~E_1~0); 57538#L714-3 assume !(1 == ~E_2~0); 57537#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 57536#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 57535#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 57534#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 57530#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 57527#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 57525#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 53388#L959 assume !(0 == start_simulation_~tmp~3#1); 53389#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 57326#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 57321#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 57318#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 57317#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 57316#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 57314#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 57312#L972 assume !(0 != start_simulation_~tmp___0~1#1); 53563#L940-2 [2023-11-19 08:06:55,479 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:55,479 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 1 times [2023-11-19 08:06:55,480 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:55,480 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1566023519] [2023-11-19 08:06:55,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:55,481 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:55,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:06:55,495 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 08:06:55,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:06:55,555 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 08:06:55,556 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:55,556 INFO L85 PathProgramCache]: Analyzing trace with hash 1616681529, now seen corresponding path program 1 times [2023-11-19 08:06:55,557 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:55,557 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [37178552] [2023-11-19 08:06:55,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:55,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:55,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:55,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:55,605 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:55,605 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [37178552] [2023-11-19 08:06:55,605 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [37178552] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:55,605 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:55,605 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:06:55,605 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [152243452] [2023-11-19 08:06:55,606 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:55,606 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:06:55,606 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:06:55,607 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:06:55,607 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:06:55,608 INFO L87 Difference]: Start difference. First operand 4808 states and 6740 transitions. cyclomatic complexity: 1936 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:55,797 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:06:55,797 INFO L93 Difference]: Finished difference Result 7801 states and 10858 transitions. [2023-11-19 08:06:55,797 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7801 states and 10858 transitions. [2023-11-19 08:06:55,853 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7627 [2023-11-19 08:06:55,891 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7801 states to 7801 states and 10858 transitions. [2023-11-19 08:06:55,891 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7801 [2023-11-19 08:06:55,900 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7801 [2023-11-19 08:06:55,901 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7801 states and 10858 transitions. [2023-11-19 08:06:55,910 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:06:55,910 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7801 states and 10858 transitions. [2023-11-19 08:06:55,921 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7801 states and 10858 transitions. [2023-11-19 08:06:56,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7801 to 7793. [2023-11-19 08:06:56,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7793 states, 7793 states have (on average 1.3922751186962659) internal successors, (10850), 7792 states have internal predecessors, (10850), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:56,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7793 states to 7793 states and 10850 transitions. [2023-11-19 08:06:56,112 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7793 states and 10850 transitions. [2023-11-19 08:06:56,113 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:06:56,114 INFO L428 stractBuchiCegarLoop]: Abstraction has 7793 states and 10850 transitions. [2023-11-19 08:06:56,114 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-19 08:06:56,114 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7793 states and 10850 transitions. [2023-11-19 08:06:56,155 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7619 [2023-11-19 08:06:56,155 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:06:56,155 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:06:56,157 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:56,157 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:56,158 INFO L748 eck$LassoCheckResult]: Stem: 65930#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 65931#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 66047#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 66048#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 66031#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 66032#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 65864#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 65865#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 65841#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 65842#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 66123#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 65956#L611 assume !(0 == ~M_E~0); 65957#L611-2 assume !(0 == ~T1_E~0); 66139#L616-1 assume !(0 == ~T2_E~0); 66140#L621-1 assume !(0 == ~T3_E~0); 65703#L626-1 assume !(0 == ~T4_E~0); 65704#L631-1 assume !(0 == ~T5_E~0); 65904#L636-1 assume 0 == ~E_M~0;~E_M~0 := 1; 65905#L641-1 assume !(0 == ~E_1~0); 66294#L646-1 assume !(0 == ~E_2~0); 66211#L651-1 assume !(0 == ~E_3~0); 66212#L656-1 assume !(0 == ~E_4~0); 66121#L661-1 assume !(0 == ~E_5~0); 66122#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66234#L304 assume !(1 == ~m_pc~0); 65782#L304-2 is_master_triggered_~__retres1~0#1 := 0; 65680#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65681#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 65628#L755 assume !(0 != activate_threads_~tmp~1#1); 65629#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65585#L323 assume !(1 == ~t1_pc~0); 65586#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 65647#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65648#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 66283#L763 assume !(0 != activate_threads_~tmp___0~0#1); 66282#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65651#L342 assume !(1 == ~t2_pc~0); 65653#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 66280#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66049#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 66050#L771 assume !(0 != activate_threads_~tmp___1~0#1); 66116#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65991#L361 assume !(1 == ~t3_pc~0); 65992#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 66020#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65601#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 65602#L779 assume !(0 != activate_threads_~tmp___2~0#1); 65670#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65671#L380 assume !(1 == ~t4_pc~0); 65990#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 66268#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66267#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 66035#L787 assume !(0 != activate_threads_~tmp___3~0#1); 66036#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65726#L399 assume !(1 == ~t5_pc~0); 65727#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 65874#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65879#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 65866#L795 assume !(0 != activate_threads_~tmp___4~0#1); 65867#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66196#L679 assume !(1 == ~M_E~0); 66258#L679-2 assume !(1 == ~T1_E~0); 66257#L684-1 assume !(1 == ~T2_E~0); 66256#L689-1 assume !(1 == ~T3_E~0); 66241#L694-1 assume !(1 == ~T4_E~0); 65998#L699-1 assume !(1 == ~T5_E~0); 65999#L704-1 assume 1 == ~E_M~0;~E_M~0 := 2; 65979#L709-1 assume !(1 == ~E_1~0); 65909#L714-1 assume !(1 == ~E_2~0); 65910#L719-1 assume !(1 == ~E_3~0); 66109#L724-1 assume !(1 == ~E_4~0); 65691#L729-1 assume !(1 == ~E_5~0); 65692#L734-1 assume { :end_inline_reset_delta_events } true; 66199#L940-2 [2023-11-19 08:06:56,158 INFO L750 eck$LassoCheckResult]: Loop: 66199#L940-2 assume !false; 69297#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 69295#L586-1 assume !false; 69293#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 69294#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 69625#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 69624#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 69623#L511 assume !(0 != eval_~tmp~0#1); 65767#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 65768#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 66065#L611-3 assume !(0 == ~M_E~0); 65693#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 65694#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 65689#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 65634#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 65635#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 65636#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 65637#L641-3 assume !(0 == ~E_1~0); 65705#L646-3 assume !(0 == ~E_2~0); 65716#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 65717#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 65972#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 66214#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 73364#L304-21 assume !(1 == ~m_pc~0); 73363#L304-23 is_master_triggered_~__retres1~0#1 := 0; 73362#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 73361#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 73360#L755-21 assume !(0 != activate_threads_~tmp~1#1); 73359#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 73358#L323-21 assume !(1 == ~t1_pc~0); 73357#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 73356#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73355#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 73354#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 73353#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 73296#L342-21 assume !(1 == ~t2_pc~0); 73293#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 73291#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 73289#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 73287#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 73285#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 73283#L361-21 assume 1 == ~t3_pc~0; 73281#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 73282#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 73300#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 73272#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 73270#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 73269#L380-21 assume !(1 == ~t4_pc~0); 73268#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 73267#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 73156#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 72689#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 72688#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 72685#L399-21 assume !(1 == ~t5_pc~0); 72687#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 72680#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 72681#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 72675#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 72676#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 72671#L679-3 assume !(1 == ~M_E~0); 69862#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 72727#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 65577#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 65578#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 72726#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 66070#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 66071#L709-3 assume !(1 == ~E_1~0); 66057#L714-3 assume !(1 == ~E_2~0); 65876#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 65614#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 65615#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 66043#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 66089#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 69482#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 69479#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 69477#L959 assume !(0 == start_simulation_~tmp~3#1); 69473#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 69474#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 69684#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 69446#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 69447#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69440#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69441#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 69435#L972 assume !(0 != start_simulation_~tmp___0~1#1); 66199#L940-2 [2023-11-19 08:06:56,159 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:56,159 INFO L85 PathProgramCache]: Analyzing trace with hash -814901243, now seen corresponding path program 1 times [2023-11-19 08:06:56,159 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:56,160 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [838590731] [2023-11-19 08:06:56,160 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:56,160 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:56,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:56,233 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:56,233 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:56,234 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [838590731] [2023-11-19 08:06:56,234 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [838590731] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:56,234 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:56,234 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:06:56,234 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1687118873] [2023-11-19 08:06:56,234 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:56,237 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:06:56,238 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:56,238 INFO L85 PathProgramCache]: Analyzing trace with hash 1480991157, now seen corresponding path program 1 times [2023-11-19 08:06:56,238 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:56,238 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1347390357] [2023-11-19 08:06:56,239 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:56,239 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:56,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:56,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:56,330 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:56,330 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1347390357] [2023-11-19 08:06:56,330 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1347390357] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:56,331 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:56,331 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 08:06:56,331 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1101982905] [2023-11-19 08:06:56,331 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:56,332 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:06:56,332 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:06:56,333 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 08:06:56,333 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 08:06:56,333 INFO L87 Difference]: Start difference. First operand 7793 states and 10850 transitions. cyclomatic complexity: 3061 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:56,490 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:06:56,491 INFO L93 Difference]: Finished difference Result 10657 states and 14827 transitions. [2023-11-19 08:06:56,491 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10657 states and 14827 transitions. [2023-11-19 08:06:56,541 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 10242 [2023-11-19 08:06:56,646 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10657 states to 10657 states and 14827 transitions. [2023-11-19 08:06:56,647 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10657 [2023-11-19 08:06:56,657 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10657 [2023-11-19 08:06:56,657 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10657 states and 14827 transitions. [2023-11-19 08:06:56,666 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:06:56,666 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10657 states and 14827 transitions. [2023-11-19 08:06:56,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10657 states and 14827 transitions. [2023-11-19 08:06:56,765 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10657 to 7516. [2023-11-19 08:06:56,776 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7516 states, 7516 states have (on average 1.391564662054284) internal successors, (10459), 7515 states have internal predecessors, (10459), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:56,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7516 states to 7516 states and 10459 transitions. [2023-11-19 08:06:56,795 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7516 states and 10459 transitions. [2023-11-19 08:06:56,795 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 08:06:56,796 INFO L428 stractBuchiCegarLoop]: Abstraction has 7516 states and 10459 transitions. [2023-11-19 08:06:56,796 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-19 08:06:56,796 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7516 states and 10459 transitions. [2023-11-19 08:06:56,820 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7397 [2023-11-19 08:06:56,820 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:06:56,820 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:06:56,822 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:56,822 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:56,822 INFO L748 eck$LassoCheckResult]: Stem: 84387#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 84388#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 84500#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 84501#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 84486#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 84487#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 84325#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 84326#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 84302#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 84303#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 84568#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 84414#L611 assume !(0 == ~M_E~0); 84415#L611-2 assume !(0 == ~T1_E~0); 84587#L616-1 assume !(0 == ~T2_E~0); 84588#L621-1 assume !(0 == ~T3_E~0); 84168#L626-1 assume !(0 == ~T4_E~0); 84169#L631-1 assume !(0 == ~T5_E~0); 84368#L636-1 assume !(0 == ~E_M~0); 84216#L641-1 assume !(0 == ~E_1~0); 84217#L646-1 assume !(0 == ~E_2~0); 84384#L651-1 assume !(0 == ~E_3~0); 84622#L656-1 assume !(0 == ~E_4~0); 84566#L661-1 assume !(0 == ~E_5~0); 84567#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 84605#L304 assume !(1 == ~m_pc~0); 84247#L304-2 is_master_triggered_~__retres1~0#1 := 0; 84140#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84141#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 84094#L755 assume !(0 != activate_threads_~tmp~1#1); 84095#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84049#L323 assume !(1 == ~t1_pc~0); 84050#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 84108#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 84109#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 84125#L763 assume !(0 != activate_threads_~tmp___0~0#1); 84653#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84116#L342 assume !(1 == ~t2_pc~0); 84118#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 84249#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 84250#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 84504#L771 assume !(0 != activate_threads_~tmp___1~0#1); 84563#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 84451#L361 assume !(1 == ~t3_pc~0); 84452#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 84479#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 84063#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 84064#L779 assume !(0 != activate_threads_~tmp___2~0#1); 84130#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 84131#L380 assume !(1 == ~t4_pc~0); 84450#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 84576#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84212#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 84213#L787 assume !(0 != activate_threads_~tmp___3~0#1); 84489#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 84186#L399 assume !(1 == ~t5_pc~0); 84187#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 84336#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 84342#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 84327#L795 assume !(0 != activate_threads_~tmp___4~0#1); 84328#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84632#L679 assume !(1 == ~M_E~0); 84413#L679-2 assume !(1 == ~T1_E~0); 84264#L684-1 assume !(1 == ~T2_E~0); 84265#L689-1 assume !(1 == ~T3_E~0); 84460#L694-1 assume !(1 == ~T4_E~0); 84458#L699-1 assume !(1 == ~T5_E~0); 84459#L704-1 assume !(1 == ~E_M~0); 84439#L709-1 assume !(1 == ~E_1~0); 84370#L714-1 assume !(1 == ~E_2~0); 84371#L719-1 assume !(1 == ~E_3~0); 84557#L724-1 assume !(1 == ~E_4~0); 84151#L729-1 assume !(1 == ~E_5~0); 84152#L734-1 assume { :end_inline_reset_delta_events } true; 84526#L940-2 [2023-11-19 08:06:56,822 INFO L750 eck$LassoCheckResult]: Loop: 84526#L940-2 assume !false; 84546#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 84503#L586-1 assume !false; 84625#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 84629#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 88841#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 88839#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 88836#L511 assume !(0 != eval_~tmp~0#1); 88833#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 88831#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 88829#L611-3 assume !(0 == ~M_E~0); 88827#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 88825#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 88823#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 88819#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 88817#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 88815#L636-3 assume !(0 == ~E_M~0); 88813#L641-3 assume !(0 == ~E_1~0); 88810#L646-3 assume !(0 == ~E_2~0); 88808#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 88806#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 88803#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 88801#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88799#L304-21 assume !(1 == ~m_pc~0); 88797#L304-23 is_master_triggered_~__retres1~0#1 := 0; 88795#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88793#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 88792#L755-21 assume !(0 != activate_threads_~tmp~1#1); 88789#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88787#L323-21 assume !(1 == ~t1_pc~0); 88785#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 88783#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88781#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 88779#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 88778#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88776#L342-21 assume !(1 == ~t2_pc~0); 88773#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 88771#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88769#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 88766#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 88764#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88762#L361-21 assume 1 == ~t3_pc~0; 88759#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 88757#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88755#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 88751#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 88749#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88747#L380-21 assume !(1 == ~t4_pc~0); 88745#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 88742#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88740#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 88738#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 88736#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88734#L399-21 assume !(1 == ~t5_pc~0); 88731#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 88728#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88726#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 88724#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 88722#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88720#L679-3 assume !(1 == ~M_E~0); 88476#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 88709#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 88704#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 84871#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 84864#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 84857#L704-3 assume !(1 == ~E_M~0); 84851#L709-3 assume !(1 == ~E_1~0); 84845#L714-3 assume !(1 == ~E_2~0); 84839#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 84833#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 84830#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 84829#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 84822#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 84811#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 84807#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 84803#L959 assume !(0 == start_simulation_~tmp~3#1); 84545#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 84372#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 84373#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 84123#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 84124#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 84285#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 84286#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 84525#L972 assume !(0 != start_simulation_~tmp___0~1#1); 84526#L940-2 [2023-11-19 08:06:56,823 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:56,823 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 2 times [2023-11-19 08:06:56,823 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:56,824 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [968056264] [2023-11-19 08:06:56,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:56,824 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:56,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:06:56,835 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 08:06:56,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:06:56,876 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 08:06:56,876 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:56,877 INFO L85 PathProgramCache]: Analyzing trace with hash 745987573, now seen corresponding path program 1 times [2023-11-19 08:06:56,877 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:56,877 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1642526353] [2023-11-19 08:06:56,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:56,877 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:56,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:56,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:56,941 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:56,941 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1642526353] [2023-11-19 08:06:56,941 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1642526353] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:56,941 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:56,941 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 08:06:56,942 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [635935572] [2023-11-19 08:06:56,942 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:56,942 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:06:56,942 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:06:56,943 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 08:06:56,943 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 08:06:56,943 INFO L87 Difference]: Start difference. First operand 7516 states and 10459 transitions. cyclomatic complexity: 2947 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:57,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:06:57,146 INFO L93 Difference]: Finished difference Result 13527 states and 18620 transitions. [2023-11-19 08:06:57,147 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13527 states and 18620 transitions. [2023-11-19 08:06:57,329 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13368 [2023-11-19 08:06:57,388 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13527 states to 13527 states and 18620 transitions. [2023-11-19 08:06:57,388 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13527 [2023-11-19 08:06:57,403 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13527 [2023-11-19 08:06:57,404 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13527 states and 18620 transitions. [2023-11-19 08:06:57,418 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:06:57,418 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13527 states and 18620 transitions. [2023-11-19 08:06:57,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13527 states and 18620 transitions. [2023-11-19 08:06:57,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13527 to 7576. [2023-11-19 08:06:57,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7576 states, 7576 states have (on average 1.3884635691657867) internal successors, (10519), 7575 states have internal predecessors, (10519), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:57,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7576 states to 7576 states and 10519 transitions. [2023-11-19 08:06:57,586 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7576 states and 10519 transitions. [2023-11-19 08:06:57,586 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-19 08:06:57,589 INFO L428 stractBuchiCegarLoop]: Abstraction has 7576 states and 10519 transitions. [2023-11-19 08:06:57,589 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-19 08:06:57,589 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7576 states and 10519 transitions. [2023-11-19 08:06:57,618 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7457 [2023-11-19 08:06:57,618 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:06:57,618 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:06:57,620 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:57,620 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:57,620 INFO L748 eck$LassoCheckResult]: Stem: 105439#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 105440#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 105551#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 105552#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 105538#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 105539#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 105380#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 105381#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 105356#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 105357#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 105624#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 105464#L611 assume !(0 == ~M_E~0); 105465#L611-2 assume !(0 == ~T1_E~0); 105639#L616-1 assume !(0 == ~T2_E~0); 105640#L621-1 assume !(0 == ~T3_E~0); 105227#L626-1 assume !(0 == ~T4_E~0); 105228#L631-1 assume !(0 == ~T5_E~0); 105420#L636-1 assume !(0 == ~E_M~0); 105275#L641-1 assume !(0 == ~E_1~0); 105276#L646-1 assume !(0 == ~E_2~0); 105436#L651-1 assume !(0 == ~E_3~0); 105683#L656-1 assume !(0 == ~E_4~0); 105622#L661-1 assume !(0 == ~E_5~0); 105623#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 105657#L304 assume !(1 == ~m_pc~0); 105303#L304-2 is_master_triggered_~__retres1~0#1 := 0; 105199#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 105200#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 105154#L755 assume !(0 != activate_threads_~tmp~1#1); 105155#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 105111#L323 assume !(1 == ~t1_pc~0); 105112#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 105167#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 105168#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 105183#L763 assume !(0 != activate_threads_~tmp___0~0#1); 105721#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 105177#L342 assume !(1 == ~t2_pc~0); 105179#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 105305#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 105306#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 105555#L771 assume !(0 != activate_threads_~tmp___1~0#1); 105619#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 105499#L361 assume !(1 == ~t3_pc~0); 105500#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 105528#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 105123#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 105124#L779 assume !(0 != activate_threads_~tmp___2~0#1); 105188#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 105189#L380 assume !(1 == ~t4_pc~0); 105498#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 105632#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 105271#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 105272#L787 assume !(0 != activate_threads_~tmp___3~0#1); 105540#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 105245#L399 assume !(1 == ~t5_pc~0); 105246#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 105390#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 105394#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 105382#L795 assume !(0 != activate_threads_~tmp___4~0#1); 105383#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 105697#L679 assume !(1 == ~M_E~0); 105463#L679-2 assume !(1 == ~T1_E~0); 105318#L684-1 assume !(1 == ~T2_E~0); 105319#L689-1 assume !(1 == ~T3_E~0); 105509#L694-1 assume !(1 == ~T4_E~0); 105507#L699-1 assume !(1 == ~T5_E~0); 105508#L704-1 assume !(1 == ~E_M~0); 105488#L709-1 assume !(1 == ~E_1~0); 105425#L714-1 assume !(1 == ~E_2~0); 105426#L719-1 assume !(1 == ~E_3~0); 105615#L724-1 assume !(1 == ~E_4~0); 105210#L729-1 assume !(1 == ~E_5~0); 105211#L734-1 assume { :end_inline_reset_delta_events } true; 105703#L940-2 [2023-11-19 08:06:57,621 INFO L750 eck$LassoCheckResult]: Loop: 105703#L940-2 assume !false; 112484#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 105280#L586-1 assume !false; 112325#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 111685#L464 assume !(0 == ~m_st~0); 111686#L468 assume !(0 == ~t1_st~0); 111688#L472 assume !(0 == ~t2_st~0); 111683#L476 assume !(0 == ~t3_st~0); 111684#L480 assume !(0 == ~t4_st~0); 111687#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 111689#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 109293#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 109294#L511 assume !(0 != eval_~tmp~0#1); 111657#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 112063#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 112062#L611-3 assume !(0 == ~M_E~0); 111647#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 111648#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 111639#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 111634#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 111613#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 111612#L636-3 assume !(0 == ~E_M~0); 111611#L641-3 assume !(0 == ~E_1~0); 111524#L646-3 assume !(0 == ~E_2~0); 105235#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 105236#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 105480#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 105722#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 105387#L304-21 assume !(1 == ~m_pc~0); 105238#L304-23 is_master_triggered_~__retres1~0#1 := 0; 105239#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 105312#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 105313#L755-21 assume !(0 != activate_threads_~tmp~1#1); 105448#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 105483#L323-21 assume !(1 == ~t1_pc~0); 105719#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 112182#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 112181#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 112180#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 112179#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112178#L342-21 assume !(1 == ~t2_pc~0); 112176#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 112175#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 112174#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 112173#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 112172#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 112171#L361-21 assume 1 == ~t3_pc~0; 112169#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 112167#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 112165#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 112163#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 112162#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 112161#L380-21 assume !(1 == ~t4_pc~0); 112160#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 112159#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 112158#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 112157#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 112156#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 112155#L399-21 assume 1 == ~t5_pc~0; 112153#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 112152#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 112151#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 112150#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 112149#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 112148#L679-3 assume !(1 == ~M_E~0); 109068#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 112147#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 112146#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 112145#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 112144#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 112143#L704-3 assume !(1 == ~E_M~0); 112142#L709-3 assume !(1 == ~E_1~0); 112141#L714-3 assume !(1 == ~E_2~0); 112140#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 112139#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 112138#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 112137#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 112133#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 112115#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 112101#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 105524#L959 assume !(0 == start_simulation_~tmp~3#1); 105525#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 112500#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 112496#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 112494#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 112492#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 112490#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 112488#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 112487#L972 assume !(0 != start_simulation_~tmp___0~1#1); 105703#L940-2 [2023-11-19 08:06:57,622 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:57,622 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 3 times [2023-11-19 08:06:57,622 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:57,622 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [515360636] [2023-11-19 08:06:57,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:57,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:57,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:06:57,641 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 08:06:57,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:06:57,674 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 08:06:57,676 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:57,677 INFO L85 PathProgramCache]: Analyzing trace with hash -1886616961, now seen corresponding path program 1 times [2023-11-19 08:06:57,677 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:57,677 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1270332419] [2023-11-19 08:06:57,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:57,677 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:57,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:57,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:57,736 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:57,737 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1270332419] [2023-11-19 08:06:57,737 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1270332419] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:57,737 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:57,737 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:06:57,737 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1304666190] [2023-11-19 08:06:57,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:57,738 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:06:57,738 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:06:57,739 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:06:57,739 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:06:57,739 INFO L87 Difference]: Start difference. First operand 7576 states and 10519 transitions. cyclomatic complexity: 2947 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:58,004 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:06:58,006 INFO L93 Difference]: Finished difference Result 14061 states and 19240 transitions. [2023-11-19 08:06:58,007 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14061 states and 19240 transitions. [2023-11-19 08:06:58,079 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13922 [2023-11-19 08:06:58,134 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14061 states to 14061 states and 19240 transitions. [2023-11-19 08:06:58,134 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14061 [2023-11-19 08:06:58,152 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14061 [2023-11-19 08:06:58,152 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14061 states and 19240 transitions. [2023-11-19 08:06:58,166 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:06:58,167 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14061 states and 19240 transitions. [2023-11-19 08:06:58,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14061 states and 19240 transitions. [2023-11-19 08:06:58,448 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14061 to 13437. [2023-11-19 08:06:58,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13437 states, 13437 states have (on average 1.3711393912331622) internal successors, (18424), 13436 states have internal predecessors, (18424), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:58,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13437 states to 13437 states and 18424 transitions. [2023-11-19 08:06:58,521 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13437 states and 18424 transitions. [2023-11-19 08:06:58,521 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:06:58,522 INFO L428 stractBuchiCegarLoop]: Abstraction has 13437 states and 18424 transitions. [2023-11-19 08:06:58,522 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-19 08:06:58,523 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13437 states and 18424 transitions. [2023-11-19 08:06:58,590 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13298 [2023-11-19 08:06:58,590 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:06:58,590 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:06:58,592 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:58,593 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:58,593 INFO L748 eck$LassoCheckResult]: Stem: 127087#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 127088#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 127200#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 127201#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 127184#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 127185#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 127026#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 127027#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 127005#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 127006#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 127280#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 127115#L611 assume !(0 == ~M_E~0); 127116#L611-2 assume !(0 == ~T1_E~0); 127295#L616-1 assume !(0 == ~T2_E~0); 127296#L621-1 assume !(0 == ~T3_E~0); 126866#L626-1 assume !(0 == ~T4_E~0); 126867#L631-1 assume !(0 == ~T5_E~0); 127065#L636-1 assume !(0 == ~E_M~0); 126916#L641-1 assume !(0 == ~E_1~0); 126917#L646-1 assume !(0 == ~E_2~0); 127083#L651-1 assume !(0 == ~E_3~0); 127340#L656-1 assume !(0 == ~E_4~0); 127278#L661-1 assume !(0 == ~E_5~0); 127279#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 127313#L304 assume !(1 == ~m_pc~0); 126944#L304-2 is_master_triggered_~__retres1~0#1 := 0; 126843#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 126844#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 126793#L755 assume !(0 != activate_threads_~tmp~1#1); 126794#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 126750#L323 assume !(1 == ~t1_pc~0); 126751#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 126810#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 126811#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 126825#L763 assume !(0 != activate_threads_~tmp___0~0#1); 127378#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 126813#L342 assume !(1 == ~t2_pc~0); 126815#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 126952#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 126953#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 127203#L771 assume !(0 != activate_threads_~tmp___1~0#1); 127275#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 127149#L361 assume !(1 == ~t3_pc~0); 127150#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 127177#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 126766#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 126767#L779 assume !(0 != activate_threads_~tmp___2~0#1); 126828#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 126829#L380 assume !(1 == ~t4_pc~0); 127148#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 127288#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 126911#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 126912#L787 assume !(0 != activate_threads_~tmp___3~0#1); 127188#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 126889#L399 assume !(1 == ~t5_pc~0); 126890#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 127036#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 127042#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 127028#L795 assume !(0 != activate_threads_~tmp___4~0#1); 127029#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 127355#L679 assume !(1 == ~M_E~0); 127113#L679-2 assume !(1 == ~T1_E~0); 126966#L684-1 assume !(1 == ~T2_E~0); 126967#L689-1 assume !(1 == ~T3_E~0); 127159#L694-1 assume !(1 == ~T4_E~0); 127157#L699-1 assume !(1 == ~T5_E~0); 127158#L704-1 assume !(1 == ~E_M~0); 127139#L709-1 assume !(1 == ~E_1~0); 127070#L714-1 assume !(1 == ~E_2~0); 127071#L719-1 assume !(1 == ~E_3~0); 127270#L724-1 assume !(1 == ~E_4~0); 126854#L729-1 assume !(1 == ~E_5~0); 126855#L734-1 assume { :end_inline_reset_delta_events } true; 127359#L940-2 [2023-11-19 08:06:58,594 INFO L750 eck$LassoCheckResult]: Loop: 127359#L940-2 assume !false; 130816#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 130814#L586-1 assume !false; 130812#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 130809#L464 assume !(0 == ~m_st~0); 130806#L468 assume !(0 == ~t1_st~0); 130804#L472 assume !(0 == ~t2_st~0); 130801#L476 assume !(0 == ~t3_st~0); 130799#L480 assume !(0 == ~t4_st~0); 130796#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 130794#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 130792#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 130789#L511 assume !(0 != eval_~tmp~0#1); 130788#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 130786#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 130784#L611-3 assume !(0 == ~M_E~0); 130783#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 130780#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 130777#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 130774#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 130772#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 130769#L636-3 assume !(0 == ~E_M~0); 130768#L641-3 assume !(0 == ~E_1~0); 130766#L646-3 assume !(0 == ~E_2~0); 130763#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 130761#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 130759#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 130756#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 130754#L304-21 assume !(1 == ~m_pc~0); 130751#L304-23 is_master_triggered_~__retres1~0#1 := 0; 130749#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 130747#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 130744#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 130742#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 130740#L323-21 assume !(1 == ~t1_pc~0); 130738#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 130735#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 130733#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 130731#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 130729#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 130727#L342-21 assume !(1 == ~t2_pc~0); 130724#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 130723#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 130719#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 130717#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 130715#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 130713#L361-21 assume !(1 == ~t3_pc~0); 130708#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 130706#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 130704#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 130702#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 130699#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 130697#L380-21 assume !(1 == ~t4_pc~0); 130695#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 130693#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 130691#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 130688#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 130686#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 130684#L399-21 assume 1 == ~t5_pc~0; 130681#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 130679#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 130675#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 130673#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 130671#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 130670#L679-3 assume !(1 == ~M_E~0); 130191#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 130667#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 130665#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 130664#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 130663#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 130661#L704-3 assume !(1 == ~E_M~0); 130660#L709-3 assume !(1 == ~E_1~0); 130659#L714-3 assume !(1 == ~E_2~0); 130658#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 130657#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 130656#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 130655#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 130654#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 130653#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 130651#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 130648#L959 assume !(0 == start_simulation_~tmp~3#1); 130649#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 131121#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 131118#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 131116#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 131114#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 131112#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 131110#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 131108#L972 assume !(0 != start_simulation_~tmp___0~1#1); 127359#L940-2 [2023-11-19 08:06:58,595 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:58,595 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 4 times [2023-11-19 08:06:58,595 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:58,596 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1586414558] [2023-11-19 08:06:58,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:58,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:58,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:06:58,612 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 08:06:58,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:06:58,641 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 08:06:58,642 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:58,642 INFO L85 PathProgramCache]: Analyzing trace with hash 1200596224, now seen corresponding path program 1 times [2023-11-19 08:06:58,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:58,642 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1161131211] [2023-11-19 08:06:58,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:58,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:58,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:06:58,771 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:06:58,771 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:06:58,772 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1161131211] [2023-11-19 08:06:58,772 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1161131211] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:06:58,772 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:06:58,772 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 08:06:58,773 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [241580206] [2023-11-19 08:06:58,773 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:06:58,773 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:06:58,774 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:06:58,774 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 08:06:58,774 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 08:06:58,775 INFO L87 Difference]: Start difference. First operand 13437 states and 18424 transitions. cyclomatic complexity: 4991 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:59,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:06:59,312 INFO L93 Difference]: Finished difference Result 19885 states and 27016 transitions. [2023-11-19 08:06:59,313 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19885 states and 27016 transitions. [2023-11-19 08:06:59,412 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 19724 [2023-11-19 08:06:59,490 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19885 states to 19885 states and 27016 transitions. [2023-11-19 08:06:59,490 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19885 [2023-11-19 08:06:59,511 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19885 [2023-11-19 08:06:59,511 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19885 states and 27016 transitions. [2023-11-19 08:06:59,529 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:06:59,529 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19885 states and 27016 transitions. [2023-11-19 08:06:59,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19885 states and 27016 transitions. [2023-11-19 08:06:59,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19885 to 12517. [2023-11-19 08:06:59,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12517 states, 12517 states have (on average 1.355915954302149) internal successors, (16972), 12516 states have internal predecessors, (16972), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:06:59,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12517 states to 12517 states and 16972 transitions. [2023-11-19 08:06:59,881 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12517 states and 16972 transitions. [2023-11-19 08:06:59,882 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-19 08:06:59,882 INFO L428 stractBuchiCegarLoop]: Abstraction has 12517 states and 16972 transitions. [2023-11-19 08:06:59,883 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-19 08:06:59,883 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12517 states and 16972 transitions. [2023-11-19 08:06:59,932 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 12388 [2023-11-19 08:06:59,932 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:06:59,932 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:06:59,933 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:59,934 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:06:59,934 INFO L748 eck$LassoCheckResult]: Stem: 160420#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 160421#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 160539#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 160540#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 160524#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 160525#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 160358#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 160359#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 160336#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 160337#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 160614#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 160449#L611 assume !(0 == ~M_E~0); 160450#L611-2 assume !(0 == ~T1_E~0); 160630#L616-1 assume !(0 == ~T2_E~0); 160631#L621-1 assume !(0 == ~T3_E~0); 160199#L626-1 assume !(0 == ~T4_E~0); 160200#L631-1 assume !(0 == ~T5_E~0); 160399#L636-1 assume !(0 == ~E_M~0); 160251#L641-1 assume !(0 == ~E_1~0); 160252#L646-1 assume !(0 == ~E_2~0); 160417#L651-1 assume !(0 == ~E_3~0); 160684#L656-1 assume !(0 == ~E_4~0); 160612#L661-1 assume !(0 == ~E_5~0); 160613#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 160652#L304 assume !(1 == ~m_pc~0); 160277#L304-2 is_master_triggered_~__retres1~0#1 := 0; 160176#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 160177#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 160127#L755 assume !(0 != activate_threads_~tmp~1#1); 160128#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 160084#L323 assume !(1 == ~t1_pc~0); 160085#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 160143#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 160144#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 160160#L763 assume !(0 != activate_threads_~tmp___0~0#1); 160722#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 160147#L342 assume !(1 == ~t2_pc~0); 160149#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 160284#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 160285#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 160543#L771 assume !(0 != activate_threads_~tmp___1~0#1); 160609#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 160483#L361 assume !(1 == ~t3_pc~0); 160484#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 160515#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 160100#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 160101#L779 assume !(0 != activate_threads_~tmp___2~0#1); 160163#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 160164#L380 assume !(1 == ~t4_pc~0); 160482#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 160621#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 160244#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 160245#L787 assume !(0 != activate_threads_~tmp___3~0#1); 160528#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 160222#L399 assume !(1 == ~t5_pc~0); 160223#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 160370#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 160376#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 160360#L795 assume !(0 != activate_threads_~tmp___4~0#1); 160361#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 160697#L679 assume !(1 == ~M_E~0); 160447#L679-2 assume !(1 == ~T1_E~0); 160297#L684-1 assume !(1 == ~T2_E~0); 160298#L689-1 assume !(1 == ~T3_E~0); 160493#L694-1 assume !(1 == ~T4_E~0); 160491#L699-1 assume !(1 == ~T5_E~0); 160492#L704-1 assume !(1 == ~E_M~0); 160472#L709-1 assume !(1 == ~E_1~0); 160404#L714-1 assume !(1 == ~E_2~0); 160405#L719-1 assume !(1 == ~E_3~0); 160604#L724-1 assume !(1 == ~E_4~0); 160187#L729-1 assume !(1 == ~E_5~0); 160188#L734-1 assume { :end_inline_reset_delta_events } true; 160702#L940-2 assume !false; 161623#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 161624#L586-1 [2023-11-19 08:06:59,934 INFO L750 eck$LassoCheckResult]: Loop: 161624#L586-1 assume !false; 161612#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 161613#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 162135#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 162133#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 162131#L511 assume 0 != eval_~tmp~0#1; 162119#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 162117#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 162116#L519-2 havoc eval_~tmp_ndt_1~0#1; 162088#L516-1 assume !(0 == ~t1_st~0); 162087#L530-1 assume !(0 == ~t2_st~0); 161762#L544-1 assume !(0 == ~t3_st~0); 161761#L558-1 assume !(0 == ~t4_st~0); 161626#L572-1 assume !(0 == ~t5_st~0); 161624#L586-1 [2023-11-19 08:06:59,935 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:59,935 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 1 times [2023-11-19 08:06:59,935 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:59,936 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [562649213] [2023-11-19 08:06:59,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:59,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:59,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:06:59,949 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 08:06:59,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:06:59,975 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 08:06:59,976 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:59,976 INFO L85 PathProgramCache]: Analyzing trace with hash -54895709, now seen corresponding path program 1 times [2023-11-19 08:06:59,976 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:59,976 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [847937687] [2023-11-19 08:06:59,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:59,977 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:06:59,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:06:59,985 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 08:06:59,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:06:59,990 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 08:06:59,991 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:06:59,991 INFO L85 PathProgramCache]: Analyzing trace with hash -1589568855, now seen corresponding path program 1 times [2023-11-19 08:06:59,991 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:06:59,992 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1483720970] [2023-11-19 08:06:59,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:06:59,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:07:00,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:07:00,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:07:00,048 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:07:00,048 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1483720970] [2023-11-19 08:07:00,048 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1483720970] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:07:00,048 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:07:00,048 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:07:00,049 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [442530973] [2023-11-19 08:07:00,049 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:07:00,175 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:07:00,176 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:07:00,176 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:07:00,176 INFO L87 Difference]: Start difference. First operand 12517 states and 16972 transitions. cyclomatic complexity: 4461 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:07:00,414 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:07:00,414 INFO L93 Difference]: Finished difference Result 23784 states and 32023 transitions. [2023-11-19 08:07:00,414 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23784 states and 32023 transitions. [2023-11-19 08:07:00,737 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 23153 [2023-11-19 08:07:00,821 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23784 states to 23784 states and 32023 transitions. [2023-11-19 08:07:00,822 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23784 [2023-11-19 08:07:00,844 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23784 [2023-11-19 08:07:00,844 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23784 states and 32023 transitions. [2023-11-19 08:07:00,864 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:07:00,864 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23784 states and 32023 transitions. [2023-11-19 08:07:00,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23784 states and 32023 transitions. [2023-11-19 08:07:01,235 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23784 to 23232. [2023-11-19 08:07:01,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23232 states, 23232 states have (on average 1.347064393939394) internal successors, (31295), 23231 states have internal predecessors, (31295), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:07:01,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23232 states to 23232 states and 31295 transitions. [2023-11-19 08:07:01,348 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23232 states and 31295 transitions. [2023-11-19 08:07:01,349 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:07:01,349 INFO L428 stractBuchiCegarLoop]: Abstraction has 23232 states and 31295 transitions. [2023-11-19 08:07:01,349 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-19 08:07:01,350 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23232 states and 31295 transitions. [2023-11-19 08:07:01,456 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 22601 [2023-11-19 08:07:01,457 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:07:01,457 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:07:01,458 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:07:01,458 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:07:01,459 INFO L748 eck$LassoCheckResult]: Stem: 196728#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 196729#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 196848#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 196849#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 196831#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 196832#L426-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 196664#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 196665#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 196643#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 196644#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 196924#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 196925#L611 assume !(0 == ~M_E~0); 196947#L611-2 assume !(0 == ~T1_E~0); 196948#L616-1 assume !(0 == ~T2_E~0); 196954#L621-1 assume !(0 == ~T3_E~0); 196955#L626-1 assume !(0 == ~T4_E~0); 196912#L631-1 assume !(0 == ~T5_E~0); 196913#L636-1 assume !(0 == ~E_M~0); 196559#L641-1 assume !(0 == ~E_1~0); 196560#L646-1 assume !(0 == ~E_2~0); 197034#L651-1 assume !(0 == ~E_3~0); 197035#L656-1 assume !(0 == ~E_4~0); 196920#L661-1 assume !(0 == ~E_5~0); 196921#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 197059#L304 assume !(1 == ~m_pc~0); 197060#L304-2 is_master_triggered_~__retres1~0#1 := 0; 196487#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 196488#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 196436#L755 assume !(0 != activate_threads_~tmp~1#1); 196437#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 196393#L323 assume !(1 == ~t1_pc~0); 196394#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 196453#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 196454#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 197036#L763 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 197037#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 197044#L342 assume !(1 == ~t2_pc~0); 196918#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 196919#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 196850#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 196851#L771 assume !(0 != activate_threads_~tmp___1~0#1); 196914#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 196915#L361 assume !(1 == ~t3_pc~0); 196823#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 196824#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 196409#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 196410#L779 assume !(0 != activate_threads_~tmp___2~0#1); 196473#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 196474#L380 assume !(1 == ~t4_pc~0); 197066#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 197067#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 196554#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 196555#L787 assume !(0 != activate_threads_~tmp___3~0#1); 197054#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 197055#L399 assume !(1 == ~t5_pc~0); 196675#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 196676#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 196681#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 196682#L795 assume !(0 != activate_threads_~tmp___4~0#1); 197011#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 197012#L679 assume !(1 == ~M_E~0); 196752#L679-2 assume !(1 == ~T1_E~0); 196753#L684-1 assume !(1 == ~T2_E~0); 196804#L689-1 assume !(1 == ~T3_E~0); 196805#L694-1 assume !(1 == ~T4_E~0); 196802#L699-1 assume !(1 == ~T5_E~0); 196803#L704-1 assume !(1 == ~E_M~0); 196779#L709-1 assume !(1 == ~E_1~0); 196780#L714-1 assume !(1 == ~E_2~0); 211376#L719-1 assume !(1 == ~E_3~0); 211374#L724-1 assume !(1 == ~E_4~0); 211372#L729-1 assume !(1 == ~E_5~0); 197017#L734-1 assume { :end_inline_reset_delta_events } true; 197018#L940-2 assume !false; 212534#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 212533#L586-1 [2023-11-19 08:07:01,459 INFO L750 eck$LassoCheckResult]: Loop: 212533#L586-1 assume !false; 212524#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 212520#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 212518#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 212515#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 212516#L511 assume 0 != eval_~tmp~0#1; 212508#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 212504#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 212505#L519-2 havoc eval_~tmp_ndt_1~0#1; 212823#L516-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 201526#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 201527#L533-2 havoc eval_~tmp_ndt_2~0#1; 212549#L530-1 assume !(0 == ~t2_st~0); 212551#L544-1 assume !(0 == ~t3_st~0); 213050#L558-1 assume !(0 == ~t4_st~0); 212536#L572-1 assume !(0 == ~t5_st~0); 212533#L586-1 [2023-11-19 08:07:01,460 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:07:01,461 INFO L85 PathProgramCache]: Analyzing trace with hash 1162562755, now seen corresponding path program 1 times [2023-11-19 08:07:01,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:07:01,461 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1526699255] [2023-11-19 08:07:01,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:07:01,462 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:07:01,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:07:01,502 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:07:01,502 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:07:01,502 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1526699255] [2023-11-19 08:07:01,502 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1526699255] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:07:01,503 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:07:01,503 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:07:01,503 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1224052266] [2023-11-19 08:07:01,503 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:07:01,505 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:07:01,507 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:07:01,507 INFO L85 PathProgramCache]: Analyzing trace with hash -1656247949, now seen corresponding path program 1 times [2023-11-19 08:07:01,508 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:07:01,508 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1866792250] [2023-11-19 08:07:01,508 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:07:01,508 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:07:01,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:01,515 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 08:07:01,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:01,523 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 08:07:01,765 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:07:01,766 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:07:01,766 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:07:01,766 INFO L87 Difference]: Start difference. First operand 23232 states and 31295 transitions. cyclomatic complexity: 8075 Second operand has 3 states, 3 states have (on average 25.0) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:07:01,891 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:07:01,891 INFO L93 Difference]: Finished difference Result 20655 states and 27844 transitions. [2023-11-19 08:07:01,891 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20655 states and 27844 transitions. [2023-11-19 08:07:01,991 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 20496 [2023-11-19 08:07:02,072 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20655 states to 20655 states and 27844 transitions. [2023-11-19 08:07:02,073 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20655 [2023-11-19 08:07:02,087 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20655 [2023-11-19 08:07:02,088 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20655 states and 27844 transitions. [2023-11-19 08:07:02,107 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:07:02,107 INFO L218 hiAutomatonCegarLoop]: Abstraction has 20655 states and 27844 transitions. [2023-11-19 08:07:02,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20655 states and 27844 transitions. [2023-11-19 08:07:02,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20655 to 20655. [2023-11-19 08:07:02,540 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20655 states, 20655 states have (on average 1.3480513192931494) internal successors, (27844), 20654 states have internal predecessors, (27844), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:07:02,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20655 states to 20655 states and 27844 transitions. [2023-11-19 08:07:02,594 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20655 states and 27844 transitions. [2023-11-19 08:07:02,594 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:07:02,595 INFO L428 stractBuchiCegarLoop]: Abstraction has 20655 states and 27844 transitions. [2023-11-19 08:07:02,595 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-19 08:07:02,595 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20655 states and 27844 transitions. [2023-11-19 08:07:02,803 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 20496 [2023-11-19 08:07:02,803 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:07:02,803 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:07:02,804 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:07:02,805 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:07:02,805 INFO L748 eck$LassoCheckResult]: Stem: 240614#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 240615#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 240732#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 240733#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 240716#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 240717#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 240556#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 240557#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 240535#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 240536#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 240804#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 240642#L611 assume !(0 == ~M_E~0); 240643#L611-2 assume !(0 == ~T1_E~0); 240820#L616-1 assume !(0 == ~T2_E~0); 240821#L621-1 assume !(0 == ~T3_E~0); 240407#L626-1 assume !(0 == ~T4_E~0); 240408#L631-1 assume !(0 == ~T5_E~0); 240598#L636-1 assume !(0 == ~E_M~0); 240453#L641-1 assume !(0 == ~E_1~0); 240454#L646-1 assume !(0 == ~E_2~0); 240612#L651-1 assume !(0 == ~E_3~0); 240865#L656-1 assume !(0 == ~E_4~0); 240802#L661-1 assume !(0 == ~E_5~0); 240803#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 240840#L304 assume !(1 == ~m_pc~0); 240481#L304-2 is_master_triggered_~__retres1~0#1 := 0; 240378#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 240379#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 240333#L755 assume !(0 != activate_threads_~tmp~1#1); 240334#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 240290#L323 assume !(1 == ~t1_pc~0); 240291#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 240346#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 240347#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 240361#L763 assume !(0 != activate_threads_~tmp___0~0#1); 240895#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 240355#L342 assume !(1 == ~t2_pc~0); 240357#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 240483#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 240484#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 240734#L771 assume !(0 != activate_threads_~tmp___1~0#1); 240798#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 240678#L361 assume !(1 == ~t3_pc~0); 240679#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 240707#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 240302#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 240303#L779 assume !(0 != activate_threads_~tmp___2~0#1); 240367#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 240368#L380 assume !(1 == ~t4_pc~0); 240676#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 240813#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 240449#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 240450#L787 assume !(0 != activate_threads_~tmp___3~0#1); 240719#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 240424#L399 assume !(1 == ~t5_pc~0); 240425#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 240567#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 240571#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 240558#L795 assume !(0 != activate_threads_~tmp___4~0#1); 240559#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 240876#L679 assume !(1 == ~M_E~0); 240641#L679-2 assume !(1 == ~T1_E~0); 240496#L684-1 assume !(1 == ~T2_E~0); 240497#L689-1 assume !(1 == ~T3_E~0); 240689#L694-1 assume !(1 == ~T4_E~0); 240687#L699-1 assume !(1 == ~T5_E~0); 240688#L704-1 assume !(1 == ~E_M~0); 240665#L709-1 assume !(1 == ~E_1~0); 240602#L714-1 assume !(1 == ~E_2~0); 240603#L719-1 assume !(1 == ~E_3~0); 240794#L724-1 assume !(1 == ~E_4~0); 240389#L729-1 assume !(1 == ~E_5~0); 240390#L734-1 assume { :end_inline_reset_delta_events } true; 240880#L940-2 assume !false; 249361#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 249359#L586-1 [2023-11-19 08:07:02,805 INFO L750 eck$LassoCheckResult]: Loop: 249359#L586-1 assume !false; 249357#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 249354#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 249351#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 249349#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 249347#L511 assume 0 != eval_~tmp~0#1; 249344#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 249341#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 249340#L519-2 havoc eval_~tmp_ndt_1~0#1; 246291#L516-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 244503#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 244504#L533-2 havoc eval_~tmp_ndt_2~0#1; 250039#L530-1 assume !(0 == ~t2_st~0); 250035#L544-1 assume !(0 == ~t3_st~0); 250031#L558-1 assume !(0 == ~t4_st~0); 249363#L572-1 assume !(0 == ~t5_st~0); 249359#L586-1 [2023-11-19 08:07:02,806 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:07:02,806 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 2 times [2023-11-19 08:07:02,806 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:07:02,806 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1877111745] [2023-11-19 08:07:02,806 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:07:02,807 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:07:02,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:02,818 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 08:07:02,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:02,839 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 08:07:02,840 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:07:02,840 INFO L85 PathProgramCache]: Analyzing trace with hash -1656247949, now seen corresponding path program 2 times [2023-11-19 08:07:02,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:07:02,841 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1253922728] [2023-11-19 08:07:02,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:07:02,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:07:02,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:02,845 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 08:07:02,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:02,849 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 08:07:02,849 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:07:02,850 INFO L85 PathProgramCache]: Analyzing trace with hash 991608569, now seen corresponding path program 1 times [2023-11-19 08:07:02,850 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:07:02,850 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [138502449] [2023-11-19 08:07:02,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:07:02,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:07:02,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:07:02,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:07:02,899 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:07:02,899 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [138502449] [2023-11-19 08:07:02,899 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [138502449] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:07:02,899 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:07:02,900 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:07:02,900 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [651765023] [2023-11-19 08:07:02,900 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:07:02,989 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:07:02,989 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:07:02,989 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:07:02,990 INFO L87 Difference]: Start difference. First operand 20655 states and 27844 transitions. cyclomatic complexity: 7195 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:07:03,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:07:03,239 INFO L93 Difference]: Finished difference Result 38477 states and 51748 transitions. [2023-11-19 08:07:03,239 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38477 states and 51748 transitions. [2023-11-19 08:07:03,673 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 38240 [2023-11-19 08:07:03,840 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38477 states to 38477 states and 51748 transitions. [2023-11-19 08:07:03,840 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38477 [2023-11-19 08:07:03,866 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38477 [2023-11-19 08:07:03,866 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38477 states and 51748 transitions. [2023-11-19 08:07:03,902 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:07:03,902 INFO L218 hiAutomatonCegarLoop]: Abstraction has 38477 states and 51748 transitions. [2023-11-19 08:07:03,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38477 states and 51748 transitions. [2023-11-19 08:07:04,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38477 to 36607. [2023-11-19 08:07:04,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36607 states, 36607 states have (on average 1.347665746988281) internal successors, (49334), 36606 states have internal predecessors, (49334), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:07:04,646 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36607 states to 36607 states and 49334 transitions. [2023-11-19 08:07:04,646 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36607 states and 49334 transitions. [2023-11-19 08:07:04,647 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:07:04,648 INFO L428 stractBuchiCegarLoop]: Abstraction has 36607 states and 49334 transitions. [2023-11-19 08:07:04,648 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-19 08:07:04,648 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36607 states and 49334 transitions. [2023-11-19 08:07:04,785 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 36370 [2023-11-19 08:07:04,786 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:07:04,786 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:07:04,787 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:07:04,787 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:07:04,788 INFO L748 eck$LassoCheckResult]: Stem: 299765#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 299766#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 299881#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 299882#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 299865#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 299866#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 299701#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 299702#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 299680#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 299681#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 299950#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 299791#L611 assume !(0 == ~M_E~0); 299792#L611-2 assume !(0 == ~T1_E~0); 299972#L616-1 assume !(0 == ~T2_E~0); 299973#L621-1 assume !(0 == ~T3_E~0); 299547#L626-1 assume !(0 == ~T4_E~0); 299548#L631-1 assume !(0 == ~T5_E~0); 299746#L636-1 assume !(0 == ~E_M~0); 299596#L641-1 assume !(0 == ~E_1~0); 299597#L646-1 assume !(0 == ~E_2~0); 299761#L651-1 assume !(0 == ~E_3~0); 300023#L656-1 assume !(0 == ~E_4~0); 299948#L661-1 assume !(0 == ~E_5~0); 299949#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 299995#L304 assume !(1 == ~m_pc~0); 299626#L304-2 is_master_triggered_~__retres1~0#1 := 0; 299519#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 299520#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 299473#L755 assume !(0 != activate_threads_~tmp~1#1); 299474#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 299430#L323 assume !(1 == ~t1_pc~0); 299431#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 299486#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 299487#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 299502#L763 assume !(0 != activate_threads_~tmp___0~0#1); 300057#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 299496#L342 assume !(1 == ~t2_pc~0); 299498#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 299628#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 299629#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 299883#L771 assume !(0 != activate_threads_~tmp___1~0#1); 299943#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 299829#L361 assume !(1 == ~t3_pc~0); 299830#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 299857#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 299442#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 299443#L779 assume !(0 != activate_threads_~tmp___2~0#1); 299508#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 299509#L380 assume !(1 == ~t4_pc~0); 299828#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 299963#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 299591#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 299592#L787 assume !(0 != activate_threads_~tmp___3~0#1); 299869#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 299565#L399 assume !(1 == ~t5_pc~0); 299566#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 299712#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 299717#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 299703#L795 assume !(0 != activate_threads_~tmp___4~0#1); 299704#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 300034#L679 assume !(1 == ~M_E~0); 299790#L679-2 assume !(1 == ~T1_E~0); 299641#L684-1 assume !(1 == ~T2_E~0); 299642#L689-1 assume !(1 == ~T3_E~0); 299839#L694-1 assume !(1 == ~T4_E~0); 299837#L699-1 assume !(1 == ~T5_E~0); 299838#L704-1 assume !(1 == ~E_M~0); 299818#L709-1 assume !(1 == ~E_1~0); 299750#L714-1 assume !(1 == ~E_2~0); 299751#L719-1 assume !(1 == ~E_3~0); 299937#L724-1 assume !(1 == ~E_4~0); 299530#L729-1 assume !(1 == ~E_5~0); 299531#L734-1 assume { :end_inline_reset_delta_events } true; 300040#L940-2 assume !false; 316972#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 316970#L586-1 [2023-11-19 08:07:04,789 INFO L750 eck$LassoCheckResult]: Loop: 316970#L586-1 assume !false; 316968#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 316965#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 316963#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 316962#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 316961#L511 assume 0 != eval_~tmp~0#1; 316957#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 316953#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 316952#L519-2 havoc eval_~tmp_ndt_1~0#1; 316947#L516-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 308312#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 308313#L533-2 havoc eval_~tmp_ndt_2~0#1; 317005#L530-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 314870#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 316994#L547-2 havoc eval_~tmp_ndt_3~0#1; 316987#L544-1 assume !(0 == ~t3_st~0); 316981#L558-1 assume !(0 == ~t4_st~0); 316974#L572-1 assume !(0 == ~t5_st~0); 316970#L586-1 [2023-11-19 08:07:04,789 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:07:04,789 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 3 times [2023-11-19 08:07:04,790 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:07:04,790 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [109495508] [2023-11-19 08:07:04,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:07:04,791 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:07:04,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:04,805 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 08:07:04,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:04,834 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 08:07:04,834 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:07:04,834 INFO L85 PathProgramCache]: Analyzing trace with hash 794581347, now seen corresponding path program 1 times [2023-11-19 08:07:04,835 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:07:04,835 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [436673160] [2023-11-19 08:07:04,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:07:04,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:07:04,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:04,840 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 08:07:04,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:04,845 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 08:07:04,845 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:07:04,846 INFO L85 PathProgramCache]: Analyzing trace with hash -1530911383, now seen corresponding path program 1 times [2023-11-19 08:07:04,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:07:04,846 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [187348872] [2023-11-19 08:07:04,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:07:04,846 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:07:04,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:07:04,911 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:07:04,912 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:07:04,912 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [187348872] [2023-11-19 08:07:04,912 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [187348872] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:07:04,913 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:07:04,914 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:07:04,914 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [437373429] [2023-11-19 08:07:04,914 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:07:05,013 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:07:05,013 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:07:05,014 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:07:05,014 INFO L87 Difference]: Start difference. First operand 36607 states and 49334 transitions. cyclomatic complexity: 12733 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:07:05,715 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:07:05,715 INFO L93 Difference]: Finished difference Result 66337 states and 89384 transitions. [2023-11-19 08:07:05,716 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 66337 states and 89384 transitions. [2023-11-19 08:07:06,305 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 65944 [2023-11-19 08:07:06,531 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 66337 states to 66337 states and 89384 transitions. [2023-11-19 08:07:06,531 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 66337 [2023-11-19 08:07:06,574 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 66337 [2023-11-19 08:07:06,574 INFO L73 IsDeterministic]: Start isDeterministic. Operand 66337 states and 89384 transitions. [2023-11-19 08:07:06,633 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:07:06,633 INFO L218 hiAutomatonCegarLoop]: Abstraction has 66337 states and 89384 transitions. [2023-11-19 08:07:06,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66337 states and 89384 transitions. [2023-11-19 08:07:07,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66337 to 63957. [2023-11-19 08:07:07,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63957 states, 63957 states have (on average 1.3497193426833654) internal successors, (86324), 63956 states have internal predecessors, (86324), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:07:08,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63957 states to 63957 states and 86324 transitions. [2023-11-19 08:07:08,025 INFO L240 hiAutomatonCegarLoop]: Abstraction has 63957 states and 86324 transitions. [2023-11-19 08:07:08,026 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:07:08,027 INFO L428 stractBuchiCegarLoop]: Abstraction has 63957 states and 86324 transitions. [2023-11-19 08:07:08,027 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-19 08:07:08,027 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63957 states and 86324 transitions. [2023-11-19 08:07:08,359 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 63564 [2023-11-19 08:07:08,359 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:07:08,360 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:07:08,361 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:07:08,365 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:07:08,366 INFO L748 eck$LassoCheckResult]: Stem: 402719#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 402720#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 402848#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 402849#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 402829#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 402830#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 402654#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 402655#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 402633#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 402634#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 402944#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 402746#L611 assume !(0 == ~M_E~0); 402747#L611-2 assume !(0 == ~T1_E~0); 402963#L616-1 assume !(0 == ~T2_E~0); 402964#L621-1 assume !(0 == ~T3_E~0); 402497#L626-1 assume !(0 == ~T4_E~0); 402498#L631-1 assume !(0 == ~T5_E~0); 402696#L636-1 assume !(0 == ~E_M~0); 402545#L641-1 assume !(0 == ~E_1~0); 402546#L646-1 assume !(0 == ~E_2~0); 402714#L651-1 assume !(0 == ~E_3~0); 403031#L656-1 assume !(0 == ~E_4~0); 402942#L661-1 assume !(0 == ~E_5~0); 402943#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 402996#L304 assume !(1 == ~m_pc~0); 402577#L304-2 is_master_triggered_~__retres1~0#1 := 0; 402469#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 402470#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 402425#L755 assume !(0 != activate_threads_~tmp~1#1); 402426#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 402378#L323 assume !(1 == ~t1_pc~0); 402379#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 402437#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 402438#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 402453#L763 assume !(0 != activate_threads_~tmp___0~0#1); 403073#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 402447#L342 assume !(1 == ~t2_pc~0); 402449#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 402581#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 402582#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 402852#L771 assume !(0 != activate_threads_~tmp___1~0#1); 402933#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 402787#L361 assume !(1 == ~t3_pc~0); 402788#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 402818#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 402394#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 402395#L779 assume !(0 != activate_threads_~tmp___2~0#1); 402458#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 402459#L380 assume !(1 == ~t4_pc~0); 402786#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 402954#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 402539#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 402540#L787 assume !(0 != activate_threads_~tmp___3~0#1); 402833#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 402515#L399 assume !(1 == ~t5_pc~0); 402516#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 402664#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 402671#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 402656#L795 assume !(0 != activate_threads_~tmp___4~0#1); 402657#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 403044#L679 assume !(1 == ~M_E~0); 402744#L679-2 assume !(1 == ~T1_E~0); 402594#L684-1 assume !(1 == ~T2_E~0); 402595#L689-1 assume !(1 == ~T3_E~0); 402798#L694-1 assume !(1 == ~T4_E~0); 402796#L699-1 assume !(1 == ~T5_E~0); 402797#L704-1 assume !(1 == ~E_M~0); 402773#L709-1 assume !(1 == ~E_1~0); 402699#L714-1 assume !(1 == ~E_2~0); 402700#L719-1 assume !(1 == ~E_3~0); 402924#L724-1 assume !(1 == ~E_4~0); 402480#L729-1 assume !(1 == ~E_5~0); 402481#L734-1 assume { :end_inline_reset_delta_events } true; 403052#L940-2 assume !false; 432897#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 432895#L586-1 [2023-11-19 08:07:08,367 INFO L750 eck$LassoCheckResult]: Loop: 432895#L586-1 assume !false; 432893#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 432890#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 432887#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 432885#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 432883#L511 assume 0 != eval_~tmp~0#1; 432880#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 432877#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 432876#L519-2 havoc eval_~tmp_ndt_1~0#1; 432875#L516-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 432342#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 432343#L533-2 havoc eval_~tmp_ndt_2~0#1; 438644#L530-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 438576#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 438642#L547-2 havoc eval_~tmp_ndt_3~0#1; 432911#L544-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 432908#L561 assume !(0 != eval_~tmp_ndt_4~0#1); 432906#L561-2 havoc eval_~tmp_ndt_4~0#1; 432903#L558-1 assume !(0 == ~t4_st~0); 432899#L572-1 assume !(0 == ~t5_st~0); 432895#L586-1 [2023-11-19 08:07:08,368 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:07:08,368 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 4 times [2023-11-19 08:07:08,369 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:07:08,369 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1009398176] [2023-11-19 08:07:08,369 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:07:08,370 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:07:08,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:08,390 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 08:07:08,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:08,425 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 08:07:08,426 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:07:08,426 INFO L85 PathProgramCache]: Analyzing trace with hash -1081740493, now seen corresponding path program 1 times [2023-11-19 08:07:08,426 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:07:08,427 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [520390357] [2023-11-19 08:07:08,427 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:07:08,427 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:07:08,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:08,435 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 08:07:08,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:08,444 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 08:07:08,445 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:07:08,445 INFO L85 PathProgramCache]: Analyzing trace with hash 1797707193, now seen corresponding path program 1 times [2023-11-19 08:07:08,445 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:07:08,446 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1909746560] [2023-11-19 08:07:08,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:07:08,446 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:07:08,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:07:08,526 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:07:08,526 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:07:08,526 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1909746560] [2023-11-19 08:07:08,527 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1909746560] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:07:08,527 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:07:08,527 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:07:08,528 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1420100116] [2023-11-19 08:07:08,528 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:07:08,681 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:07:08,682 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:07:08,682 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:07:08,683 INFO L87 Difference]: Start difference. First operand 63957 states and 86324 transitions. cyclomatic complexity: 22373 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:07:09,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:07:09,596 INFO L93 Difference]: Finished difference Result 74367 states and 100212 transitions. [2023-11-19 08:07:09,596 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 74367 states and 100212 transitions. [2023-11-19 08:07:09,967 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 74082 [2023-11-19 08:07:10,214 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 74367 states to 74367 states and 100212 transitions. [2023-11-19 08:07:10,215 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 74367 [2023-11-19 08:07:10,264 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 74367 [2023-11-19 08:07:10,264 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74367 states and 100212 transitions. [2023-11-19 08:07:10,430 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:07:10,456 INFO L218 hiAutomatonCegarLoop]: Abstraction has 74367 states and 100212 transitions. [2023-11-19 08:07:10,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74367 states and 100212 transitions. [2023-11-19 08:07:11,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74367 to 72871. [2023-11-19 08:07:11,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72871 states, 72871 states have (on average 1.3490689025812737) internal successors, (98308), 72870 states have internal predecessors, (98308), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:07:12,056 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72871 states to 72871 states and 98308 transitions. [2023-11-19 08:07:12,057 INFO L240 hiAutomatonCegarLoop]: Abstraction has 72871 states and 98308 transitions. [2023-11-19 08:07:12,057 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:07:12,058 INFO L428 stractBuchiCegarLoop]: Abstraction has 72871 states and 98308 transitions. [2023-11-19 08:07:12,058 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-19 08:07:12,058 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72871 states and 98308 transitions. [2023-11-19 08:07:12,344 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 72586 [2023-11-19 08:07:12,344 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:07:12,344 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:07:12,346 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:07:12,346 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:07:12,347 INFO L748 eck$LassoCheckResult]: Stem: 541054#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 541055#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 541181#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 541182#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 541164#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 541165#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 540988#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 540989#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 540967#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 540968#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 541273#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 541081#L611 assume !(0 == ~M_E~0); 541082#L611-2 assume !(0 == ~T1_E~0); 541296#L616-1 assume !(0 == ~T2_E~0); 541297#L621-1 assume !(0 == ~T3_E~0); 540832#L626-1 assume !(0 == ~T4_E~0); 540833#L631-1 assume !(0 == ~T5_E~0); 541036#L636-1 assume !(0 == ~E_M~0); 540879#L641-1 assume !(0 == ~E_1~0); 540880#L646-1 assume !(0 == ~E_2~0); 541051#L651-1 assume !(0 == ~E_3~0); 541358#L656-1 assume !(0 == ~E_4~0); 541271#L661-1 assume !(0 == ~E_5~0); 541272#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 541325#L304 assume !(1 == ~m_pc~0); 540911#L304-2 is_master_triggered_~__retres1~0#1 := 0; 540801#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 540802#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 540757#L755 assume !(0 != activate_threads_~tmp~1#1); 540758#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 540710#L323 assume !(1 == ~t1_pc~0); 540711#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 540769#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 540770#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 540786#L763 assume !(0 != activate_threads_~tmp___0~0#1); 541407#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 540779#L342 assume !(1 == ~t2_pc~0); 540781#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 540913#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 540914#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 541185#L771 assume !(0 != activate_threads_~tmp___1~0#1); 541265#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 541120#L361 assume !(1 == ~t3_pc~0); 541121#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 541151#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 540726#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 540727#L779 assume !(0 != activate_threads_~tmp___2~0#1); 540791#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 540792#L380 assume !(1 == ~t4_pc~0); 541119#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 541286#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 540875#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 540876#L787 assume !(0 != activate_threads_~tmp___3~0#1); 541169#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 540850#L399 assume !(1 == ~t5_pc~0); 540851#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 541000#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 541006#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 540990#L795 assume !(0 != activate_threads_~tmp___4~0#1); 540991#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 541372#L679 assume !(1 == ~M_E~0); 541080#L679-2 assume !(1 == ~T1_E~0); 540926#L684-1 assume !(1 == ~T2_E~0); 540927#L689-1 assume !(1 == ~T3_E~0); 541130#L694-1 assume !(1 == ~T4_E~0); 541128#L699-1 assume !(1 == ~T5_E~0); 541129#L704-1 assume !(1 == ~E_M~0); 541109#L709-1 assume !(1 == ~E_1~0); 541037#L714-1 assume !(1 == ~E_2~0); 541038#L719-1 assume !(1 == ~E_3~0); 541255#L724-1 assume !(1 == ~E_4~0); 540813#L729-1 assume !(1 == ~E_5~0); 540814#L734-1 assume { :end_inline_reset_delta_events } true; 541380#L940-2 assume !false; 587552#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 587551#L586-1 [2023-11-19 08:07:12,347 INFO L750 eck$LassoCheckResult]: Loop: 587551#L586-1 assume !false; 587535#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 587527#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 587516#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 587505#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 587495#L511 assume 0 != eval_~tmp~0#1; 587487#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 587477#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 587468#L519-2 havoc eval_~tmp_ndt_1~0#1; 587460#L516-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 587451#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 587443#L533-2 havoc eval_~tmp_ndt_2~0#1; 587433#L530-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 587382#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 587422#L547-2 havoc eval_~tmp_ndt_3~0#1; 587629#L544-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 587547#L561 assume !(0 != eval_~tmp_ndt_4~0#1); 587625#L561-2 havoc eval_~tmp_ndt_4~0#1; 587609#L558-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 587600#L575 assume !(0 != eval_~tmp_ndt_5~0#1); 587594#L575-2 havoc eval_~tmp_ndt_5~0#1; 587554#L572-1 assume !(0 == ~t5_st~0); 587551#L586-1 [2023-11-19 08:07:12,348 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:07:12,348 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 5 times [2023-11-19 08:07:12,348 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:07:12,349 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [672581845] [2023-11-19 08:07:12,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:07:12,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:07:12,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:12,364 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 08:07:12,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:12,391 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 08:07:12,392 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:07:12,392 INFO L85 PathProgramCache]: Analyzing trace with hash -175966429, now seen corresponding path program 1 times [2023-11-19 08:07:12,392 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:07:12,392 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1024791903] [2023-11-19 08:07:12,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:07:12,393 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:07:12,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:12,401 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 08:07:12,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:12,408 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 08:07:12,410 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:07:12,411 INFO L85 PathProgramCache]: Analyzing trace with hash 1014321193, now seen corresponding path program 1 times [2023-11-19 08:07:12,411 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:07:12,412 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2139879088] [2023-11-19 08:07:12,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:07:12,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:07:12,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:07:12,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:07:12,467 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:07:12,467 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2139879088] [2023-11-19 08:07:12,467 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2139879088] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:07:12,467 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:07:12,468 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 08:07:12,468 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [780012796] [2023-11-19 08:07:12,468 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:07:12,595 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:07:12,595 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:07:12,596 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:07:12,596 INFO L87 Difference]: Start difference. First operand 72871 states and 98308 transitions. cyclomatic complexity: 25443 Second operand has 3 states, 2 states have (on average 48.5) internal successors, (97), 3 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:07:13,636 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:07:13,636 INFO L93 Difference]: Finished difference Result 132403 states and 178164 transitions. [2023-11-19 08:07:13,636 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 132403 states and 178164 transitions. [2023-11-19 08:07:14,182 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 131914 [2023-11-19 08:07:15,134 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 132403 states to 132403 states and 178164 transitions. [2023-11-19 08:07:15,135 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 132403 [2023-11-19 08:07:15,222 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 132403 [2023-11-19 08:07:15,222 INFO L73 IsDeterministic]: Start isDeterministic. Operand 132403 states and 178164 transitions. [2023-11-19 08:07:15,360 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:07:15,361 INFO L218 hiAutomatonCegarLoop]: Abstraction has 132403 states and 178164 transitions. [2023-11-19 08:07:15,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132403 states and 178164 transitions. [2023-11-19 08:07:17,126 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132403 to 131667. [2023-11-19 08:07:17,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 131667 states, 131667 states have (on average 1.34755101885818) internal successors, (177428), 131666 states have internal predecessors, (177428), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:07:17,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131667 states to 131667 states and 177428 transitions. [2023-11-19 08:07:17,529 INFO L240 hiAutomatonCegarLoop]: Abstraction has 131667 states and 177428 transitions. [2023-11-19 08:07:17,529 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:07:17,529 INFO L428 stractBuchiCegarLoop]: Abstraction has 131667 states and 177428 transitions. [2023-11-19 08:07:17,530 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-19 08:07:17,530 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 131667 states and 177428 transitions. [2023-11-19 08:07:17,931 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 131178 [2023-11-19 08:07:17,931 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:07:17,932 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:07:17,933 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:07:17,933 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:07:17,933 INFO L748 eck$LassoCheckResult]: Stem: 746336#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 746337#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 746460#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 746461#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 746444#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 746445#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 746272#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 746273#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 746250#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 746251#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 746547#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 746362#L611 assume !(0 == ~M_E~0); 746363#L611-2 assume !(0 == ~T1_E~0); 746570#L616-1 assume !(0 == ~T2_E~0); 746571#L621-1 assume !(0 == ~T3_E~0); 746109#L626-1 assume !(0 == ~T4_E~0); 746110#L631-1 assume !(0 == ~T5_E~0); 746314#L636-1 assume !(0 == ~E_M~0); 746161#L641-1 assume !(0 == ~E_1~0); 746162#L646-1 assume !(0 == ~E_2~0); 746332#L651-1 assume !(0 == ~E_3~0); 746643#L656-1 assume !(0 == ~E_4~0); 746545#L661-1 assume !(0 == ~E_5~0); 746546#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 746602#L304 assume !(1 == ~m_pc~0); 746188#L304-2 is_master_triggered_~__retres1~0#1 := 0; 746085#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 746086#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 746035#L755 assume !(0 != activate_threads_~tmp~1#1); 746036#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 745992#L323 assume !(1 == ~t1_pc~0); 745993#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 746052#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 746053#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 746069#L763 assume !(0 != activate_threads_~tmp___0~0#1); 746701#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 746056#L342 assume !(1 == ~t2_pc~0); 746058#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 746196#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 746197#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 746464#L771 assume !(0 != activate_threads_~tmp___1~0#1); 746540#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 746404#L361 assume !(1 == ~t3_pc~0); 746405#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 746434#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 746008#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 746009#L779 assume !(0 != activate_threads_~tmp___2~0#1); 746072#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 746073#L380 assume !(1 == ~t4_pc~0); 746403#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 746559#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 746154#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 746155#L787 assume !(0 != activate_threads_~tmp___3~0#1); 746447#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 746131#L399 assume !(1 == ~t5_pc~0); 746132#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 746283#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 746289#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 746274#L795 assume !(0 != activate_threads_~tmp___4~0#1); 746275#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 746659#L679 assume !(1 == ~M_E~0); 746360#L679-2 assume !(1 == ~T1_E~0); 746211#L684-1 assume !(1 == ~T2_E~0); 746212#L689-1 assume !(1 == ~T3_E~0); 746415#L694-1 assume !(1 == ~T4_E~0); 746413#L699-1 assume !(1 == ~T5_E~0); 746414#L704-1 assume !(1 == ~E_M~0); 746390#L709-1 assume !(1 == ~E_1~0); 746318#L714-1 assume !(1 == ~E_2~0); 746319#L719-1 assume !(1 == ~E_3~0); 746535#L724-1 assume !(1 == ~E_4~0); 746097#L729-1 assume !(1 == ~E_5~0); 746098#L734-1 assume { :end_inline_reset_delta_events } true; 746666#L940-2 assume !false; 803497#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 803494#L586-1 [2023-11-19 08:07:17,934 INFO L750 eck$LassoCheckResult]: Loop: 803494#L586-1 assume !false; 803491#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 803487#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 803484#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 803480#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 803477#L511 assume 0 != eval_~tmp~0#1; 803474#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 803470#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 803466#L519-2 havoc eval_~tmp_ndt_1~0#1; 803463#L516-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 803459#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 803455#L533-2 havoc eval_~tmp_ndt_2~0#1; 803452#L530-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 803303#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 803448#L547-2 havoc eval_~tmp_ndt_3~0#1; 822134#L544-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 822131#L561 assume !(0 != eval_~tmp_ndt_4~0#1); 822130#L561-2 havoc eval_~tmp_ndt_4~0#1; 822129#L558-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 822127#L575 assume !(0 != eval_~tmp_ndt_5~0#1); 822126#L575-2 havoc eval_~tmp_ndt_5~0#1; 803505#L572-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet12#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet12#1;havoc eval_#t~nondet12#1; 803501#L589 assume !(0 != eval_~tmp_ndt_6~0#1); 803498#L589-2 havoc eval_~tmp_ndt_6~0#1; 803494#L586-1 [2023-11-19 08:07:17,934 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:07:17,935 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 6 times [2023-11-19 08:07:17,935 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:07:17,935 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [556521289] [2023-11-19 08:07:17,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:07:17,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:07:17,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:17,949 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 08:07:17,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:17,977 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 08:07:17,977 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:07:17,977 INFO L85 PathProgramCache]: Analyzing trace with hash -1600135949, now seen corresponding path program 1 times [2023-11-19 08:07:17,978 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:07:17,978 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [488235294] [2023-11-19 08:07:17,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:07:17,978 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:07:17,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:17,983 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 08:07:17,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:17,988 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 08:07:17,988 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:07:17,989 INFO L85 PathProgramCache]: Analyzing trace with hash -195031943, now seen corresponding path program 1 times [2023-11-19 08:07:17,989 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:07:17,989 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2075038680] [2023-11-19 08:07:17,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:07:17,989 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:07:18,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:18,002 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 08:07:18,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:18,034 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 08:07:20,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:20,740 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 08:07:20,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 08:07:21,031 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 19.11 08:07:21 BoogieIcfgContainer [2023-11-19 08:07:21,032 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-19 08:07:21,032 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-19 08:07:21,032 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-19 08:07:21,033 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-19 08:07:21,033 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 08:06:50" (3/4) ... [2023-11-19 08:07:21,035 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-19 08:07:21,165 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_29fd8cb5-ea16-406b-9e9c-449480d3a906/bin/uautomizer-verify-uCwYo4JHxu/witness.graphml [2023-11-19 08:07:21,166 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-19 08:07:21,167 INFO L158 Benchmark]: Toolchain (without parser) took 33314.30ms. Allocated memory was 142.6MB in the beginning and 11.7GB in the end (delta: 11.6GB). Free memory was 94.9MB in the beginning and 9.9GB in the end (delta: -9.8GB). Peak memory consumption was 1.8GB. Max. memory is 16.1GB. [2023-11-19 08:07:21,167 INFO L158 Benchmark]: CDTParser took 0.69ms. Allocated memory is still 142.6MB. Free memory is still 111.5MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-19 08:07:21,168 INFO L158 Benchmark]: CACSL2BoogieTranslator took 431.31ms. Allocated memory is still 142.6MB. Free memory was 94.4MB in the beginning and 78.2MB in the end (delta: 16.2MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2023-11-19 08:07:21,168 INFO L158 Benchmark]: Boogie Procedure Inliner took 104.11ms. Allocated memory is still 142.6MB. Free memory was 78.2MB in the beginning and 72.9MB in the end (delta: 5.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-19 08:07:21,169 INFO L158 Benchmark]: Boogie Preprocessor took 80.72ms. Allocated memory is still 142.6MB. Free memory was 72.9MB in the beginning and 68.2MB in the end (delta: 4.7MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2023-11-19 08:07:21,169 INFO L158 Benchmark]: RCFGBuilder took 1646.64ms. Allocated memory was 142.6MB in the beginning and 182.5MB in the end (delta: 39.8MB). Free memory was 68.2MB in the beginning and 112.3MB in the end (delta: -44.0MB). Peak memory consumption was 33.0MB. Max. memory is 16.1GB. [2023-11-19 08:07:21,170 INFO L158 Benchmark]: BuchiAutomizer took 30912.19ms. Allocated memory was 182.5MB in the beginning and 11.7GB in the end (delta: 11.5GB). Free memory was 111.2MB in the beginning and 9.9GB in the end (delta: -9.8GB). Peak memory consumption was 1.7GB. Max. memory is 16.1GB. [2023-11-19 08:07:21,170 INFO L158 Benchmark]: Witness Printer took 133.39ms. Allocated memory is still 11.7GB. Free memory was 9.9GB in the beginning and 9.9GB in the end (delta: 10.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2023-11-19 08:07:21,173 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.69ms. Allocated memory is still 142.6MB. Free memory is still 111.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 431.31ms. Allocated memory is still 142.6MB. Free memory was 94.4MB in the beginning and 78.2MB in the end (delta: 16.2MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 104.11ms. Allocated memory is still 142.6MB. Free memory was 78.2MB in the beginning and 72.9MB in the end (delta: 5.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 80.72ms. Allocated memory is still 142.6MB. Free memory was 72.9MB in the beginning and 68.2MB in the end (delta: 4.7MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * RCFGBuilder took 1646.64ms. Allocated memory was 142.6MB in the beginning and 182.5MB in the end (delta: 39.8MB). Free memory was 68.2MB in the beginning and 112.3MB in the end (delta: -44.0MB). Peak memory consumption was 33.0MB. Max. memory is 16.1GB. * BuchiAutomizer took 30912.19ms. Allocated memory was 182.5MB in the beginning and 11.7GB in the end (delta: 11.5GB). Free memory was 111.2MB in the beginning and 9.9GB in the end (delta: -9.8GB). Peak memory consumption was 1.7GB. Max. memory is 16.1GB. * Witness Printer took 133.39ms. Allocated memory is still 11.7GB. Free memory was 9.9GB in the beginning and 9.9GB in the end (delta: 10.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 23 terminating modules (23 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.23 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 131667 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 30.6s and 24 iterations. TraceHistogramMax:1. Analysis of lassos took 7.2s. Construction of modules took 1.2s. Büchi inclusion checks took 20.1s. Highest rank in rank-based complementation 0. Minimization of det autom 23. Minimization of nondet autom 0. Automata minimization 8.8s AutomataMinimizationTime, 23 MinimizatonAttempts, 31190 StatesRemovedByMinimization, 15 NontrivialMinimizations. Non-live state removal took 5.5s Buchi closure took 0.3s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 21344 SdHoareTripleChecker+Valid, 1.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 21344 mSDsluCounter, 39046 SdHoareTripleChecker+Invalid, 1.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 18059 mSDsCounter, 331 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 806 IncrementalHoareTripleChecker+Invalid, 1137 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 331 mSolverCounterUnsat, 20987 mSDtfsCounter, 806 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc5 concLT0 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 506]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int t5_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int t5_st ; [L36] int m_i ; [L37] int t1_i ; [L38] int t2_i ; [L39] int t3_i ; [L40] int t4_i ; [L41] int t5_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int E_M = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; [L61] int token ; [L63] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, token=0] [L985] int __retres1 ; [L989] CALL init_model() [L896] m_i = 1 [L897] t1_i = 1 [L898] t2_i = 1 [L899] t3_i = 1 [L900] t4_i = 1 [L901] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L989] RET init_model() [L990] CALL start_simulation() [L926] int kernel_st ; [L927] int tmp ; [L928] int tmp___0 ; [L932] kernel_st = 0 [L933] FCALL update_channels() [L934] CALL init_threads() [L426] COND TRUE m_i == 1 [L427] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L431] COND TRUE t1_i == 1 [L432] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L436] COND TRUE t2_i == 1 [L437] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L441] COND TRUE t3_i == 1 [L442] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L446] COND TRUE t4_i == 1 [L447] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L451] COND TRUE t5_i == 1 [L452] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L934] RET init_threads() [L935] CALL fire_delta_events() [L611] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L616] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L621] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L626] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L631] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L636] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L641] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L646] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L651] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L656] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L661] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L666] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L935] RET fire_delta_events() [L936] CALL activate_threads() [L744] int tmp ; [L745] int tmp___0 ; [L746] int tmp___1 ; [L747] int tmp___2 ; [L748] int tmp___3 ; [L749] int tmp___4 ; [L753] CALL, EXPR is_master_triggered() [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L304] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L314] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L316] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L753] RET, EXPR is_master_triggered() [L753] tmp = is_master_triggered() [L755] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, token=0] [L761] CALL, EXPR is_transmit1_triggered() [L320] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L323] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L333] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L335] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L761] RET, EXPR is_transmit1_triggered() [L761] tmp___0 = is_transmit1_triggered() [L763] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, token=0] [L769] CALL, EXPR is_transmit2_triggered() [L339] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L342] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L352] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L354] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L769] RET, EXPR is_transmit2_triggered() [L769] tmp___1 = is_transmit2_triggered() [L771] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L777] CALL, EXPR is_transmit3_triggered() [L358] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L361] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L371] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L373] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L777] RET, EXPR is_transmit3_triggered() [L777] tmp___2 = is_transmit3_triggered() [L779] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L785] CALL, EXPR is_transmit4_triggered() [L377] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L380] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L390] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L392] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L785] RET, EXPR is_transmit4_triggered() [L785] tmp___3 = is_transmit4_triggered() [L787] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L793] CALL, EXPR is_transmit5_triggered() [L396] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L399] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L409] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L411] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L793] RET, EXPR is_transmit5_triggered() [L793] tmp___4 = is_transmit5_triggered() [L795] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, token=0] [L936] RET activate_threads() [L937] CALL reset_delta_events() [L679] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L684] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L689] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L694] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L699] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L704] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L709] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L714] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L719] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L724] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L729] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L734] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L937] RET reset_delta_events() [L940] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, kernel_st=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L943] kernel_st = 1 [L944] CALL eval() [L502] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] Loop: [L506] COND TRUE 1 [L509] CALL, EXPR exists_runnable_thread() [L461] int __retres1 ; [L464] COND TRUE m_st == 0 [L465] __retres1 = 1 [L497] return (__retres1); [L509] RET, EXPR exists_runnable_thread() [L509] tmp = exists_runnable_thread() [L511] COND TRUE \read(tmp) [L516] COND TRUE m_st == 0 [L517] int tmp_ndt_1; [L518] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L519] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L516-L527] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L530] COND TRUE t1_st == 0 [L531] int tmp_ndt_2; [L532] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L533] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L530-L541] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L544] COND TRUE t2_st == 0 [L545] int tmp_ndt_3; [L546] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L547] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L544-L555] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L558] COND TRUE t3_st == 0 [L559] int tmp_ndt_4; [L560] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L561] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L558-L569] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L572] COND TRUE t4_st == 0 [L573] int tmp_ndt_5; [L574] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L575] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L572-L583] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } [L586] COND TRUE t5_st == 0 [L587] int tmp_ndt_6; [L588] EXPR tmp_ndt_6 = __VERIFIER_nondet_int() [L589] COND FALSE, EXPR !(\read(tmp_ndt_6)) [L586-L597] { int tmp_ndt_6; tmp_ndt_6 = __VERIFIER_nondet_int(); if (tmp_ndt_6) { { t5_st = 1; transmit5(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 506]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int t5_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int t5_st ; [L36] int m_i ; [L37] int t1_i ; [L38] int t2_i ; [L39] int t3_i ; [L40] int t4_i ; [L41] int t5_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int E_M = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; [L61] int token ; [L63] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, token=0] [L985] int __retres1 ; [L989] CALL init_model() [L896] m_i = 1 [L897] t1_i = 1 [L898] t2_i = 1 [L899] t3_i = 1 [L900] t4_i = 1 [L901] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L989] RET init_model() [L990] CALL start_simulation() [L926] int kernel_st ; [L927] int tmp ; [L928] int tmp___0 ; [L932] kernel_st = 0 [L933] FCALL update_channels() [L934] CALL init_threads() [L426] COND TRUE m_i == 1 [L427] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L431] COND TRUE t1_i == 1 [L432] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L436] COND TRUE t2_i == 1 [L437] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L441] COND TRUE t3_i == 1 [L442] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L446] COND TRUE t4_i == 1 [L447] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L451] COND TRUE t5_i == 1 [L452] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L934] RET init_threads() [L935] CALL fire_delta_events() [L611] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L616] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L621] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L626] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L631] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L636] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L641] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L646] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L651] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L656] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L661] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L666] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L935] RET fire_delta_events() [L936] CALL activate_threads() [L744] int tmp ; [L745] int tmp___0 ; [L746] int tmp___1 ; [L747] int tmp___2 ; [L748] int tmp___3 ; [L749] int tmp___4 ; [L753] CALL, EXPR is_master_triggered() [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L304] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L314] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L316] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L753] RET, EXPR is_master_triggered() [L753] tmp = is_master_triggered() [L755] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, token=0] [L761] CALL, EXPR is_transmit1_triggered() [L320] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L323] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L333] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L335] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L761] RET, EXPR is_transmit1_triggered() [L761] tmp___0 = is_transmit1_triggered() [L763] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, token=0] [L769] CALL, EXPR is_transmit2_triggered() [L339] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L342] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L352] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L354] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L769] RET, EXPR is_transmit2_triggered() [L769] tmp___1 = is_transmit2_triggered() [L771] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L777] CALL, EXPR is_transmit3_triggered() [L358] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L361] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L371] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L373] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L777] RET, EXPR is_transmit3_triggered() [L777] tmp___2 = is_transmit3_triggered() [L779] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L785] CALL, EXPR is_transmit4_triggered() [L377] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L380] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L390] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L392] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L785] RET, EXPR is_transmit4_triggered() [L785] tmp___3 = is_transmit4_triggered() [L787] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L793] CALL, EXPR is_transmit5_triggered() [L396] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L399] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L409] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L411] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L793] RET, EXPR is_transmit5_triggered() [L793] tmp___4 = is_transmit5_triggered() [L795] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, token=0] [L936] RET activate_threads() [L937] CALL reset_delta_events() [L679] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L684] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L689] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L694] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L699] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L704] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L709] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L714] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L719] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L724] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L729] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L734] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L937] RET reset_delta_events() [L940] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, kernel_st=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L943] kernel_st = 1 [L944] CALL eval() [L502] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] Loop: [L506] COND TRUE 1 [L509] CALL, EXPR exists_runnable_thread() [L461] int __retres1 ; [L464] COND TRUE m_st == 0 [L465] __retres1 = 1 [L497] return (__retres1); [L509] RET, EXPR exists_runnable_thread() [L509] tmp = exists_runnable_thread() [L511] COND TRUE \read(tmp) [L516] COND TRUE m_st == 0 [L517] int tmp_ndt_1; [L518] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L519] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L516-L527] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L530] COND TRUE t1_st == 0 [L531] int tmp_ndt_2; [L532] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L533] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L530-L541] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L544] COND TRUE t2_st == 0 [L545] int tmp_ndt_3; [L546] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L547] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L544-L555] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L558] COND TRUE t3_st == 0 [L559] int tmp_ndt_4; [L560] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L561] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L558-L569] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L572] COND TRUE t4_st == 0 [L573] int tmp_ndt_5; [L574] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L575] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L572-L583] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } [L586] COND TRUE t5_st == 0 [L587] int tmp_ndt_6; [L588] EXPR tmp_ndt_6 = __VERIFIER_nondet_int() [L589] COND FALSE, EXPR !(\read(tmp_ndt_6)) [L586-L597] { int tmp_ndt_6; tmp_ndt_6 = __VERIFIER_nondet_int(); if (tmp_ndt_6) { { t5_st = 1; transmit5(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-19 08:07:21,392 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_29fd8cb5-ea16-406b-9e9c-449480d3a906/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)