./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.07.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 9bd2c7ff Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1204218a-7a5c-4b6b-a88c-3feec50ecca9/bin/uautomizer-verify-uCwYo4JHxu/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1204218a-7a5c-4b6b-a88c-3feec50ecca9/bin/uautomizer-verify-uCwYo4JHxu/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1204218a-7a5c-4b6b-a88c-3feec50ecca9/bin/uautomizer-verify-uCwYo4JHxu/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1204218a-7a5c-4b6b-a88c-3feec50ecca9/bin/uautomizer-verify-uCwYo4JHxu/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.07.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1204218a-7a5c-4b6b-a88c-3feec50ecca9/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1204218a-7a5c-4b6b-a88c-3feec50ecca9/bin/uautomizer-verify-uCwYo4JHxu --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a6baa92d18991a792383fc99c5c300f37f700ba00714b15a3dbe7d2191a67ca9 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-9bd2c7f [2023-11-19 07:54:25,267 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-19 07:54:25,406 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1204218a-7a5c-4b6b-a88c-3feec50ecca9/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-19 07:54:25,423 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-19 07:54:25,424 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-19 07:54:25,472 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-19 07:54:25,474 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-19 07:54:25,474 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-19 07:54:25,476 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-19 07:54:25,482 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-19 07:54:25,483 INFO L153 SettingsManager]: * Use SBE=true [2023-11-19 07:54:25,484 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-19 07:54:25,484 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-19 07:54:25,487 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-19 07:54:25,487 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-19 07:54:25,488 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-19 07:54:25,488 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-19 07:54:25,489 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-19 07:54:25,490 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-19 07:54:25,490 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-19 07:54:25,491 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-19 07:54:25,491 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-19 07:54:25,492 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-19 07:54:25,492 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-19 07:54:25,493 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-19 07:54:25,493 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-19 07:54:25,494 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-19 07:54:25,494 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-19 07:54:25,495 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-19 07:54:25,495 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-19 07:54:25,497 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-19 07:54:25,497 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-19 07:54:25,498 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-19 07:54:25,498 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-19 07:54:25,498 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-19 07:54:25,499 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-19 07:54:25,499 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1204218a-7a5c-4b6b-a88c-3feec50ecca9/bin/uautomizer-verify-uCwYo4JHxu/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1204218a-7a5c-4b6b-a88c-3feec50ecca9/bin/uautomizer-verify-uCwYo4JHxu Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a6baa92d18991a792383fc99c5c300f37f700ba00714b15a3dbe7d2191a67ca9 [2023-11-19 07:54:25,778 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-19 07:54:25,801 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-19 07:54:25,804 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-19 07:54:25,805 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-19 07:54:25,806 INFO L274 PluginConnector]: CDTParser initialized [2023-11-19 07:54:25,807 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1204218a-7a5c-4b6b-a88c-3feec50ecca9/bin/uautomizer-verify-uCwYo4JHxu/../../sv-benchmarks/c/systemc/token_ring.07.cil-1.c [2023-11-19 07:54:29,141 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-19 07:54:29,530 INFO L384 CDTParser]: Found 1 translation units. [2023-11-19 07:54:29,534 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1204218a-7a5c-4b6b-a88c-3feec50ecca9/sv-benchmarks/c/systemc/token_ring.07.cil-1.c [2023-11-19 07:54:29,561 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1204218a-7a5c-4b6b-a88c-3feec50ecca9/bin/uautomizer-verify-uCwYo4JHxu/data/6e8388d6b/3b82496f1b094ea995149d93330240c1/FLAG379ee46ea [2023-11-19 07:54:29,584 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1204218a-7a5c-4b6b-a88c-3feec50ecca9/bin/uautomizer-verify-uCwYo4JHxu/data/6e8388d6b/3b82496f1b094ea995149d93330240c1 [2023-11-19 07:54:29,590 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-19 07:54:29,593 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-19 07:54:29,596 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-19 07:54:29,598 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-19 07:54:29,604 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-19 07:54:29,605 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:54:29" (1/1) ... [2023-11-19 07:54:29,606 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@690eab88 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:54:29, skipping insertion in model container [2023-11-19 07:54:29,607 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:54:29" (1/1) ... [2023-11-19 07:54:29,681 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-19 07:54:29,976 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:54:29,994 INFO L202 MainTranslator]: Completed pre-run [2023-11-19 07:54:30,068 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:54:30,094 INFO L206 MainTranslator]: Completed translation [2023-11-19 07:54:30,094 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:54:30 WrapperNode [2023-11-19 07:54:30,095 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-19 07:54:30,096 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-19 07:54:30,096 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-19 07:54:30,096 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-19 07:54:30,106 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:54:30" (1/1) ... [2023-11-19 07:54:30,122 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:54:30" (1/1) ... [2023-11-19 07:54:30,202 INFO L138 Inliner]: procedures = 42, calls = 53, calls flagged for inlining = 48, calls inlined = 135, statements flattened = 2006 [2023-11-19 07:54:30,203 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-19 07:54:30,203 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-19 07:54:30,204 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-19 07:54:30,204 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-19 07:54:30,215 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:54:30" (1/1) ... [2023-11-19 07:54:30,216 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:54:30" (1/1) ... [2023-11-19 07:54:30,230 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:54:30" (1/1) ... [2023-11-19 07:54:30,231 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:54:30" (1/1) ... [2023-11-19 07:54:30,269 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:54:30" (1/1) ... [2023-11-19 07:54:30,296 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:54:30" (1/1) ... [2023-11-19 07:54:30,305 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:54:30" (1/1) ... [2023-11-19 07:54:30,313 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:54:30" (1/1) ... [2023-11-19 07:54:30,343 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-19 07:54:30,344 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-19 07:54:30,344 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-19 07:54:30,344 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-19 07:54:30,345 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:54:30" (1/1) ... [2023-11-19 07:54:30,365 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 07:54:30,385 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1204218a-7a5c-4b6b-a88c-3feec50ecca9/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:54:30,404 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1204218a-7a5c-4b6b-a88c-3feec50ecca9/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 07:54:30,429 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1204218a-7a5c-4b6b-a88c-3feec50ecca9/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-19 07:54:30,463 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-19 07:54:30,464 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-19 07:54:30,464 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-19 07:54:30,465 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-19 07:54:30,646 INFO L236 CfgBuilder]: Building ICFG [2023-11-19 07:54:30,649 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-19 07:54:32,395 INFO L277 CfgBuilder]: Performing block encoding [2023-11-19 07:54:32,422 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-19 07:54:32,422 INFO L302 CfgBuilder]: Removed 10 assume(true) statements. [2023-11-19 07:54:32,436 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:54:32 BoogieIcfgContainer [2023-11-19 07:54:32,436 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-19 07:54:32,438 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-19 07:54:32,438 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-19 07:54:32,442 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-19 07:54:32,443 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:54:32,443 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 07:54:29" (1/3) ... [2023-11-19 07:54:32,445 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@ab7f372 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:54:32, skipping insertion in model container [2023-11-19 07:54:32,445 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:54:32,445 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:54:30" (2/3) ... [2023-11-19 07:54:32,447 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@ab7f372 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:54:32, skipping insertion in model container [2023-11-19 07:54:32,447 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:54:32,448 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:54:32" (3/3) ... [2023-11-19 07:54:32,449 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.07.cil-1.c [2023-11-19 07:54:32,537 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-19 07:54:32,538 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-19 07:54:32,538 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-19 07:54:32,538 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-19 07:54:32,538 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-19 07:54:32,538 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-19 07:54:32,538 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-19 07:54:32,539 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-19 07:54:32,548 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 845 states, 844 states have (on average 1.5130331753554502) internal successors, (1277), 844 states have internal predecessors, (1277), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:32,627 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 738 [2023-11-19 07:54:32,627 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:54:32,627 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:54:32,642 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:32,642 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:32,642 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-19 07:54:32,644 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 845 states, 844 states have (on average 1.5130331753554502) internal successors, (1277), 844 states have internal predecessors, (1277), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:32,680 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 738 [2023-11-19 07:54:32,681 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:54:32,681 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:54:32,687 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:32,687 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:32,714 INFO L748 eck$LassoCheckResult]: Stem: 111#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 764#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 625#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 760#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 581#L536true assume !(1 == ~m_i~0);~m_st~0 := 2; 793#L536-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 264#L541-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 151#L546-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 650#L551-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 139#L556-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 599#L561-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 578#L566-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 376#L571-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 670#L769true assume !(0 == ~M_E~0); 393#L769-2true assume !(0 == ~T1_E~0); 417#L774-1true assume !(0 == ~T2_E~0); 688#L779-1true assume !(0 == ~T3_E~0); 559#L784-1true assume !(0 == ~T4_E~0); 374#L789-1true assume !(0 == ~T5_E~0); 473#L794-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 826#L799-1true assume !(0 == ~T7_E~0); 378#L804-1true assume !(0 == ~E_M~0); 410#L809-1true assume !(0 == ~E_1~0); 592#L814-1true assume !(0 == ~E_2~0); 9#L819-1true assume !(0 == ~E_3~0); 189#L824-1true assume !(0 == ~E_4~0); 816#L829-1true assume !(0 == ~E_5~0); 683#L834-1true assume 0 == ~E_6~0;~E_6~0 := 1; 72#L839-1true assume !(0 == ~E_7~0); 479#L844-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 330#L376true assume !(1 == ~m_pc~0); 328#L376-2true is_master_triggered_~__retres1~0#1 := 0; 775#L387true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 538#is_master_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 43#L955true assume !(0 != activate_threads_~tmp~1#1); 256#L955-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 394#L395true assume 1 == ~t1_pc~0; 61#L396true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 560#L406true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 606#L963true assume !(0 != activate_threads_~tmp___0~0#1); 336#L963-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 836#L414true assume !(1 == ~t2_pc~0); 590#L414-2true is_transmit2_triggered_~__retres1~2#1 := 0; 824#L425true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 196#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 588#L971true assume !(0 != activate_threads_~tmp___1~0#1); 699#L971-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 261#L433true assume 1 == ~t3_pc~0; 220#L434true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 709#L444true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 522#L979true assume !(0 != activate_threads_~tmp___2~0#1); 55#L979-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 794#L452true assume !(1 == ~t4_pc~0); 137#L452-2true is_transmit4_triggered_~__retres1~4#1 := 0; 363#L463true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 706#L987true assume !(0 != activate_threads_~tmp___3~0#1); 156#L987-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 458#L471true assume 1 == ~t5_pc~0; 755#L472true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 145#L482true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 542#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 822#L995true assume !(0 != activate_threads_~tmp___4~0#1); 673#L995-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 741#L490true assume 1 == ~t6_pc~0; 632#L491true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 368#L501true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 186#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 371#L1003true assume !(0 != activate_threads_~tmp___5~0#1); 270#L1003-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 244#L509true assume !(1 == ~t7_pc~0); 593#L509-2true is_transmit7_triggered_~__retres1~7#1 := 0; 123#L520true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 778#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 159#L1011true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 708#L1011-2true havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 603#L857true assume !(1 == ~M_E~0); 46#L857-2true assume !(1 == ~T1_E~0); 198#L862-1true assume !(1 == ~T2_E~0); 203#L867-1true assume !(1 == ~T3_E~0); 262#L872-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 436#L877-1true assume !(1 == ~T5_E~0); 631#L882-1true assume !(1 == ~T6_E~0); 748#L887-1true assume !(1 == ~T7_E~0); 497#L892-1true assume !(1 == ~E_M~0); 714#L897-1true assume !(1 == ~E_1~0); 213#L902-1true assume !(1 == ~E_2~0); 514#L907-1true assume !(1 == ~E_3~0); 448#L912-1true assume 1 == ~E_4~0;~E_4~0 := 2; 442#L917-1true assume !(1 == ~E_5~0); 692#L922-1true assume !(1 == ~E_6~0); 801#L927-1true assume !(1 == ~E_7~0); 433#L932-1true assume { :end_inline_reset_delta_events } true; 727#L1178-2true [2023-11-19 07:54:32,717 INFO L750 eck$LassoCheckResult]: Loop: 727#L1178-2true assume !false; 420#L1179true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 536#L744-1true assume false; 500#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 306#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 668#L769-3true assume 0 == ~M_E~0;~M_E~0 := 1; 259#L769-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 399#L774-3true assume !(0 == ~T2_E~0); 99#L779-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 14#L784-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 837#L789-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 10#L794-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 32#L799-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 162#L804-3true assume 0 == ~E_M~0;~E_M~0 := 1; 332#L809-3true assume 0 == ~E_1~0;~E_1~0 := 1; 30#L814-3true assume !(0 == ~E_2~0); 570#L819-3true assume 0 == ~E_3~0;~E_3~0 := 1; 525#L824-3true assume 0 == ~E_4~0;~E_4~0 := 1; 518#L829-3true assume 0 == ~E_5~0;~E_5~0 := 1; 199#L834-3true assume 0 == ~E_6~0;~E_6~0 := 1; 472#L839-3true assume 0 == ~E_7~0;~E_7~0 := 1; 600#L844-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 740#L376-27true assume !(1 == ~m_pc~0); 827#L376-29true is_master_triggered_~__retres1~0#1 := 0; 397#L387-9true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 464#is_master_triggered_returnLabel#10true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 701#L955-27true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 832#L955-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 817#L395-27true assume !(1 == ~t1_pc~0); 275#L395-29true is_transmit1_triggered_~__retres1~1#1 := 0; 200#L406-9true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 366#is_transmit1_triggered_returnLabel#10true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 392#L963-27true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 266#L963-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 664#L414-27true assume !(1 == ~t2_pc~0); 757#L414-29true is_transmit2_triggered_~__retres1~2#1 := 0; 441#L425-9true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 439#is_transmit2_triggered_returnLabel#10true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 319#L971-27true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36#L971-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85#L433-27true assume !(1 == ~t3_pc~0); 323#L433-29true is_transmit3_triggered_~__retres1~3#1 := 0; 272#L444-9true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 302#is_transmit3_triggered_returnLabel#10true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 125#L979-27true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 765#L979-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 751#L452-27true assume !(1 == ~t4_pc~0); 408#L452-29true is_transmit4_triggered_~__retres1~4#1 := 0; 563#L463-9true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 243#is_transmit4_triggered_returnLabel#10true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 659#L987-27true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 671#L987-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33#L471-27true assume 1 == ~t5_pc~0; 501#L472-9true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 833#L482-9true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 555#is_transmit5_triggered_returnLabel#10true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 461#L995-27true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 395#L995-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 329#L490-27true assume !(1 == ~t6_pc~0); 622#L490-29true is_transmit6_triggered_~__retres1~6#1 := 0; 131#L501-9true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 684#is_transmit6_triggered_returnLabel#10true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 447#L1003-27true assume !(0 != activate_threads_~tmp___5~0#1); 722#L1003-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18#L509-27true assume !(1 == ~t7_pc~0); 242#L509-29true is_transmit7_triggered_~__retres1~7#1 := 0; 552#L520-9true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 166#is_transmit7_triggered_returnLabel#10true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 349#L1011-27true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 811#L1011-29true havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 359#L857-3true assume 1 == ~M_E~0;~M_E~0 := 2; 389#L857-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 798#L862-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 742#L867-3true assume !(1 == ~T3_E~0); 273#L872-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 354#L877-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 776#L882-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 386#L887-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 109#L892-3true assume 1 == ~E_M~0;~E_M~0 := 2; 548#L897-3true assume 1 == ~E_1~0;~E_1~0 := 2; 835#L902-3true assume 1 == ~E_2~0;~E_2~0 := 2; 212#L907-3true assume !(1 == ~E_3~0); 310#L912-3true assume 1 == ~E_4~0;~E_4~0 := 2; 585#L917-3true assume 1 == ~E_5~0;~E_5~0 := 2; 276#L922-3true assume 1 == ~E_6~0;~E_6~0 := 2; 138#L927-3true assume 1 == ~E_7~0;~E_7~0 := 2; 221#L932-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 60#L584-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 476#L626-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 170#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 251#L1197true assume !(0 == start_simulation_~tmp~3#1); 529#L1197-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 88#L584-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 258#L626-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 21#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 753#L1152true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 545#L1159true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 321#stop_simulation_returnLabel#1true start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 24#L1210true assume !(0 != start_simulation_~tmp___0~1#1); 727#L1178-2true [2023-11-19 07:54:32,730 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:32,735 INFO L85 PathProgramCache]: Analyzing trace with hash 1617538625, now seen corresponding path program 1 times [2023-11-19 07:54:32,746 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:32,747 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [311965324] [2023-11-19 07:54:32,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:32,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:32,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:33,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:33,135 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:33,136 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [311965324] [2023-11-19 07:54:33,136 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [311965324] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:33,137 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:33,137 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:33,138 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [667944796] [2023-11-19 07:54:33,139 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:33,144 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:54:33,147 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:33,147 INFO L85 PathProgramCache]: Analyzing trace with hash 698466512, now seen corresponding path program 1 times [2023-11-19 07:54:33,147 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:33,147 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1253395388] [2023-11-19 07:54:33,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:33,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:33,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:33,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:33,263 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:33,263 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1253395388] [2023-11-19 07:54:33,264 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1253395388] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:33,264 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:33,264 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:54:33,264 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1525953149] [2023-11-19 07:54:33,264 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:33,266 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:54:33,266 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:54:33,311 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:54:33,313 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:54:33,323 INFO L87 Difference]: Start difference. First operand has 845 states, 844 states have (on average 1.5130331753554502) internal successors, (1277), 844 states have internal predecessors, (1277), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:33,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:54:33,407 INFO L93 Difference]: Finished difference Result 843 states and 1253 transitions. [2023-11-19 07:54:33,409 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1253 transitions. [2023-11-19 07:54:33,421 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2023-11-19 07:54:33,438 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 838 states and 1248 transitions. [2023-11-19 07:54:33,439 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 838 [2023-11-19 07:54:33,442 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 838 [2023-11-19 07:54:33,442 INFO L73 IsDeterministic]: Start isDeterministic. Operand 838 states and 1248 transitions. [2023-11-19 07:54:33,448 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:54:33,448 INFO L218 hiAutomatonCegarLoop]: Abstraction has 838 states and 1248 transitions. [2023-11-19 07:54:33,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 838 states and 1248 transitions. [2023-11-19 07:54:33,514 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 838 to 838. [2023-11-19 07:54:33,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 838 states, 838 states have (on average 1.4892601431980907) internal successors, (1248), 837 states have internal predecessors, (1248), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:33,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 838 states to 838 states and 1248 transitions. [2023-11-19 07:54:33,522 INFO L240 hiAutomatonCegarLoop]: Abstraction has 838 states and 1248 transitions. [2023-11-19 07:54:33,524 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:54:33,528 INFO L428 stractBuchiCegarLoop]: Abstraction has 838 states and 1248 transitions. [2023-11-19 07:54:33,528 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-19 07:54:33,528 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 838 states and 1248 transitions. [2023-11-19 07:54:33,536 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2023-11-19 07:54:33,536 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:54:33,537 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:54:33,540 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:33,541 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:33,541 INFO L748 eck$LassoCheckResult]: Stem: 1924#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1925#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2481#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2482#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2461#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 2462#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2169#L541-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1993#L546-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1994#L551-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1975#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1976#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2460#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2285#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2286#L769 assume !(0 == ~M_E~0); 2305#L769-2 assume !(0 == ~T1_E~0); 2306#L774-1 assume !(0 == ~T2_E~0); 2333#L779-1 assume !(0 == ~T3_E~0); 2450#L784-1 assume !(0 == ~T4_E~0); 2283#L789-1 assume !(0 == ~T5_E~0); 2284#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2389#L799-1 assume !(0 == ~T7_E~0); 2288#L804-1 assume !(0 == ~E_M~0); 2289#L809-1 assume !(0 == ~E_1~0); 2328#L814-1 assume !(0 == ~E_2~0); 1712#L819-1 assume !(0 == ~E_3~0); 1713#L824-1 assume !(0 == ~E_4~0); 2066#L829-1 assume !(0 == ~E_5~0); 2509#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 1849#L839-1 assume !(0 == ~E_7~0); 1850#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2241#L376 assume !(1 == ~m_pc~0); 2230#L376-2 is_master_triggered_~__retres1~0#1 := 0; 2229#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2435#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1790#L955 assume !(0 != activate_threads_~tmp~1#1); 1791#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2162#L395 assume 1 == ~t1_pc~0; 1826#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1827#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1742#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1743#L963 assume !(0 != activate_threads_~tmp___0~0#1); 2245#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2246#L414 assume !(1 == ~t2_pc~0); 1852#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1853#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2072#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2073#L971 assume !(0 != activate_threads_~tmp___1~0#1); 2465#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2166#L433 assume 1 == ~t3_pc~0; 2108#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1964#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1710#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1711#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1815#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1816#L452 assume !(1 == ~t4_pc~0); 1971#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1972#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1809#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1810#L987 assume !(0 != activate_threads_~tmp___3~0#1); 2004#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2005#L471 assume 1 == ~t5_pc~0; 2376#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1986#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1987#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2438#L995 assume !(0 != activate_threads_~tmp___4~0#1); 2500#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2501#L490 assume 1 == ~t6_pc~0; 2486#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2244#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2059#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2060#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 2176#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2144#L509 assume !(1 == ~t7_pc~0); 2145#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1946#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1947#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2011#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2012#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2471#L857 assume !(1 == ~M_E~0); 1797#L857-2 assume !(1 == ~T1_E~0); 1798#L862-1 assume !(1 == ~T2_E~0); 2076#L867-1 assume !(1 == ~T3_E~0); 2081#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2167#L877-1 assume !(1 == ~T5_E~0); 2352#L882-1 assume !(1 == ~T6_E~0); 2485#L887-1 assume !(1 == ~T7_E~0); 2405#L892-1 assume !(1 == ~E_M~0); 2406#L897-1 assume !(1 == ~E_1~0); 2096#L902-1 assume !(1 == ~E_2~0); 2097#L907-1 assume !(1 == ~E_3~0); 2366#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2358#L917-1 assume !(1 == ~E_5~0); 2359#L922-1 assume !(1 == ~E_6~0); 2511#L927-1 assume !(1 == ~E_7~0); 2347#L932-1 assume { :end_inline_reset_delta_events } true; 1747#L1178-2 [2023-11-19 07:54:33,542 INFO L750 eck$LassoCheckResult]: Loop: 1747#L1178-2 assume !false; 2334#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2335#L744-1 assume !false; 2208#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2209#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1782#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1991#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2093#L641 assume !(0 != eval_~tmp~0#1); 2407#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2216#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2217#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2164#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2165#L774-3 assume !(0 == ~T2_E~0); 1903#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1723#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1724#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1714#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1715#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1764#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2018#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1760#L814-3 assume !(0 == ~E_2~0); 1761#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2426#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2421#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2077#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2078#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2388#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2469#L376-27 assume 1 == ~m_pc~0; 2362#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2311#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2312#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2383#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2513#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2534#L395-27 assume 1 == ~t1_pc~0; 2530#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2079#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2080#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2276#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2171#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2172#L414-27 assume 1 == ~t2_pc~0; 2497#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2357#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2356#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2232#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1772#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1773#L433-27 assume !(1 == ~t3_pc~0); 1875#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 2178#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2179#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1949#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1950#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2525#L452-27 assume !(1 == ~t4_pc~0); 2325#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 2326#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2142#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2143#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2494#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1765#L471-27 assume 1 == ~t5_pc~0; 1766#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2090#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2447#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2380#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2307#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2240#L490-27 assume 1 == ~t6_pc~0; 2139#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1960#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1961#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2364#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 2365#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1732#L509-27 assume 1 == ~t7_pc~0; 1733#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2141#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2022#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2023#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2260#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2272#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2273#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2303#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2524#L867-3 assume !(1 == ~T3_E~0); 2180#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2181#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2267#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2297#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1920#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1921#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2444#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2094#L907-3 assume !(1 == ~E_3~0); 2095#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2220#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2185#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1973#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1974#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1824#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1721#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2031#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 2032#L1197 assume !(0 == start_simulation_~tmp~3#1); 2153#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1883#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1847#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1740#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1741#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2441#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2234#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1746#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1747#L1178-2 [2023-11-19 07:54:33,543 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:33,544 INFO L85 PathProgramCache]: Analyzing trace with hash -736846657, now seen corresponding path program 1 times [2023-11-19 07:54:33,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:33,544 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [356162476] [2023-11-19 07:54:33,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:33,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:33,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:33,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:33,622 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:33,622 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [356162476] [2023-11-19 07:54:33,623 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [356162476] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:33,623 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:33,623 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:33,624 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [795371062] [2023-11-19 07:54:33,624 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:33,624 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:54:33,625 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:33,625 INFO L85 PathProgramCache]: Analyzing trace with hash -542624296, now seen corresponding path program 1 times [2023-11-19 07:54:33,626 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:33,626 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1465495531] [2023-11-19 07:54:33,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:33,626 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:33,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:33,773 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:33,775 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:33,777 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1465495531] [2023-11-19 07:54:33,778 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1465495531] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:33,778 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:33,778 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:33,778 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1777262122] [2023-11-19 07:54:33,779 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:33,779 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:54:33,780 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:54:33,780 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:54:33,780 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:54:33,781 INFO L87 Difference]: Start difference. First operand 838 states and 1248 transitions. cyclomatic complexity: 411 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:33,810 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:54:33,811 INFO L93 Difference]: Finished difference Result 838 states and 1247 transitions. [2023-11-19 07:54:33,811 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 838 states and 1247 transitions. [2023-11-19 07:54:33,821 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2023-11-19 07:54:33,829 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 838 states to 838 states and 1247 transitions. [2023-11-19 07:54:33,830 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 838 [2023-11-19 07:54:33,831 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 838 [2023-11-19 07:54:33,832 INFO L73 IsDeterministic]: Start isDeterministic. Operand 838 states and 1247 transitions. [2023-11-19 07:54:33,834 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:54:33,835 INFO L218 hiAutomatonCegarLoop]: Abstraction has 838 states and 1247 transitions. [2023-11-19 07:54:33,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 838 states and 1247 transitions. [2023-11-19 07:54:33,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 838 to 838. [2023-11-19 07:54:33,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 838 states, 838 states have (on average 1.4880668257756564) internal successors, (1247), 837 states have internal predecessors, (1247), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:33,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 838 states to 838 states and 1247 transitions. [2023-11-19 07:54:33,868 INFO L240 hiAutomatonCegarLoop]: Abstraction has 838 states and 1247 transitions. [2023-11-19 07:54:33,870 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:54:33,871 INFO L428 stractBuchiCegarLoop]: Abstraction has 838 states and 1247 transitions. [2023-11-19 07:54:33,871 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-19 07:54:33,872 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 838 states and 1247 transitions. [2023-11-19 07:54:33,880 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2023-11-19 07:54:33,882 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:54:33,882 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:54:33,888 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:33,894 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:33,897 INFO L748 eck$LassoCheckResult]: Stem: 3607#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 3608#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 4164#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4165#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4144#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 4145#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3852#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3676#L546-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3677#L551-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3658#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3659#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4143#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3968#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3969#L769 assume !(0 == ~M_E~0); 3988#L769-2 assume !(0 == ~T1_E~0); 3989#L774-1 assume !(0 == ~T2_E~0); 4016#L779-1 assume !(0 == ~T3_E~0); 4133#L784-1 assume !(0 == ~T4_E~0); 3966#L789-1 assume !(0 == ~T5_E~0); 3967#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4072#L799-1 assume !(0 == ~T7_E~0); 3971#L804-1 assume !(0 == ~E_M~0); 3972#L809-1 assume !(0 == ~E_1~0); 4011#L814-1 assume !(0 == ~E_2~0); 3395#L819-1 assume !(0 == ~E_3~0); 3396#L824-1 assume !(0 == ~E_4~0); 3749#L829-1 assume !(0 == ~E_5~0); 4192#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 3532#L839-1 assume !(0 == ~E_7~0); 3533#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3924#L376 assume !(1 == ~m_pc~0); 3913#L376-2 is_master_triggered_~__retres1~0#1 := 0; 3912#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4118#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3473#L955 assume !(0 != activate_threads_~tmp~1#1); 3474#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3845#L395 assume 1 == ~t1_pc~0; 3509#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3510#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3425#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3426#L963 assume !(0 != activate_threads_~tmp___0~0#1); 3928#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3929#L414 assume !(1 == ~t2_pc~0); 3535#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3536#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3755#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3756#L971 assume !(0 != activate_threads_~tmp___1~0#1); 4148#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3849#L433 assume 1 == ~t3_pc~0; 3791#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3647#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3393#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3394#L979 assume !(0 != activate_threads_~tmp___2~0#1); 3498#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3499#L452 assume !(1 == ~t4_pc~0); 3654#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3655#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3492#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3493#L987 assume !(0 != activate_threads_~tmp___3~0#1); 3687#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3688#L471 assume 1 == ~t5_pc~0; 4059#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3669#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3670#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4121#L995 assume !(0 != activate_threads_~tmp___4~0#1); 4183#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4184#L490 assume 1 == ~t6_pc~0; 4169#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3927#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3742#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3743#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 3859#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3827#L509 assume !(1 == ~t7_pc~0); 3828#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3629#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3630#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3694#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3695#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4154#L857 assume !(1 == ~M_E~0); 3480#L857-2 assume !(1 == ~T1_E~0); 3481#L862-1 assume !(1 == ~T2_E~0); 3759#L867-1 assume !(1 == ~T3_E~0); 3764#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3850#L877-1 assume !(1 == ~T5_E~0); 4035#L882-1 assume !(1 == ~T6_E~0); 4168#L887-1 assume !(1 == ~T7_E~0); 4088#L892-1 assume !(1 == ~E_M~0); 4089#L897-1 assume !(1 == ~E_1~0); 3779#L902-1 assume !(1 == ~E_2~0); 3780#L907-1 assume !(1 == ~E_3~0); 4049#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4041#L917-1 assume !(1 == ~E_5~0); 4042#L922-1 assume !(1 == ~E_6~0); 4194#L927-1 assume !(1 == ~E_7~0); 4030#L932-1 assume { :end_inline_reset_delta_events } true; 3430#L1178-2 [2023-11-19 07:54:33,898 INFO L750 eck$LassoCheckResult]: Loop: 3430#L1178-2 assume !false; 4017#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4018#L744-1 assume !false; 3891#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3892#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3465#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3674#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3776#L641 assume !(0 != eval_~tmp~0#1); 4090#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3899#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3900#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3847#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3848#L774-3 assume !(0 == ~T2_E~0); 3586#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3406#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3407#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3397#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3398#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3447#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3701#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3443#L814-3 assume !(0 == ~E_2~0); 3444#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4109#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4104#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3760#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3761#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4071#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4152#L376-27 assume 1 == ~m_pc~0; 4045#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3994#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3995#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4066#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4196#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4217#L395-27 assume 1 == ~t1_pc~0; 4213#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3762#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3763#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3959#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3854#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3855#L414-27 assume 1 == ~t2_pc~0; 4180#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4040#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4039#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3915#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3455#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3456#L433-27 assume !(1 == ~t3_pc~0); 3558#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 3861#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3862#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3632#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3633#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4208#L452-27 assume 1 == ~t4_pc~0; 4209#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4009#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3825#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3826#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4177#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3448#L471-27 assume 1 == ~t5_pc~0; 3449#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3773#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4130#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4063#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3990#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3923#L490-27 assume 1 == ~t6_pc~0; 3822#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3643#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3644#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4047#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 4048#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3415#L509-27 assume 1 == ~t7_pc~0; 3416#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3824#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3705#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3706#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3943#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3955#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3956#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3986#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4207#L867-3 assume !(1 == ~T3_E~0); 3863#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3864#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3950#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3980#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3603#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3604#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4127#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3777#L907-3 assume !(1 == ~E_3~0); 3778#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3903#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3868#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3656#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3657#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3507#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3404#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3714#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 3715#L1197 assume !(0 == start_simulation_~tmp~3#1); 3836#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3566#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3530#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3423#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 3424#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4124#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3917#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 3429#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 3430#L1178-2 [2023-11-19 07:54:33,899 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:33,900 INFO L85 PathProgramCache]: Analyzing trace with hash 33886909, now seen corresponding path program 1 times [2023-11-19 07:54:33,900 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:33,900 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1540676880] [2023-11-19 07:54:33,901 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:33,901 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:33,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:34,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:34,030 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:34,030 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1540676880] [2023-11-19 07:54:34,031 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1540676880] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:34,031 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:34,031 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:34,031 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [742922536] [2023-11-19 07:54:34,032 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:34,032 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:54:34,033 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:34,033 INFO L85 PathProgramCache]: Analyzing trace with hash -268845801, now seen corresponding path program 1 times [2023-11-19 07:54:34,033 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:34,033 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [910396611] [2023-11-19 07:54:34,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:34,034 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:34,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:34,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:34,125 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:34,125 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [910396611] [2023-11-19 07:54:34,125 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [910396611] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:34,125 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:34,126 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:34,126 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1928679578] [2023-11-19 07:54:34,126 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:34,127 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:54:34,127 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:54:34,127 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:54:34,128 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:54:34,128 INFO L87 Difference]: Start difference. First operand 838 states and 1247 transitions. cyclomatic complexity: 410 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:34,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:54:34,159 INFO L93 Difference]: Finished difference Result 838 states and 1246 transitions. [2023-11-19 07:54:34,159 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 838 states and 1246 transitions. [2023-11-19 07:54:34,169 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2023-11-19 07:54:34,178 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 838 states to 838 states and 1246 transitions. [2023-11-19 07:54:34,179 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 838 [2023-11-19 07:54:34,180 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 838 [2023-11-19 07:54:34,180 INFO L73 IsDeterministic]: Start isDeterministic. Operand 838 states and 1246 transitions. [2023-11-19 07:54:34,182 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:54:34,182 INFO L218 hiAutomatonCegarLoop]: Abstraction has 838 states and 1246 transitions. [2023-11-19 07:54:34,185 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 838 states and 1246 transitions. [2023-11-19 07:54:34,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 838 to 838. [2023-11-19 07:54:34,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 838 states, 838 states have (on average 1.4868735083532219) internal successors, (1246), 837 states have internal predecessors, (1246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:34,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 838 states to 838 states and 1246 transitions. [2023-11-19 07:54:34,211 INFO L240 hiAutomatonCegarLoop]: Abstraction has 838 states and 1246 transitions. [2023-11-19 07:54:34,211 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:54:34,213 INFO L428 stractBuchiCegarLoop]: Abstraction has 838 states and 1246 transitions. [2023-11-19 07:54:34,213 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-19 07:54:34,213 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 838 states and 1246 transitions. [2023-11-19 07:54:34,221 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2023-11-19 07:54:34,222 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:54:34,222 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:54:34,225 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:34,225 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:34,226 INFO L748 eck$LassoCheckResult]: Stem: 5290#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 5291#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5847#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5848#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5827#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 5828#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5535#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5359#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5360#L551-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5341#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5342#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5826#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5651#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5652#L769 assume !(0 == ~M_E~0); 5671#L769-2 assume !(0 == ~T1_E~0); 5672#L774-1 assume !(0 == ~T2_E~0); 5699#L779-1 assume !(0 == ~T3_E~0); 5816#L784-1 assume !(0 == ~T4_E~0); 5649#L789-1 assume !(0 == ~T5_E~0); 5650#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5755#L799-1 assume !(0 == ~T7_E~0); 5654#L804-1 assume !(0 == ~E_M~0); 5655#L809-1 assume !(0 == ~E_1~0); 5694#L814-1 assume !(0 == ~E_2~0); 5078#L819-1 assume !(0 == ~E_3~0); 5079#L824-1 assume !(0 == ~E_4~0); 5432#L829-1 assume !(0 == ~E_5~0); 5875#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 5215#L839-1 assume !(0 == ~E_7~0); 5216#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5607#L376 assume !(1 == ~m_pc~0); 5596#L376-2 is_master_triggered_~__retres1~0#1 := 0; 5595#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5801#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5156#L955 assume !(0 != activate_threads_~tmp~1#1); 5157#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5528#L395 assume 1 == ~t1_pc~0; 5192#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5193#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5108#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5109#L963 assume !(0 != activate_threads_~tmp___0~0#1); 5611#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5612#L414 assume !(1 == ~t2_pc~0); 5218#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5219#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5438#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5439#L971 assume !(0 != activate_threads_~tmp___1~0#1); 5831#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5532#L433 assume 1 == ~t3_pc~0; 5474#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5330#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5076#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5077#L979 assume !(0 != activate_threads_~tmp___2~0#1); 5181#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5182#L452 assume !(1 == ~t4_pc~0); 5337#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5338#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5175#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5176#L987 assume !(0 != activate_threads_~tmp___3~0#1); 5370#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5371#L471 assume 1 == ~t5_pc~0; 5742#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5352#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5353#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5804#L995 assume !(0 != activate_threads_~tmp___4~0#1); 5866#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5867#L490 assume 1 == ~t6_pc~0; 5852#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5610#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5425#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5426#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 5542#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5510#L509 assume !(1 == ~t7_pc~0); 5511#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5312#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5313#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5377#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5378#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5837#L857 assume !(1 == ~M_E~0); 5163#L857-2 assume !(1 == ~T1_E~0); 5164#L862-1 assume !(1 == ~T2_E~0); 5442#L867-1 assume !(1 == ~T3_E~0); 5447#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5533#L877-1 assume !(1 == ~T5_E~0); 5718#L882-1 assume !(1 == ~T6_E~0); 5851#L887-1 assume !(1 == ~T7_E~0); 5771#L892-1 assume !(1 == ~E_M~0); 5772#L897-1 assume !(1 == ~E_1~0); 5462#L902-1 assume !(1 == ~E_2~0); 5463#L907-1 assume !(1 == ~E_3~0); 5732#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5724#L917-1 assume !(1 == ~E_5~0); 5725#L922-1 assume !(1 == ~E_6~0); 5877#L927-1 assume !(1 == ~E_7~0); 5713#L932-1 assume { :end_inline_reset_delta_events } true; 5113#L1178-2 [2023-11-19 07:54:34,226 INFO L750 eck$LassoCheckResult]: Loop: 5113#L1178-2 assume !false; 5700#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5701#L744-1 assume !false; 5574#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5575#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5148#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5357#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5459#L641 assume !(0 != eval_~tmp~0#1); 5773#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5582#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5583#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5530#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5531#L774-3 assume !(0 == ~T2_E~0); 5269#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5089#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5090#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5080#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5081#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5130#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5384#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5126#L814-3 assume !(0 == ~E_2~0); 5127#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5792#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5787#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5443#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5444#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5754#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5835#L376-27 assume 1 == ~m_pc~0; 5728#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5677#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5678#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5749#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5879#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5900#L395-27 assume 1 == ~t1_pc~0; 5896#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5445#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5446#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5642#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5537#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5538#L414-27 assume 1 == ~t2_pc~0; 5863#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5723#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5722#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5598#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5138#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5139#L433-27 assume !(1 == ~t3_pc~0); 5241#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 5544#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5545#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5315#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5316#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5891#L452-27 assume 1 == ~t4_pc~0; 5892#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5692#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5508#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5509#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5860#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5131#L471-27 assume 1 == ~t5_pc~0; 5132#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5456#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5813#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5746#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5673#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5606#L490-27 assume 1 == ~t6_pc~0; 5505#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5326#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5327#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5730#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 5731#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5098#L509-27 assume 1 == ~t7_pc~0; 5099#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5507#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5388#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5389#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5626#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5638#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5639#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5669#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5890#L867-3 assume !(1 == ~T3_E~0); 5546#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5547#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5633#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5663#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5286#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5287#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5810#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5460#L907-3 assume !(1 == ~E_3~0); 5461#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5586#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5551#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5339#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5340#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5190#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5087#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5397#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 5398#L1197 assume !(0 == start_simulation_~tmp~3#1); 5519#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5249#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5213#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5106#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 5107#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5807#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5600#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 5112#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 5113#L1178-2 [2023-11-19 07:54:34,227 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:34,227 INFO L85 PathProgramCache]: Analyzing trace with hash 1028580607, now seen corresponding path program 1 times [2023-11-19 07:54:34,227 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:34,228 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [188648005] [2023-11-19 07:54:34,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:34,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:34,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:34,284 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:34,284 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:34,285 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [188648005] [2023-11-19 07:54:34,285 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [188648005] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:34,285 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:34,285 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:34,286 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1938524815] [2023-11-19 07:54:34,286 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:34,286 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:54:34,287 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:34,287 INFO L85 PathProgramCache]: Analyzing trace with hash -268845801, now seen corresponding path program 2 times [2023-11-19 07:54:34,287 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:34,287 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [655571128] [2023-11-19 07:54:34,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:34,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:34,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:34,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:34,386 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:34,386 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [655571128] [2023-11-19 07:54:34,386 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [655571128] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:34,387 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:34,387 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:34,387 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1299408685] [2023-11-19 07:54:34,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:34,388 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:54:34,388 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:54:34,389 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:54:34,389 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:54:34,389 INFO L87 Difference]: Start difference. First operand 838 states and 1246 transitions. cyclomatic complexity: 409 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:34,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:54:34,419 INFO L93 Difference]: Finished difference Result 838 states and 1245 transitions. [2023-11-19 07:54:34,419 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 838 states and 1245 transitions. [2023-11-19 07:54:34,428 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2023-11-19 07:54:34,437 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 838 states to 838 states and 1245 transitions. [2023-11-19 07:54:34,437 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 838 [2023-11-19 07:54:34,438 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 838 [2023-11-19 07:54:34,438 INFO L73 IsDeterministic]: Start isDeterministic. Operand 838 states and 1245 transitions. [2023-11-19 07:54:34,440 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:54:34,440 INFO L218 hiAutomatonCegarLoop]: Abstraction has 838 states and 1245 transitions. [2023-11-19 07:54:34,442 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 838 states and 1245 transitions. [2023-11-19 07:54:34,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 838 to 838. [2023-11-19 07:54:34,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 838 states, 838 states have (on average 1.4856801909307875) internal successors, (1245), 837 states have internal predecessors, (1245), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:34,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 838 states to 838 states and 1245 transitions. [2023-11-19 07:54:34,503 INFO L240 hiAutomatonCegarLoop]: Abstraction has 838 states and 1245 transitions. [2023-11-19 07:54:34,503 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:54:34,506 INFO L428 stractBuchiCegarLoop]: Abstraction has 838 states and 1245 transitions. [2023-11-19 07:54:34,511 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-19 07:54:34,511 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 838 states and 1245 transitions. [2023-11-19 07:54:34,517 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2023-11-19 07:54:34,518 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:54:34,518 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:54:34,520 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:34,520 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:34,521 INFO L748 eck$LassoCheckResult]: Stem: 6975#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 6976#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 7530#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7531#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7510#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 7511#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7218#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7042#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7043#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7024#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7025#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7509#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7334#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7335#L769 assume !(0 == ~M_E~0); 7354#L769-2 assume !(0 == ~T1_E~0); 7355#L774-1 assume !(0 == ~T2_E~0); 7382#L779-1 assume !(0 == ~T3_E~0); 7499#L784-1 assume !(0 == ~T4_E~0); 7332#L789-1 assume !(0 == ~T5_E~0); 7333#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7438#L799-1 assume !(0 == ~T7_E~0); 7337#L804-1 assume !(0 == ~E_M~0); 7338#L809-1 assume !(0 == ~E_1~0); 7377#L814-1 assume !(0 == ~E_2~0); 6763#L819-1 assume !(0 == ~E_3~0); 6764#L824-1 assume !(0 == ~E_4~0); 7115#L829-1 assume !(0 == ~E_5~0); 7558#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 6898#L839-1 assume !(0 == ~E_7~0); 6899#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7290#L376 assume !(1 == ~m_pc~0); 7283#L376-2 is_master_triggered_~__retres1~0#1 := 0; 7282#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7484#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6841#L955 assume !(0 != activate_threads_~tmp~1#1); 6842#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7211#L395 assume 1 == ~t1_pc~0; 6875#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6876#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6791#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6792#L963 assume !(0 != activate_threads_~tmp___0~0#1); 7295#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7296#L414 assume !(1 == ~t2_pc~0); 6901#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6902#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7121#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7122#L971 assume !(0 != activate_threads_~tmp___1~0#1); 7514#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7215#L433 assume 1 == ~t3_pc~0; 7157#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7015#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6759#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6760#L979 assume !(0 != activate_threads_~tmp___2~0#1); 6864#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6865#L452 assume !(1 == ~t4_pc~0); 7020#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7021#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6858#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6859#L987 assume !(0 != activate_threads_~tmp___3~0#1); 7053#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7054#L471 assume 1 == ~t5_pc~0; 7425#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7035#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7036#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7487#L995 assume !(0 != activate_threads_~tmp___4~0#1); 7549#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7550#L490 assume 1 == ~t6_pc~0; 7536#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7293#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7108#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7109#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 7227#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7193#L509 assume !(1 == ~t7_pc~0); 7194#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 7000#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7001#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7060#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7061#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7520#L857 assume !(1 == ~M_E~0); 6846#L857-2 assume !(1 == ~T1_E~0); 6847#L862-1 assume !(1 == ~T2_E~0); 7125#L867-1 assume !(1 == ~T3_E~0); 7130#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7216#L877-1 assume !(1 == ~T5_E~0); 7401#L882-1 assume !(1 == ~T6_E~0); 7534#L887-1 assume !(1 == ~T7_E~0); 7454#L892-1 assume !(1 == ~E_M~0); 7455#L897-1 assume !(1 == ~E_1~0); 7147#L902-1 assume !(1 == ~E_2~0); 7148#L907-1 assume !(1 == ~E_3~0); 7417#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7407#L917-1 assume !(1 == ~E_5~0); 7408#L922-1 assume !(1 == ~E_6~0); 7560#L927-1 assume !(1 == ~E_7~0); 7396#L932-1 assume { :end_inline_reset_delta_events } true; 6796#L1178-2 [2023-11-19 07:54:34,521 INFO L750 eck$LassoCheckResult]: Loop: 6796#L1178-2 assume !false; 7383#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7384#L744-1 assume !false; 7257#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 7258#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6831#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7040#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7144#L641 assume !(0 != eval_~tmp~0#1); 7456#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7265#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7266#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7213#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7214#L774-3 assume !(0 == ~T2_E~0); 6954#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6772#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6773#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6765#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6766#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6813#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7068#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6809#L814-3 assume !(0 == ~E_2~0); 6810#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7475#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7470#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7126#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7127#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7437#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7518#L376-27 assume 1 == ~m_pc~0; 7411#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7360#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7361#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7432#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7562#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7583#L395-27 assume !(1 == ~t1_pc~0); 7233#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 7128#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7129#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7325#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7220#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7221#L414-27 assume 1 == ~t2_pc~0; 7546#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7406#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7405#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7278#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6821#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6822#L433-27 assume !(1 == ~t3_pc~0); 6924#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 7225#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7226#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6996#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6997#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7574#L452-27 assume 1 == ~t4_pc~0; 7575#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7375#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7191#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7192#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7543#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6814#L471-27 assume !(1 == ~t5_pc~0); 6816#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 7136#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7496#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7429#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7356#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7289#L490-27 assume 1 == ~t6_pc~0; 7188#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7009#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7010#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7413#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 7414#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6781#L509-27 assume 1 == ~t7_pc~0; 6782#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7190#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7071#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7072#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7309#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7321#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7322#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7352#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7573#L867-3 assume !(1 == ~T3_E~0); 7229#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7230#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7316#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7346#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6967#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6968#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7493#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7142#L907-3 assume !(1 == ~E_3~0); 7143#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7269#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7234#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7022#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7023#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6873#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6770#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7080#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 7081#L1197 assume !(0 == start_simulation_~tmp~3#1); 7201#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6932#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6896#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6789#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 6790#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7490#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7280#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 6795#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 6796#L1178-2 [2023-11-19 07:54:34,525 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:34,525 INFO L85 PathProgramCache]: Analyzing trace with hash 1614856829, now seen corresponding path program 1 times [2023-11-19 07:54:34,526 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:34,526 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [466945544] [2023-11-19 07:54:34,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:34,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:34,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:34,585 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:34,586 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:34,586 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [466945544] [2023-11-19 07:54:34,586 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [466945544] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:34,586 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:34,587 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:34,587 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [836832042] [2023-11-19 07:54:34,587 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:34,587 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:54:34,588 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:34,588 INFO L85 PathProgramCache]: Analyzing trace with hash 177358105, now seen corresponding path program 1 times [2023-11-19 07:54:34,588 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:34,589 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1557161463] [2023-11-19 07:54:34,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:34,589 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:34,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:34,680 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:34,680 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:34,681 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1557161463] [2023-11-19 07:54:34,681 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1557161463] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:34,681 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:34,681 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:34,681 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1891197964] [2023-11-19 07:54:34,681 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:34,682 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:54:34,682 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:54:34,682 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:54:34,683 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:54:34,683 INFO L87 Difference]: Start difference. First operand 838 states and 1245 transitions. cyclomatic complexity: 408 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:34,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:54:34,713 INFO L93 Difference]: Finished difference Result 838 states and 1244 transitions. [2023-11-19 07:54:34,713 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 838 states and 1244 transitions. [2023-11-19 07:54:34,723 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2023-11-19 07:54:34,730 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 838 states to 838 states and 1244 transitions. [2023-11-19 07:54:34,731 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 838 [2023-11-19 07:54:34,732 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 838 [2023-11-19 07:54:34,732 INFO L73 IsDeterministic]: Start isDeterministic. Operand 838 states and 1244 transitions. [2023-11-19 07:54:34,733 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:54:34,734 INFO L218 hiAutomatonCegarLoop]: Abstraction has 838 states and 1244 transitions. [2023-11-19 07:54:34,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 838 states and 1244 transitions. [2023-11-19 07:54:34,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 838 to 838. [2023-11-19 07:54:34,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 838 states, 838 states have (on average 1.4844868735083532) internal successors, (1244), 837 states have internal predecessors, (1244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:34,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 838 states to 838 states and 1244 transitions. [2023-11-19 07:54:34,756 INFO L240 hiAutomatonCegarLoop]: Abstraction has 838 states and 1244 transitions. [2023-11-19 07:54:34,756 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:54:34,759 INFO L428 stractBuchiCegarLoop]: Abstraction has 838 states and 1244 transitions. [2023-11-19 07:54:34,759 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-19 07:54:34,759 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 838 states and 1244 transitions. [2023-11-19 07:54:34,765 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2023-11-19 07:54:34,766 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:54:34,766 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:54:34,767 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:34,768 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:34,768 INFO L748 eck$LassoCheckResult]: Stem: 8656#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 8657#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 9213#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9214#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9193#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 9194#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8901#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8725#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8726#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8707#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8708#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9192#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9017#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9018#L769 assume !(0 == ~M_E~0); 9037#L769-2 assume !(0 == ~T1_E~0); 9038#L774-1 assume !(0 == ~T2_E~0); 9065#L779-1 assume !(0 == ~T3_E~0); 9182#L784-1 assume !(0 == ~T4_E~0); 9015#L789-1 assume !(0 == ~T5_E~0); 9016#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9121#L799-1 assume !(0 == ~T7_E~0); 9020#L804-1 assume !(0 == ~E_M~0); 9021#L809-1 assume !(0 == ~E_1~0); 9060#L814-1 assume !(0 == ~E_2~0); 8446#L819-1 assume !(0 == ~E_3~0); 8447#L824-1 assume !(0 == ~E_4~0); 8798#L829-1 assume !(0 == ~E_5~0); 9241#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 8581#L839-1 assume !(0 == ~E_7~0); 8582#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8973#L376 assume !(1 == ~m_pc~0); 8963#L376-2 is_master_triggered_~__retres1~0#1 := 0; 8962#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9167#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8524#L955 assume !(0 != activate_threads_~tmp~1#1); 8525#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8894#L395 assume 1 == ~t1_pc~0; 8558#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8559#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8474#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8475#L963 assume !(0 != activate_threads_~tmp___0~0#1); 8978#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8979#L414 assume !(1 == ~t2_pc~0); 8584#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8585#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8804#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8805#L971 assume !(0 != activate_threads_~tmp___1~0#1); 9197#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8898#L433 assume 1 == ~t3_pc~0; 8840#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8698#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8442#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8443#L979 assume !(0 != activate_threads_~tmp___2~0#1); 8547#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8548#L452 assume !(1 == ~t4_pc~0); 8703#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8704#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8541#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8542#L987 assume !(0 != activate_threads_~tmp___3~0#1); 8736#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8737#L471 assume 1 == ~t5_pc~0; 9108#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8718#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8719#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9170#L995 assume !(0 != activate_threads_~tmp___4~0#1); 9232#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9233#L490 assume 1 == ~t6_pc~0; 9219#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8976#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8791#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8792#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 8908#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8876#L509 assume !(1 == ~t7_pc~0); 8877#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8680#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8681#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8743#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8744#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9203#L857 assume !(1 == ~M_E~0); 8529#L857-2 assume !(1 == ~T1_E~0); 8530#L862-1 assume !(1 == ~T2_E~0); 8808#L867-1 assume !(1 == ~T3_E~0); 8813#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8899#L877-1 assume !(1 == ~T5_E~0); 9084#L882-1 assume !(1 == ~T6_E~0); 9217#L887-1 assume !(1 == ~T7_E~0); 9137#L892-1 assume !(1 == ~E_M~0); 9138#L897-1 assume !(1 == ~E_1~0); 8830#L902-1 assume !(1 == ~E_2~0); 8831#L907-1 assume !(1 == ~E_3~0); 9100#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 9090#L917-1 assume !(1 == ~E_5~0); 9091#L922-1 assume !(1 == ~E_6~0); 9243#L927-1 assume !(1 == ~E_7~0); 9079#L932-1 assume { :end_inline_reset_delta_events } true; 8479#L1178-2 [2023-11-19 07:54:34,769 INFO L750 eck$LassoCheckResult]: Loop: 8479#L1178-2 assume !false; 9066#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9067#L744-1 assume !false; 8940#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8941#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8514#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8723#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8827#L641 assume !(0 != eval_~tmp~0#1); 9139#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8948#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8949#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8896#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8897#L774-3 assume !(0 == ~T2_E~0); 8635#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8455#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8456#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8448#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8449#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8496#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8751#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8494#L814-3 assume !(0 == ~E_2~0); 8495#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9158#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9153#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8809#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8810#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9120#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9201#L376-27 assume 1 == ~m_pc~0; 9094#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9043#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9044#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9115#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9245#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9266#L395-27 assume !(1 == ~t1_pc~0); 8917#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 8811#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8812#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9008#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8903#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8904#L414-27 assume 1 == ~t2_pc~0; 9229#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9089#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9088#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8965#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8504#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8505#L433-27 assume 1 == ~t3_pc~0; 8608#L434-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8910#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8911#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8683#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8684#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9257#L452-27 assume !(1 == ~t4_pc~0); 9057#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 9058#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8874#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8875#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9226#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8497#L471-27 assume 1 == ~t5_pc~0; 8498#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8817#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9179#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9112#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9039#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8972#L490-27 assume 1 == ~t6_pc~0; 8871#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8692#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8693#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9096#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 9097#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8464#L509-27 assume 1 == ~t7_pc~0; 8465#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8873#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8754#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8755#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8991#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9004#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9005#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9033#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9256#L867-3 assume !(1 == ~T3_E~0); 8912#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8913#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8999#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9029#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8650#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8651#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9176#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8825#L907-3 assume !(1 == ~E_3~0); 8826#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8952#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8916#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8705#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8706#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8556#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8451#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8763#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 8764#L1197 assume !(0 == start_simulation_~tmp~3#1); 8883#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8612#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8579#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8472#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 8473#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9173#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8960#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 8478#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 8479#L1178-2 [2023-11-19 07:54:34,770 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:34,770 INFO L85 PathProgramCache]: Analyzing trace with hash -721535681, now seen corresponding path program 1 times [2023-11-19 07:54:34,771 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:34,771 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1863730992] [2023-11-19 07:54:34,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:34,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:34,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:34,826 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:34,826 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:34,826 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1863730992] [2023-11-19 07:54:34,827 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1863730992] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:34,827 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:34,827 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:34,827 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [28591142] [2023-11-19 07:54:34,827 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:34,828 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:54:34,828 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:34,828 INFO L85 PathProgramCache]: Analyzing trace with hash -1466614696, now seen corresponding path program 1 times [2023-11-19 07:54:34,829 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:34,834 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [536976701] [2023-11-19 07:54:34,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:34,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:34,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:34,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:34,897 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:34,898 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [536976701] [2023-11-19 07:54:34,899 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [536976701] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:34,899 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:34,899 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:34,899 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2059816546] [2023-11-19 07:54:34,900 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:34,900 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:54:34,901 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:54:34,901 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:54:34,901 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:54:34,901 INFO L87 Difference]: Start difference. First operand 838 states and 1244 transitions. cyclomatic complexity: 407 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:34,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:54:34,927 INFO L93 Difference]: Finished difference Result 838 states and 1243 transitions. [2023-11-19 07:54:34,927 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 838 states and 1243 transitions. [2023-11-19 07:54:34,936 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2023-11-19 07:54:34,945 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 838 states to 838 states and 1243 transitions. [2023-11-19 07:54:34,945 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 838 [2023-11-19 07:54:34,946 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 838 [2023-11-19 07:54:34,946 INFO L73 IsDeterministic]: Start isDeterministic. Operand 838 states and 1243 transitions. [2023-11-19 07:54:34,948 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:54:34,948 INFO L218 hiAutomatonCegarLoop]: Abstraction has 838 states and 1243 transitions. [2023-11-19 07:54:34,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 838 states and 1243 transitions. [2023-11-19 07:54:34,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 838 to 838. [2023-11-19 07:54:34,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 838 states, 838 states have (on average 1.4832935560859188) internal successors, (1243), 837 states have internal predecessors, (1243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:34,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 838 states to 838 states and 1243 transitions. [2023-11-19 07:54:34,970 INFO L240 hiAutomatonCegarLoop]: Abstraction has 838 states and 1243 transitions. [2023-11-19 07:54:34,970 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:54:34,972 INFO L428 stractBuchiCegarLoop]: Abstraction has 838 states and 1243 transitions. [2023-11-19 07:54:34,973 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-19 07:54:34,973 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 838 states and 1243 transitions. [2023-11-19 07:54:34,985 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2023-11-19 07:54:34,985 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:54:34,985 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:54:34,987 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:34,987 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:34,987 INFO L748 eck$LassoCheckResult]: Stem: 10339#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 10340#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10896#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10897#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10876#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 10877#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10584#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10408#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10409#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10390#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10391#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10875#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10700#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10701#L769 assume !(0 == ~M_E~0); 10720#L769-2 assume !(0 == ~T1_E~0); 10721#L774-1 assume !(0 == ~T2_E~0); 10748#L779-1 assume !(0 == ~T3_E~0); 10865#L784-1 assume !(0 == ~T4_E~0); 10698#L789-1 assume !(0 == ~T5_E~0); 10699#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10804#L799-1 assume !(0 == ~T7_E~0); 10703#L804-1 assume !(0 == ~E_M~0); 10704#L809-1 assume !(0 == ~E_1~0); 10743#L814-1 assume !(0 == ~E_2~0); 10127#L819-1 assume !(0 == ~E_3~0); 10128#L824-1 assume !(0 == ~E_4~0); 10481#L829-1 assume !(0 == ~E_5~0); 10924#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 10264#L839-1 assume !(0 == ~E_7~0); 10265#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10656#L376 assume !(1 == ~m_pc~0); 10645#L376-2 is_master_triggered_~__retres1~0#1 := 0; 10644#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10850#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10205#L955 assume !(0 != activate_threads_~tmp~1#1); 10206#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10577#L395 assume 1 == ~t1_pc~0; 10241#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10242#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10157#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10158#L963 assume !(0 != activate_threads_~tmp___0~0#1); 10660#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10661#L414 assume !(1 == ~t2_pc~0); 10267#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10268#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10487#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10488#L971 assume !(0 != activate_threads_~tmp___1~0#1); 10880#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10581#L433 assume 1 == ~t3_pc~0; 10523#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10379#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10125#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10126#L979 assume !(0 != activate_threads_~tmp___2~0#1); 10230#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10231#L452 assume !(1 == ~t4_pc~0); 10386#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10387#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10224#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10225#L987 assume !(0 != activate_threads_~tmp___3~0#1); 10419#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10420#L471 assume 1 == ~t5_pc~0; 10791#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10401#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10402#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10853#L995 assume !(0 != activate_threads_~tmp___4~0#1); 10915#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10916#L490 assume 1 == ~t6_pc~0; 10901#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10659#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10474#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10475#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 10591#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10559#L509 assume !(1 == ~t7_pc~0); 10560#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10361#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10362#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10426#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10427#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10886#L857 assume !(1 == ~M_E~0); 10212#L857-2 assume !(1 == ~T1_E~0); 10213#L862-1 assume !(1 == ~T2_E~0); 10491#L867-1 assume !(1 == ~T3_E~0); 10496#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10582#L877-1 assume !(1 == ~T5_E~0); 10767#L882-1 assume !(1 == ~T6_E~0); 10900#L887-1 assume !(1 == ~T7_E~0); 10820#L892-1 assume !(1 == ~E_M~0); 10821#L897-1 assume !(1 == ~E_1~0); 10511#L902-1 assume !(1 == ~E_2~0); 10512#L907-1 assume !(1 == ~E_3~0); 10781#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10773#L917-1 assume !(1 == ~E_5~0); 10774#L922-1 assume !(1 == ~E_6~0); 10926#L927-1 assume !(1 == ~E_7~0); 10762#L932-1 assume { :end_inline_reset_delta_events } true; 10162#L1178-2 [2023-11-19 07:54:34,988 INFO L750 eck$LassoCheckResult]: Loop: 10162#L1178-2 assume !false; 10749#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10750#L744-1 assume !false; 10623#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10624#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10197#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10406#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10508#L641 assume !(0 != eval_~tmp~0#1); 10822#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10631#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10632#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10579#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10580#L774-3 assume !(0 == ~T2_E~0); 10318#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10138#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10139#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10129#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10130#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10179#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10433#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10175#L814-3 assume !(0 == ~E_2~0); 10176#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10841#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10836#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10492#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10493#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10803#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10884#L376-27 assume 1 == ~m_pc~0; 10777#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10726#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10727#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10798#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10928#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10949#L395-27 assume 1 == ~t1_pc~0; 10945#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10494#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10495#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10691#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10586#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10587#L414-27 assume 1 == ~t2_pc~0; 10912#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10772#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10771#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10647#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10187#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10188#L433-27 assume !(1 == ~t3_pc~0); 10290#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 10593#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10594#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10364#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10365#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10940#L452-27 assume !(1 == ~t4_pc~0); 10740#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 10741#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10557#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10558#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10909#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10180#L471-27 assume 1 == ~t5_pc~0; 10181#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10505#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10862#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10795#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10722#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10655#L490-27 assume 1 == ~t6_pc~0; 10554#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10375#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10376#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10779#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 10780#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10147#L509-27 assume 1 == ~t7_pc~0; 10148#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10556#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10437#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10438#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10675#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10687#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10688#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10718#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10939#L867-3 assume !(1 == ~T3_E~0); 10595#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10596#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10682#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10712#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10335#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10336#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10859#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10509#L907-3 assume !(1 == ~E_3~0); 10510#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10635#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10600#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10388#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10389#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10239#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10136#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10446#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 10447#L1197 assume !(0 == start_simulation_~tmp~3#1); 10568#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10298#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10262#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10155#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 10156#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10856#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10649#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 10161#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 10162#L1178-2 [2023-11-19 07:54:34,989 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:34,989 INFO L85 PathProgramCache]: Analyzing trace with hash 1696948797, now seen corresponding path program 1 times [2023-11-19 07:54:34,989 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:34,989 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [194024700] [2023-11-19 07:54:34,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:34,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:35,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:35,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:35,037 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:35,037 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [194024700] [2023-11-19 07:54:35,037 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [194024700] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:35,037 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:35,037 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:35,038 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [220348643] [2023-11-19 07:54:35,038 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:35,038 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:54:35,039 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:35,039 INFO L85 PathProgramCache]: Analyzing trace with hash -542624296, now seen corresponding path program 2 times [2023-11-19 07:54:35,039 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:35,039 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [520296884] [2023-11-19 07:54:35,039 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:35,039 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:35,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:35,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:35,100 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:35,100 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [520296884] [2023-11-19 07:54:35,101 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [520296884] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:35,101 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:35,101 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:35,101 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [819015886] [2023-11-19 07:54:35,101 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:35,102 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:54:35,102 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:54:35,102 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:54:35,102 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:54:35,102 INFO L87 Difference]: Start difference. First operand 838 states and 1243 transitions. cyclomatic complexity: 406 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:35,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:54:35,133 INFO L93 Difference]: Finished difference Result 838 states and 1242 transitions. [2023-11-19 07:54:35,133 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 838 states and 1242 transitions. [2023-11-19 07:54:35,176 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2023-11-19 07:54:35,183 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 838 states to 838 states and 1242 transitions. [2023-11-19 07:54:35,183 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 838 [2023-11-19 07:54:35,184 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 838 [2023-11-19 07:54:35,184 INFO L73 IsDeterministic]: Start isDeterministic. Operand 838 states and 1242 transitions. [2023-11-19 07:54:35,189 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:54:35,189 INFO L218 hiAutomatonCegarLoop]: Abstraction has 838 states and 1242 transitions. [2023-11-19 07:54:35,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 838 states and 1242 transitions. [2023-11-19 07:54:35,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 838 to 838. [2023-11-19 07:54:35,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 838 states, 838 states have (on average 1.4821002386634845) internal successors, (1242), 837 states have internal predecessors, (1242), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:35,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 838 states to 838 states and 1242 transitions. [2023-11-19 07:54:35,209 INFO L240 hiAutomatonCegarLoop]: Abstraction has 838 states and 1242 transitions. [2023-11-19 07:54:35,210 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:54:35,211 INFO L428 stractBuchiCegarLoop]: Abstraction has 838 states and 1242 transitions. [2023-11-19 07:54:35,211 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-19 07:54:35,211 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 838 states and 1242 transitions. [2023-11-19 07:54:35,218 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2023-11-19 07:54:35,218 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:54:35,218 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:54:35,220 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:35,220 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:35,220 INFO L748 eck$LassoCheckResult]: Stem: 12022#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 12023#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 12579#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12580#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12559#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 12560#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12267#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12091#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12092#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12073#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12074#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12558#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 12383#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12384#L769 assume !(0 == ~M_E~0); 12403#L769-2 assume !(0 == ~T1_E~0); 12404#L774-1 assume !(0 == ~T2_E~0); 12431#L779-1 assume !(0 == ~T3_E~0); 12548#L784-1 assume !(0 == ~T4_E~0); 12381#L789-1 assume !(0 == ~T5_E~0); 12382#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12487#L799-1 assume !(0 == ~T7_E~0); 12386#L804-1 assume !(0 == ~E_M~0); 12387#L809-1 assume !(0 == ~E_1~0); 12426#L814-1 assume !(0 == ~E_2~0); 11810#L819-1 assume !(0 == ~E_3~0); 11811#L824-1 assume !(0 == ~E_4~0); 12164#L829-1 assume !(0 == ~E_5~0); 12607#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 11947#L839-1 assume !(0 == ~E_7~0); 11948#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12339#L376 assume !(1 == ~m_pc~0); 12328#L376-2 is_master_triggered_~__retres1~0#1 := 0; 12327#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12533#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11888#L955 assume !(0 != activate_threads_~tmp~1#1); 11889#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12260#L395 assume 1 == ~t1_pc~0; 11924#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11925#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11840#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11841#L963 assume !(0 != activate_threads_~tmp___0~0#1); 12343#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12344#L414 assume !(1 == ~t2_pc~0); 11950#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11951#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12170#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12171#L971 assume !(0 != activate_threads_~tmp___1~0#1); 12563#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12264#L433 assume 1 == ~t3_pc~0; 12206#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12062#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11808#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11809#L979 assume !(0 != activate_threads_~tmp___2~0#1); 11913#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11914#L452 assume !(1 == ~t4_pc~0); 12069#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12070#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11907#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11908#L987 assume !(0 != activate_threads_~tmp___3~0#1); 12102#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12103#L471 assume 1 == ~t5_pc~0; 12474#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12084#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12085#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12536#L995 assume !(0 != activate_threads_~tmp___4~0#1); 12598#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12599#L490 assume 1 == ~t6_pc~0; 12584#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12342#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12157#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12158#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 12274#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12242#L509 assume !(1 == ~t7_pc~0); 12243#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 12044#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12045#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12109#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12110#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12569#L857 assume !(1 == ~M_E~0); 11895#L857-2 assume !(1 == ~T1_E~0); 11896#L862-1 assume !(1 == ~T2_E~0); 12174#L867-1 assume !(1 == ~T3_E~0); 12179#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12265#L877-1 assume !(1 == ~T5_E~0); 12450#L882-1 assume !(1 == ~T6_E~0); 12583#L887-1 assume !(1 == ~T7_E~0); 12503#L892-1 assume !(1 == ~E_M~0); 12504#L897-1 assume !(1 == ~E_1~0); 12194#L902-1 assume !(1 == ~E_2~0); 12195#L907-1 assume !(1 == ~E_3~0); 12464#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 12456#L917-1 assume !(1 == ~E_5~0); 12457#L922-1 assume !(1 == ~E_6~0); 12609#L927-1 assume !(1 == ~E_7~0); 12445#L932-1 assume { :end_inline_reset_delta_events } true; 11845#L1178-2 [2023-11-19 07:54:35,221 INFO L750 eck$LassoCheckResult]: Loop: 11845#L1178-2 assume !false; 12432#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12433#L744-1 assume !false; 12306#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12307#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11880#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12089#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12191#L641 assume !(0 != eval_~tmp~0#1); 12505#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12314#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12315#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12262#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12263#L774-3 assume !(0 == ~T2_E~0); 12001#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11821#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11822#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11812#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11813#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11862#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12116#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11858#L814-3 assume !(0 == ~E_2~0); 11859#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12524#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12519#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12175#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12176#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12486#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12567#L376-27 assume 1 == ~m_pc~0; 12460#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12409#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12410#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12481#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12611#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12632#L395-27 assume 1 == ~t1_pc~0; 12628#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12177#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12178#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12374#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12269#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12270#L414-27 assume 1 == ~t2_pc~0; 12595#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12455#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12454#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12330#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11870#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11871#L433-27 assume !(1 == ~t3_pc~0); 11973#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 12276#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12277#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12047#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12048#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12623#L452-27 assume 1 == ~t4_pc~0; 12624#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12424#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12240#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12241#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12592#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11863#L471-27 assume 1 == ~t5_pc~0; 11864#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12188#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12545#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12478#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12405#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12338#L490-27 assume 1 == ~t6_pc~0; 12237#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12058#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12059#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12462#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 12463#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11830#L509-27 assume 1 == ~t7_pc~0; 11831#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12239#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12120#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12121#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12358#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12370#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12371#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12401#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12622#L867-3 assume !(1 == ~T3_E~0); 12278#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12279#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12365#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12395#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12018#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12019#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12542#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12192#L907-3 assume !(1 == ~E_3~0); 12193#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12318#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12283#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12071#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12072#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11922#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11819#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12129#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 12130#L1197 assume !(0 == start_simulation_~tmp~3#1); 12251#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11981#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11945#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11838#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 11839#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12539#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12332#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 11844#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 11845#L1178-2 [2023-11-19 07:54:35,222 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:35,223 INFO L85 PathProgramCache]: Analyzing trace with hash -718887553, now seen corresponding path program 1 times [2023-11-19 07:54:35,223 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:35,223 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [818711694] [2023-11-19 07:54:35,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:35,223 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:35,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:35,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:35,345 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:35,345 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [818711694] [2023-11-19 07:54:35,346 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [818711694] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:35,346 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:35,346 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:35,346 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1406498359] [2023-11-19 07:54:35,346 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:35,347 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:54:35,347 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:35,347 INFO L85 PathProgramCache]: Analyzing trace with hash -268845801, now seen corresponding path program 3 times [2023-11-19 07:54:35,347 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:35,347 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [222098374] [2023-11-19 07:54:35,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:35,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:35,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:35,420 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:35,420 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:35,420 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [222098374] [2023-11-19 07:54:35,423 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [222098374] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:35,423 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:35,423 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:35,423 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1015403093] [2023-11-19 07:54:35,423 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:35,424 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:54:35,424 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:54:35,424 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:54:35,425 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:54:35,425 INFO L87 Difference]: Start difference. First operand 838 states and 1242 transitions. cyclomatic complexity: 405 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:35,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:54:35,585 INFO L93 Difference]: Finished difference Result 1515 states and 2236 transitions. [2023-11-19 07:54:35,585 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1515 states and 2236 transitions. [2023-11-19 07:54:35,601 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1396 [2023-11-19 07:54:35,615 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1515 states to 1515 states and 2236 transitions. [2023-11-19 07:54:35,615 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1515 [2023-11-19 07:54:35,617 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1515 [2023-11-19 07:54:35,617 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1515 states and 2236 transitions. [2023-11-19 07:54:35,619 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:54:35,620 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1515 states and 2236 transitions. [2023-11-19 07:54:35,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1515 states and 2236 transitions. [2023-11-19 07:54:35,651 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1515 to 1515. [2023-11-19 07:54:35,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1515 states, 1515 states have (on average 1.475907590759076) internal successors, (2236), 1514 states have internal predecessors, (2236), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:35,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1515 states to 1515 states and 2236 transitions. [2023-11-19 07:54:35,663 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1515 states and 2236 transitions. [2023-11-19 07:54:35,663 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:54:35,664 INFO L428 stractBuchiCegarLoop]: Abstraction has 1515 states and 2236 transitions. [2023-11-19 07:54:35,664 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-19 07:54:35,664 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1515 states and 2236 transitions. [2023-11-19 07:54:35,675 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1396 [2023-11-19 07:54:35,675 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:54:35,675 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:54:35,677 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:35,677 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:35,678 INFO L748 eck$LassoCheckResult]: Stem: 14385#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 14386#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 14974#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14975#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14948#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 14949#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14635#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14455#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14456#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14436#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14437#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14947#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14758#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14759#L769 assume !(0 == ~M_E~0); 14779#L769-2 assume !(0 == ~T1_E~0); 14780#L774-1 assume !(0 == ~T2_E~0); 14809#L779-1 assume !(0 == ~T3_E~0); 14936#L784-1 assume !(0 == ~T4_E~0); 14756#L789-1 assume !(0 == ~T5_E~0); 14757#L794-1 assume !(0 == ~T6_E~0); 14869#L799-1 assume !(0 == ~T7_E~0); 14761#L804-1 assume !(0 == ~E_M~0); 14762#L809-1 assume !(0 == ~E_1~0); 14803#L814-1 assume !(0 == ~E_2~0); 14173#L819-1 assume !(0 == ~E_3~0); 14174#L824-1 assume !(0 == ~E_4~0); 14530#L829-1 assume !(0 == ~E_5~0); 15008#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 14310#L839-1 assume !(0 == ~E_7~0); 14311#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14709#L376 assume !(1 == ~m_pc~0); 14696#L376-2 is_master_triggered_~__retres1~0#1 := 0; 14695#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14916#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14251#L955 assume !(0 != activate_threads_~tmp~1#1); 14252#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14628#L395 assume 1 == ~t1_pc~0; 14287#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14288#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14203#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14204#L963 assume !(0 != activate_threads_~tmp___0~0#1); 14713#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14714#L414 assume !(1 == ~t2_pc~0); 14313#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14314#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14536#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14537#L971 assume !(0 != activate_threads_~tmp___1~0#1); 14953#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14632#L433 assume 1 == ~t3_pc~0; 14573#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14425#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14171#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14172#L979 assume !(0 != activate_threads_~tmp___2~0#1); 14276#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14277#L452 assume !(1 == ~t4_pc~0); 14432#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14433#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14270#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14271#L987 assume !(0 != activate_threads_~tmp___3~0#1); 14466#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14467#L471 assume 1 == ~t5_pc~0; 14856#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14447#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14448#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14920#L995 assume !(0 != activate_threads_~tmp___4~0#1); 14999#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15000#L490 assume 1 == ~t6_pc~0; 14979#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14712#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14523#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14524#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 14642#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14610#L509 assume !(1 == ~t7_pc~0); 14611#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 14407#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14408#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14473#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14474#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14959#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 14258#L857-2 assume !(1 == ~T1_E~0); 14259#L862-1 assume !(1 == ~T2_E~0); 14540#L867-1 assume !(1 == ~T3_E~0); 14545#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14633#L877-1 assume !(1 == ~T5_E~0); 14831#L882-1 assume !(1 == ~T6_E~0); 14978#L887-1 assume !(1 == ~T7_E~0); 15159#L892-1 assume !(1 == ~E_M~0); 15157#L897-1 assume !(1 == ~E_1~0); 15155#L902-1 assume !(1 == ~E_2~0); 15153#L907-1 assume !(1 == ~E_3~0); 14845#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 14846#L917-1 assume !(1 == ~E_5~0); 15076#L922-1 assume !(1 == ~E_6~0); 15072#L927-1 assume !(1 == ~E_7~0); 14826#L932-1 assume { :end_inline_reset_delta_events } true; 14208#L1178-2 [2023-11-19 07:54:35,678 INFO L750 eck$LassoCheckResult]: Loop: 14208#L1178-2 assume !false; 14810#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14811#L744-1 assume !false; 14674#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14675#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14243#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14453#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14558#L641 assume !(0 != eval_~tmp~0#1); 14887#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14682#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14683#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14630#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14631#L774-3 assume !(0 == ~T2_E~0); 14364#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14184#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14185#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14175#L794-3 assume !(0 == ~T6_E~0); 14176#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14225#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14480#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14221#L814-3 assume !(0 == ~E_2~0); 14222#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14907#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14902#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14541#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14542#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14868#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14957#L376-27 assume 1 == ~m_pc~0; 14841#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14785#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14786#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14863#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15012#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15040#L395-27 assume 1 == ~t1_pc~0; 15032#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14543#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14544#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14749#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14637#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14638#L414-27 assume 1 == ~t2_pc~0; 14992#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14836#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14835#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14698#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14233#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14234#L433-27 assume !(1 == ~t3_pc~0); 14336#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 14644#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14645#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14410#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14411#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15026#L452-27 assume !(1 == ~t4_pc~0); 14800#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 14801#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14608#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14609#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14989#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14997#L471-27 assume !(1 == ~t5_pc~0); 15146#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 15145#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15144#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15143#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15142#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15141#L490-27 assume 1 == ~t6_pc~0; 15139#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15138#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15134#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15132#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 15130#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15129#L509-27 assume 1 == ~t7_pc~0; 14739#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14607#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14484#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14485#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14729#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15037#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14745#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14777#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15024#L867-3 assume !(1 == ~T3_E~0); 14646#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14647#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14738#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14771#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14381#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14382#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14927#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14559#L907-3 assume !(1 == ~E_3~0); 14560#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14686#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14951#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15099#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15098#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15097#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 15088#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15086#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 15085#L1197 assume !(0 == start_simulation_~tmp~3#1); 15031#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15084#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 15068#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15067#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 15066#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15065#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14700#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 14207#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 14208#L1178-2 [2023-11-19 07:54:35,679 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:35,679 INFO L85 PathProgramCache]: Analyzing trace with hash -1207876549, now seen corresponding path program 1 times [2023-11-19 07:54:35,679 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:35,679 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [703145951] [2023-11-19 07:54:35,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:35,680 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:35,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:35,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:35,749 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:35,749 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [703145951] [2023-11-19 07:54:35,750 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [703145951] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:35,750 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:35,750 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:35,750 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [232985844] [2023-11-19 07:54:35,750 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:35,750 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:54:35,751 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:35,751 INFO L85 PathProgramCache]: Analyzing trace with hash 864207127, now seen corresponding path program 1 times [2023-11-19 07:54:35,751 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:35,751 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2005426490] [2023-11-19 07:54:35,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:35,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:35,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:35,805 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:35,805 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:35,805 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2005426490] [2023-11-19 07:54:35,805 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2005426490] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:35,805 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:35,806 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:35,806 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1905591852] [2023-11-19 07:54:35,806 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:35,806 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:54:35,806 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:54:35,807 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:54:35,807 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:54:35,807 INFO L87 Difference]: Start difference. First operand 1515 states and 2236 transitions. cyclomatic complexity: 723 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:36,024 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:54:36,024 INFO L93 Difference]: Finished difference Result 2735 states and 4023 transitions. [2023-11-19 07:54:36,025 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2735 states and 4023 transitions. [2023-11-19 07:54:36,053 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2602 [2023-11-19 07:54:36,078 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2735 states to 2735 states and 4023 transitions. [2023-11-19 07:54:36,079 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2735 [2023-11-19 07:54:36,082 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2735 [2023-11-19 07:54:36,082 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2735 states and 4023 transitions. [2023-11-19 07:54:36,086 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:54:36,087 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2735 states and 4023 transitions. [2023-11-19 07:54:36,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2735 states and 4023 transitions. [2023-11-19 07:54:36,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2735 to 2733. [2023-11-19 07:54:36,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2733 states, 2733 states have (on average 1.4712769849981706) internal successors, (4021), 2732 states have internal predecessors, (4021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:36,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2733 states to 2733 states and 4021 transitions. [2023-11-19 07:54:36,155 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2733 states and 4021 transitions. [2023-11-19 07:54:36,156 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:54:36,156 INFO L428 stractBuchiCegarLoop]: Abstraction has 2733 states and 4021 transitions. [2023-11-19 07:54:36,157 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-19 07:54:36,157 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2733 states and 4021 transitions. [2023-11-19 07:54:36,171 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2602 [2023-11-19 07:54:36,172 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:54:36,172 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:54:36,174 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:36,174 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:36,174 INFO L748 eck$LassoCheckResult]: Stem: 18647#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 18648#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 19216#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19217#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19194#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 19195#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18893#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18714#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18715#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18696#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18697#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19193#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19012#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19013#L769 assume !(0 == ~M_E~0); 19032#L769-2 assume !(0 == ~T1_E~0); 19033#L774-1 assume !(0 == ~T2_E~0); 19060#L779-1 assume !(0 == ~T3_E~0); 19181#L784-1 assume !(0 == ~T4_E~0); 19010#L789-1 assume !(0 == ~T5_E~0); 19011#L794-1 assume !(0 == ~T6_E~0); 19117#L799-1 assume !(0 == ~T7_E~0); 19015#L804-1 assume !(0 == ~E_M~0); 19016#L809-1 assume !(0 == ~E_1~0); 19055#L814-1 assume !(0 == ~E_2~0); 18435#L819-1 assume !(0 == ~E_3~0); 18436#L824-1 assume !(0 == ~E_4~0); 18789#L829-1 assume !(0 == ~E_5~0); 19245#L834-1 assume !(0 == ~E_6~0); 18570#L839-1 assume !(0 == ~E_7~0); 18571#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18966#L376 assume !(1 == ~m_pc~0); 18959#L376-2 is_master_triggered_~__retres1~0#1 := 0; 18958#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19165#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18513#L955 assume !(0 != activate_threads_~tmp~1#1); 18514#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18886#L395 assume 1 == ~t1_pc~0; 18547#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18548#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18463#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18464#L963 assume !(0 != activate_threads_~tmp___0~0#1); 18971#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18972#L414 assume !(1 == ~t2_pc~0); 18573#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18574#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18795#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18796#L971 assume !(0 != activate_threads_~tmp___1~0#1); 19198#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18890#L433 assume 1 == ~t3_pc~0; 18832#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18687#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18431#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18432#L979 assume !(0 != activate_threads_~tmp___2~0#1); 18536#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18537#L452 assume !(1 == ~t4_pc~0); 18692#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18693#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18530#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18531#L987 assume !(0 != activate_threads_~tmp___3~0#1); 18725#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18726#L471 assume 1 == ~t5_pc~0; 19103#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18707#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18708#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19168#L995 assume !(0 != activate_threads_~tmp___4~0#1); 19236#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19237#L490 assume 1 == ~t6_pc~0; 19222#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18969#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18782#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18783#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 18902#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18868#L509 assume !(1 == ~t7_pc~0); 18869#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18672#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18673#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18732#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18733#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19204#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 19205#L857-2 assume !(1 == ~T1_E~0); 19402#L862-1 assume !(1 == ~T2_E~0); 18804#L867-1 assume !(1 == ~T3_E~0); 18805#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18891#L877-1 assume !(1 == ~T5_E~0); 19079#L882-1 assume !(1 == ~T6_E~0); 19220#L887-1 assume !(1 == ~T7_E~0); 19133#L892-1 assume !(1 == ~E_M~0); 19134#L897-1 assume !(1 == ~E_1~0); 19352#L902-1 assume !(1 == ~E_2~0); 19350#L907-1 assume !(1 == ~E_3~0); 19095#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 19085#L917-1 assume !(1 == ~E_5~0); 19086#L922-1 assume !(1 == ~E_6~0); 19322#L927-1 assume !(1 == ~E_7~0); 19314#L932-1 assume { :end_inline_reset_delta_events } true; 19308#L1178-2 [2023-11-19 07:54:36,175 INFO L750 eck$LassoCheckResult]: Loop: 19308#L1178-2 assume !false; 19304#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19303#L744-1 assume !false; 19302#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19301#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19293#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19292#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19290#L641 assume !(0 != eval_~tmp~0#1); 19289#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19288#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19286#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19287#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20481#L774-3 assume !(0 == ~T2_E~0); 20156#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20147#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20145#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20143#L794-3 assume !(0 == ~T6_E~0); 20141#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20139#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20137#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20135#L814-3 assume !(0 == ~E_2~0); 20116#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20113#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20110#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20106#L834-3 assume !(0 == ~E_6~0); 20103#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20100#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20097#L376-27 assume 1 == ~m_pc~0; 20073#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20069#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20065#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20049#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20044#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20038#L395-27 assume !(1 == ~t1_pc~0); 20030#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 20025#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20021#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20016#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20012#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20006#L414-27 assume 1 == ~t2_pc~0; 19998#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19993#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19988#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19981#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19976#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19971#L433-27 assume !(1 == ~t3_pc~0); 19963#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 19958#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19953#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19946#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19941#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19937#L452-27 assume 1 == ~t4_pc~0; 19930#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19851#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19849#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19847#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19844#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19842#L471-27 assume 1 == ~t5_pc~0; 19840#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19837#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19767#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19765#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19763#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19761#L490-27 assume 1 == ~t6_pc~0; 19758#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19756#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19753#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19752#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 19722#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19721#L509-27 assume 1 == ~t7_pc~0; 19719#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19716#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19714#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19712#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19710#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19708#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18998#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19705#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19703#L867-3 assume !(1 == ~T3_E~0); 19701#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19685#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19641#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19638#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19636#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19635#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19634#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19633#L907-3 assume !(1 == ~E_3~0); 19631#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19628#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19604#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19599#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19594#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19586#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19575#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19572#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 19571#L1197 assume !(0 == start_simulation_~tmp~3#1); 19278#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19370#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19360#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19358#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 19336#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19332#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19323#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 19315#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 19308#L1178-2 [2023-11-19 07:54:36,175 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:36,176 INFO L85 PathProgramCache]: Analyzing trace with hash -253936391, now seen corresponding path program 1 times [2023-11-19 07:54:36,176 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:36,176 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1092279549] [2023-11-19 07:54:36,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:36,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:36,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:36,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:36,246 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:36,246 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1092279549] [2023-11-19 07:54:36,246 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1092279549] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:36,246 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:36,246 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:36,246 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [299204663] [2023-11-19 07:54:36,246 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:36,247 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:54:36,247 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:36,247 INFO L85 PathProgramCache]: Analyzing trace with hash -66395884, now seen corresponding path program 1 times [2023-11-19 07:54:36,247 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:36,248 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [850775086] [2023-11-19 07:54:36,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:36,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:36,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:36,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:36,302 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:36,302 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [850775086] [2023-11-19 07:54:36,302 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [850775086] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:36,302 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:36,302 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:36,303 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1898133517] [2023-11-19 07:54:36,303 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:36,303 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:54:36,303 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:54:36,304 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:54:36,304 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:54:36,304 INFO L87 Difference]: Start difference. First operand 2733 states and 4021 transitions. cyclomatic complexity: 1292 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:36,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:54:36,602 INFO L93 Difference]: Finished difference Result 7554 states and 10942 transitions. [2023-11-19 07:54:36,602 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7554 states and 10942 transitions. [2023-11-19 07:54:36,669 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7173 [2023-11-19 07:54:36,785 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7554 states to 7554 states and 10942 transitions. [2023-11-19 07:54:36,786 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7554 [2023-11-19 07:54:36,794 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7554 [2023-11-19 07:54:36,794 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7554 states and 10942 transitions. [2023-11-19 07:54:36,808 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:54:36,808 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7554 states and 10942 transitions. [2023-11-19 07:54:36,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7554 states and 10942 transitions. [2023-11-19 07:54:36,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7554 to 7122. [2023-11-19 07:54:36,998 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7122 states, 7122 states have (on average 1.4532434709351305) internal successors, (10350), 7121 states have internal predecessors, (10350), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:37,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7122 states to 7122 states and 10350 transitions. [2023-11-19 07:54:37,030 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7122 states and 10350 transitions. [2023-11-19 07:54:37,031 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:54:37,032 INFO L428 stractBuchiCegarLoop]: Abstraction has 7122 states and 10350 transitions. [2023-11-19 07:54:37,032 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-19 07:54:37,032 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7122 states and 10350 transitions. [2023-11-19 07:54:37,068 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6973 [2023-11-19 07:54:37,069 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:54:37,069 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:54:37,071 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:37,071 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:37,071 INFO L748 eck$LassoCheckResult]: Stem: 28940#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 28941#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 29567#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29568#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29541#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 29542#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29201#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29013#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29014#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28994#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28995#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29540#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29334#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29335#L769 assume !(0 == ~M_E~0); 29359#L769-2 assume !(0 == ~T1_E~0); 29360#L774-1 assume !(0 == ~T2_E~0); 29392#L779-1 assume !(0 == ~T3_E~0); 29523#L784-1 assume !(0 == ~T4_E~0); 29332#L789-1 assume !(0 == ~T5_E~0); 29333#L794-1 assume !(0 == ~T6_E~0); 29453#L799-1 assume !(0 == ~T7_E~0); 29337#L804-1 assume !(0 == ~E_M~0); 29338#L809-1 assume !(0 == ~E_1~0); 29384#L814-1 assume !(0 == ~E_2~0); 28730#L819-1 assume !(0 == ~E_3~0); 28731#L824-1 assume !(0 == ~E_4~0); 29086#L829-1 assume !(0 == ~E_5~0); 29611#L834-1 assume !(0 == ~E_6~0); 28862#L839-1 assume !(0 == ~E_7~0); 28863#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29278#L376 assume !(1 == ~m_pc~0); 29275#L376-2 is_master_triggered_~__retres1~0#1 := 0; 29276#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29507#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 28805#L955 assume !(0 != activate_threads_~tmp~1#1); 28806#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29193#L395 assume !(1 == ~t1_pc~0); 29361#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29508#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28759#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 28760#L963 assume !(0 != activate_threads_~tmp___0~0#1); 29282#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29283#L414 assume !(1 == ~t2_pc~0); 28865#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28866#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29093#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 29094#L971 assume !(0 != activate_threads_~tmp___1~0#1); 29546#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29197#L433 assume 1 == ~t3_pc~0; 29133#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28983#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28728#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28729#L979 assume !(0 != activate_threads_~tmp___2~0#1); 28830#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28831#L452 assume !(1 == ~t4_pc~0); 28990#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28991#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28824#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28825#L987 assume !(0 != activate_threads_~tmp___3~0#1); 29024#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29025#L471 assume 1 == ~t5_pc~0; 29437#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29005#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29006#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29511#L995 assume !(0 != activate_threads_~tmp___4~0#1); 29602#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29603#L490 assume 1 == ~t6_pc~0; 29579#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29281#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29080#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29081#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 29208#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29173#L509 assume !(1 == ~t7_pc~0); 29174#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 28962#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28963#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29031#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29032#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29553#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 29554#L857-2 assume !(1 == ~T1_E~0); 29097#L862-1 assume !(1 == ~T2_E~0); 29098#L867-1 assume !(1 == ~T3_E~0); 29198#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29199#L877-1 assume !(1 == ~T5_E~0); 29577#L882-1 assume !(1 == ~T6_E~0); 29578#L887-1 assume !(1 == ~T7_E~0); 34768#L892-1 assume !(1 == ~E_M~0); 34767#L897-1 assume !(1 == ~E_1~0); 34766#L902-1 assume !(1 == ~E_2~0); 34765#L907-1 assume !(1 == ~E_3~0); 34764#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 34763#L917-1 assume !(1 == ~E_5~0); 34762#L922-1 assume !(1 == ~E_6~0); 29614#L927-1 assume !(1 == ~E_7~0); 29668#L932-1 assume { :end_inline_reset_delta_events } true; 34611#L1178-2 [2023-11-19 07:54:37,072 INFO L750 eck$LassoCheckResult]: Loop: 34611#L1178-2 assume !false; 34468#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34467#L744-1 assume !false; 34465#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 34344#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 34328#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 34326#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 34324#L641 assume !(0 != eval_~tmp~0#1); 29473#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29250#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29251#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29195#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29196#L774-3 assume !(0 == ~T2_E~0); 28918#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28741#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28742#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28732#L794-3 assume !(0 == ~T6_E~0); 28733#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28780#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29038#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28776#L814-3 assume !(0 == ~E_2~0); 28777#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29498#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29492#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29099#L834-3 assume !(0 == ~E_6~0); 29100#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34304#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29637#L376-27 assume !(1 == ~m_pc~0); 29638#L376-29 is_master_triggered_~__retres1~0#1 := 0; 35556#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35555#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 35552#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35550#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35548#L395-27 assume !(1 == ~t1_pc~0); 35546#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 35545#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29321#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 29322#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29358#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29598#L414-27 assume !(1 == ~t2_pc~0); 29600#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 29643#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35537#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 35535#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28788#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28789#L433-27 assume !(1 == ~t3_pc~0); 28890#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 29267#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35521#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 35519#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29646#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29647#L452-27 assume 1 == ~t4_pc~0; 35514#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29525#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29526#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29594#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29595#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28781#L471-27 assume 1 == ~t5_pc~0; 28782#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29673#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29520#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29441#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29362#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29277#L490-27 assume 1 == ~t6_pc~0; 29168#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28978#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28979#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29612#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 35483#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35481#L509-27 assume 1 == ~t7_pc~0; 35477#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35473#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35469#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35467#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35466#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35465#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29354#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29355#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29639#L867-3 assume !(1 == ~T3_E~0); 29212#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29213#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35397#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32347#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 35302#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 35301#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35300#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35299#L907-3 assume !(1 == ~E_3~0); 35023#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35022#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34294#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 34292#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 34293#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 34687#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 34678#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 34675#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 34673#L1197 assume !(0 == start_simulation_~tmp~3#1); 34670#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 34668#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 34659#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 34658#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 34656#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34655#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34654#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 34624#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 34611#L1178-2 [2023-11-19 07:54:37,072 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:37,073 INFO L85 PathProgramCache]: Analyzing trace with hash -1285267206, now seen corresponding path program 1 times [2023-11-19 07:54:37,073 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:37,073 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1341977546] [2023-11-19 07:54:37,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:37,073 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:37,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:37,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:37,141 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:37,142 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1341977546] [2023-11-19 07:54:37,142 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1341977546] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:37,142 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:37,142 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:37,142 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1900977572] [2023-11-19 07:54:37,142 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:37,143 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:54:37,143 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:37,143 INFO L85 PathProgramCache]: Analyzing trace with hash -1531066858, now seen corresponding path program 1 times [2023-11-19 07:54:37,144 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:37,144 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [838802908] [2023-11-19 07:54:37,144 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:37,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:37,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:37,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:37,197 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:37,197 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [838802908] [2023-11-19 07:54:37,197 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [838802908] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:37,197 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:37,197 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:37,197 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [423567214] [2023-11-19 07:54:37,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:37,198 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:54:37,198 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:54:37,199 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:54:37,199 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:54:37,199 INFO L87 Difference]: Start difference. First operand 7122 states and 10350 transitions. cyclomatic complexity: 3236 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:37,653 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:54:37,653 INFO L93 Difference]: Finished difference Result 19887 states and 28575 transitions. [2023-11-19 07:54:37,653 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19887 states and 28575 transitions. [2023-11-19 07:54:37,775 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19183 [2023-11-19 07:54:37,889 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19887 states to 19887 states and 28575 transitions. [2023-11-19 07:54:37,889 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19887 [2023-11-19 07:54:37,908 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19887 [2023-11-19 07:54:37,908 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19887 states and 28575 transitions. [2023-11-19 07:54:37,933 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:54:37,933 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19887 states and 28575 transitions. [2023-11-19 07:54:37,957 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19887 states and 28575 transitions. [2023-11-19 07:54:38,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19887 to 18939. [2023-11-19 07:54:38,385 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18939 states, 18939 states have (on average 1.4414171814773746) internal successors, (27299), 18938 states have internal predecessors, (27299), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:38,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18939 states to 18939 states and 27299 transitions. [2023-11-19 07:54:38,449 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18939 states and 27299 transitions. [2023-11-19 07:54:38,449 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:54:38,450 INFO L428 stractBuchiCegarLoop]: Abstraction has 18939 states and 27299 transitions. [2023-11-19 07:54:38,450 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-19 07:54:38,450 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18939 states and 27299 transitions. [2023-11-19 07:54:38,695 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18751 [2023-11-19 07:54:38,695 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:54:38,695 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:54:38,697 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:38,697 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:38,698 INFO L748 eck$LassoCheckResult]: Stem: 55959#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 55960#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 56641#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 56642#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 56612#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 56613#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56220#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 56036#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56037#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56017#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 56018#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 56611#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 56365#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 56366#L769 assume !(0 == ~M_E~0); 56388#L769-2 assume !(0 == ~T1_E~0); 56389#L774-1 assume !(0 == ~T2_E~0); 56426#L779-1 assume !(0 == ~T3_E~0); 56590#L784-1 assume !(0 == ~T4_E~0); 56363#L789-1 assume !(0 == ~T5_E~0); 56364#L794-1 assume !(0 == ~T6_E~0); 56500#L799-1 assume !(0 == ~T7_E~0); 56368#L804-1 assume !(0 == ~E_M~0); 56369#L809-1 assume !(0 == ~E_1~0); 56418#L814-1 assume !(0 == ~E_2~0); 55749#L819-1 assume !(0 == ~E_3~0); 55750#L824-1 assume !(0 == ~E_4~0); 56110#L829-1 assume !(0 == ~E_5~0); 56701#L834-1 assume !(0 == ~E_6~0); 55882#L839-1 assume !(0 == ~E_7~0); 55883#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56308#L376 assume !(1 == ~m_pc~0); 56303#L376-2 is_master_triggered_~__retres1~0#1 := 0; 56304#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56566#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 55826#L955 assume !(0 != activate_threads_~tmp~1#1); 55827#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56213#L395 assume !(1 == ~t1_pc~0); 56390#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 56567#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55779#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 55780#L963 assume !(0 != activate_threads_~tmp___0~0#1); 56316#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56317#L414 assume !(1 == ~t2_pc~0); 55885#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 55886#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56118#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 56119#L971 assume !(0 != activate_threads_~tmp___1~0#1); 56618#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56217#L433 assume !(1 == ~t3_pc~0); 56004#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 56005#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55747#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 55748#L979 assume !(0 != activate_threads_~tmp___2~0#1); 55850#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55851#L452 assume !(1 == ~t4_pc~0); 56013#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 56014#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55844#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 55845#L987 assume !(0 != activate_threads_~tmp___3~0#1); 56047#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56048#L471 assume 1 == ~t5_pc~0; 56484#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56029#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56030#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 56570#L995 assume !(0 != activate_threads_~tmp___4~0#1); 56690#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 56691#L490 assume 1 == ~t6_pc~0; 56648#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 56315#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 56104#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56105#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 56228#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56193#L509 assume !(1 == ~t7_pc~0); 56194#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 55982#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55983#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 56054#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 56055#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56625#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 55833#L857-2 assume !(1 == ~T1_E~0); 55834#L862-1 assume !(1 == ~T2_E~0); 56122#L867-1 assume !(1 == ~T3_E~0); 56127#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56218#L877-1 assume !(1 == ~T5_E~0); 56448#L882-1 assume !(1 == ~T6_E~0); 56647#L887-1 assume !(1 == ~T7_E~0); 56522#L892-1 assume !(1 == ~E_M~0); 56523#L897-1 assume !(1 == ~E_1~0); 56145#L902-1 assume !(1 == ~E_2~0); 56146#L907-1 assume !(1 == ~E_3~0); 56469#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 56457#L917-1 assume !(1 == ~E_5~0); 56458#L922-1 assume !(1 == ~E_6~0); 56704#L927-1 assume !(1 == ~E_7~0); 56784#L932-1 assume { :end_inline_reset_delta_events } true; 71213#L1178-2 [2023-11-19 07:54:38,698 INFO L750 eck$LassoCheckResult]: Loop: 71213#L1178-2 assume !false; 70858#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 70859#L744-1 assume !false; 70852#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 70853#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 74065#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 74064#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 74063#L641 assume !(0 != eval_~tmp~0#1); 73809#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 73810#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 73782#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 73783#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 56401#L774-3 assume !(0 == ~T2_E~0); 55936#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55760#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 55761#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 55751#L794-3 assume !(0 == ~T6_E~0); 55752#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 56061#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 56062#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 55796#L814-3 assume !(0 == ~E_2~0); 55797#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 56554#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 56555#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 56123#L834-3 assume !(0 == ~E_6~0); 56124#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 56622#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56623#L376-27 assume !(1 == ~m_pc~0); 73776#L376-29 is_master_triggered_~__retres1~0#1 := 0; 73777#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 73770#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 73771#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 56798#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56799#L395-27 assume !(1 == ~t1_pc~0); 56236#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 56125#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56126#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 56353#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 56222#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56223#L414-27 assume 1 == ~t2_pc~0; 56797#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 56751#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56453#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 56454#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 55809#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55810#L433-27 assume !(1 == ~t3_pc~0); 55909#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 56230#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56231#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 55987#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 55988#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56753#L452-27 assume 1 == ~t4_pc~0; 56806#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 56416#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56191#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 56192#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 74386#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55802#L471-27 assume 1 == ~t5_pc~0; 55803#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56800#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56801#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 56488#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 56391#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 56392#L490-27 assume 1 == ~t6_pc~0; 56186#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 56187#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 74384#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56467#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 56468#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 72711#L509-27 assume !(1 == ~t7_pc~0); 72713#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 72706#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 72707#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 72701#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 72702#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 72696#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 67484#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 72691#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 72692#L867-3 assume !(1 == ~T3_E~0); 72685#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 72686#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 72679#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 71697#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 72674#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 72675#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 72668#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 72669#L907-3 assume !(1 == ~E_3~0); 72663#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 72664#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 72658#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 67458#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 72653#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 72654#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 74245#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 74244#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 72527#L1197 assume !(0 == start_simulation_~tmp~3#1); 72520#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 72521#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 74080#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 74079#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 74078#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 74077#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 74076#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 74075#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 71213#L1178-2 [2023-11-19 07:54:38,698 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:38,699 INFO L85 PathProgramCache]: Analyzing trace with hash 1116257915, now seen corresponding path program 1 times [2023-11-19 07:54:38,699 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:38,699 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1713275228] [2023-11-19 07:54:38,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:38,699 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:38,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:38,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:38,770 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:38,770 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1713275228] [2023-11-19 07:54:38,770 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1713275228] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:38,772 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:38,772 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:54:38,773 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1909457706] [2023-11-19 07:54:38,774 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:38,774 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:54:38,774 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:38,775 INFO L85 PathProgramCache]: Analyzing trace with hash -857260586, now seen corresponding path program 1 times [2023-11-19 07:54:38,775 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:38,775 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1521691878] [2023-11-19 07:54:38,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:38,775 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:38,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:38,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:38,819 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:38,819 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1521691878] [2023-11-19 07:54:38,820 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1521691878] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:38,820 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:38,820 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:38,820 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1745273100] [2023-11-19 07:54:38,820 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:38,821 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:54:38,821 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:54:38,821 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:54:38,821 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:54:38,822 INFO L87 Difference]: Start difference. First operand 18939 states and 27299 transitions. cyclomatic complexity: 8376 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:39,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:54:39,310 INFO L93 Difference]: Finished difference Result 36474 states and 52261 transitions. [2023-11-19 07:54:39,310 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36474 states and 52261 transitions. [2023-11-19 07:54:39,550 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36155 [2023-11-19 07:54:39,903 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36474 states to 36474 states and 52261 transitions. [2023-11-19 07:54:39,904 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 36474 [2023-11-19 07:54:39,943 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 36474 [2023-11-19 07:54:39,943 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36474 states and 52261 transitions. [2023-11-19 07:54:39,975 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:54:39,975 INFO L218 hiAutomatonCegarLoop]: Abstraction has 36474 states and 52261 transitions. [2023-11-19 07:54:40,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36474 states and 52261 transitions. [2023-11-19 07:54:40,482 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36474 to 36402. [2023-11-19 07:54:40,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36402 states, 36402 states have (on average 1.4336849623647052) internal successors, (52189), 36401 states have internal predecessors, (52189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:40,643 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36402 states to 36402 states and 52189 transitions. [2023-11-19 07:54:40,643 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36402 states and 52189 transitions. [2023-11-19 07:54:40,644 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:54:40,645 INFO L428 stractBuchiCegarLoop]: Abstraction has 36402 states and 52189 transitions. [2023-11-19 07:54:40,645 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-19 07:54:40,645 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36402 states and 52189 transitions. [2023-11-19 07:54:40,950 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36083 [2023-11-19 07:54:40,950 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:54:40,951 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:54:40,952 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:40,953 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:40,953 INFO L748 eck$LassoCheckResult]: Stem: 111376#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 111377#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 112004#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 112005#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 111982#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 111983#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 111640#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 111449#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 111450#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 111430#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 111431#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 111981#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 111768#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 111769#L769 assume !(0 == ~M_E~0); 111791#L769-2 assume !(0 == ~T1_E~0); 111792#L774-1 assume !(0 == ~T2_E~0); 111822#L779-1 assume !(0 == ~T3_E~0); 111966#L784-1 assume !(0 == ~T4_E~0); 111766#L789-1 assume !(0 == ~T5_E~0); 111767#L794-1 assume !(0 == ~T6_E~0); 111885#L799-1 assume !(0 == ~T7_E~0); 111771#L804-1 assume !(0 == ~E_M~0); 111772#L809-1 assume !(0 == ~E_1~0); 111814#L814-1 assume !(0 == ~E_2~0); 111169#L819-1 assume !(0 == ~E_3~0); 111170#L824-1 assume !(0 == ~E_4~0); 111523#L829-1 assume !(0 == ~E_5~0); 112054#L834-1 assume !(0 == ~E_6~0); 111300#L839-1 assume !(0 == ~E_7~0); 111301#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 111718#L376 assume !(1 == ~m_pc~0); 111715#L376-2 is_master_triggered_~__retres1~0#1 := 0; 111716#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 111945#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 111244#L955 assume !(0 != activate_threads_~tmp~1#1); 111245#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 111629#L395 assume !(1 == ~t1_pc~0); 111793#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 111946#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 111198#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 111199#L963 assume !(0 != activate_threads_~tmp___0~0#1); 111722#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 111723#L414 assume !(1 == ~t2_pc~0); 111303#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 111304#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 111531#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 111532#L971 assume !(0 != activate_threads_~tmp___1~0#1); 111987#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 111636#L433 assume !(1 == ~t3_pc~0); 111418#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 111419#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 111167#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 111168#L979 assume !(0 != activate_threads_~tmp___2~0#1); 111268#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 111269#L452 assume !(1 == ~t4_pc~0); 111426#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 111427#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 111262#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 111263#L987 assume !(0 != activate_threads_~tmp___3~0#1); 111461#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 111462#L471 assume !(1 == ~t5_pc~0); 111873#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 111441#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 111442#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 111949#L995 assume !(0 != activate_threads_~tmp___4~0#1); 112043#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 112044#L490 assume 1 == ~t6_pc~0; 112016#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 111721#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 111517#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 111518#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 111648#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 111609#L509 assume !(1 == ~t7_pc~0); 111610#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 111398#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 111399#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 111468#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 111469#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 111993#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 111994#L857-2 assume !(1 == ~T1_E~0); 111535#L862-1 assume !(1 == ~T2_E~0); 111536#L867-1 assume !(1 == ~T3_E~0); 111637#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 111638#L877-1 assume !(1 == ~T5_E~0); 112014#L882-1 assume !(1 == ~T6_E~0); 112015#L887-1 assume !(1 == ~T7_E~0); 118202#L892-1 assume !(1 == ~E_M~0); 118200#L897-1 assume !(1 == ~E_1~0); 118198#L902-1 assume !(1 == ~E_2~0); 118196#L907-1 assume !(1 == ~E_3~0); 118194#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 118192#L917-1 assume !(1 == ~E_5~0); 118190#L922-1 assume !(1 == ~E_6~0); 118188#L927-1 assume !(1 == ~E_7~0); 118186#L932-1 assume { :end_inline_reset_delta_events } true; 118184#L1178-2 [2023-11-19 07:54:40,954 INFO L750 eck$LassoCheckResult]: Loop: 118184#L1178-2 assume !false; 117790#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 117787#L744-1 assume !false; 117785#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 117783#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 117774#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 117738#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 117729#L641 assume !(0 != eval_~tmp~0#1); 117730#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 142638#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 142637#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 142636#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 142635#L774-3 assume !(0 == ~T2_E~0); 142634#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 142633#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 142632#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 142631#L794-3 assume !(0 == ~T6_E~0); 142630#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 142629#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 142628#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 142627#L814-3 assume !(0 == ~E_2~0); 142626#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 142625#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 142624#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 142623#L834-3 assume !(0 == ~E_6~0); 142622#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 142621#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 142620#L376-27 assume !(1 == ~m_pc~0); 142619#L376-29 is_master_triggered_~__retres1~0#1 := 0; 142618#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 142617#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 142616#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 142615#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 142614#L395-27 assume !(1 == ~t1_pc~0); 142613#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 142612#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 142611#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 120424#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 120425#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 120412#L414-27 assume 1 == ~t2_pc~0; 120413#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 120402#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 120403#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 120396#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 120397#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 120386#L433-27 assume !(1 == ~t3_pc~0); 120387#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 120373#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 120374#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 120357#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 120358#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 120342#L452-27 assume 1 == ~t4_pc~0; 120343#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 120327#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 120322#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 120316#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 120317#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 120301#L471-27 assume !(1 == ~t5_pc~0); 120302#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 120285#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 120286#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 120270#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 120271#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 120255#L490-27 assume 1 == ~t6_pc~0; 120257#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 120239#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 120240#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 120225#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 120226#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 120208#L509-27 assume 1 == ~t7_pc~0; 120209#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 120191#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 120192#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 120174#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 120175#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 120067#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 118701#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 120022#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 120023#L867-3 assume !(1 == ~T3_E~0); 120014#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 120015#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 120006#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 118689#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 119997#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 119998#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 119988#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 119989#L907-3 assume !(1 == ~E_3~0); 119977#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 119978#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 119967#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 119968#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 119961#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 119962#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 139734#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 139732#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 119853#L1197 assume !(0 == start_simulation_~tmp~3#1); 119849#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 119846#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 119833#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 119829#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 119824#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 119817#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 119813#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 118187#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 118184#L1178-2 [2023-11-19 07:54:40,954 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:40,955 INFO L85 PathProgramCache]: Analyzing trace with hash -2127260292, now seen corresponding path program 1 times [2023-11-19 07:54:40,955 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:40,955 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [913884660] [2023-11-19 07:54:40,955 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:40,956 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:40,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:41,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:41,041 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:41,041 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [913884660] [2023-11-19 07:54:41,041 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [913884660] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:41,041 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:41,042 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:41,042 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1176898463] [2023-11-19 07:54:41,042 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:41,043 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:54:41,044 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:41,044 INFO L85 PathProgramCache]: Analyzing trace with hash 492815446, now seen corresponding path program 1 times [2023-11-19 07:54:41,044 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:41,044 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2106336917] [2023-11-19 07:54:41,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:41,045 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:41,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:41,103 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:41,104 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:41,104 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2106336917] [2023-11-19 07:54:41,104 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2106336917] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:41,104 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:41,104 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:41,105 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [199238072] [2023-11-19 07:54:41,105 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:41,106 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:54:41,106 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:54:41,107 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:54:41,107 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:54:41,107 INFO L87 Difference]: Start difference. First operand 36402 states and 52189 transitions. cyclomatic complexity: 15819 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:42,067 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:54:42,071 INFO L93 Difference]: Finished difference Result 100655 states and 143184 transitions. [2023-11-19 07:54:42,071 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100655 states and 143184 transitions. [2023-11-19 07:54:42,742 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 97825 [2023-11-19 07:54:43,194 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100655 states to 100655 states and 143184 transitions. [2023-11-19 07:54:43,195 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 100655 [2023-11-19 07:54:43,261 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 100655 [2023-11-19 07:54:43,262 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100655 states and 143184 transitions. [2023-11-19 07:54:43,521 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:54:43,535 INFO L218 hiAutomatonCegarLoop]: Abstraction has 100655 states and 143184 transitions. [2023-11-19 07:54:43,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100655 states and 143184 transitions. [2023-11-19 07:54:45,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100655 to 97367. [2023-11-19 07:54:45,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97367 states, 97367 states have (on average 1.4270132591124303) internal successors, (138944), 97366 states have internal predecessors, (138944), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:45,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97367 states to 97367 states and 138944 transitions. [2023-11-19 07:54:45,618 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97367 states and 138944 transitions. [2023-11-19 07:54:45,618 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:54:45,619 INFO L428 stractBuchiCegarLoop]: Abstraction has 97367 states and 138944 transitions. [2023-11-19 07:54:45,619 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-19 07:54:45,619 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97367 states and 138944 transitions. [2023-11-19 07:54:45,931 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 96745 [2023-11-19 07:54:45,931 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:54:45,931 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:54:45,933 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:45,934 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:45,934 INFO L748 eck$LassoCheckResult]: Stem: 248442#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 248443#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 249102#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 249103#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 249075#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 249076#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 248699#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 248514#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 248515#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 248496#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 248497#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 249072#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 248835#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 248836#L769 assume !(0 == ~M_E~0); 248858#L769-2 assume !(0 == ~T1_E~0); 248859#L774-1 assume !(0 == ~T2_E~0); 248891#L779-1 assume !(0 == ~T3_E~0); 249055#L784-1 assume !(0 == ~T4_E~0); 248833#L789-1 assume !(0 == ~T5_E~0); 248834#L794-1 assume !(0 == ~T6_E~0); 248964#L799-1 assume !(0 == ~T7_E~0); 248838#L804-1 assume !(0 == ~E_M~0); 248839#L809-1 assume !(0 == ~E_1~0); 248883#L814-1 assume !(0 == ~E_2~0); 248236#L819-1 assume !(0 == ~E_3~0); 248237#L824-1 assume !(0 == ~E_4~0); 248588#L829-1 assume !(0 == ~E_5~0); 249165#L834-1 assume !(0 == ~E_6~0); 248365#L839-1 assume !(0 == ~E_7~0); 248366#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 248784#L376 assume !(1 == ~m_pc~0); 248780#L376-2 is_master_triggered_~__retres1~0#1 := 0; 248781#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 249032#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 248310#L955 assume !(0 != activate_threads_~tmp~1#1); 248311#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 248692#L395 assume !(1 == ~t1_pc~0); 248860#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 249033#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 248265#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 248266#L963 assume !(0 != activate_threads_~tmp___0~0#1); 248788#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 248789#L414 assume !(1 == ~t2_pc~0); 248368#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 248369#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 248596#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 248597#L971 assume !(0 != activate_threads_~tmp___1~0#1); 249081#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 248696#L433 assume !(1 == ~t3_pc~0); 248483#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 248484#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 248234#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 248235#L979 assume !(0 != activate_threads_~tmp___2~0#1); 248334#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 248335#L452 assume !(1 == ~t4_pc~0); 248492#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 248493#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 248328#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 248329#L987 assume !(0 != activate_threads_~tmp___3~0#1); 248524#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 248525#L471 assume !(1 == ~t5_pc~0); 248946#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 248507#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 248508#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 249036#L995 assume !(0 != activate_threads_~tmp___4~0#1); 249149#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 249150#L490 assume !(1 == ~t6_pc~0); 248786#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 248787#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 248582#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 248583#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 248707#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 248672#L509 assume !(1 == ~t7_pc~0); 248673#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 248464#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 248465#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 248531#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 248532#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 249089#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 249090#L857-2 assume !(1 == ~T1_E~0); 299281#L862-1 assume !(1 == ~T2_E~0); 248605#L867-1 assume !(1 == ~T3_E~0); 248606#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 248697#L877-1 assume !(1 == ~T5_E~0); 248914#L882-1 assume !(1 == ~T6_E~0); 298208#L887-1 assume !(1 == ~T7_E~0); 298206#L892-1 assume !(1 == ~E_M~0); 298204#L897-1 assume !(1 == ~E_1~0); 298201#L902-1 assume !(1 == ~E_2~0); 298199#L907-1 assume !(1 == ~E_3~0); 298190#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 298188#L917-1 assume !(1 == ~E_5~0); 298186#L922-1 assume !(1 == ~E_6~0); 298182#L927-1 assume !(1 == ~E_7~0); 298178#L932-1 assume { :end_inline_reset_delta_events } true; 298176#L1178-2 [2023-11-19 07:54:45,935 INFO L750 eck$LassoCheckResult]: Loop: 298176#L1178-2 assume !false; 298033#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 298031#L744-1 assume !false; 298028#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 298026#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 298017#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 298015#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 298012#L641 assume !(0 != eval_~tmp~0#1); 298013#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 299901#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 299899#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 299897#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 299895#L774-3 assume !(0 == ~T2_E~0); 299893#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 299891#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 299889#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 299887#L794-3 assume !(0 == ~T6_E~0); 299885#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 299883#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 299881#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 299879#L814-3 assume !(0 == ~E_2~0); 299877#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 299875#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 299873#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 299871#L834-3 assume !(0 == ~E_6~0); 299869#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 299867#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 299865#L376-27 assume !(1 == ~m_pc~0); 299863#L376-29 is_master_triggered_~__retres1~0#1 := 0; 299861#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 299859#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 299857#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 299855#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 299853#L395-27 assume !(1 == ~t1_pc~0); 299851#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 299849#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 299847#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 299845#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 299843#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 299841#L414-27 assume 1 == ~t2_pc~0; 299837#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 299835#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 299833#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 299831#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 299829#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 299827#L433-27 assume !(1 == ~t3_pc~0); 299825#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 299823#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 299821#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 299819#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 299817#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 299815#L452-27 assume !(1 == ~t4_pc~0); 299812#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 299809#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 299807#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 299805#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 299803#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 299801#L471-27 assume !(1 == ~t5_pc~0); 299799#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 299797#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 299795#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 299793#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 299791#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 299789#L490-27 assume !(1 == ~t6_pc~0); 299787#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 299785#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 299783#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 299781#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 299779#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 299777#L509-27 assume 1 == ~t7_pc~0; 299773#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 299771#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 299769#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 299767#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 299765#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 299764#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 293837#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 299760#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 299758#L867-3 assume !(1 == ~T3_E~0); 299756#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 299754#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 299752#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 293821#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 299750#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 299748#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 299746#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 299744#L907-3 assume !(1 == ~E_3~0); 299742#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 299740#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 299739#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 299736#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 299275#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 298216#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 298207#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 298205#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 298203#L1197 assume !(0 == start_simulation_~tmp~3#1); 298200#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 298198#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 298189#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 298187#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 298183#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 298181#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 298180#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 298179#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 298176#L1178-2 [2023-11-19 07:54:45,935 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:45,935 INFO L85 PathProgramCache]: Analyzing trace with hash 1196032317, now seen corresponding path program 1 times [2023-11-19 07:54:45,936 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:45,936 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [417507827] [2023-11-19 07:54:45,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:45,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:45,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:46,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:46,017 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:46,018 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [417507827] [2023-11-19 07:54:46,018 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [417507827] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:46,019 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:46,019 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:54:46,019 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [310334251] [2023-11-19 07:54:46,019 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:46,022 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:54:46,023 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:46,023 INFO L85 PathProgramCache]: Analyzing trace with hash -266137768, now seen corresponding path program 1 times [2023-11-19 07:54:46,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:46,023 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1305930040] [2023-11-19 07:54:46,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:46,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:46,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:46,078 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:46,078 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:46,078 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1305930040] [2023-11-19 07:54:46,078 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1305930040] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:46,079 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:46,079 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:46,079 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [758981255] [2023-11-19 07:54:46,079 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:46,080 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:54:46,080 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:54:46,081 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 07:54:46,081 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 07:54:46,081 INFO L87 Difference]: Start difference. First operand 97367 states and 138944 transitions. cyclomatic complexity: 41641 Second operand has 5 states, 5 states have (on average 19.0) internal successors, (95), 5 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:47,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:54:47,405 INFO L93 Difference]: Finished difference Result 192154 states and 271524 transitions. [2023-11-19 07:54:47,405 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 192154 states and 271524 transitions. [2023-11-19 07:54:48,506 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 190986 [2023-11-19 07:54:49,386 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 192154 states to 192154 states and 271524 transitions. [2023-11-19 07:54:49,386 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 192154 [2023-11-19 07:54:49,489 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 192154 [2023-11-19 07:54:49,489 INFO L73 IsDeterministic]: Start isDeterministic. Operand 192154 states and 271524 transitions. [2023-11-19 07:54:49,610 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:54:49,610 INFO L218 hiAutomatonCegarLoop]: Abstraction has 192154 states and 271524 transitions. [2023-11-19 07:54:49,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 192154 states and 271524 transitions. [2023-11-19 07:54:51,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 192154 to 101126. [2023-11-19 07:54:51,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 101126 states, 101126 states have (on average 1.411140557324526) internal successors, (142703), 101125 states have internal predecessors, (142703), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:51,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101126 states to 101126 states and 142703 transitions. [2023-11-19 07:54:51,527 INFO L240 hiAutomatonCegarLoop]: Abstraction has 101126 states and 142703 transitions. [2023-11-19 07:54:51,528 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-19 07:54:51,528 INFO L428 stractBuchiCegarLoop]: Abstraction has 101126 states and 142703 transitions. [2023-11-19 07:54:51,528 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-19 07:54:51,529 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 101126 states and 142703 transitions. [2023-11-19 07:54:52,277 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 100501 [2023-11-19 07:54:52,278 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:54:52,278 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:54:52,280 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:52,280 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:52,280 INFO L748 eck$LassoCheckResult]: Stem: 537980#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 537981#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 538638#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 538639#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 538608#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 538609#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 538236#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 538052#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 538053#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 538033#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 538034#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 538607#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 538375#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 538376#L769 assume !(0 == ~M_E~0); 538395#L769-2 assume !(0 == ~T1_E~0); 538396#L774-1 assume !(0 == ~T2_E~0); 538432#L779-1 assume !(0 == ~T3_E~0); 538588#L784-1 assume !(0 == ~T4_E~0); 538373#L789-1 assume !(0 == ~T5_E~0); 538374#L794-1 assume !(0 == ~T6_E~0); 538498#L799-1 assume !(0 == ~T7_E~0); 538378#L804-1 assume !(0 == ~E_M~0); 538379#L809-1 assume !(0 == ~E_1~0); 538423#L814-1 assume !(0 == ~E_2~0); 537770#L819-1 assume !(0 == ~E_3~0); 537771#L824-1 assume !(0 == ~E_4~0); 538124#L829-1 assume !(0 == ~E_5~0); 538695#L834-1 assume !(0 == ~E_6~0); 537900#L839-1 assume !(0 == ~E_7~0); 537901#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 538323#L376 assume !(1 == ~m_pc~0); 538319#L376-2 is_master_triggered_~__retres1~0#1 := 0; 538320#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 538567#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 537843#L955 assume !(0 != activate_threads_~tmp~1#1); 537844#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 538228#L395 assume !(1 == ~t1_pc~0); 538397#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 538568#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 537799#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 537800#L963 assume !(0 != activate_threads_~tmp___0~0#1); 538328#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 538329#L414 assume !(1 == ~t2_pc~0); 537903#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 537904#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 538131#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 538132#L971 assume !(0 != activate_threads_~tmp___1~0#1); 538614#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 538232#L433 assume !(1 == ~t3_pc~0); 538023#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 538024#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 537768#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 537769#L979 assume !(0 != activate_threads_~tmp___2~0#1); 537868#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 537869#L452 assume !(1 == ~t4_pc~0); 538029#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 538030#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 537862#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 537863#L987 assume !(0 != activate_threads_~tmp___3~0#1); 538062#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 538063#L471 assume !(1 == ~t5_pc~0); 538480#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 538044#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 538045#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 538572#L995 assume !(0 != activate_threads_~tmp___4~0#1); 538682#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 538683#L490 assume !(1 == ~t6_pc~0); 538326#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 538327#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 538118#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 538119#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 538245#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 538207#L509 assume !(1 == ~t7_pc~0); 538208#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 538005#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 538006#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 538069#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 538070#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 538622#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 537850#L857-2 assume !(1 == ~T1_E~0); 537851#L862-1 assume !(1 == ~T2_E~0); 538141#L867-1 assume !(1 == ~T3_E~0); 538142#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 573074#L877-1 assume !(1 == ~T5_E~0); 538647#L882-1 assume !(1 == ~T6_E~0); 538648#L887-1 assume !(1 == ~T7_E~0); 538525#L892-1 assume !(1 == ~E_M~0); 538526#L897-1 assume !(1 == ~E_1~0); 538157#L902-1 assume !(1 == ~E_2~0); 538158#L907-1 assume !(1 == ~E_3~0); 538469#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 538460#L917-1 assume !(1 == ~E_5~0); 538461#L922-1 assume !(1 == ~E_6~0); 538698#L927-1 assume !(1 == ~E_7~0); 538448#L932-1 assume { :end_inline_reset_delta_events } true; 538449#L1178-2 [2023-11-19 07:54:52,281 INFO L750 eck$LassoCheckResult]: Loop: 538449#L1178-2 assume !false; 633243#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 633242#L744-1 assume !false; 633241#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 633238#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 633228#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 633224#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 633217#L641 assume !(0 != eval_~tmp~0#1); 633218#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 634505#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 634503#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 634501#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 634499#L774-3 assume !(0 == ~T2_E~0); 634497#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 634495#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 634493#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 634491#L794-3 assume !(0 == ~T6_E~0); 634489#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 634487#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 634486#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 634470#L814-3 assume !(0 == ~E_2~0); 634466#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 634462#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 634458#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 634454#L834-3 assume !(0 == ~E_6~0); 634450#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 634446#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 634441#L376-27 assume !(1 == ~m_pc~0); 634435#L376-29 is_master_triggered_~__retres1~0#1 := 0; 634431#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 634430#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 634420#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 634416#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 634411#L395-27 assume !(1 == ~t1_pc~0); 634402#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 634391#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 634382#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 634374#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 634365#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 634356#L414-27 assume 1 == ~t2_pc~0; 634349#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 634344#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 634341#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 634338#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 634335#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 634333#L433-27 assume !(1 == ~t3_pc~0); 634329#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 634326#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 634322#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 634318#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 634314#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 634309#L452-27 assume !(1 == ~t4_pc~0); 634305#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 634300#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 634296#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 634292#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 634288#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 634283#L471-27 assume !(1 == ~t5_pc~0); 634279#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 634273#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 634269#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 634265#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 634261#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 634257#L490-27 assume !(1 == ~t6_pc~0); 634253#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 634250#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 634247#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 634235#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 634233#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 634232#L509-27 assume !(1 == ~t7_pc~0); 634231#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 634229#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 634227#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 634225#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 633371#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 633369#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 573110#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 633366#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 633364#L867-3 assume !(1 == ~T3_E~0); 633361#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 633357#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 633354#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 599870#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 633349#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 633346#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 633342#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 633337#L907-3 assume !(1 == ~E_3~0); 633334#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 633330#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 633326#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 584294#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 633319#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 633316#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 633307#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 633305#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 633304#L1197 assume !(0 == start_simulation_~tmp~3#1); 633302#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 633301#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 633293#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 633292#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 633291#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 633290#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 633289#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 633288#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 538449#L1178-2 [2023-11-19 07:54:52,281 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:52,282 INFO L85 PathProgramCache]: Analyzing trace with hash -492911425, now seen corresponding path program 1 times [2023-11-19 07:54:52,282 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:52,282 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [185715513] [2023-11-19 07:54:52,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:52,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:52,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:52,339 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:52,339 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:52,340 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [185715513] [2023-11-19 07:54:52,340 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [185715513] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:52,340 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:52,340 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:54:52,340 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [392803720] [2023-11-19 07:54:52,340 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:52,341 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:54:52,341 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:52,341 INFO L85 PathProgramCache]: Analyzing trace with hash 1486911195, now seen corresponding path program 1 times [2023-11-19 07:54:52,341 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:52,342 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1705119954] [2023-11-19 07:54:52,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:52,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:52,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:52,414 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:52,414 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:52,414 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1705119954] [2023-11-19 07:54:52,415 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1705119954] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:52,415 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:52,415 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:52,415 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [172825776] [2023-11-19 07:54:52,415 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:52,416 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:54:52,416 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:54:52,416 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:54:52,416 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:54:52,417 INFO L87 Difference]: Start difference. First operand 101126 states and 142703 transitions. cyclomatic complexity: 41641 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:52,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:54:52,864 INFO L93 Difference]: Finished difference Result 127016 states and 179333 transitions. [2023-11-19 07:54:52,864 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 127016 states and 179333 transitions. [2023-11-19 07:54:53,869 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 126281 [2023-11-19 07:54:54,112 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 127016 states to 127016 states and 179333 transitions. [2023-11-19 07:54:54,112 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 127016 [2023-11-19 07:54:54,170 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 127016 [2023-11-19 07:54:54,170 INFO L73 IsDeterministic]: Start isDeterministic. Operand 127016 states and 179333 transitions. [2023-11-19 07:54:54,261 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:54:54,261 INFO L218 hiAutomatonCegarLoop]: Abstraction has 127016 states and 179333 transitions. [2023-11-19 07:54:54,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127016 states and 179333 transitions. [2023-11-19 07:54:55,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127016 to 55030. [2023-11-19 07:54:55,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55030 states, 55030 states have (on average 1.4177539523896057) internal successors, (78019), 55029 states have internal predecessors, (78019), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:55,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55030 states to 55030 states and 78019 transitions. [2023-11-19 07:54:55,547 INFO L240 hiAutomatonCegarLoop]: Abstraction has 55030 states and 78019 transitions. [2023-11-19 07:54:55,547 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:54:55,549 INFO L428 stractBuchiCegarLoop]: Abstraction has 55030 states and 78019 transitions. [2023-11-19 07:54:55,551 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-19 07:54:55,551 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55030 states and 78019 transitions. [2023-11-19 07:54:55,683 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 54681 [2023-11-19 07:54:55,683 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:54:55,683 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:54:55,684 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:55,685 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:55,685 INFO L748 eck$LassoCheckResult]: Stem: 766129#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 766130#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 766788#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 766789#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 766758#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 766759#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 766375#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 766201#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 766202#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 766183#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 766184#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 766755#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 766523#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 766524#L769 assume !(0 == ~M_E~0); 766547#L769-2 assume !(0 == ~T1_E~0); 766548#L774-1 assume !(0 == ~T2_E~0); 766581#L779-1 assume !(0 == ~T3_E~0); 766739#L784-1 assume !(0 == ~T4_E~0); 766521#L789-1 assume !(0 == ~T5_E~0); 766522#L794-1 assume !(0 == ~T6_E~0); 766653#L799-1 assume !(0 == ~T7_E~0); 766526#L804-1 assume !(0 == ~E_M~0); 766527#L809-1 assume !(0 == ~E_1~0); 766574#L814-1 assume !(0 == ~E_2~0); 765919#L819-1 assume !(0 == ~E_3~0); 765920#L824-1 assume !(0 == ~E_4~0); 766271#L829-1 assume !(0 == ~E_5~0); 766841#L834-1 assume !(0 == ~E_6~0); 766051#L839-1 assume !(0 == ~E_7~0); 766052#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 766470#L376 assume !(1 == ~m_pc~0); 766466#L376-2 is_master_triggered_~__retres1~0#1 := 0; 766467#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 766720#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 765993#L955 assume !(0 != activate_threads_~tmp~1#1); 765994#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 766368#L395 assume !(1 == ~t1_pc~0); 766549#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 766721#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 765948#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 765949#L963 assume !(0 != activate_threads_~tmp___0~0#1); 766475#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 766476#L414 assume !(1 == ~t2_pc~0); 766054#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 766055#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 766277#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 766278#L971 assume !(0 != activate_threads_~tmp___1~0#1); 766767#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 766372#L433 assume !(1 == ~t3_pc~0); 766170#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 766171#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 765917#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 765918#L979 assume !(0 != activate_threads_~tmp___2~0#1); 766018#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 766019#L452 assume !(1 == ~t4_pc~0); 766179#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 766180#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 766012#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 766013#L987 assume !(0 != activate_threads_~tmp___3~0#1); 766211#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 766212#L471 assume !(1 == ~t5_pc~0); 766634#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 766194#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 766195#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 766724#L995 assume !(0 != activate_threads_~tmp___4~0#1); 766826#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 766827#L490 assume !(1 == ~t6_pc~0); 766473#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 766474#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 766265#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 766266#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 766382#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 766350#L509 assume !(1 == ~t7_pc~0); 766351#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 766151#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 766152#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 766218#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 766219#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 766776#L857 assume !(1 == ~M_E~0); 766000#L857-2 assume !(1 == ~T1_E~0); 766001#L862-1 assume !(1 == ~T2_E~0); 766281#L867-1 assume !(1 == ~T3_E~0); 766286#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 766373#L877-1 assume !(1 == ~T5_E~0); 766603#L882-1 assume !(1 == ~T6_E~0); 766797#L887-1 assume !(1 == ~T7_E~0); 766676#L892-1 assume !(1 == ~E_M~0); 766677#L897-1 assume !(1 == ~E_1~0); 766302#L902-1 assume !(1 == ~E_2~0); 766303#L907-1 assume !(1 == ~E_3~0); 766624#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 766612#L917-1 assume !(1 == ~E_5~0); 766613#L922-1 assume !(1 == ~E_6~0); 766844#L927-1 assume !(1 == ~E_7~0); 766598#L932-1 assume { :end_inline_reset_delta_events } true; 766599#L1178-2 [2023-11-19 07:54:55,685 INFO L750 eck$LassoCheckResult]: Loop: 766599#L1178-2 assume !false; 797653#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 797649#L744-1 assume !false; 797644#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 797618#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 797606#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 797602#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 797597#L641 assume !(0 != eval_~tmp~0#1); 797593#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 797589#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 797585#L769-3 assume !(0 == ~M_E~0); 797580#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 797576#L774-3 assume !(0 == ~T2_E~0); 797571#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 797567#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 797562#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 797557#L794-3 assume !(0 == ~T6_E~0); 796813#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 796812#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 796811#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 796810#L814-3 assume !(0 == ~E_2~0); 796809#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 796808#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 796807#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 796806#L834-3 assume !(0 == ~E_6~0); 796805#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 796804#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 796802#L376-27 assume !(1 == ~m_pc~0); 796801#L376-29 is_master_triggered_~__retres1~0#1 := 0; 796800#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 796799#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 796798#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 796796#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 796794#L395-27 assume !(1 == ~t1_pc~0); 796792#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 796790#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 796788#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 796786#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 796784#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 796783#L414-27 assume 1 == ~t2_pc~0; 796781#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 796778#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 796776#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 796774#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 796772#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 796770#L433-27 assume !(1 == ~t3_pc~0); 796768#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 796766#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 796764#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 796762#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 796760#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 796758#L452-27 assume !(1 == ~t4_pc~0); 796756#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 796752#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 796750#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 796748#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 796746#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 796744#L471-27 assume !(1 == ~t5_pc~0); 796742#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 796740#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 796738#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 796736#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 796734#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 796732#L490-27 assume !(1 == ~t6_pc~0); 796730#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 796728#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 796726#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 796724#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 796722#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 796720#L509-27 assume !(1 == ~t7_pc~0); 796716#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 796713#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 796711#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 796709#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 796707#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 796704#L857-3 assume !(1 == ~M_E~0); 786350#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 796701#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 796700#L867-3 assume !(1 == ~T3_E~0); 796698#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 796696#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 796694#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 796692#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 796690#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 796688#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 796686#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 796684#L907-3 assume !(1 == ~E_3~0); 796682#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 796680#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 796678#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 796676#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 796674#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 796672#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 796663#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 796662#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 786477#L1197 assume !(0 == start_simulation_~tmp~3#1); 786478#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 797763#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 797753#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 797751#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 797749#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 797686#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 797677#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 797668#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 766599#L1178-2 [2023-11-19 07:54:55,685 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:55,686 INFO L85 PathProgramCache]: Analyzing trace with hash -2081259327, now seen corresponding path program 1 times [2023-11-19 07:54:55,686 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:55,686 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [202753302] [2023-11-19 07:54:55,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:55,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:55,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:55,753 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:55,754 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:55,754 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [202753302] [2023-11-19 07:54:55,754 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [202753302] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:55,754 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:55,754 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:55,754 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2025206245] [2023-11-19 07:54:55,755 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:55,755 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:54:55,755 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:55,755 INFO L85 PathProgramCache]: Analyzing trace with hash 1254139675, now seen corresponding path program 1 times [2023-11-19 07:54:55,756 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:55,756 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [524146219] [2023-11-19 07:54:55,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:55,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:55,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:55,798 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:55,798 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:55,798 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [524146219] [2023-11-19 07:54:55,798 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [524146219] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:55,799 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:55,799 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:55,799 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1899434047] [2023-11-19 07:54:55,799 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:55,799 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:54:55,800 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:54:55,800 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:54:55,800 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:54:55,800 INFO L87 Difference]: Start difference. First operand 55030 states and 78019 transitions. cyclomatic complexity: 23005 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:56,088 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:54:56,088 INFO L93 Difference]: Finished difference Result 88015 states and 124236 transitions. [2023-11-19 07:54:56,088 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88015 states and 124236 transitions. [2023-11-19 07:54:56,381 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 87459 [2023-11-19 07:54:57,157 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88015 states to 88015 states and 124236 transitions. [2023-11-19 07:54:57,157 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 88015 [2023-11-19 07:54:57,191 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 88015 [2023-11-19 07:54:57,191 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88015 states and 124236 transitions. [2023-11-19 07:54:57,228 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:54:57,228 INFO L218 hiAutomatonCegarLoop]: Abstraction has 88015 states and 124236 transitions. [2023-11-19 07:54:57,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88015 states and 124236 transitions. [2023-11-19 07:54:57,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88015 to 62963. [2023-11-19 07:54:57,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62963 states, 62963 states have (on average 1.4154344615091403) internal successors, (89120), 62962 states have internal predecessors, (89120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:57,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62963 states to 62963 states and 89120 transitions. [2023-11-19 07:54:57,969 INFO L240 hiAutomatonCegarLoop]: Abstraction has 62963 states and 89120 transitions. [2023-11-19 07:54:57,970 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:54:57,971 INFO L428 stractBuchiCegarLoop]: Abstraction has 62963 states and 89120 transitions. [2023-11-19 07:54:57,971 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-19 07:54:57,971 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62963 states and 89120 transitions. [2023-11-19 07:54:58,153 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 62543 [2023-11-19 07:54:58,153 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:54:58,153 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:54:58,155 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:58,155 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:54:58,155 INFO L748 eck$LassoCheckResult]: Stem: 909183#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 909184#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 909850#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 909851#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 909813#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 909814#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 909439#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 909254#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 909255#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 909236#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 909237#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 909812#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 909579#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 909580#L769 assume !(0 == ~M_E~0); 909600#L769-2 assume !(0 == ~T1_E~0); 909601#L774-1 assume !(0 == ~T2_E~0); 909638#L779-1 assume !(0 == ~T3_E~0); 909793#L784-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 909577#L789-1 assume !(0 == ~T5_E~0); 909578#L794-1 assume !(0 == ~T6_E~0); 909701#L799-1 assume !(0 == ~T7_E~0); 909582#L804-1 assume !(0 == ~E_M~0); 909583#L809-1 assume !(0 == ~E_1~0); 909823#L814-1 assume !(0 == ~E_2~0); 909824#L819-1 assume !(0 == ~E_3~0); 909324#L824-1 assume !(0 == ~E_4~0); 909325#L829-1 assume !(0 == ~E_5~0); 909898#L834-1 assume !(0 == ~E_6~0); 909899#L839-1 assume !(0 == ~E_7~0); 910012#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 909524#L376 assume !(1 == ~m_pc~0); 909525#L376-2 is_master_triggered_~__retres1~0#1 := 0; 909959#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 909960#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 909049#L955 assume !(0 != activate_threads_~tmp~1#1); 909050#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 909429#L395 assume !(1 == ~t1_pc~0); 909770#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 909771#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 909005#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 909006#L963 assume !(0 != activate_threads_~tmp___0~0#1); 909530#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 909531#L414 assume !(1 == ~t2_pc~0); 909109#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 909110#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 909331#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 909332#L971 assume !(0 != activate_threads_~tmp___1~0#1); 909905#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 909434#L433 assume !(1 == ~t3_pc~0); 909435#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 909915#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 909916#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 909752#L979 assume !(0 != activate_threads_~tmp___2~0#1); 909753#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 909968#L452 assume !(1 == ~t4_pc~0); 909969#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 909562#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 909563#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 909909#L987 assume !(0 != activate_threads_~tmp___3~0#1); 909910#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 910009#L471 assume !(1 == ~t5_pc~0); 909926#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 909927#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 909775#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 909776#L995 assume !(0 != activate_threads_~tmp___4~0#1); 909886#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 909887#L490 assume !(1 == ~t6_pc~0); 909528#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 909529#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 909318#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 909319#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 909447#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 909411#L509 assume !(1 == ~t7_pc~0); 909412#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 910006#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 910002#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 910003#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 909913#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 909914#L857 assume !(1 == ~M_E~0); 909056#L857-2 assume !(1 == ~T1_E~0); 909057#L862-1 assume !(1 == ~T2_E~0); 909341#L867-1 assume !(1 == ~T3_E~0); 909342#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 909437#L877-1 assume !(1 == ~T5_E~0); 909658#L882-1 assume !(1 == ~T6_E~0); 909856#L887-1 assume !(1 == ~T7_E~0); 909727#L892-1 assume !(1 == ~E_M~0); 909728#L897-1 assume !(1 == ~E_1~0); 909358#L902-1 assume !(1 == ~E_2~0); 909359#L907-1 assume !(1 == ~E_3~0); 909673#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 909664#L917-1 assume !(1 == ~E_5~0); 909665#L922-1 assume !(1 == ~E_6~0); 909902#L927-1 assume !(1 == ~E_7~0); 909653#L932-1 assume { :end_inline_reset_delta_events } true; 909654#L1178-2 [2023-11-19 07:54:58,156 INFO L750 eck$LassoCheckResult]: Loop: 909654#L1178-2 assume !false; 934261#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 934256#L744-1 assume !false; 934251#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 933176#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 933167#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 933165#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 933162#L641 assume !(0 != eval_~tmp~0#1); 933160#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 933158#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 933155#L769-3 assume !(0 == ~M_E~0); 933153#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 933151#L774-3 assume !(0 == ~T2_E~0); 933150#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 933148#L784-3 assume !(0 == ~T4_E~0); 933149#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 934010#L794-3 assume !(0 == ~T6_E~0); 934008#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 934006#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 934004#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 934000#L814-3 assume !(0 == ~E_2~0); 933998#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 933996#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 933994#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 933991#L834-3 assume !(0 == ~E_6~0); 933989#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 933988#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 933984#L376-27 assume !(1 == ~m_pc~0); 933982#L376-29 is_master_triggered_~__retres1~0#1 := 0; 933980#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 933979#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 933976#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 933975#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 933974#L395-27 assume !(1 == ~t1_pc~0); 933973#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 933971#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 933970#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 933969#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 933968#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 933967#L414-27 assume !(1 == ~t2_pc~0); 933964#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 933961#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 933959#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 933957#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 933955#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 933951#L433-27 assume !(1 == ~t3_pc~0); 933949#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 933947#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 933945#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 933942#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 933940#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 933939#L452-27 assume !(1 == ~t4_pc~0); 933938#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 933933#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 933931#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 933929#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 933928#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 933925#L471-27 assume !(1 == ~t5_pc~0); 933924#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 933922#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 933921#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 933919#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 933918#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 933915#L490-27 assume !(1 == ~t6_pc~0); 933911#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 933907#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 933903#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 933823#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 933812#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 933803#L509-27 assume !(1 == ~t7_pc~0); 933794#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 933779#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 933767#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 933760#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 933544#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 933535#L857-3 assume !(1 == ~M_E~0); 932511#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 933509#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 933497#L867-3 assume !(1 == ~T3_E~0); 933078#L872-3 assume !(1 == ~T4_E~0); 933074#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 933072#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 933070#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 933069#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 932960#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 932958#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 932956#L907-3 assume !(1 == ~E_3~0); 932954#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 932952#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 932950#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 932948#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 932946#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 932884#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 932870#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 932866#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 932475#L1197 assume !(0 == start_simulation_~tmp~3#1); 932476#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 934473#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 934460#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 934453#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 934447#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 934438#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 934431#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 934425#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 909654#L1178-2 [2023-11-19 07:54:58,157 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:58,157 INFO L85 PathProgramCache]: Analyzing trace with hash 1374674307, now seen corresponding path program 1 times [2023-11-19 07:54:58,158 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:58,158 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1521088101] [2023-11-19 07:54:58,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:58,158 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:58,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:58,231 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:58,231 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:58,231 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1521088101] [2023-11-19 07:54:58,232 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1521088101] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:58,232 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:58,232 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:58,232 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2114746504] [2023-11-19 07:54:58,232 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:58,233 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:54:58,233 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:54:58,233 INFO L85 PathProgramCache]: Analyzing trace with hash -645572964, now seen corresponding path program 1 times [2023-11-19 07:54:58,234 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:54:58,234 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [534121608] [2023-11-19 07:54:58,234 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:54:58,234 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:54:58,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:54:58,284 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:54:58,285 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:54:58,285 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [534121608] [2023-11-19 07:54:58,285 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [534121608] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:54:58,285 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:54:58,285 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:54:58,285 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1773178216] [2023-11-19 07:54:58,286 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:54:58,286 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:54:58,286 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:54:58,287 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:54:58,287 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:54:58,287 INFO L87 Difference]: Start difference. First operand 62963 states and 89120 transitions. cyclomatic complexity: 26173 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:54:59,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:54:59,074 INFO L93 Difference]: Finished difference Result 80070 states and 112732 transitions. [2023-11-19 07:54:59,074 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 80070 states and 112732 transitions. [2023-11-19 07:54:59,399 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 79597 [2023-11-19 07:54:59,572 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 80070 states to 80070 states and 112732 transitions. [2023-11-19 07:54:59,572 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 80070 [2023-11-19 07:54:59,606 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 80070 [2023-11-19 07:54:59,606 INFO L73 IsDeterministic]: Start isDeterministic. Operand 80070 states and 112732 transitions. [2023-11-19 07:54:59,635 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:54:59,635 INFO L218 hiAutomatonCegarLoop]: Abstraction has 80070 states and 112732 transitions. [2023-11-19 07:54:59,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80070 states and 112732 transitions. [2023-11-19 07:55:00,093 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80070 to 55030. [2023-11-19 07:55:00,126 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55030 states, 55030 states have (on average 1.4118299109576595) internal successors, (77693), 55029 states have internal predecessors, (77693), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:55:00,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55030 states to 55030 states and 77693 transitions. [2023-11-19 07:55:00,809 INFO L240 hiAutomatonCegarLoop]: Abstraction has 55030 states and 77693 transitions. [2023-11-19 07:55:00,810 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:55:00,821 INFO L428 stractBuchiCegarLoop]: Abstraction has 55030 states and 77693 transitions. [2023-11-19 07:55:00,821 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-19 07:55:00,821 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55030 states and 77693 transitions. [2023-11-19 07:55:00,972 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 54681 [2023-11-19 07:55:00,972 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:55:00,972 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:55:00,974 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:55:00,974 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:55:00,975 INFO L748 eck$LassoCheckResult]: Stem: 1052224#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1052225#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1052854#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1052855#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1052824#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1052825#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1052470#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1052295#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1052296#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1052276#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1052277#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1052822#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1052599#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1052600#L769 assume !(0 == ~M_E~0); 1052620#L769-2 assume !(0 == ~T1_E~0); 1052621#L774-1 assume !(0 == ~T2_E~0); 1052654#L779-1 assume !(0 == ~T3_E~0); 1052806#L784-1 assume !(0 == ~T4_E~0); 1052597#L789-1 assume !(0 == ~T5_E~0); 1052598#L794-1 assume !(0 == ~T6_E~0); 1052722#L799-1 assume !(0 == ~T7_E~0); 1052602#L804-1 assume !(0 == ~E_M~0); 1052603#L809-1 assume !(0 == ~E_1~0); 1052647#L814-1 assume !(0 == ~E_2~0); 1052019#L819-1 assume !(0 == ~E_3~0); 1052020#L824-1 assume !(0 == ~E_4~0); 1052367#L829-1 assume !(0 == ~E_5~0); 1052910#L834-1 assume !(0 == ~E_6~0); 1052147#L839-1 assume !(0 == ~E_7~0); 1052148#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1052548#L376 assume !(1 == ~m_pc~0); 1052544#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1052545#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1052783#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1052092#L955 assume !(0 != activate_threads_~tmp~1#1); 1052093#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1052463#L395 assume !(1 == ~t1_pc~0); 1052622#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1052784#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1052046#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1052047#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1052553#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1052554#L414 assume !(1 == ~t2_pc~0); 1052150#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1052151#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1052374#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1052375#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1052831#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1052467#L433 assume !(1 == ~t3_pc~0); 1052264#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1052265#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1052015#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1052016#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1052116#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1052117#L452 assume !(1 == ~t4_pc~0); 1052272#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1052273#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1052110#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1052111#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1052305#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1052306#L471 assume !(1 == ~t5_pc~0); 1052704#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1052288#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1052289#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1052787#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1052897#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1052898#L490 assume !(1 == ~t6_pc~0); 1052551#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1052552#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1052361#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1052362#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1052477#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1052445#L509 assume !(1 == ~t7_pc~0); 1052446#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1052245#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1052246#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1052312#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1052313#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1052839#L857 assume !(1 == ~M_E~0); 1052099#L857-2 assume !(1 == ~T1_E~0); 1052100#L862-1 assume !(1 == ~T2_E~0); 1052378#L867-1 assume !(1 == ~T3_E~0); 1052383#L872-1 assume !(1 == ~T4_E~0); 1052468#L877-1 assume !(1 == ~T5_E~0); 1052673#L882-1 assume !(1 == ~T6_E~0); 1052863#L887-1 assume !(1 == ~T7_E~0); 1052744#L892-1 assume !(1 == ~E_M~0); 1052745#L897-1 assume !(1 == ~E_1~0); 1052399#L902-1 assume !(1 == ~E_2~0); 1052400#L907-1 assume !(1 == ~E_3~0); 1052691#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1052680#L917-1 assume !(1 == ~E_5~0); 1052681#L922-1 assume !(1 == ~E_6~0); 1052913#L927-1 assume !(1 == ~E_7~0); 1052668#L932-1 assume { :end_inline_reset_delta_events } true; 1052669#L1178-2 [2023-11-19 07:55:00,975 INFO L750 eck$LassoCheckResult]: Loop: 1052669#L1178-2 assume !false; 1066313#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1066310#L744-1 assume !false; 1066305#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1066302#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1066292#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1066289#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1066285#L641 assume !(0 != eval_~tmp~0#1); 1066281#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1066277#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1066273#L769-3 assume !(0 == ~M_E~0); 1066268#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1066263#L774-3 assume !(0 == ~T2_E~0); 1066258#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1066253#L784-3 assume !(0 == ~T4_E~0); 1066247#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1066240#L794-3 assume !(0 == ~T6_E~0); 1066235#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1066229#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1066224#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1066219#L814-3 assume !(0 == ~E_2~0); 1066214#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1066209#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1066204#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1066199#L834-3 assume !(0 == ~E_6~0); 1066194#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1066188#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1066180#L376-27 assume !(1 == ~m_pc~0); 1066173#L376-29 is_master_triggered_~__retres1~0#1 := 0; 1066167#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1066161#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1066156#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1066151#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1066145#L395-27 assume !(1 == ~t1_pc~0); 1066137#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1066129#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1066120#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1066112#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1066104#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1066096#L414-27 assume 1 == ~t2_pc~0; 1066089#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1066080#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1066073#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1066067#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1066061#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1066056#L433-27 assume !(1 == ~t3_pc~0); 1066041#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1066032#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1066030#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1066028#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1066025#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1066023#L452-27 assume 1 == ~t4_pc~0; 1066020#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1066018#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1066016#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1066014#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1066012#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1066010#L471-27 assume !(1 == ~t5_pc~0); 1066008#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1066006#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1066004#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1066002#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1066000#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1065998#L490-27 assume !(1 == ~t6_pc~0); 1065996#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1065994#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1065992#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1065990#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 1065988#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1065986#L509-27 assume 1 == ~t7_pc~0; 1065984#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1065985#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1095648#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1065974#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1065972#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1065970#L857-3 assume !(1 == ~M_E~0); 1065768#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1065965#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1065963#L867-3 assume !(1 == ~T3_E~0); 1065961#L872-3 assume !(1 == ~T4_E~0); 1065959#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1065957#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1065955#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1065952#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1065950#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1065948#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1065946#L907-3 assume !(1 == ~E_3~0); 1065944#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1065942#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1065941#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1065939#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1065937#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1065935#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1065926#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1065924#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1065898#L1197 assume !(0 == start_simulation_~tmp~3#1); 1065899#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1066369#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1066360#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1066358#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1066356#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1066342#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1066334#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1066326#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1052669#L1178-2 [2023-11-19 07:55:00,976 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:55:00,976 INFO L85 PathProgramCache]: Analyzing trace with hash 1626901955, now seen corresponding path program 1 times [2023-11-19 07:55:00,976 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:55:00,976 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [810556410] [2023-11-19 07:55:00,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:55:00,977 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:55:00,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:55:01,053 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:55:01,053 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:55:01,053 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [810556410] [2023-11-19 07:55:01,054 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [810556410] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:55:01,054 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:55:01,054 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:55:01,054 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2133878388] [2023-11-19 07:55:01,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:55:01,055 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:55:01,055 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:55:01,055 INFO L85 PathProgramCache]: Analyzing trace with hash 1792481047, now seen corresponding path program 1 times [2023-11-19 07:55:01,055 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:55:01,055 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1598354420] [2023-11-19 07:55:01,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:55:01,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:55:01,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:55:01,097 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:55:01,098 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:55:01,098 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1598354420] [2023-11-19 07:55:01,098 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1598354420] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:55:01,098 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:55:01,098 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:55:01,098 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [177111319] [2023-11-19 07:55:01,099 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:55:01,099 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:55:01,099 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:55:01,100 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:55:01,100 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:55:01,100 INFO L87 Difference]: Start difference. First operand 55030 states and 77693 transitions. cyclomatic complexity: 22679 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:55:01,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:55:01,465 INFO L93 Difference]: Finished difference Result 88048 states and 122833 transitions. [2023-11-19 07:55:01,466 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88048 states and 122833 transitions. [2023-11-19 07:55:01,760 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 87442 [2023-11-19 07:55:01,953 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88048 states to 88048 states and 122833 transitions. [2023-11-19 07:55:01,953 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 88048 [2023-11-19 07:55:01,996 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 88048 [2023-11-19 07:55:01,996 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88048 states and 122833 transitions. [2023-11-19 07:55:02,034 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:55:02,034 INFO L218 hiAutomatonCegarLoop]: Abstraction has 88048 states and 122833 transitions. [2023-11-19 07:55:02,083 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88048 states and 122833 transitions. [2023-11-19 07:55:03,252 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88048 to 62963. [2023-11-19 07:55:03,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62963 states, 62963 states have (on average 1.4000127058748788) internal successors, (88149), 62962 states have internal predecessors, (88149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:55:03,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62963 states to 62963 states and 88149 transitions. [2023-11-19 07:55:03,405 INFO L240 hiAutomatonCegarLoop]: Abstraction has 62963 states and 88149 transitions. [2023-11-19 07:55:03,405 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:55:03,406 INFO L428 stractBuchiCegarLoop]: Abstraction has 62963 states and 88149 transitions. [2023-11-19 07:55:03,406 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-19 07:55:03,406 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62963 states and 88149 transitions. [2023-11-19 07:55:03,574 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 62543 [2023-11-19 07:55:03,574 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:55:03,575 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:55:03,576 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:55:03,576 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:55:03,577 INFO L748 eck$LassoCheckResult]: Stem: 1195310#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1195311#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1195990#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1195991#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1195956#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1195957#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1195570#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1195382#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1195383#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1195363#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1195364#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1195955#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1195720#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1195721#L769 assume !(0 == ~M_E~0); 1195739#L769-2 assume !(0 == ~T1_E~0); 1195740#L774-1 assume !(0 == ~T2_E~0); 1195776#L779-1 assume !(0 == ~T3_E~0); 1195936#L784-1 assume !(0 == ~T4_E~0); 1195718#L789-1 assume !(0 == ~T5_E~0); 1195719#L794-1 assume !(0 == ~T6_E~0); 1195845#L799-1 assume !(0 == ~T7_E~0); 1195723#L804-1 assume !(0 == ~E_M~0); 1195724#L809-1 assume !(0 == ~E_1~0); 1195767#L814-1 assume !(0 == ~E_2~0); 1195107#L819-1 assume !(0 == ~E_3~0); 1195108#L824-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1195455#L829-1 assume !(0 == ~E_5~0); 1196037#L834-1 assume !(0 == ~E_6~0); 1196038#L839-1 assume !(0 == ~E_7~0); 1195851#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1195852#L376 assume !(1 == ~m_pc~0); 1195660#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1195661#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1195915#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1195916#L955 assume !(0 != activate_threads_~tmp~1#1); 1195560#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1195561#L395 assume !(1 == ~t1_pc~0); 1195918#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1195919#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1195135#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1195136#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1195671#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1195672#L414 assume !(1 == ~t2_pc~0); 1195237#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1195238#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1195463#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1195464#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1196043#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1196044#L433 assume !(1 == ~t3_pc~0); 1195350#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1195351#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1195103#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1195104#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1195203#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1195204#L452 assume !(1 == ~t4_pc~0); 1196177#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1196176#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1196175#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1196174#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1196173#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1196172#L471 assume !(1 == ~t5_pc~0); 1196171#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1196170#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1196169#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1196168#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1196167#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1196166#L490 assume !(1 == ~t6_pc~0); 1196165#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1196164#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1196163#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1196162#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1196161#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1196160#L509 assume !(1 == ~t7_pc~0); 1196158#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1196156#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1196154#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1196152#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1196151#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1196150#L857 assume !(1 == ~M_E~0); 1196149#L857-2 assume !(1 == ~T1_E~0); 1196148#L862-1 assume !(1 == ~T2_E~0); 1196147#L867-1 assume !(1 == ~T3_E~0); 1196146#L872-1 assume !(1 == ~T4_E~0); 1196145#L877-1 assume !(1 == ~T5_E~0); 1196144#L882-1 assume !(1 == ~T6_E~0); 1196143#L887-1 assume !(1 == ~T7_E~0); 1196142#L892-1 assume !(1 == ~E_M~0); 1196141#L897-1 assume !(1 == ~E_1~0); 1196140#L902-1 assume !(1 == ~E_2~0); 1196139#L907-1 assume !(1 == ~E_3~0); 1196138#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1195804#L917-1 assume !(1 == ~E_5~0); 1195805#L922-1 assume !(1 == ~E_6~0); 1196040#L927-1 assume !(1 == ~E_7~0); 1195792#L932-1 assume { :end_inline_reset_delta_events } true; 1195793#L1178-2 [2023-11-19 07:55:03,577 INFO L750 eck$LassoCheckResult]: Loop: 1195793#L1178-2 assume !false; 1240420#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1240419#L744-1 assume !false; 1240416#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1239934#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1239925#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1239924#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1239904#L641 assume !(0 != eval_~tmp~0#1); 1239903#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1239902#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1239901#L769-3 assume !(0 == ~M_E~0); 1239900#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1239899#L774-3 assume !(0 == ~T2_E~0); 1239898#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1239897#L784-3 assume !(0 == ~T4_E~0); 1239896#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1239836#L794-3 assume !(0 == ~T6_E~0); 1239812#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1239808#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1239805#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1239802#L814-3 assume !(0 == ~E_2~0); 1239799#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1239796#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1206131#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1206132#L834-3 assume !(0 == ~E_6~0); 1206127#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1206128#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1206123#L376-27 assume !(1 == ~m_pc~0); 1206124#L376-29 is_master_triggered_~__retres1~0#1 := 0; 1206119#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1206120#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1206115#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1206116#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1206111#L395-27 assume !(1 == ~t1_pc~0); 1206112#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1206108#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1206109#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1206104#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1206105#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1239411#L414-27 assume !(1 == ~t2_pc~0); 1239410#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1239408#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1239406#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1239404#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1239402#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1239400#L433-27 assume !(1 == ~t3_pc~0); 1239398#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1239396#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1239394#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1239392#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1239390#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1239388#L452-27 assume !(1 == ~t4_pc~0); 1206083#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1206084#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1206078#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1206079#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1241604#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1206073#L471-27 assume !(1 == ~t5_pc~0); 1206074#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1206070#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1206069#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1206068#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1206067#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1206066#L490-27 assume !(1 == ~t6_pc~0); 1206065#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1206064#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1206063#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1206062#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 1206061#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1206059#L509-27 assume !(1 == ~t7_pc~0); 1206057#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1206058#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1241577#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1206046#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 1206043#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1206044#L857-3 assume !(1 == ~M_E~0); 1206040#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1206041#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1241575#L867-3 assume !(1 == ~T3_E~0); 1206035#L872-3 assume !(1 == ~T4_E~0); 1206036#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1206031#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1206032#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1206027#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1206028#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1206023#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1206024#L907-3 assume !(1 == ~E_3~0); 1239074#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1239073#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1239072#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1239071#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1239070#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1239061#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1239052#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1239050#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1223098#L1197 assume !(0 == start_simulation_~tmp~3#1); 1223099#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1241170#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1241161#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1241157#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1241156#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1241155#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1241154#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1240687#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1195793#L1178-2 [2023-11-19 07:55:03,578 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:55:03,578 INFO L85 PathProgramCache]: Analyzing trace with hash -281555835, now seen corresponding path program 1 times [2023-11-19 07:55:03,578 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:55:03,579 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1874396211] [2023-11-19 07:55:03,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:55:03,579 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:55:03,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:55:03,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:55:03,640 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:55:03,640 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1874396211] [2023-11-19 07:55:03,640 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1874396211] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:55:03,640 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:55:03,640 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:55:03,641 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1929123891] [2023-11-19 07:55:03,641 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:55:03,641 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:55:03,642 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:55:03,642 INFO L85 PathProgramCache]: Analyzing trace with hash -645572964, now seen corresponding path program 2 times [2023-11-19 07:55:03,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:55:03,642 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [802996272] [2023-11-19 07:55:03,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:55:03,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:55:03,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:55:03,683 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:55:03,683 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:55:03,683 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [802996272] [2023-11-19 07:55:03,684 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [802996272] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:55:03,684 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:55:03,684 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:55:03,684 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [42041093] [2023-11-19 07:55:03,684 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:55:03,685 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:55:03,685 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:55:03,685 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:55:03,685 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:55:03,686 INFO L87 Difference]: Start difference. First operand 62963 states and 88149 transitions. cyclomatic complexity: 25202 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:55:03,986 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:55:03,986 INFO L93 Difference]: Finished difference Result 79033 states and 109975 transitions. [2023-11-19 07:55:03,987 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 79033 states and 109975 transitions. [2023-11-19 07:55:04,917 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 78542 [2023-11-19 07:55:05,084 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 79033 states to 79033 states and 109975 transitions. [2023-11-19 07:55:05,084 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 79033 [2023-11-19 07:55:05,114 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 79033 [2023-11-19 07:55:05,114 INFO L73 IsDeterministic]: Start isDeterministic. Operand 79033 states and 109975 transitions. [2023-11-19 07:55:05,148 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:55:05,148 INFO L218 hiAutomatonCegarLoop]: Abstraction has 79033 states and 109975 transitions. [2023-11-19 07:55:05,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79033 states and 109975 transitions. [2023-11-19 07:55:05,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79033 to 55030. [2023-11-19 07:55:05,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55030 states, 55030 states have (on average 1.3941849900054515) internal successors, (76722), 55029 states have internal predecessors, (76722), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:55:05,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55030 states to 55030 states and 76722 transitions. [2023-11-19 07:55:05,856 INFO L240 hiAutomatonCegarLoop]: Abstraction has 55030 states and 76722 transitions. [2023-11-19 07:55:05,856 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:55:05,857 INFO L428 stractBuchiCegarLoop]: Abstraction has 55030 states and 76722 transitions. [2023-11-19 07:55:05,857 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-19 07:55:05,857 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55030 states and 76722 transitions. [2023-11-19 07:55:06,021 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 54681 [2023-11-19 07:55:06,021 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:55:06,021 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:55:06,023 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:55:06,023 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:55:06,024 INFO L748 eck$LassoCheckResult]: Stem: 1337321#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1337322#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1337953#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1337954#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1337925#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1337926#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1337568#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1337390#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1337391#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1337373#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1337374#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1337923#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1337705#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1337706#L769 assume !(0 == ~M_E~0); 1337726#L769-2 assume !(0 == ~T1_E~0); 1337727#L774-1 assume !(0 == ~T2_E~0); 1337762#L779-1 assume !(0 == ~T3_E~0); 1337913#L784-1 assume !(0 == ~T4_E~0); 1337702#L789-1 assume !(0 == ~T5_E~0); 1337703#L794-1 assume !(0 == ~T6_E~0); 1337828#L799-1 assume !(0 == ~T7_E~0); 1337708#L804-1 assume !(0 == ~E_M~0); 1337709#L809-1 assume !(0 == ~E_1~0); 1337752#L814-1 assume !(0 == ~E_2~0); 1337115#L819-1 assume !(0 == ~E_3~0); 1337116#L824-1 assume !(0 == ~E_4~0); 1337463#L829-1 assume !(0 == ~E_5~0); 1338011#L834-1 assume !(0 == ~E_6~0); 1337241#L839-1 assume !(0 == ~E_7~0); 1337242#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1337652#L376 assume !(1 == ~m_pc~0); 1337648#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1337649#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1337893#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1337188#L955 assume !(0 != activate_threads_~tmp~1#1); 1337189#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1337561#L395 assume !(1 == ~t1_pc~0); 1337728#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1337896#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1337142#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1337143#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1337657#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1337658#L414 assume !(1 == ~t2_pc~0); 1337244#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1337245#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1337470#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1337471#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1337932#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1337565#L433 assume !(1 == ~t3_pc~0); 1337360#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1337361#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1337109#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1337110#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1337210#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1337211#L452 assume !(1 == ~t4_pc~0); 1337369#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1337370#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1337204#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1337205#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1337400#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1337401#L471 assume !(1 == ~t5_pc~0); 1337810#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1337385#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1337386#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1337897#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1337997#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1337998#L490 assume !(1 == ~t6_pc~0); 1337654#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1337655#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1337457#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1337458#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1337580#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1337542#L509 assume !(1 == ~t7_pc~0); 1337543#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1337346#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1337347#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1337407#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1337408#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1337944#L857 assume !(1 == ~M_E~0); 1337193#L857-2 assume !(1 == ~T1_E~0); 1337194#L862-1 assume !(1 == ~T2_E~0); 1337474#L867-1 assume !(1 == ~T3_E~0); 1337479#L872-1 assume !(1 == ~T4_E~0); 1337566#L877-1 assume !(1 == ~T5_E~0); 1337784#L882-1 assume !(1 == ~T6_E~0); 1337962#L887-1 assume !(1 == ~T7_E~0); 1337851#L892-1 assume !(1 == ~E_M~0); 1337852#L897-1 assume !(1 == ~E_1~0); 1337497#L902-1 assume !(1 == ~E_2~0); 1337498#L907-1 assume !(1 == ~E_3~0); 1337798#L912-1 assume !(1 == ~E_4~0); 1337790#L917-1 assume !(1 == ~E_5~0); 1337791#L922-1 assume !(1 == ~E_6~0); 1338013#L927-1 assume !(1 == ~E_7~0); 1337779#L932-1 assume { :end_inline_reset_delta_events } true; 1337780#L1178-2 [2023-11-19 07:55:06,024 INFO L750 eck$LassoCheckResult]: Loop: 1337780#L1178-2 assume !false; 1356494#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1356491#L744-1 assume !false; 1356488#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1356482#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1356470#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1356466#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1356461#L641 assume !(0 != eval_~tmp~0#1); 1356457#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1356453#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1356450#L769-3 assume !(0 == ~M_E~0); 1356446#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1356441#L774-3 assume !(0 == ~T2_E~0); 1356436#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1356431#L784-3 assume !(0 == ~T4_E~0); 1356426#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1356421#L794-3 assume !(0 == ~T6_E~0); 1356416#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1356409#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1355602#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1355599#L814-3 assume !(0 == ~E_2~0); 1355597#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1355595#L824-3 assume !(0 == ~E_4~0); 1355593#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1355591#L834-3 assume !(0 == ~E_6~0); 1355589#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1355580#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1355578#L376-27 assume !(1 == ~m_pc~0); 1355576#L376-29 is_master_triggered_~__retres1~0#1 := 0; 1355573#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1355571#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1355568#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1355526#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1355525#L395-27 assume !(1 == ~t1_pc~0); 1355524#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1355520#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1355518#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1355516#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1355514#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1355511#L414-27 assume !(1 == ~t2_pc~0); 1355500#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1355489#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1355480#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1355475#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1355467#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1355466#L433-27 assume !(1 == ~t3_pc~0); 1355464#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1355463#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1355460#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1355450#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1355444#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1355133#L452-27 assume !(1 == ~t4_pc~0); 1355114#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1355105#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1355098#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1355095#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1355082#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1355079#L471-27 assume !(1 == ~t5_pc~0); 1355068#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1355063#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1355059#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1355054#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1355049#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1355045#L490-27 assume !(1 == ~t6_pc~0); 1355041#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1355037#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1355033#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1355029#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 1355025#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1355021#L509-27 assume 1 == ~t7_pc~0; 1355016#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1355011#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1355006#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1355001#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1354996#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1354992#L857-3 assume !(1 == ~M_E~0); 1352126#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1354983#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1354978#L867-3 assume !(1 == ~T3_E~0); 1354973#L872-3 assume !(1 == ~T4_E~0); 1354967#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1354961#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1354955#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1354949#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1354943#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1354938#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1354933#L907-3 assume !(1 == ~E_3~0); 1354929#L912-3 assume !(1 == ~E_4~0); 1354924#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1354919#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1354914#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1354909#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1354894#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1354883#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1354879#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1352269#L1197 assume !(0 == start_simulation_~tmp~3#1); 1352270#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1356576#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1356566#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1356564#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1356563#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1356559#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1356557#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1356555#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1337780#L1178-2 [2023-11-19 07:55:06,024 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:55:06,025 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 1 times [2023-11-19 07:55:06,025 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:55:06,025 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2012609308] [2023-11-19 07:55:06,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:55:06,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:55:06,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:55:06,040 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:55:06,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:55:06,108 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:55:06,108 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:55:06,109 INFO L85 PathProgramCache]: Analyzing trace with hash 1874755417, now seen corresponding path program 1 times [2023-11-19 07:55:06,109 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:55:06,109 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1912289798] [2023-11-19 07:55:06,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:55:06,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:55:06,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:55:06,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:55:06,157 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:55:06,158 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1912289798] [2023-11-19 07:55:06,158 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1912289798] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:55:06,158 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:55:06,158 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:55:06,158 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1952839279] [2023-11-19 07:55:06,158 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:55:06,159 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:55:06,159 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:55:06,159 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:55:06,160 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:55:06,160 INFO L87 Difference]: Start difference. First operand 55030 states and 76722 transitions. cyclomatic complexity: 21708 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:55:06,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:55:06,783 INFO L93 Difference]: Finished difference Result 62963 states and 87604 transitions. [2023-11-19 07:55:06,783 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62963 states and 87604 transitions. [2023-11-19 07:55:06,990 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 62543 [2023-11-19 07:55:07,126 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62963 states to 62963 states and 87604 transitions. [2023-11-19 07:55:07,126 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 62963 [2023-11-19 07:55:07,157 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 62963 [2023-11-19 07:55:07,158 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62963 states and 87604 transitions. [2023-11-19 07:55:07,182 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:55:07,183 INFO L218 hiAutomatonCegarLoop]: Abstraction has 62963 states and 87604 transitions. [2023-11-19 07:55:07,216 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62963 states and 87604 transitions. [2023-11-19 07:55:07,622 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62963 to 62963. [2023-11-19 07:55:07,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62963 states, 62963 states have (on average 1.3913568286136302) internal successors, (87604), 62962 states have internal predecessors, (87604), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:55:07,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62963 states to 62963 states and 87604 transitions. [2023-11-19 07:55:07,779 INFO L240 hiAutomatonCegarLoop]: Abstraction has 62963 states and 87604 transitions. [2023-11-19 07:55:07,779 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:55:07,779 INFO L428 stractBuchiCegarLoop]: Abstraction has 62963 states and 87604 transitions. [2023-11-19 07:55:07,779 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-19 07:55:07,780 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62963 states and 87604 transitions. [2023-11-19 07:55:07,946 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 62543 [2023-11-19 07:55:07,946 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:55:07,946 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:55:07,948 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:55:07,948 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:55:07,949 INFO L748 eck$LassoCheckResult]: Stem: 1455320#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1455321#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1455980#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1455981#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1455947#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1455948#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1455577#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1455391#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1455392#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1455373#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1455374#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1455945#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1455714#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1455715#L769 assume !(0 == ~M_E~0); 1455736#L769-2 assume !(0 == ~T1_E~0); 1455737#L774-1 assume !(0 == ~T2_E~0); 1455772#L779-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1455926#L784-1 assume !(0 == ~T4_E~0); 1455927#L789-1 assume !(0 == ~T5_E~0); 1456157#L794-1 assume !(0 == ~T6_E~0); 1456156#L799-1 assume !(0 == ~T7_E~0); 1455718#L804-1 assume !(0 == ~E_M~0); 1455719#L809-1 assume !(0 == ~E_1~0); 1455764#L814-1 assume !(0 == ~E_2~0); 1455112#L819-1 assume !(0 == ~E_3~0); 1455113#L824-1 assume !(0 == ~E_4~0); 1456154#L829-1 assume !(0 == ~E_5~0); 1456037#L834-1 assume !(0 == ~E_6~0); 1456038#L839-1 assume !(0 == ~E_7~0); 1456153#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1455658#L376 assume !(1 == ~m_pc~0); 1455659#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1456101#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1456102#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1455186#L955 assume !(0 != activate_threads_~tmp~1#1); 1455187#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1455568#L395 assume !(1 == ~t1_pc~0); 1455738#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1455928#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1455929#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1455970#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1455971#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1456150#L414 assume !(1 == ~t2_pc~0); 1455242#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1455243#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1456125#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1455954#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1455955#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1456148#L433 assume !(1 == ~t3_pc~0); 1455360#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1455361#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1456147#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1455891#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1455208#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1455209#L452 assume !(1 == ~t4_pc~0); 1456095#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1455696#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1455202#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1455203#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1455401#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1455402#L471 assume !(1 == ~t5_pc~0); 1455818#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1455384#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1455385#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1456141#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1456026#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1456027#L490 assume !(1 == ~t6_pc~0); 1455662#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1455663#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1455457#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1455458#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1455587#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1455547#L509 assume !(1 == ~t7_pc~0); 1455548#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1456137#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1456138#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1456134#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1456133#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1456132#L857 assume !(1 == ~M_E~0); 1456131#L857-2 assume !(1 == ~T1_E~0); 1455475#L862-1 assume !(1 == ~T2_E~0); 1455476#L867-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1455481#L872-1 assume !(1 == ~T4_E~0); 1455575#L877-1 assume !(1 == ~T5_E~0); 1455792#L882-1 assume !(1 == ~T6_E~0); 1455987#L887-1 assume !(1 == ~T7_E~0); 1455860#L892-1 assume !(1 == ~E_M~0); 1455861#L897-1 assume !(1 == ~E_1~0); 1455498#L902-1 assume !(1 == ~E_2~0); 1455499#L907-1 assume !(1 == ~E_3~0); 1455806#L912-1 assume !(1 == ~E_4~0); 1455798#L917-1 assume !(1 == ~E_5~0); 1455799#L922-1 assume !(1 == ~E_6~0); 1456042#L927-1 assume !(1 == ~E_7~0); 1455787#L932-1 assume { :end_inline_reset_delta_events } true; 1455788#L1178-2 [2023-11-19 07:55:07,949 INFO L750 eck$LassoCheckResult]: Loop: 1455788#L1178-2 assume !false; 1493317#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1493316#L744-1 assume !false; 1493314#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1493312#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1493298#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1493292#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1493284#L641 assume !(0 != eval_~tmp~0#1); 1493280#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1492729#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1492711#L769-3 assume !(0 == ~M_E~0); 1492705#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1492699#L774-3 assume !(0 == ~T2_E~0); 1492697#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1492698#L784-3 assume !(0 == ~T4_E~0); 1493271#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1493269#L794-3 assume !(0 == ~T6_E~0); 1493267#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1493265#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1493263#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1493260#L814-3 assume !(0 == ~E_2~0); 1493258#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1493256#L824-3 assume !(0 == ~E_4~0); 1493254#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1493252#L834-3 assume !(0 == ~E_6~0); 1493250#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1493248#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1493206#L376-27 assume !(1 == ~m_pc~0); 1493200#L376-29 is_master_triggered_~__retres1~0#1 := 0; 1493193#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1493187#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1492832#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1492822#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1492819#L395-27 assume !(1 == ~t1_pc~0); 1492817#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1492815#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1492813#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1492811#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1492809#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1492807#L414-27 assume 1 == ~t2_pc~0; 1492804#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1492802#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1492800#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1492798#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1492795#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1492793#L433-27 assume !(1 == ~t3_pc~0); 1492791#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1492789#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1492787#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1492785#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1492783#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1492781#L452-27 assume !(1 == ~t4_pc~0); 1492778#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1492776#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1492774#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1492772#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1492770#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1492768#L471-27 assume !(1 == ~t5_pc~0); 1492766#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1492764#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1492762#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1492760#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1492756#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1492754#L490-27 assume !(1 == ~t6_pc~0); 1492752#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1492750#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1492747#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1492745#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 1492742#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1492740#L509-27 assume 1 == ~t7_pc~0; 1492738#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1492644#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1492495#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1492485#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1492474#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1492465#L857-3 assume !(1 == ~M_E~0); 1492227#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1492449#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1492441#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1492433#L872-3 assume !(1 == ~T4_E~0); 1492424#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1492418#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1492412#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1492404#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1492397#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1492390#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1492382#L907-3 assume !(1 == ~E_3~0); 1492374#L912-3 assume !(1 == ~E_4~0); 1492367#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1492360#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1492356#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1492354#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1492282#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1492267#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1492258#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1492247#L1197 assume !(0 == start_simulation_~tmp~3#1); 1492248#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1493457#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1493440#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1493431#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1493424#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1493416#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1493410#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1493403#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1455788#L1178-2 [2023-11-19 07:55:07,950 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:55:07,950 INFO L85 PathProgramCache]: Analyzing trace with hash -1895340795, now seen corresponding path program 1 times [2023-11-19 07:55:07,950 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:55:07,950 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2134024954] [2023-11-19 07:55:07,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:55:07,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:55:07,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:55:08,432 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:55:08,432 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:55:08,433 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2134024954] [2023-11-19 07:55:08,433 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2134024954] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:55:08,433 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:55:08,433 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:55:08,433 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1564942549] [2023-11-19 07:55:08,433 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:55:08,434 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:55:08,434 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:55:08,434 INFO L85 PathProgramCache]: Analyzing trace with hash 1435072986, now seen corresponding path program 1 times [2023-11-19 07:55:08,435 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:55:08,435 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1066496780] [2023-11-19 07:55:08,435 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:55:08,435 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:55:08,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:55:08,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:55:08,480 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:55:08,480 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1066496780] [2023-11-19 07:55:08,480 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1066496780] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:55:08,480 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:55:08,480 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:55:08,481 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [41906321] [2023-11-19 07:55:08,481 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:55:08,481 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:55:08,481 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:55:08,482 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:55:08,482 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:55:08,482 INFO L87 Difference]: Start difference. First operand 62963 states and 87604 transitions. cyclomatic complexity: 24657 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:55:08,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:55:08,742 INFO L93 Difference]: Finished difference Result 80083 states and 111218 transitions. [2023-11-19 07:55:08,742 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 80083 states and 111218 transitions. [2023-11-19 07:55:09,016 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 79597 [2023-11-19 07:55:09,180 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 80083 states to 80083 states and 111218 transitions. [2023-11-19 07:55:09,180 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 80083 [2023-11-19 07:55:09,219 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 80083 [2023-11-19 07:55:09,219 INFO L73 IsDeterministic]: Start isDeterministic. Operand 80083 states and 111218 transitions. [2023-11-19 07:55:09,251 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:55:09,251 INFO L218 hiAutomatonCegarLoop]: Abstraction has 80083 states and 111218 transitions. [2023-11-19 07:55:09,293 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80083 states and 111218 transitions. [2023-11-19 07:55:09,743 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80083 to 55030. [2023-11-19 07:55:09,776 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55030 states, 55030 states have (on average 1.3922042522260585) internal successors, (76613), 55029 states have internal predecessors, (76613), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:55:10,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55030 states to 55030 states and 76613 transitions. [2023-11-19 07:55:10,454 INFO L240 hiAutomatonCegarLoop]: Abstraction has 55030 states and 76613 transitions. [2023-11-19 07:55:10,454 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:55:10,455 INFO L428 stractBuchiCegarLoop]: Abstraction has 55030 states and 76613 transitions. [2023-11-19 07:55:10,455 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-19 07:55:10,455 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55030 states and 76613 transitions. [2023-11-19 07:55:10,579 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 54681 [2023-11-19 07:55:10,580 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:55:10,580 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:55:10,581 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:55:10,582 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:55:10,582 INFO L748 eck$LassoCheckResult]: Stem: 1598374#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1598375#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1599009#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1599010#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1598983#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1598984#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1598623#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1598442#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1598443#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1598425#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1598426#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1598980#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1598757#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1598758#L769 assume !(0 == ~M_E~0); 1598777#L769-2 assume !(0 == ~T1_E~0); 1598778#L774-1 assume !(0 == ~T2_E~0); 1598812#L779-1 assume !(0 == ~T3_E~0); 1598963#L784-1 assume !(0 == ~T4_E~0); 1598755#L789-1 assume !(0 == ~T5_E~0); 1598756#L794-1 assume !(0 == ~T6_E~0); 1598875#L799-1 assume !(0 == ~T7_E~0); 1598760#L804-1 assume !(0 == ~E_M~0); 1598761#L809-1 assume !(0 == ~E_1~0); 1598804#L814-1 assume !(0 == ~E_2~0); 1598170#L819-1 assume !(0 == ~E_3~0); 1598171#L824-1 assume !(0 == ~E_4~0); 1598513#L829-1 assume !(0 == ~E_5~0); 1599061#L834-1 assume !(0 == ~E_6~0); 1598294#L839-1 assume !(0 == ~E_7~0); 1598295#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1598708#L376 assume !(1 == ~m_pc~0); 1598704#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1598705#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1598941#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1598241#L955 assume !(0 != activate_threads_~tmp~1#1); 1598242#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1598616#L395 assume !(1 == ~t1_pc~0); 1598779#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1598944#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1598197#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1598198#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1598714#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1598715#L414 assume !(1 == ~t2_pc~0); 1598297#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1598298#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1598521#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1598522#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1598989#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1598620#L433 assume !(1 == ~t3_pc~0); 1598412#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1598413#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1598164#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1598165#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1598264#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1598265#L452 assume !(1 == ~t4_pc~0); 1598421#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1598422#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1598258#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1598259#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1598452#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1598453#L471 assume !(1 == ~t5_pc~0); 1598857#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1598437#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1598438#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1598945#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1599047#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1599048#L490 assume !(1 == ~t6_pc~0); 1598711#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1598712#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1598507#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1598508#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1598635#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1598596#L509 assume !(1 == ~t7_pc~0); 1598597#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1598990#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1599110#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1598459#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1598460#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1598998#L857 assume !(1 == ~M_E~0); 1598246#L857-2 assume !(1 == ~T1_E~0); 1598247#L862-1 assume !(1 == ~T2_E~0); 1598525#L867-1 assume !(1 == ~T3_E~0); 1598530#L872-1 assume !(1 == ~T4_E~0); 1598621#L877-1 assume !(1 == ~T5_E~0); 1598830#L882-1 assume !(1 == ~T6_E~0); 1599018#L887-1 assume !(1 == ~T7_E~0); 1598901#L892-1 assume !(1 == ~E_M~0); 1598902#L897-1 assume !(1 == ~E_1~0); 1598549#L902-1 assume !(1 == ~E_2~0); 1598550#L907-1 assume !(1 == ~E_3~0); 1598846#L912-1 assume !(1 == ~E_4~0); 1598836#L917-1 assume !(1 == ~E_5~0); 1598837#L922-1 assume !(1 == ~E_6~0); 1599064#L927-1 assume !(1 == ~E_7~0); 1598825#L932-1 assume { :end_inline_reset_delta_events } true; 1598826#L1178-2 [2023-11-19 07:55:10,583 INFO L750 eck$LassoCheckResult]: Loop: 1598826#L1178-2 assume !false; 1617179#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1617178#L744-1 assume !false; 1617176#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1617174#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1617165#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1617163#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1617160#L641 assume !(0 != eval_~tmp~0#1); 1617161#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1618327#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1618320#L769-3 assume !(0 == ~M_E~0); 1618315#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1618312#L774-3 assume !(0 == ~T2_E~0); 1618309#L779-3 assume !(0 == ~T3_E~0); 1618308#L784-3 assume !(0 == ~T4_E~0); 1618307#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1618306#L794-3 assume !(0 == ~T6_E~0); 1618305#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1618296#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1618294#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1618292#L814-3 assume !(0 == ~E_2~0); 1618289#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1618287#L824-3 assume !(0 == ~E_4~0); 1618285#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1618283#L834-3 assume !(0 == ~E_6~0); 1618281#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1618279#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1618277#L376-27 assume !(1 == ~m_pc~0); 1618275#L376-29 is_master_triggered_~__retres1~0#1 := 0; 1618273#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1618271#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1618269#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1618267#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1618265#L395-27 assume !(1 == ~t1_pc~0); 1618263#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1618261#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1618259#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1618249#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1618246#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1618243#L414-27 assume 1 == ~t2_pc~0; 1618238#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1618235#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1618232#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1618229#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1618226#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1618223#L433-27 assume !(1 == ~t3_pc~0); 1618220#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1618217#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1618214#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1618211#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1618207#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1618203#L452-27 assume !(1 == ~t4_pc~0); 1618198#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1618194#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1618189#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1618185#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1618181#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1618177#L471-27 assume !(1 == ~t5_pc~0); 1618173#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1618169#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1618166#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1618161#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1618157#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1618152#L490-27 assume !(1 == ~t6_pc~0); 1618147#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1618141#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1618136#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1618132#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 1618126#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1618120#L509-27 assume 1 == ~t7_pc~0; 1618114#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1618106#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1618100#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1618093#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1618087#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1618080#L857-3 assume !(1 == ~M_E~0); 1617830#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1618067#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1618060#L867-3 assume !(1 == ~T3_E~0); 1618053#L872-3 assume !(1 == ~T4_E~0); 1618047#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1618040#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1618035#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1618029#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1618023#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1618016#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1618009#L907-3 assume !(1 == ~E_3~0); 1618003#L912-3 assume !(1 == ~E_4~0); 1618002#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1617954#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1617951#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1617949#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1617947#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1617934#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1617927#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1617801#L1197 assume !(0 == start_simulation_~tmp~3#1); 1617792#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1617206#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1617197#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1617195#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1617193#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1617191#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1617189#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1617187#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1598826#L1178-2 [2023-11-19 07:55:10,583 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:55:10,583 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 2 times [2023-11-19 07:55:10,584 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:55:10,584 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [487022794] [2023-11-19 07:55:10,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:55:10,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:55:10,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:55:10,597 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:55:10,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:55:10,635 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:55:10,636 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:55:10,636 INFO L85 PathProgramCache]: Analyzing trace with hash -443469414, now seen corresponding path program 1 times [2023-11-19 07:55:10,636 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:55:10,636 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [19624666] [2023-11-19 07:55:10,636 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:55:10,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:55:10,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:55:10,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:55:10,676 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:55:10,677 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [19624666] [2023-11-19 07:55:10,677 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [19624666] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:55:10,677 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:55:10,677 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:55:10,677 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1632189806] [2023-11-19 07:55:10,678 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:55:10,678 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:55:10,678 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:55:10,679 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:55:10,679 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:55:10,679 INFO L87 Difference]: Start difference. First operand 55030 states and 76613 transitions. cyclomatic complexity: 21599 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:55:10,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:55:10,972 INFO L93 Difference]: Finished difference Result 87036 states and 120523 transitions. [2023-11-19 07:55:10,972 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 87036 states and 120523 transitions. [2023-11-19 07:55:11,291 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 86424 [2023-11-19 07:55:11,487 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 87036 states to 87036 states and 120523 transitions. [2023-11-19 07:55:11,487 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 87036 [2023-11-19 07:55:11,544 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 87036 [2023-11-19 07:55:11,545 INFO L73 IsDeterministic]: Start isDeterministic. Operand 87036 states and 120523 transitions. [2023-11-19 07:55:11,592 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:55:11,592 INFO L218 hiAutomatonCegarLoop]: Abstraction has 87036 states and 120523 transitions. [2023-11-19 07:55:11,647 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87036 states and 120523 transitions. [2023-11-19 07:55:12,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87036 to 86964. [2023-11-19 07:55:13,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 86964 states, 86964 states have (on average 1.3850673842049583) internal successors, (120451), 86963 states have internal predecessors, (120451), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:55:13,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86964 states to 86964 states and 120451 transitions. [2023-11-19 07:55:13,286 INFO L240 hiAutomatonCegarLoop]: Abstraction has 86964 states and 120451 transitions. [2023-11-19 07:55:13,286 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:55:13,287 INFO L428 stractBuchiCegarLoop]: Abstraction has 86964 states and 120451 transitions. [2023-11-19 07:55:13,287 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-19 07:55:13,287 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 86964 states and 120451 transitions. [2023-11-19 07:55:13,582 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 86352 [2023-11-19 07:55:13,582 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:55:13,582 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:55:13,585 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:55:13,585 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:55:13,585 INFO L748 eck$LassoCheckResult]: Stem: 1740448#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1740449#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1741138#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1741139#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1741107#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1741108#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1740704#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1740516#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1740517#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1740499#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1740500#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1741105#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1740849#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1740850#L769 assume !(0 == ~M_E~0); 1740871#L769-2 assume !(0 == ~T1_E~0); 1740872#L774-1 assume !(0 == ~T2_E~0); 1740910#L779-1 assume !(0 == ~T3_E~0); 1741081#L784-1 assume !(0 == ~T4_E~0); 1740846#L789-1 assume !(0 == ~T5_E~0); 1740847#L794-1 assume !(0 == ~T6_E~0); 1740977#L799-1 assume !(0 == ~T7_E~0); 1740852#L804-1 assume !(0 == ~E_M~0); 1740853#L809-1 assume !(0 == ~E_1~0); 1740900#L814-1 assume !(0 == ~E_2~0); 1740242#L819-1 assume 0 == ~E_3~0;~E_3~0 := 1; 1740243#L824-1 assume !(0 == ~E_4~0); 1741297#L829-1 assume !(0 == ~E_5~0); 1741298#L834-1 assume !(0 == ~E_6~0); 1740369#L839-1 assume !(0 == ~E_7~0); 1740370#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1740983#L376 assume !(1 == ~m_pc~0); 1740780#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1740781#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1741056#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1741057#L955 assume !(0 != activate_threads_~tmp~1#1); 1741337#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1740873#L395 assume !(1 == ~t1_pc~0); 1740874#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1741082#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1741083#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1741127#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1741128#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1741336#L414 assume !(1 == ~t2_pc~0); 1740372#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1740373#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1740597#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1740598#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1741203#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1740699#L433 assume !(1 == ~t3_pc~0); 1740700#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1741212#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1741213#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1741040#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1740338#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1740339#L452 assume !(1 == ~t4_pc~0); 1740495#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1740496#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1741332#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1741208#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1741209#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1741331#L471 assume !(1 == ~t5_pc~0); 1741230#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1741231#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1741062#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1741063#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1741299#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1741241#L490 assume !(1 == ~t6_pc~0); 1741242#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1740836#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1740837#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1740843#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1740844#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1741329#L509 assume !(1 == ~t7_pc~0); 1741115#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1740472#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1740473#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1741323#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1741210#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1741211#L857 assume !(1 == ~M_E~0); 1740321#L857-2 assume !(1 == ~T1_E~0); 1740322#L862-1 assume !(1 == ~T2_E~0); 1740601#L867-1 assume !(1 == ~T3_E~0); 1740701#L872-1 assume !(1 == ~T4_E~0); 1740702#L877-1 assume !(1 == ~T5_E~0); 1740932#L882-1 assume !(1 == ~T6_E~0); 1741147#L887-1 assume !(1 == ~T7_E~0); 1741002#L892-1 assume !(1 == ~E_M~0); 1741003#L897-1 assume !(1 == ~E_1~0); 1740629#L902-1 assume !(1 == ~E_2~0); 1740630#L907-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1740946#L912-1 assume !(1 == ~E_4~0); 1740938#L917-1 assume !(1 == ~E_5~0); 1740939#L922-1 assume !(1 == ~E_6~0); 1741200#L927-1 assume !(1 == ~E_7~0); 1740926#L932-1 assume { :end_inline_reset_delta_events } true; 1740927#L1178-2 [2023-11-19 07:55:13,586 INFO L750 eck$LassoCheckResult]: Loop: 1740927#L1178-2 assume !false; 1781361#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1781357#L744-1 assume !false; 1781352#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1781312#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1781301#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1781296#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1781290#L641 assume !(0 != eval_~tmp~0#1); 1781280#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1781271#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1781263#L769-3 assume !(0 == ~M_E~0); 1781253#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1781246#L774-3 assume !(0 == ~T2_E~0); 1781239#L779-3 assume !(0 == ~T3_E~0); 1781233#L784-3 assume !(0 == ~T4_E~0); 1781214#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1781209#L794-3 assume !(0 == ~T6_E~0); 1781204#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1781198#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1781193#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1781188#L814-3 assume !(0 == ~E_2~0); 1781182#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1781176#L824-3 assume !(0 == ~E_4~0); 1781171#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1781166#L834-3 assume !(0 == ~E_6~0); 1781161#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1781156#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1781151#L376-27 assume !(1 == ~m_pc~0); 1781146#L376-29 is_master_triggered_~__retres1~0#1 := 0; 1781141#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1781134#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1781128#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1781122#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1781117#L395-27 assume !(1 == ~t1_pc~0); 1781111#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1781105#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1781099#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1781093#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1781087#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1781081#L414-27 assume !(1 == ~t2_pc~0); 1781075#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1781065#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1781059#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1781052#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1781046#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1781040#L433-27 assume !(1 == ~t3_pc~0); 1781034#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1781028#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1781022#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1781016#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1781010#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1781003#L452-27 assume !(1 == ~t4_pc~0); 1780995#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1780989#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1780983#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1780977#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1780971#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1780966#L471-27 assume !(1 == ~t5_pc~0); 1780960#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1780954#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1780946#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1780938#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1780928#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1780920#L490-27 assume !(1 == ~t6_pc~0); 1780914#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1780907#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1780902#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1780897#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 1780893#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1780888#L509-27 assume !(1 == ~t7_pc~0); 1780883#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1780876#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1780869#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1780861#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 1780854#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1780850#L857-3 assume !(1 == ~M_E~0); 1780846#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1780844#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1780842#L867-3 assume !(1 == ~T3_E~0); 1780840#L872-3 assume !(1 == ~T4_E~0); 1780838#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1780836#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1780834#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1780832#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1780830#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1780828#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1780827#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1780825#L912-3 assume !(1 == ~E_4~0); 1780824#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1780822#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1780820#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1780818#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1780816#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1780805#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1780800#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1780794#L1197 assume !(0 == start_simulation_~tmp~3#1); 1780795#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1781459#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1781422#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1781411#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1781402#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1781392#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1781383#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1781375#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1740927#L1178-2 [2023-11-19 07:55:13,587 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:55:13,587 INFO L85 PathProgramCache]: Analyzing trace with hash -1756125947, now seen corresponding path program 1 times [2023-11-19 07:55:13,587 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:55:13,588 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2374125] [2023-11-19 07:55:13,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:55:13,588 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:55:13,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:55:13,664 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:55:13,665 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:55:13,665 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2374125] [2023-11-19 07:55:13,665 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2374125] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:55:13,665 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:55:13,665 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:55:13,666 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1666810541] [2023-11-19 07:55:13,666 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:55:13,666 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:55:13,667 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:55:13,667 INFO L85 PathProgramCache]: Analyzing trace with hash -613600224, now seen corresponding path program 1 times [2023-11-19 07:55:13,667 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:55:13,667 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1981228728] [2023-11-19 07:55:13,667 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:55:13,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:55:13,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:55:13,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:55:13,746 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:55:13,746 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1981228728] [2023-11-19 07:55:13,746 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1981228728] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:55:13,746 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:55:13,747 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:55:13,747 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [72882814] [2023-11-19 07:55:13,747 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:55:13,747 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:55:13,747 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:55:13,748 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:55:13,748 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:55:13,748 INFO L87 Difference]: Start difference. First operand 86964 states and 120451 transitions. cyclomatic complexity: 33503 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:55:14,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:55:14,337 INFO L93 Difference]: Finished difference Result 120412 states and 166576 transitions. [2023-11-19 07:55:14,337 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 120412 states and 166576 transitions.