./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.07.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 9bd2c7ff Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_23e57511-f345-486d-aa33-5cafdb89fdf3/bin/uautomizer-verify-uCwYo4JHxu/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_23e57511-f345-486d-aa33-5cafdb89fdf3/bin/uautomizer-verify-uCwYo4JHxu/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_23e57511-f345-486d-aa33-5cafdb89fdf3/bin/uautomizer-verify-uCwYo4JHxu/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_23e57511-f345-486d-aa33-5cafdb89fdf3/bin/uautomizer-verify-uCwYo4JHxu/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.07.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_23e57511-f345-486d-aa33-5cafdb89fdf3/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_23e57511-f345-486d-aa33-5cafdb89fdf3/bin/uautomizer-verify-uCwYo4JHxu --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 32b030e5f1b46150870f8dd8e24821389f0ffe4175e43053767dc9109bffcf9b --- Real Ultimate output --- This is Ultimate 0.2.3-dev-9bd2c7f [2023-11-19 07:39:43,623 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-19 07:39:43,742 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_23e57511-f345-486d-aa33-5cafdb89fdf3/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-19 07:39:43,746 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-19 07:39:43,747 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-19 07:39:43,795 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-19 07:39:43,796 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-19 07:39:43,796 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-19 07:39:43,798 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-19 07:39:43,802 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-19 07:39:43,803 INFO L153 SettingsManager]: * Use SBE=true [2023-11-19 07:39:43,804 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-19 07:39:43,804 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-19 07:39:43,806 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-19 07:39:43,806 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-19 07:39:43,807 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-19 07:39:43,807 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-19 07:39:43,808 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-19 07:39:43,808 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-19 07:39:43,809 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-19 07:39:43,809 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-19 07:39:43,809 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-19 07:39:43,810 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-19 07:39:43,810 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-19 07:39:43,811 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-19 07:39:43,811 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-19 07:39:43,811 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-19 07:39:43,812 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-19 07:39:43,812 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-19 07:39:43,813 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-19 07:39:43,814 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-19 07:39:43,814 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-19 07:39:43,814 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-19 07:39:43,815 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-19 07:39:43,815 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-19 07:39:43,815 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-19 07:39:43,816 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_23e57511-f345-486d-aa33-5cafdb89fdf3/bin/uautomizer-verify-uCwYo4JHxu/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_23e57511-f345-486d-aa33-5cafdb89fdf3/bin/uautomizer-verify-uCwYo4JHxu Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 32b030e5f1b46150870f8dd8e24821389f0ffe4175e43053767dc9109bffcf9b [2023-11-19 07:39:44,126 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-19 07:39:44,156 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-19 07:39:44,158 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-19 07:39:44,160 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-19 07:39:44,160 INFO L274 PluginConnector]: CDTParser initialized [2023-11-19 07:39:44,161 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_23e57511-f345-486d-aa33-5cafdb89fdf3/bin/uautomizer-verify-uCwYo4JHxu/../../sv-benchmarks/c/systemc/token_ring.07.cil-2.c [2023-11-19 07:39:47,225 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-19 07:39:47,484 INFO L384 CDTParser]: Found 1 translation units. [2023-11-19 07:39:47,485 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_23e57511-f345-486d-aa33-5cafdb89fdf3/sv-benchmarks/c/systemc/token_ring.07.cil-2.c [2023-11-19 07:39:47,513 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_23e57511-f345-486d-aa33-5cafdb89fdf3/bin/uautomizer-verify-uCwYo4JHxu/data/c03196176/c2b2ac6bb50f4927816848ea58e742af/FLAGbccde59f4 [2023-11-19 07:39:47,558 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_23e57511-f345-486d-aa33-5cafdb89fdf3/bin/uautomizer-verify-uCwYo4JHxu/data/c03196176/c2b2ac6bb50f4927816848ea58e742af [2023-11-19 07:39:47,561 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-19 07:39:47,562 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-19 07:39:47,564 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-19 07:39:47,564 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-19 07:39:47,572 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-19 07:39:47,574 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:39:47" (1/1) ... [2023-11-19 07:39:47,575 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@794ee156 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:39:47, skipping insertion in model container [2023-11-19 07:39:47,577 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:39:47" (1/1) ... [2023-11-19 07:39:47,650 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-19 07:39:47,881 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:39:47,898 INFO L202 MainTranslator]: Completed pre-run [2023-11-19 07:39:47,971 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:39:47,992 INFO L206 MainTranslator]: Completed translation [2023-11-19 07:39:47,993 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:39:47 WrapperNode [2023-11-19 07:39:47,993 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-19 07:39:47,996 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-19 07:39:47,996 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-19 07:39:47,996 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-19 07:39:48,004 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:39:47" (1/1) ... [2023-11-19 07:39:48,016 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:39:47" (1/1) ... [2023-11-19 07:39:48,117 INFO L138 Inliner]: procedures = 42, calls = 54, calls flagged for inlining = 49, calls inlined = 137, statements flattened = 2020 [2023-11-19 07:39:48,118 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-19 07:39:48,118 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-19 07:39:48,119 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-19 07:39:48,119 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-19 07:39:48,129 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:39:47" (1/1) ... [2023-11-19 07:39:48,130 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:39:47" (1/1) ... [2023-11-19 07:39:48,138 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:39:47" (1/1) ... [2023-11-19 07:39:48,139 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:39:47" (1/1) ... [2023-11-19 07:39:48,174 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:39:47" (1/1) ... [2023-11-19 07:39:48,198 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:39:47" (1/1) ... [2023-11-19 07:39:48,203 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:39:47" (1/1) ... [2023-11-19 07:39:48,211 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:39:47" (1/1) ... [2023-11-19 07:39:48,222 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-19 07:39:48,223 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-19 07:39:48,223 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-19 07:39:48,223 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-19 07:39:48,224 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:39:47" (1/1) ... [2023-11-19 07:39:48,236 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 07:39:48,248 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_23e57511-f345-486d-aa33-5cafdb89fdf3/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:39:48,269 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_23e57511-f345-486d-aa33-5cafdb89fdf3/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 07:39:48,285 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_23e57511-f345-486d-aa33-5cafdb89fdf3/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-19 07:39:48,316 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-19 07:39:48,317 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-19 07:39:48,317 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-19 07:39:48,317 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-19 07:39:48,427 INFO L236 CfgBuilder]: Building ICFG [2023-11-19 07:39:48,430 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-19 07:39:49,896 INFO L277 CfgBuilder]: Performing block encoding [2023-11-19 07:39:49,929 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-19 07:39:49,930 INFO L302 CfgBuilder]: Removed 10 assume(true) statements. [2023-11-19 07:39:49,939 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:39:49 BoogieIcfgContainer [2023-11-19 07:39:49,940 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-19 07:39:49,941 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-19 07:39:49,941 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-19 07:39:49,945 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-19 07:39:49,946 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:39:49,946 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 07:39:47" (1/3) ... [2023-11-19 07:39:49,947 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@15ed98b4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:39:49, skipping insertion in model container [2023-11-19 07:39:49,948 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:39:49,948 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:39:47" (2/3) ... [2023-11-19 07:39:49,948 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@15ed98b4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:39:49, skipping insertion in model container [2023-11-19 07:39:49,949 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:39:49,949 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:39:49" (3/3) ... [2023-11-19 07:39:49,950 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.07.cil-2.c [2023-11-19 07:39:50,034 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-19 07:39:50,035 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-19 07:39:50,035 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-19 07:39:50,035 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-19 07:39:50,035 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-19 07:39:50,036 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-19 07:39:50,036 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-19 07:39:50,036 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-19 07:39:50,051 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 853 states, 852 states have (on average 1.5140845070422535) internal successors, (1290), 852 states have internal predecessors, (1290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:50,123 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 746 [2023-11-19 07:39:50,123 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:39:50,123 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:39:50,139 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:50,139 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:50,139 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-19 07:39:50,142 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 853 states, 852 states have (on average 1.5140845070422535) internal successors, (1290), 852 states have internal predecessors, (1290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:50,160 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 746 [2023-11-19 07:39:50,161 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:39:50,161 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:39:50,169 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:50,169 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:50,180 INFO L748 eck$LassoCheckResult]: Stem: 127#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 784#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 622#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 782#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 807#L548true assume !(1 == ~m_i~0);~m_st~0 := 2; 213#L548-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 401#L553-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 295#L558-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 760#L563-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 153#L568-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 41#L573-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 791#L578-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 130#L583-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 505#L781true assume !(0 == ~M_E~0); 822#L781-2true assume !(0 == ~T1_E~0); 846#L786-1true assume !(0 == ~T2_E~0); 21#L791-1true assume !(0 == ~T3_E~0); 385#L796-1true assume !(0 == ~T4_E~0); 355#L801-1true assume !(0 == ~T5_E~0); 387#L806-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 766#L811-1true assume !(0 == ~T7_E~0); 134#L816-1true assume !(0 == ~E_M~0); 626#L821-1true assume !(0 == ~E_1~0); 37#L826-1true assume !(0 == ~E_2~0); 353#L831-1true assume !(0 == ~E_3~0); 210#L836-1true assume !(0 == ~E_4~0); 507#L841-1true assume !(0 == ~E_5~0); 107#L846-1true assume 0 == ~E_6~0;~E_6~0 := 1; 799#L851-1true assume !(0 == ~E_7~0); 119#L856-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 651#L388true assume !(1 == ~m_pc~0); 116#L388-2true is_master_triggered_~__retres1~0#1 := 0; 478#L399true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 545#is_master_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 44#L967true assume !(0 != activate_threads_~tmp~1#1); 767#L967-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11#L407true assume 1 == ~t1_pc~0; 414#L408true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13#L418true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 618#L975true assume !(0 != activate_threads_~tmp___0~0#1); 644#L975-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 184#L426true assume !(1 == ~t2_pc~0); 662#L426-2true is_transmit2_triggered_~__retres1~2#1 := 0; 753#L437true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 198#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 745#L983true assume !(0 != activate_threads_~tmp___1~0#1); 847#L983-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 241#L445true assume 1 == ~t3_pc~0; 838#L446true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 517#L456true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 441#L991true assume !(0 != activate_threads_~tmp___2~0#1); 512#L991-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 415#L464true assume !(1 == ~t4_pc~0); 121#L464-2true is_transmit4_triggered_~__retres1~4#1 := 0; 52#L475true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 845#L999true assume !(0 != activate_threads_~tmp___3~0#1); 227#L999-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 410#L483true assume 1 == ~t5_pc~0; 737#L484true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 593#L494true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 548#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 701#L1007true assume !(0 != activate_threads_~tmp___4~0#1); 175#L1007-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 461#L502true assume 1 == ~t6_pc~0; 383#L503true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 73#L513true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 190#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 322#L1015true assume !(0 != activate_threads_~tmp___5~0#1); 560#L1015-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 711#L521true assume !(1 == ~t7_pc~0); 666#L521-2true is_transmit7_triggered_~__retres1~7#1 := 0; 42#L532true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 800#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 607#L1023true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 569#L1023-2true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 469#L869true assume !(1 == ~M_E~0); 223#L869-2true assume !(1 == ~T1_E~0); 738#L874-1true assume !(1 == ~T2_E~0); 686#L879-1true assume !(1 == ~T3_E~0); 272#L884-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 5#L889-1true assume !(1 == ~T5_E~0); 139#L894-1true assume !(1 == ~T6_E~0); 836#L899-1true assume !(1 == ~T7_E~0); 431#L904-1true assume !(1 == ~E_M~0); 239#L909-1true assume !(1 == ~E_1~0); 371#L914-1true assume !(1 == ~E_2~0); 394#L919-1true assume !(1 == ~E_3~0); 183#L924-1true assume 1 == ~E_4~0;~E_4~0 := 2; 90#L929-1true assume !(1 == ~E_5~0); 705#L934-1true assume !(1 == ~E_6~0); 225#L939-1true assume !(1 == ~E_7~0); 559#L944-1true assume { :end_inline_reset_delta_events } true; 555#L1190-2true [2023-11-19 07:39:50,183 INFO L750 eck$LassoCheckResult]: Loop: 555#L1190-2true assume !false; 135#L1191true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 136#L756-1true assume false; 491#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 302#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 398#L781-3true assume 0 == ~M_E~0;~M_E~0 := 1; 59#L781-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 253#L786-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 308#L791-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 34#L796-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 632#L801-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 176#L806-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 303#L811-3true assume !(0 == ~T7_E~0); 497#L816-3true assume 0 == ~E_M~0;~E_M~0 := 1; 663#L821-3true assume 0 == ~E_1~0;~E_1~0 := 1; 777#L826-3true assume 0 == ~E_2~0;~E_2~0 := 1; 437#L831-3true assume 0 == ~E_3~0;~E_3~0 := 1; 679#L836-3true assume 0 == ~E_4~0;~E_4~0 := 1; 112#L841-3true assume 0 == ~E_5~0;~E_5~0 := 1; 606#L846-3true assume 0 == ~E_6~0;~E_6~0 := 1; 321#L851-3true assume !(0 == ~E_7~0); 55#L856-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 759#L388-27true assume 1 == ~m_pc~0; 608#L389-9true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 773#L399-9true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 458#is_master_triggered_returnLabel#10true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 709#L967-27true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 155#L967-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 459#L407-27true assume 1 == ~t1_pc~0; 442#L408-9true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 540#L418-9true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 365#is_transmit1_triggered_returnLabel#10true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 482#L975-27true assume !(0 != activate_threads_~tmp___0~0#1); 337#L975-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 108#L426-27true assume !(1 == ~t2_pc~0); 851#L426-29true is_transmit2_triggered_~__retres1~2#1 := 0; 113#L437-9true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 438#is_transmit2_triggered_returnLabel#10true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 707#L983-27true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 602#L983-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 298#L445-27true assume 1 == ~t3_pc~0; 278#L446-9true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32#L456-9true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 299#is_transmit3_triggered_returnLabel#10true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 854#L991-27true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 376#L991-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 171#L464-27true assume 1 == ~t4_pc~0; 483#L465-9true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 65#L475-9true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 251#is_transmit4_triggered_returnLabel#10true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 304#L999-27true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 104#L999-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 796#L483-27true assume !(1 == ~t5_pc~0); 587#L483-29true is_transmit5_triggered_~__retres1~5#1 := 0; 56#L494-9true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 563#is_transmit5_triggered_returnLabel#10true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 552#L1007-27true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 824#L1007-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 717#L502-27true assume !(1 == ~t6_pc~0); 317#L502-29true is_transmit6_triggered_~__retres1~6#1 := 0; 706#L513-9true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 690#is_transmit6_triggered_returnLabel#10true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 464#L1015-27true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 750#L1015-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6#L521-27true assume 1 == ~t7_pc~0; 193#L522-9true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 785#L532-9true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 162#is_transmit7_triggered_returnLabel#10true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30#L1023-27true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 328#L1023-29true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 678#L869-3true assume 1 == ~M_E~0;~M_E~0 := 2; 462#L869-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 252#L874-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 291#L879-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 320#L884-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 284#L889-3true assume !(1 == ~T5_E~0); 85#L894-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 425#L899-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 97#L904-3true assume 1 == ~E_M~0;~E_M~0 := 2; 269#L909-3true assume 1 == ~E_1~0;~E_1~0 := 2; 74#L914-3true assume 1 == ~E_2~0;~E_2~0 := 2; 94#L919-3true assume 1 == ~E_3~0;~E_3~0 := 2; 619#L924-3true assume 1 == ~E_4~0;~E_4~0 := 2; 448#L929-3true assume !(1 == ~E_5~0); 374#L934-3true assume 1 == ~E_6~0;~E_6~0 := 2; 565#L939-3true assume 1 == ~E_7~0;~E_7~0 := 2; 100#L944-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 601#L596-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 674#L638-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 169#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 790#L1209true assume !(0 == start_simulation_~tmp~3#1); 314#L1209-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 301#L596-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 544#L638-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 27#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 609#L1164true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 25#L1171true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 315#stop_simulation_returnLabel#1true start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 128#L1222true assume !(0 != start_simulation_~tmp___0~1#1); 555#L1190-2true [2023-11-19 07:39:50,198 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:50,199 INFO L85 PathProgramCache]: Analyzing trace with hash 1617538625, now seen corresponding path program 1 times [2023-11-19 07:39:50,210 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:50,211 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [163663061] [2023-11-19 07:39:50,211 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:50,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:50,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:50,603 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:50,603 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:50,603 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [163663061] [2023-11-19 07:39:50,604 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [163663061] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:50,604 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:50,605 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:39:50,606 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [56164069] [2023-11-19 07:39:50,607 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:50,612 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:39:50,613 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:50,613 INFO L85 PathProgramCache]: Analyzing trace with hash -41697262, now seen corresponding path program 1 times [2023-11-19 07:39:50,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:50,614 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1200949893] [2023-11-19 07:39:50,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:50,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:50,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:50,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:50,675 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:50,675 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1200949893] [2023-11-19 07:39:50,675 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1200949893] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:50,676 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:50,676 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:39:50,676 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [887642891] [2023-11-19 07:39:50,676 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:50,678 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:39:50,679 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:39:50,729 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:39:50,729 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:39:50,733 INFO L87 Difference]: Start difference. First operand has 853 states, 852 states have (on average 1.5140845070422535) internal successors, (1290), 852 states have internal predecessors, (1290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:50,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:39:50,812 INFO L93 Difference]: Finished difference Result 849 states and 1263 transitions. [2023-11-19 07:39:50,814 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 849 states and 1263 transitions. [2023-11-19 07:39:50,824 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-19 07:39:50,839 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 849 states to 843 states and 1257 transitions. [2023-11-19 07:39:50,841 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2023-11-19 07:39:50,844 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2023-11-19 07:39:50,845 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1257 transitions. [2023-11-19 07:39:50,850 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:39:50,850 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1257 transitions. [2023-11-19 07:39:50,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1257 transitions. [2023-11-19 07:39:50,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2023-11-19 07:39:50,914 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.491103202846975) internal successors, (1257), 842 states have internal predecessors, (1257), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:50,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1257 transitions. [2023-11-19 07:39:50,919 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1257 transitions. [2023-11-19 07:39:50,924 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:39:50,927 INFO L428 stractBuchiCegarLoop]: Abstraction has 843 states and 1257 transitions. [2023-11-19 07:39:50,927 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-19 07:39:50,928 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1257 transitions. [2023-11-19 07:39:50,937 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-19 07:39:50,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:39:50,938 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:39:50,960 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:50,961 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:50,962 INFO L748 eck$LassoCheckResult]: Stem: 1961#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1962#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2509#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2510#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2549#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 2104#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2105#L553-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2227#L558-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2228#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2005#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1796#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1797#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1966#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1967#L781 assume !(0 == ~M_E~0); 2444#L781-2 assume !(0 == ~T1_E~0); 2552#L786-1 assume !(0 == ~T2_E~0); 1756#L791-1 assume !(0 == ~T3_E~0); 1757#L796-1 assume !(0 == ~T4_E~0); 2296#L801-1 assume !(0 == ~T5_E~0); 2297#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2327#L811-1 assume !(0 == ~T7_E~0); 1973#L816-1 assume !(0 == ~E_M~0); 1974#L821-1 assume !(0 == ~E_1~0); 1787#L826-1 assume !(0 == ~E_2~0); 1788#L831-1 assume !(0 == ~E_3~0); 2099#L836-1 assume !(0 == ~E_4~0); 2100#L841-1 assume !(0 == ~E_5~0); 1924#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 1925#L851-1 assume !(0 == ~E_7~0); 1948#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1949#L388 assume !(1 == ~m_pc~0); 1942#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1943#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2422#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1802#L967 assume !(0 != activate_threads_~tmp~1#1); 1803#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1732#L407 assume 1 == ~t1_pc~0; 1733#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1737#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1738#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1773#L975 assume !(0 != activate_threads_~tmp___0~0#1); 2507#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2059#L426 assume !(1 == ~t2_pc~0); 2060#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2524#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2081#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2082#L983 assume !(0 != activate_threads_~tmp___1~0#1); 2545#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2145#L445 assume 1 == ~t3_pc~0; 2146#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2450#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1730#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1731#L991 assume !(0 != activate_threads_~tmp___2~0#1); 2386#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2354#L464 assume !(1 == ~t4_pc~0); 1952#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1822#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1823#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1834#L999 assume !(0 != activate_threads_~tmp___3~0#1); 2124#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2125#L483 assume 1 == ~t5_pc~0; 2350#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2490#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2463#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2464#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 2042#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2043#L502 assume 1 == ~t6_pc~0; 2324#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1862#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1863#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2067#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 2264#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2473#L521 assume !(1 == ~t7_pc~0); 2504#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1798#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1799#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2498#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2477#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2413#L869 assume !(1 == ~M_E~0); 2118#L869-2 assume !(1 == ~T1_E~0); 2119#L874-1 assume !(1 == ~T2_E~0); 2532#L879-1 assume !(1 == ~T3_E~0); 2193#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1718#L889-1 assume !(1 == ~T5_E~0); 1719#L894-1 assume !(1 == ~T6_E~0); 1981#L899-1 assume !(1 == ~T7_E~0); 2375#L904-1 assume !(1 == ~E_M~0); 2142#L909-1 assume !(1 == ~E_1~0); 2143#L914-1 assume !(1 == ~E_2~0); 2312#L919-1 assume !(1 == ~E_3~0); 2058#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1895#L929-1 assume !(1 == ~E_5~0); 1896#L934-1 assume !(1 == ~E_6~0); 2120#L939-1 assume !(1 == ~E_7~0); 2121#L944-1 assume { :end_inline_reset_delta_events } true; 1964#L1190-2 [2023-11-19 07:39:50,964 INFO L750 eck$LassoCheckResult]: Loop: 1964#L1190-2 assume !false; 1975#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1976#L756-1 assume !false; 1977#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2550#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1815#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2106#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2107#L653 assume !(0 != eval_~tmp~0#1); 2158#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2237#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2238#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1835#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1836#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2164#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1781#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1782#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2044#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2045#L811-3 assume !(0 == ~T7_E~0); 2239#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2436#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2525#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2379#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2380#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1935#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1936#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2263#L851-3 assume !(0 == ~E_7~0); 1829#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1830#L388-27 assume 1 == ~m_pc~0; 2499#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2500#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2403#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2404#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2008#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2009#L407-27 assume 1 == ~t1_pc~0; 2387#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2388#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2306#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2307#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 2280#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1926#L426-27 assume 1 == ~t2_pc~0; 1927#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1940#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1941#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2381#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2496#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2231#L445-27 assume 1 == ~t3_pc~0; 2205#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1778#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1779#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2232#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2317#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2034#L464-27 assume !(1 == ~t4_pc~0); 1776#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1777#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1848#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2161#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1919#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1920#L483-27 assume 1 == ~t5_pc~0; 2455#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1831#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1832#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2468#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2469#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2536#L502-27 assume !(1 == ~t6_pc~0); 2257#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 2258#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2533#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2409#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2410#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1720#L521-27 assume 1 == ~t7_pc~0; 1721#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2072#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2020#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1774#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1775#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2270#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2406#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2162#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2163#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2223#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2216#L889-3 assume !(1 == ~T5_E~0); 1885#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1886#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1906#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1907#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1864#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1865#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1901#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2393#L929-3 assume !(1 == ~E_5~0); 2314#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2315#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1911#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1912#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1740#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2031#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2032#L1209 assume !(0 == start_simulation_~tmp~3#1); 2253#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2236#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1879#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1769#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1770#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1765#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1766#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1963#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1964#L1190-2 [2023-11-19 07:39:50,965 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:50,965 INFO L85 PathProgramCache]: Analyzing trace with hash -736846657, now seen corresponding path program 1 times [2023-11-19 07:39:50,966 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:50,966 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2143681958] [2023-11-19 07:39:50,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:50,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:51,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:51,102 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:51,102 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:51,102 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2143681958] [2023-11-19 07:39:51,103 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2143681958] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:51,103 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:51,103 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:39:51,104 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1197651498] [2023-11-19 07:39:51,104 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:51,105 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:39:51,106 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:51,107 INFO L85 PathProgramCache]: Analyzing trace with hash 1400482270, now seen corresponding path program 1 times [2023-11-19 07:39:51,111 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:51,112 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1860052706] [2023-11-19 07:39:51,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:51,113 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:51,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:51,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:51,247 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:51,247 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1860052706] [2023-11-19 07:39:51,248 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1860052706] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:51,248 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:51,249 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:39:51,249 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [66306929] [2023-11-19 07:39:51,250 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:51,251 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:39:51,252 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:39:51,252 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:39:51,253 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:39:51,253 INFO L87 Difference]: Start difference. First operand 843 states and 1257 transitions. cyclomatic complexity: 415 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:51,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:39:51,285 INFO L93 Difference]: Finished difference Result 843 states and 1256 transitions. [2023-11-19 07:39:51,285 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1256 transitions. [2023-11-19 07:39:51,295 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-19 07:39:51,304 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1256 transitions. [2023-11-19 07:39:51,304 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2023-11-19 07:39:51,305 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2023-11-19 07:39:51,305 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1256 transitions. [2023-11-19 07:39:51,307 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:39:51,308 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1256 transitions. [2023-11-19 07:39:51,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1256 transitions. [2023-11-19 07:39:51,326 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2023-11-19 07:39:51,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4899169632265719) internal successors, (1256), 842 states have internal predecessors, (1256), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:51,333 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1256 transitions. [2023-11-19 07:39:51,337 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1256 transitions. [2023-11-19 07:39:51,339 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:39:51,340 INFO L428 stractBuchiCegarLoop]: Abstraction has 843 states and 1256 transitions. [2023-11-19 07:39:51,340 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-19 07:39:51,341 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1256 transitions. [2023-11-19 07:39:51,347 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-19 07:39:51,348 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:39:51,348 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:39:51,351 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:51,357 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:51,359 INFO L748 eck$LassoCheckResult]: Stem: 3654#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 3655#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 4202#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4203#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4242#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 3797#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3798#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3920#L558-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3921#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3698#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3489#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3490#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3659#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3660#L781 assume !(0 == ~M_E~0); 4137#L781-2 assume !(0 == ~T1_E~0); 4245#L786-1 assume !(0 == ~T2_E~0); 3449#L791-1 assume !(0 == ~T3_E~0); 3450#L796-1 assume !(0 == ~T4_E~0); 3989#L801-1 assume !(0 == ~T5_E~0); 3990#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4020#L811-1 assume !(0 == ~T7_E~0); 3666#L816-1 assume !(0 == ~E_M~0); 3667#L821-1 assume !(0 == ~E_1~0); 3480#L826-1 assume !(0 == ~E_2~0); 3481#L831-1 assume !(0 == ~E_3~0); 3792#L836-1 assume !(0 == ~E_4~0); 3793#L841-1 assume !(0 == ~E_5~0); 3617#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 3618#L851-1 assume !(0 == ~E_7~0); 3641#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3642#L388 assume !(1 == ~m_pc~0); 3635#L388-2 is_master_triggered_~__retres1~0#1 := 0; 3636#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4115#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3495#L967 assume !(0 != activate_threads_~tmp~1#1); 3496#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3425#L407 assume 1 == ~t1_pc~0; 3426#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3430#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3431#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3466#L975 assume !(0 != activate_threads_~tmp___0~0#1); 4200#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3752#L426 assume !(1 == ~t2_pc~0); 3753#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4217#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3774#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3775#L983 assume !(0 != activate_threads_~tmp___1~0#1); 4238#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3838#L445 assume 1 == ~t3_pc~0; 3839#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4143#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3423#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3424#L991 assume !(0 != activate_threads_~tmp___2~0#1); 4079#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4047#L464 assume !(1 == ~t4_pc~0); 3645#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3515#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3516#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3527#L999 assume !(0 != activate_threads_~tmp___3~0#1); 3817#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3818#L483 assume 1 == ~t5_pc~0; 4043#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4183#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4156#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4157#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 3735#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3736#L502 assume 1 == ~t6_pc~0; 4017#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3555#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3556#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3760#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 3957#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4166#L521 assume !(1 == ~t7_pc~0); 4197#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3491#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3492#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4191#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4170#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4106#L869 assume !(1 == ~M_E~0); 3811#L869-2 assume !(1 == ~T1_E~0); 3812#L874-1 assume !(1 == ~T2_E~0); 4225#L879-1 assume !(1 == ~T3_E~0); 3886#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3411#L889-1 assume !(1 == ~T5_E~0); 3412#L894-1 assume !(1 == ~T6_E~0); 3674#L899-1 assume !(1 == ~T7_E~0); 4068#L904-1 assume !(1 == ~E_M~0); 3835#L909-1 assume !(1 == ~E_1~0); 3836#L914-1 assume !(1 == ~E_2~0); 4005#L919-1 assume !(1 == ~E_3~0); 3751#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3588#L929-1 assume !(1 == ~E_5~0); 3589#L934-1 assume !(1 == ~E_6~0); 3813#L939-1 assume !(1 == ~E_7~0); 3814#L944-1 assume { :end_inline_reset_delta_events } true; 3657#L1190-2 [2023-11-19 07:39:51,360 INFO L750 eck$LassoCheckResult]: Loop: 3657#L1190-2 assume !false; 3668#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3669#L756-1 assume !false; 3670#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 4243#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3508#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3799#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3800#L653 assume !(0 != eval_~tmp~0#1); 3851#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3930#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3931#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3528#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3529#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3857#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3474#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3475#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3737#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3738#L811-3 assume !(0 == ~T7_E~0); 3932#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4129#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4218#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4072#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4073#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3628#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3629#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3956#L851-3 assume !(0 == ~E_7~0); 3522#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3523#L388-27 assume 1 == ~m_pc~0; 4192#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4193#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4096#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4097#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3701#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3702#L407-27 assume 1 == ~t1_pc~0; 4080#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4081#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3999#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4000#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 3973#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3619#L426-27 assume 1 == ~t2_pc~0; 3620#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3633#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3634#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4074#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4189#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3924#L445-27 assume 1 == ~t3_pc~0; 3898#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3471#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3472#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3925#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4010#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3727#L464-27 assume 1 == ~t4_pc~0; 3728#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3470#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3541#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3854#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3612#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3613#L483-27 assume 1 == ~t5_pc~0; 4148#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3524#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3525#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4161#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4162#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4229#L502-27 assume 1 == ~t6_pc~0; 4230#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3951#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4226#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4102#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4103#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3413#L521-27 assume 1 == ~t7_pc~0; 3414#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3765#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3713#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3467#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3468#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3963#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4099#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3855#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3856#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3916#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3909#L889-3 assume !(1 == ~T5_E~0); 3578#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3579#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3599#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3600#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3557#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3558#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3594#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4086#L929-3 assume !(1 == ~E_5~0); 4007#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4008#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3604#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3605#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3433#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3724#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 3725#L1209 assume !(0 == start_simulation_~tmp~3#1); 3946#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3929#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3572#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3462#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 3463#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 3458#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3459#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 3656#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 3657#L1190-2 [2023-11-19 07:39:51,360 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:51,360 INFO L85 PathProgramCache]: Analyzing trace with hash 33886909, now seen corresponding path program 1 times [2023-11-19 07:39:51,361 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:51,361 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [514157200] [2023-11-19 07:39:51,361 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:51,361 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:51,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:51,448 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:51,448 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:51,448 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [514157200] [2023-11-19 07:39:51,448 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [514157200] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:51,449 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:51,449 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:39:51,449 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1781339959] [2023-11-19 07:39:51,449 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:51,450 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:39:51,450 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:51,450 INFO L85 PathProgramCache]: Analyzing trace with hash -2135531812, now seen corresponding path program 1 times [2023-11-19 07:39:51,451 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:51,451 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1446666622] [2023-11-19 07:39:51,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:51,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:51,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:51,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:51,571 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:51,572 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1446666622] [2023-11-19 07:39:51,572 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1446666622] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:51,572 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:51,572 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:39:51,572 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1707945865] [2023-11-19 07:39:51,573 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:51,573 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:39:51,573 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:39:51,574 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:39:51,574 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:39:51,574 INFO L87 Difference]: Start difference. First operand 843 states and 1256 transitions. cyclomatic complexity: 414 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:51,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:39:51,624 INFO L93 Difference]: Finished difference Result 843 states and 1255 transitions. [2023-11-19 07:39:51,625 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1255 transitions. [2023-11-19 07:39:51,632 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-19 07:39:51,639 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1255 transitions. [2023-11-19 07:39:51,640 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2023-11-19 07:39:51,641 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2023-11-19 07:39:51,641 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1255 transitions. [2023-11-19 07:39:51,642 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:39:51,642 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1255 transitions. [2023-11-19 07:39:51,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1255 transitions. [2023-11-19 07:39:51,656 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2023-11-19 07:39:51,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4887307236061684) internal successors, (1255), 842 states have internal predecessors, (1255), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:51,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1255 transitions. [2023-11-19 07:39:51,662 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1255 transitions. [2023-11-19 07:39:51,663 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:39:51,664 INFO L428 stractBuchiCegarLoop]: Abstraction has 843 states and 1255 transitions. [2023-11-19 07:39:51,664 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-19 07:39:51,664 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1255 transitions. [2023-11-19 07:39:51,669 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-19 07:39:51,670 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:39:51,670 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:39:51,672 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:51,672 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:51,672 INFO L748 eck$LassoCheckResult]: Stem: 5347#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 5348#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5895#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5896#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5935#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 5490#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5491#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5613#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5614#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5391#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5182#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5183#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5352#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5353#L781 assume !(0 == ~M_E~0); 5830#L781-2 assume !(0 == ~T1_E~0); 5938#L786-1 assume !(0 == ~T2_E~0); 5142#L791-1 assume !(0 == ~T3_E~0); 5143#L796-1 assume !(0 == ~T4_E~0); 5682#L801-1 assume !(0 == ~T5_E~0); 5683#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5713#L811-1 assume !(0 == ~T7_E~0); 5359#L816-1 assume !(0 == ~E_M~0); 5360#L821-1 assume !(0 == ~E_1~0); 5173#L826-1 assume !(0 == ~E_2~0); 5174#L831-1 assume !(0 == ~E_3~0); 5485#L836-1 assume !(0 == ~E_4~0); 5486#L841-1 assume !(0 == ~E_5~0); 5310#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 5311#L851-1 assume !(0 == ~E_7~0); 5334#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5335#L388 assume !(1 == ~m_pc~0); 5328#L388-2 is_master_triggered_~__retres1~0#1 := 0; 5329#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5808#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5188#L967 assume !(0 != activate_threads_~tmp~1#1); 5189#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5118#L407 assume 1 == ~t1_pc~0; 5119#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5123#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5124#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5159#L975 assume !(0 != activate_threads_~tmp___0~0#1); 5893#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5445#L426 assume !(1 == ~t2_pc~0); 5446#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5910#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5467#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5468#L983 assume !(0 != activate_threads_~tmp___1~0#1); 5931#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5531#L445 assume 1 == ~t3_pc~0; 5532#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5836#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5116#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5117#L991 assume !(0 != activate_threads_~tmp___2~0#1); 5772#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5740#L464 assume !(1 == ~t4_pc~0); 5338#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5208#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5209#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5220#L999 assume !(0 != activate_threads_~tmp___3~0#1); 5510#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5511#L483 assume 1 == ~t5_pc~0; 5736#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5876#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5849#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5850#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 5428#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5429#L502 assume 1 == ~t6_pc~0; 5710#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5248#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5249#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5453#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 5650#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5859#L521 assume !(1 == ~t7_pc~0); 5890#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5184#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5185#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5884#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5863#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5799#L869 assume !(1 == ~M_E~0); 5504#L869-2 assume !(1 == ~T1_E~0); 5505#L874-1 assume !(1 == ~T2_E~0); 5918#L879-1 assume !(1 == ~T3_E~0); 5579#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5104#L889-1 assume !(1 == ~T5_E~0); 5105#L894-1 assume !(1 == ~T6_E~0); 5367#L899-1 assume !(1 == ~T7_E~0); 5761#L904-1 assume !(1 == ~E_M~0); 5528#L909-1 assume !(1 == ~E_1~0); 5529#L914-1 assume !(1 == ~E_2~0); 5698#L919-1 assume !(1 == ~E_3~0); 5444#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5281#L929-1 assume !(1 == ~E_5~0); 5282#L934-1 assume !(1 == ~E_6~0); 5506#L939-1 assume !(1 == ~E_7~0); 5507#L944-1 assume { :end_inline_reset_delta_events } true; 5350#L1190-2 [2023-11-19 07:39:51,673 INFO L750 eck$LassoCheckResult]: Loop: 5350#L1190-2 assume !false; 5361#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5362#L756-1 assume !false; 5363#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5936#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5201#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5492#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5493#L653 assume !(0 != eval_~tmp~0#1); 5544#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5623#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5624#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5221#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5222#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5550#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5167#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5168#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5430#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5431#L811-3 assume !(0 == ~T7_E~0); 5625#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5822#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5911#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5765#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5766#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5321#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5322#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5649#L851-3 assume !(0 == ~E_7~0); 5215#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5216#L388-27 assume 1 == ~m_pc~0; 5885#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5886#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5789#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5790#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5394#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5395#L407-27 assume 1 == ~t1_pc~0; 5773#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5774#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5692#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5693#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 5666#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5312#L426-27 assume 1 == ~t2_pc~0; 5313#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5326#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5327#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5767#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5882#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5617#L445-27 assume 1 == ~t3_pc~0; 5591#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5164#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5165#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5618#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5703#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5420#L464-27 assume !(1 == ~t4_pc~0); 5162#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 5163#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5234#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5547#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5305#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5306#L483-27 assume 1 == ~t5_pc~0; 5841#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5217#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5218#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5854#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5855#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5922#L502-27 assume 1 == ~t6_pc~0; 5923#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5644#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5919#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5795#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5796#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5106#L521-27 assume 1 == ~t7_pc~0; 5107#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5458#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5406#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5160#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5161#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5656#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5792#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5548#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5549#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5609#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5602#L889-3 assume !(1 == ~T5_E~0); 5271#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5272#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5292#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5293#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5250#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5251#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5287#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5779#L929-3 assume !(1 == ~E_5~0); 5700#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5701#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5297#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5298#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5126#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5417#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 5418#L1209 assume !(0 == start_simulation_~tmp~3#1); 5639#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5622#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5265#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5155#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 5156#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 5151#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5152#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 5349#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 5350#L1190-2 [2023-11-19 07:39:51,673 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:51,678 INFO L85 PathProgramCache]: Analyzing trace with hash 1028580607, now seen corresponding path program 1 times [2023-11-19 07:39:51,678 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:51,679 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1622531213] [2023-11-19 07:39:51,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:51,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:51,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:51,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:51,769 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:51,769 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1622531213] [2023-11-19 07:39:51,769 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1622531213] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:51,769 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:51,770 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:39:51,770 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1381097112] [2023-11-19 07:39:51,770 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:51,770 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:39:51,771 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:51,771 INFO L85 PathProgramCache]: Analyzing trace with hash 1885656989, now seen corresponding path program 1 times [2023-11-19 07:39:51,771 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:51,771 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1815077143] [2023-11-19 07:39:51,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:51,772 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:51,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:51,857 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:51,857 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:51,857 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1815077143] [2023-11-19 07:39:51,858 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1815077143] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:51,858 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:51,858 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:39:51,858 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1331544755] [2023-11-19 07:39:51,859 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:51,860 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:39:51,860 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:39:51,860 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:39:51,860 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:39:51,861 INFO L87 Difference]: Start difference. First operand 843 states and 1255 transitions. cyclomatic complexity: 413 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:51,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:39:51,885 INFO L93 Difference]: Finished difference Result 843 states and 1254 transitions. [2023-11-19 07:39:51,885 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1254 transitions. [2023-11-19 07:39:51,893 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-19 07:39:51,901 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1254 transitions. [2023-11-19 07:39:51,902 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2023-11-19 07:39:51,903 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2023-11-19 07:39:51,903 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1254 transitions. [2023-11-19 07:39:51,904 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:39:51,905 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1254 transitions. [2023-11-19 07:39:51,907 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1254 transitions. [2023-11-19 07:39:51,918 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2023-11-19 07:39:51,921 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4875444839857652) internal successors, (1254), 842 states have internal predecessors, (1254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:51,925 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1254 transitions. [2023-11-19 07:39:51,926 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1254 transitions. [2023-11-19 07:39:51,926 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:39:51,929 INFO L428 stractBuchiCegarLoop]: Abstraction has 843 states and 1254 transitions. [2023-11-19 07:39:51,933 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-19 07:39:51,933 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1254 transitions. [2023-11-19 07:39:51,939 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-19 07:39:51,939 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:39:51,939 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:39:51,941 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:51,941 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:51,942 INFO L748 eck$LassoCheckResult]: Stem: 7040#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 7041#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 7588#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7589#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7628#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 7183#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7184#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7306#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7307#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7084#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6875#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6876#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7048#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7049#L781 assume !(0 == ~M_E~0); 7523#L781-2 assume !(0 == ~T1_E~0); 7631#L786-1 assume !(0 == ~T2_E~0); 6838#L791-1 assume !(0 == ~T3_E~0); 6839#L796-1 assume !(0 == ~T4_E~0); 7375#L801-1 assume !(0 == ~T5_E~0); 7376#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7406#L811-1 assume !(0 == ~T7_E~0); 7052#L816-1 assume !(0 == ~E_M~0); 7053#L821-1 assume !(0 == ~E_1~0); 6866#L826-1 assume !(0 == ~E_2~0); 6867#L831-1 assume !(0 == ~E_3~0); 7178#L836-1 assume !(0 == ~E_4~0); 7179#L841-1 assume !(0 == ~E_5~0); 7003#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 7004#L851-1 assume !(0 == ~E_7~0); 7027#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7028#L388 assume !(1 == ~m_pc~0); 7021#L388-2 is_master_triggered_~__retres1~0#1 := 0; 7022#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7501#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6881#L967 assume !(0 != activate_threads_~tmp~1#1); 6882#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6811#L407 assume 1 == ~t1_pc~0; 6812#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6819#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6820#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6854#L975 assume !(0 != activate_threads_~tmp___0~0#1); 7586#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7138#L426 assume !(1 == ~t2_pc~0); 7139#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7603#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7160#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7161#L983 assume !(0 != activate_threads_~tmp___1~0#1); 7624#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7224#L445 assume 1 == ~t3_pc~0; 7225#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7529#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6809#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6810#L991 assume !(0 != activate_threads_~tmp___2~0#1); 7465#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7433#L464 assume !(1 == ~t4_pc~0); 7031#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6901#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6902#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6913#L999 assume !(0 != activate_threads_~tmp___3~0#1); 7203#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7204#L483 assume 1 == ~t5_pc~0; 7429#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7569#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7542#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7543#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 7123#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7124#L502 assume 1 == ~t6_pc~0; 7404#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6941#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6942#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7148#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 7343#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7552#L521 assume !(1 == ~t7_pc~0); 7583#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6877#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6878#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7577#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7556#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7494#L869 assume !(1 == ~M_E~0); 7197#L869-2 assume !(1 == ~T1_E~0); 7198#L874-1 assume !(1 == ~T2_E~0); 7611#L879-1 assume !(1 == ~T3_E~0); 7272#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6797#L889-1 assume !(1 == ~T5_E~0); 6798#L894-1 assume !(1 == ~T6_E~0); 7063#L899-1 assume !(1 == ~T7_E~0); 7455#L904-1 assume !(1 == ~E_M~0); 7221#L909-1 assume !(1 == ~E_1~0); 7222#L914-1 assume !(1 == ~E_2~0); 7392#L919-1 assume !(1 == ~E_3~0); 7137#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6974#L929-1 assume !(1 == ~E_5~0); 6975#L934-1 assume !(1 == ~E_6~0); 7201#L939-1 assume !(1 == ~E_7~0); 7202#L944-1 assume { :end_inline_reset_delta_events } true; 7043#L1190-2 [2023-11-19 07:39:51,942 INFO L750 eck$LassoCheckResult]: Loop: 7043#L1190-2 assume !false; 7054#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7055#L756-1 assume !false; 7056#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 7629#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6896#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7186#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7187#L653 assume !(0 != eval_~tmp~0#1); 7240#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7317#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7318#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6914#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6915#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7243#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6860#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6861#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7121#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7122#L811-3 assume !(0 == ~T7_E~0); 7316#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7515#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7604#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7458#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7459#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7014#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7015#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7342#L851-3 assume !(0 == ~E_7~0); 6908#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6909#L388-27 assume 1 == ~m_pc~0; 7578#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7579#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7482#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7483#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7087#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7088#L407-27 assume 1 == ~t1_pc~0; 7466#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7467#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7385#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7386#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 7359#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7005#L426-27 assume 1 == ~t2_pc~0; 7006#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7019#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7020#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7460#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7575#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7310#L445-27 assume 1 == ~t3_pc~0; 7282#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6857#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6858#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7311#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7395#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7113#L464-27 assume !(1 == ~t4_pc~0); 6855#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 6856#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6927#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7238#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6998#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6999#L483-27 assume 1 == ~t5_pc~0; 7534#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6910#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6911#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7547#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7548#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7615#L502-27 assume 1 == ~t6_pc~0; 7616#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7337#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7612#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7488#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7489#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6799#L521-27 assume 1 == ~t7_pc~0; 6800#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7151#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7099#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6852#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6853#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7349#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7485#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7241#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7242#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7302#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7295#L889-3 assume !(1 == ~T5_E~0); 6964#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6965#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6985#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6986#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6943#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6944#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6980#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7472#L929-3 assume !(1 == ~E_5~0); 7393#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7394#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6990#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6991#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6817#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7110#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 7111#L1209 assume !(0 == start_simulation_~tmp~3#1); 7332#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 7315#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6958#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6848#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 6849#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 6844#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6845#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 7042#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 7043#L1190-2 [2023-11-19 07:39:51,944 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:51,945 INFO L85 PathProgramCache]: Analyzing trace with hash 1614856829, now seen corresponding path program 1 times [2023-11-19 07:39:51,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:51,945 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [928077840] [2023-11-19 07:39:51,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:51,946 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:51,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:52,004 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:52,004 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:52,005 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [928077840] [2023-11-19 07:39:52,005 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [928077840] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:52,005 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:52,005 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:39:52,005 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [266857700] [2023-11-19 07:39:52,006 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:52,006 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:39:52,006 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:52,007 INFO L85 PathProgramCache]: Analyzing trace with hash 1885656989, now seen corresponding path program 2 times [2023-11-19 07:39:52,007 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:52,007 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [115804312] [2023-11-19 07:39:52,007 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:52,007 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:52,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:52,118 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:52,118 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:52,118 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [115804312] [2023-11-19 07:39:52,119 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [115804312] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:52,119 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:52,119 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:39:52,119 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1861002619] [2023-11-19 07:39:52,120 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:52,120 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:39:52,120 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:39:52,121 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:39:52,121 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:39:52,121 INFO L87 Difference]: Start difference. First operand 843 states and 1254 transitions. cyclomatic complexity: 412 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:52,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:39:52,146 INFO L93 Difference]: Finished difference Result 843 states and 1253 transitions. [2023-11-19 07:39:52,146 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1253 transitions. [2023-11-19 07:39:52,155 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-19 07:39:52,163 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1253 transitions. [2023-11-19 07:39:52,163 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2023-11-19 07:39:52,164 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2023-11-19 07:39:52,164 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1253 transitions. [2023-11-19 07:39:52,165 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:39:52,166 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1253 transitions. [2023-11-19 07:39:52,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1253 transitions. [2023-11-19 07:39:52,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2023-11-19 07:39:52,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4863582443653618) internal successors, (1253), 842 states have internal predecessors, (1253), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:52,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1253 transitions. [2023-11-19 07:39:52,186 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1253 transitions. [2023-11-19 07:39:52,187 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:39:52,189 INFO L428 stractBuchiCegarLoop]: Abstraction has 843 states and 1253 transitions. [2023-11-19 07:39:52,190 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-19 07:39:52,190 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1253 transitions. [2023-11-19 07:39:52,195 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-19 07:39:52,196 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:39:52,196 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:39:52,197 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:52,198 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:52,198 INFO L748 eck$LassoCheckResult]: Stem: 8733#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 8734#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 9281#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9282#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9321#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 8876#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8877#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8999#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9000#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8777#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8568#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8569#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8741#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8742#L781 assume !(0 == ~M_E~0); 9216#L781-2 assume !(0 == ~T1_E~0); 9324#L786-1 assume !(0 == ~T2_E~0); 8528#L791-1 assume !(0 == ~T3_E~0); 8529#L796-1 assume !(0 == ~T4_E~0); 9068#L801-1 assume !(0 == ~T5_E~0); 9069#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9099#L811-1 assume !(0 == ~T7_E~0); 8745#L816-1 assume !(0 == ~E_M~0); 8746#L821-1 assume !(0 == ~E_1~0); 8559#L826-1 assume !(0 == ~E_2~0); 8560#L831-1 assume !(0 == ~E_3~0); 8871#L836-1 assume !(0 == ~E_4~0); 8872#L841-1 assume !(0 == ~E_5~0); 8696#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 8697#L851-1 assume !(0 == ~E_7~0); 8720#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8721#L388 assume !(1 == ~m_pc~0); 8714#L388-2 is_master_triggered_~__retres1~0#1 := 0; 8715#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9194#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8574#L967 assume !(0 != activate_threads_~tmp~1#1); 8575#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8504#L407 assume 1 == ~t1_pc~0; 8505#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8512#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8513#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8547#L975 assume !(0 != activate_threads_~tmp___0~0#1); 9279#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8831#L426 assume !(1 == ~t2_pc~0); 8832#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9296#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8853#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8854#L983 assume !(0 != activate_threads_~tmp___1~0#1); 9317#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8917#L445 assume 1 == ~t3_pc~0; 8918#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9222#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8502#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8503#L991 assume !(0 != activate_threads_~tmp___2~0#1); 9158#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9126#L464 assume !(1 == ~t4_pc~0); 8724#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8594#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8595#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8606#L999 assume !(0 != activate_threads_~tmp___3~0#1); 8896#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8897#L483 assume 1 == ~t5_pc~0; 9122#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9262#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9235#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9236#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 8814#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8815#L502 assume 1 == ~t6_pc~0; 9097#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8634#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8635#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8839#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 9036#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9245#L521 assume !(1 == ~t7_pc~0); 9276#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8570#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8571#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9270#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9249#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9185#L869 assume !(1 == ~M_E~0); 8890#L869-2 assume !(1 == ~T1_E~0); 8891#L874-1 assume !(1 == ~T2_E~0); 9304#L879-1 assume !(1 == ~T3_E~0); 8965#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8490#L889-1 assume !(1 == ~T5_E~0); 8491#L894-1 assume !(1 == ~T6_E~0); 8753#L899-1 assume !(1 == ~T7_E~0); 9148#L904-1 assume !(1 == ~E_M~0); 8914#L909-1 assume !(1 == ~E_1~0); 8915#L914-1 assume !(1 == ~E_2~0); 9084#L919-1 assume !(1 == ~E_3~0); 8830#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8667#L929-1 assume !(1 == ~E_5~0); 8668#L934-1 assume !(1 == ~E_6~0); 8892#L939-1 assume !(1 == ~E_7~0); 8893#L944-1 assume { :end_inline_reset_delta_events } true; 8736#L1190-2 [2023-11-19 07:39:52,199 INFO L750 eck$LassoCheckResult]: Loop: 8736#L1190-2 assume !false; 8747#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8748#L756-1 assume !false; 8749#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9322#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8589#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8878#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8879#L653 assume !(0 != eval_~tmp~0#1); 8931#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9009#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9010#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8607#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8608#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8936#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8553#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8554#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8816#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8817#L811-3 assume !(0 == ~T7_E~0); 9011#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9208#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9297#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9151#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9152#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8707#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8708#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9035#L851-3 assume !(0 == ~E_7~0); 8601#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8602#L388-27 assume 1 == ~m_pc~0; 9271#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9272#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9175#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9176#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8780#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8781#L407-27 assume 1 == ~t1_pc~0; 9159#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9160#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9078#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9079#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 9052#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8698#L426-27 assume 1 == ~t2_pc~0; 8699#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8712#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8713#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9153#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9268#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9003#L445-27 assume 1 == ~t3_pc~0; 8977#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8550#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8551#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9004#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9088#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8806#L464-27 assume !(1 == ~t4_pc~0); 8548#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 8549#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8618#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8929#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8691#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8692#L483-27 assume 1 == ~t5_pc~0; 9227#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8603#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8604#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9240#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9241#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9308#L502-27 assume !(1 == ~t6_pc~0); 9029#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 9030#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9305#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9181#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9182#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8492#L521-27 assume 1 == ~t7_pc~0; 8493#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8844#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8792#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8545#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8546#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9040#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9178#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8934#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8935#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8995#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8988#L889-3 assume !(1 == ~T5_E~0); 8657#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8658#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8678#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8679#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8636#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8637#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8673#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9165#L929-3 assume !(1 == ~E_5~0); 9086#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9087#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8683#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8684#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8510#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8803#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 8804#L1209 assume !(0 == start_simulation_~tmp~3#1); 9025#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9008#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8651#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8541#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 8542#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 8537#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8538#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 8735#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 8736#L1190-2 [2023-11-19 07:39:52,200 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:52,200 INFO L85 PathProgramCache]: Analyzing trace with hash -721535681, now seen corresponding path program 1 times [2023-11-19 07:39:52,200 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:52,201 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [722430797] [2023-11-19 07:39:52,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:52,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:52,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:52,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:52,244 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:52,245 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [722430797] [2023-11-19 07:39:52,245 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [722430797] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:52,245 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:52,245 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:39:52,246 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [410303481] [2023-11-19 07:39:52,246 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:52,246 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:39:52,247 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:52,247 INFO L85 PathProgramCache]: Analyzing trace with hash 1400482270, now seen corresponding path program 2 times [2023-11-19 07:39:52,248 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:52,252 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [934984566] [2023-11-19 07:39:52,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:52,253 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:52,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:52,315 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:52,316 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:52,316 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [934984566] [2023-11-19 07:39:52,316 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [934984566] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:52,316 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:52,317 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:39:52,317 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [363844229] [2023-11-19 07:39:52,317 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:52,318 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:39:52,318 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:39:52,318 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:39:52,318 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:39:52,319 INFO L87 Difference]: Start difference. First operand 843 states and 1253 transitions. cyclomatic complexity: 411 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:52,343 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:39:52,343 INFO L93 Difference]: Finished difference Result 843 states and 1252 transitions. [2023-11-19 07:39:52,343 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1252 transitions. [2023-11-19 07:39:52,351 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-19 07:39:52,359 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1252 transitions. [2023-11-19 07:39:52,359 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2023-11-19 07:39:52,360 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2023-11-19 07:39:52,360 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1252 transitions. [2023-11-19 07:39:52,361 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:39:52,362 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1252 transitions. [2023-11-19 07:39:52,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1252 transitions. [2023-11-19 07:39:52,375 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2023-11-19 07:39:52,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4851720047449586) internal successors, (1252), 842 states have internal predecessors, (1252), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:52,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1252 transitions. [2023-11-19 07:39:52,382 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1252 transitions. [2023-11-19 07:39:52,383 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:39:52,384 INFO L428 stractBuchiCegarLoop]: Abstraction has 843 states and 1252 transitions. [2023-11-19 07:39:52,385 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-19 07:39:52,385 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1252 transitions. [2023-11-19 07:39:52,392 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-19 07:39:52,393 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:39:52,393 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:39:52,394 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:52,395 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:52,395 INFO L748 eck$LassoCheckResult]: Stem: 10426#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 10427#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10974#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10975#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11014#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 10569#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10570#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10692#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10693#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10470#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10261#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10262#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10431#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10432#L781 assume !(0 == ~M_E~0); 10909#L781-2 assume !(0 == ~T1_E~0); 11017#L786-1 assume !(0 == ~T2_E~0); 10221#L791-1 assume !(0 == ~T3_E~0); 10222#L796-1 assume !(0 == ~T4_E~0); 10761#L801-1 assume !(0 == ~T5_E~0); 10762#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10792#L811-1 assume !(0 == ~T7_E~0); 10438#L816-1 assume !(0 == ~E_M~0); 10439#L821-1 assume !(0 == ~E_1~0); 10252#L826-1 assume !(0 == ~E_2~0); 10253#L831-1 assume !(0 == ~E_3~0); 10564#L836-1 assume !(0 == ~E_4~0); 10565#L841-1 assume !(0 == ~E_5~0); 10389#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 10390#L851-1 assume !(0 == ~E_7~0); 10413#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10414#L388 assume !(1 == ~m_pc~0); 10407#L388-2 is_master_triggered_~__retres1~0#1 := 0; 10408#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10887#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10267#L967 assume !(0 != activate_threads_~tmp~1#1); 10268#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10197#L407 assume 1 == ~t1_pc~0; 10198#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10202#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10203#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10238#L975 assume !(0 != activate_threads_~tmp___0~0#1); 10972#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10524#L426 assume !(1 == ~t2_pc~0); 10525#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10989#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10546#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10547#L983 assume !(0 != activate_threads_~tmp___1~0#1); 11010#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10610#L445 assume 1 == ~t3_pc~0; 10611#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10915#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10195#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10196#L991 assume !(0 != activate_threads_~tmp___2~0#1); 10851#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10819#L464 assume !(1 == ~t4_pc~0); 10417#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10287#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10288#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10299#L999 assume !(0 != activate_threads_~tmp___3~0#1); 10589#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10590#L483 assume 1 == ~t5_pc~0; 10815#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10955#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10928#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10929#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 10507#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10508#L502 assume 1 == ~t6_pc~0; 10789#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10327#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10328#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10532#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 10729#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10938#L521 assume !(1 == ~t7_pc~0); 10969#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10263#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10264#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10963#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10942#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10878#L869 assume !(1 == ~M_E~0); 10583#L869-2 assume !(1 == ~T1_E~0); 10584#L874-1 assume !(1 == ~T2_E~0); 10997#L879-1 assume !(1 == ~T3_E~0); 10658#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10183#L889-1 assume !(1 == ~T5_E~0); 10184#L894-1 assume !(1 == ~T6_E~0); 10446#L899-1 assume !(1 == ~T7_E~0); 10840#L904-1 assume !(1 == ~E_M~0); 10607#L909-1 assume !(1 == ~E_1~0); 10608#L914-1 assume !(1 == ~E_2~0); 10777#L919-1 assume !(1 == ~E_3~0); 10523#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10360#L929-1 assume !(1 == ~E_5~0); 10361#L934-1 assume !(1 == ~E_6~0); 10585#L939-1 assume !(1 == ~E_7~0); 10586#L944-1 assume { :end_inline_reset_delta_events } true; 10429#L1190-2 [2023-11-19 07:39:52,395 INFO L750 eck$LassoCheckResult]: Loop: 10429#L1190-2 assume !false; 10440#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10441#L756-1 assume !false; 10442#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11015#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10280#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10571#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10572#L653 assume !(0 != eval_~tmp~0#1); 10623#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10702#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10703#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10300#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10301#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10629#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10246#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10247#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10509#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10510#L811-3 assume !(0 == ~T7_E~0); 10704#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10901#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10990#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10844#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10845#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10400#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10401#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10728#L851-3 assume !(0 == ~E_7~0); 10294#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10295#L388-27 assume 1 == ~m_pc~0; 10964#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10965#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10868#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10869#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10473#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10474#L407-27 assume 1 == ~t1_pc~0; 10852#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10853#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10771#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10772#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 10745#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10391#L426-27 assume 1 == ~t2_pc~0; 10392#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10405#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10406#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10846#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10961#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10696#L445-27 assume 1 == ~t3_pc~0; 10670#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10243#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10244#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10697#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10782#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10499#L464-27 assume !(1 == ~t4_pc~0); 10241#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 10242#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10313#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10626#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10384#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10385#L483-27 assume 1 == ~t5_pc~0; 10920#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10296#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10297#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10933#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10934#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11001#L502-27 assume !(1 == ~t6_pc~0); 10722#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 10723#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10998#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10874#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10875#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10185#L521-27 assume 1 == ~t7_pc~0; 10186#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10537#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10485#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10239#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10240#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10735#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10871#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10627#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10628#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10688#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10681#L889-3 assume !(1 == ~T5_E~0); 10350#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10351#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10371#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10372#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10329#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10330#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10366#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10858#L929-3 assume !(1 == ~E_5~0); 10779#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10780#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10376#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10377#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10205#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10496#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 10497#L1209 assume !(0 == start_simulation_~tmp~3#1); 10718#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10701#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10344#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10234#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 10235#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 10230#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10231#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 10428#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 10429#L1190-2 [2023-11-19 07:39:52,396 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:52,396 INFO L85 PathProgramCache]: Analyzing trace with hash 1696948797, now seen corresponding path program 1 times [2023-11-19 07:39:52,397 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:52,397 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [233369509] [2023-11-19 07:39:52,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:52,397 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:52,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:52,435 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:52,435 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:52,436 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [233369509] [2023-11-19 07:39:52,436 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [233369509] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:52,436 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:52,436 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:39:52,436 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [509068941] [2023-11-19 07:39:52,437 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:52,437 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:39:52,437 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:52,438 INFO L85 PathProgramCache]: Analyzing trace with hash 1400482270, now seen corresponding path program 3 times [2023-11-19 07:39:52,438 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:52,438 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1381822324] [2023-11-19 07:39:52,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:52,439 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:52,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:52,516 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:52,517 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:52,517 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1381822324] [2023-11-19 07:39:52,517 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1381822324] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:52,517 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:52,517 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:39:52,518 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [442756369] [2023-11-19 07:39:52,518 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:52,518 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:39:52,519 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:39:52,519 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:39:52,519 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:39:52,519 INFO L87 Difference]: Start difference. First operand 843 states and 1252 transitions. cyclomatic complexity: 410 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:52,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:39:52,548 INFO L93 Difference]: Finished difference Result 843 states and 1251 transitions. [2023-11-19 07:39:52,548 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1251 transitions. [2023-11-19 07:39:52,557 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-19 07:39:52,566 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1251 transitions. [2023-11-19 07:39:52,566 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2023-11-19 07:39:52,567 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2023-11-19 07:39:52,567 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1251 transitions. [2023-11-19 07:39:52,568 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:39:52,569 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1251 transitions. [2023-11-19 07:39:52,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1251 transitions. [2023-11-19 07:39:52,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2023-11-19 07:39:52,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4839857651245552) internal successors, (1251), 842 states have internal predecessors, (1251), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:52,591 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1251 transitions. [2023-11-19 07:39:52,592 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1251 transitions. [2023-11-19 07:39:52,592 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:39:52,593 INFO L428 stractBuchiCegarLoop]: Abstraction has 843 states and 1251 transitions. [2023-11-19 07:39:52,593 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-19 07:39:52,593 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1251 transitions. [2023-11-19 07:39:52,600 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2023-11-19 07:39:52,600 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:39:52,600 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:39:52,602 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:52,602 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:52,602 INFO L748 eck$LassoCheckResult]: Stem: 12119#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 12120#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 12667#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12668#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12707#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 12262#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12263#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12385#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12386#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12163#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11954#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11955#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 12124#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12125#L781 assume !(0 == ~M_E~0); 12602#L781-2 assume !(0 == ~T1_E~0); 12710#L786-1 assume !(0 == ~T2_E~0); 11914#L791-1 assume !(0 == ~T3_E~0); 11915#L796-1 assume !(0 == ~T4_E~0); 12454#L801-1 assume !(0 == ~T5_E~0); 12455#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12485#L811-1 assume !(0 == ~T7_E~0); 12131#L816-1 assume !(0 == ~E_M~0); 12132#L821-1 assume !(0 == ~E_1~0); 11945#L826-1 assume !(0 == ~E_2~0); 11946#L831-1 assume !(0 == ~E_3~0); 12257#L836-1 assume !(0 == ~E_4~0); 12258#L841-1 assume !(0 == ~E_5~0); 12082#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 12083#L851-1 assume !(0 == ~E_7~0); 12106#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12107#L388 assume !(1 == ~m_pc~0); 12100#L388-2 is_master_triggered_~__retres1~0#1 := 0; 12101#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12580#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11960#L967 assume !(0 != activate_threads_~tmp~1#1); 11961#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11890#L407 assume 1 == ~t1_pc~0; 11891#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11895#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11896#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11931#L975 assume !(0 != activate_threads_~tmp___0~0#1); 12665#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12217#L426 assume !(1 == ~t2_pc~0); 12218#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12682#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12239#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12240#L983 assume !(0 != activate_threads_~tmp___1~0#1); 12703#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12303#L445 assume 1 == ~t3_pc~0; 12304#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12608#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11888#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11889#L991 assume !(0 != activate_threads_~tmp___2~0#1); 12544#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12512#L464 assume !(1 == ~t4_pc~0); 12110#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11980#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11981#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11992#L999 assume !(0 != activate_threads_~tmp___3~0#1); 12282#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12283#L483 assume 1 == ~t5_pc~0; 12508#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12648#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12621#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12622#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 12200#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12201#L502 assume 1 == ~t6_pc~0; 12482#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12020#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12021#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12225#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 12422#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12631#L521 assume !(1 == ~t7_pc~0); 12662#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11956#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11957#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12656#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12635#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12571#L869 assume !(1 == ~M_E~0); 12276#L869-2 assume !(1 == ~T1_E~0); 12277#L874-1 assume !(1 == ~T2_E~0); 12690#L879-1 assume !(1 == ~T3_E~0); 12351#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11876#L889-1 assume !(1 == ~T5_E~0); 11877#L894-1 assume !(1 == ~T6_E~0); 12139#L899-1 assume !(1 == ~T7_E~0); 12533#L904-1 assume !(1 == ~E_M~0); 12300#L909-1 assume !(1 == ~E_1~0); 12301#L914-1 assume !(1 == ~E_2~0); 12470#L919-1 assume !(1 == ~E_3~0); 12216#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 12053#L929-1 assume !(1 == ~E_5~0); 12054#L934-1 assume !(1 == ~E_6~0); 12278#L939-1 assume !(1 == ~E_7~0); 12279#L944-1 assume { :end_inline_reset_delta_events } true; 12122#L1190-2 [2023-11-19 07:39:52,603 INFO L750 eck$LassoCheckResult]: Loop: 12122#L1190-2 assume !false; 12133#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12134#L756-1 assume !false; 12135#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12708#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11973#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12264#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12265#L653 assume !(0 != eval_~tmp~0#1); 12316#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12395#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12396#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11993#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11994#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12322#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11939#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11940#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12202#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12203#L811-3 assume !(0 == ~T7_E~0); 12397#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12594#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12683#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12537#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12538#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12093#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12094#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12421#L851-3 assume !(0 == ~E_7~0); 11987#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11988#L388-27 assume 1 == ~m_pc~0; 12657#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12658#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12561#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12562#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12166#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12167#L407-27 assume 1 == ~t1_pc~0; 12545#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12546#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12464#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12465#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 12438#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12084#L426-27 assume 1 == ~t2_pc~0; 12085#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12098#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12099#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12539#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12654#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12389#L445-27 assume 1 == ~t3_pc~0; 12363#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11936#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11937#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12390#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12475#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12192#L464-27 assume 1 == ~t4_pc~0; 12193#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11935#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12006#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12319#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12077#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12078#L483-27 assume 1 == ~t5_pc~0; 12613#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11989#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11990#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12626#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12627#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12694#L502-27 assume 1 == ~t6_pc~0; 12695#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12416#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12691#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12567#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12568#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11878#L521-27 assume 1 == ~t7_pc~0; 11879#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12230#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12178#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11932#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11933#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12428#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12564#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12320#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12321#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12381#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12374#L889-3 assume !(1 == ~T5_E~0); 12043#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12044#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12064#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12065#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12022#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12023#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12059#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12551#L929-3 assume !(1 == ~E_5~0); 12472#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12473#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12069#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12070#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11898#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12189#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 12190#L1209 assume !(0 == start_simulation_~tmp~3#1); 12411#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12394#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 12037#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11927#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 11928#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 11923#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11924#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 12121#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 12122#L1190-2 [2023-11-19 07:39:52,604 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:52,604 INFO L85 PathProgramCache]: Analyzing trace with hash -718887553, now seen corresponding path program 1 times [2023-11-19 07:39:52,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:52,604 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1080824275] [2023-11-19 07:39:52,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:52,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:52,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:52,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:52,690 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:52,690 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1080824275] [2023-11-19 07:39:52,690 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1080824275] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:52,690 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:52,690 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:39:52,690 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1661593451] [2023-11-19 07:39:52,691 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:52,691 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:39:52,691 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:52,692 INFO L85 PathProgramCache]: Analyzing trace with hash -2135531812, now seen corresponding path program 2 times [2023-11-19 07:39:52,692 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:52,692 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [437071175] [2023-11-19 07:39:52,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:52,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:52,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:52,742 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:52,743 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:52,743 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [437071175] [2023-11-19 07:39:52,743 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [437071175] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:52,743 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:52,743 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:39:52,743 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [978078257] [2023-11-19 07:39:52,744 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:52,744 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:39:52,744 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:39:52,744 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:39:52,744 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:39:52,745 INFO L87 Difference]: Start difference. First operand 843 states and 1251 transitions. cyclomatic complexity: 409 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:52,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:39:52,868 INFO L93 Difference]: Finished difference Result 1525 states and 2254 transitions. [2023-11-19 07:39:52,868 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1525 states and 2254 transitions. [2023-11-19 07:39:52,883 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1406 [2023-11-19 07:39:52,896 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1525 states to 1525 states and 2254 transitions. [2023-11-19 07:39:52,896 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1525 [2023-11-19 07:39:52,898 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1525 [2023-11-19 07:39:52,898 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1525 states and 2254 transitions. [2023-11-19 07:39:52,900 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:39:52,901 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1525 states and 2254 transitions. [2023-11-19 07:39:52,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1525 states and 2254 transitions. [2023-11-19 07:39:52,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1525 to 1525. [2023-11-19 07:39:52,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1525 states, 1525 states have (on average 1.4780327868852459) internal successors, (2254), 1524 states have internal predecessors, (2254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:52,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1525 states to 1525 states and 2254 transitions. [2023-11-19 07:39:52,975 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1525 states and 2254 transitions. [2023-11-19 07:39:52,975 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:39:52,976 INFO L428 stractBuchiCegarLoop]: Abstraction has 1525 states and 2254 transitions. [2023-11-19 07:39:52,976 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-19 07:39:52,976 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1525 states and 2254 transitions. [2023-11-19 07:39:52,986 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1406 [2023-11-19 07:39:52,987 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:39:52,987 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:39:52,989 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:52,989 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:52,989 INFO L748 eck$LassoCheckResult]: Stem: 14498#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 14499#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 15072#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15073#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15121#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 14642#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14643#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14769#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14770#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14542#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14332#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14333#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14503#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14504#L781 assume !(0 == ~M_E~0); 15005#L781-2 assume !(0 == ~T1_E~0); 15127#L786-1 assume !(0 == ~T2_E~0); 14292#L791-1 assume !(0 == ~T3_E~0); 14293#L796-1 assume !(0 == ~T4_E~0); 14843#L801-1 assume !(0 == ~T5_E~0); 14844#L806-1 assume !(0 == ~T6_E~0); 14876#L811-1 assume !(0 == ~T7_E~0); 14510#L816-1 assume !(0 == ~E_M~0); 14511#L821-1 assume !(0 == ~E_1~0); 14323#L826-1 assume !(0 == ~E_2~0); 14324#L831-1 assume !(0 == ~E_3~0); 14637#L836-1 assume !(0 == ~E_4~0); 14638#L841-1 assume !(0 == ~E_5~0); 14460#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 14461#L851-1 assume !(0 == ~E_7~0); 14484#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14485#L388 assume !(1 == ~m_pc~0); 14478#L388-2 is_master_triggered_~__retres1~0#1 := 0; 14479#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14981#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14338#L967 assume !(0 != activate_threads_~tmp~1#1); 14339#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14268#L407 assume 1 == ~t1_pc~0; 14269#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14273#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14274#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14309#L975 assume !(0 != activate_threads_~tmp___0~0#1); 15070#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14596#L426 assume !(1 == ~t2_pc~0); 14597#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15089#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14619#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14620#L983 assume !(0 != activate_threads_~tmp___1~0#1); 15116#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14684#L445 assume 1 == ~t3_pc~0; 14685#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15011#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14266#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14267#L991 assume !(0 != activate_threads_~tmp___2~0#1); 14942#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14908#L464 assume !(1 == ~t4_pc~0); 14488#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14358#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14359#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14370#L999 assume !(0 != activate_threads_~tmp___3~0#1); 14662#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14663#L483 assume 1 == ~t5_pc~0; 14904#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15053#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15024#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15025#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 14579#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14580#L502 assume 1 == ~t6_pc~0; 14873#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14398#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14399#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14605#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 14809#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15036#L521 assume !(1 == ~t7_pc~0); 15067#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 14334#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14335#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15061#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15040#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14970#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 14656#L869-2 assume !(1 == ~T1_E~0); 14657#L874-1 assume !(1 == ~T2_E~0); 15101#L879-1 assume !(1 == ~T3_E~0); 14734#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14254#L889-1 assume !(1 == ~T5_E~0); 14255#L894-1 assume !(1 == ~T6_E~0); 14518#L899-1 assume !(1 == ~T7_E~0); 14930#L904-1 assume !(1 == ~E_M~0); 14681#L909-1 assume !(1 == ~E_1~0); 14682#L914-1 assume !(1 == ~E_2~0); 14860#L919-1 assume !(1 == ~E_3~0); 14595#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 14431#L929-1 assume !(1 == ~E_5~0); 14432#L934-1 assume !(1 == ~E_6~0); 15105#L939-1 assume !(1 == ~E_7~0); 15035#L944-1 assume { :end_inline_reset_delta_events } true; 14501#L1190-2 [2023-11-19 07:39:52,990 INFO L750 eck$LassoCheckResult]: Loop: 14501#L1190-2 assume !false; 15139#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15138#L756-1 assume !false; 15137#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15136#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14899#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14900#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14696#L653 assume !(0 != eval_~tmp~0#1); 14698#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14780#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14781#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14371#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14372#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14704#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14317#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14318#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14581#L806-3 assume !(0 == ~T6_E~0); 14582#L811-3 assume !(0 == ~T7_E~0); 14782#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14997#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15090#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14935#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14936#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14471#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14472#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14808#L851-3 assume !(0 == ~E_7~0); 14365#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14366#L388-27 assume 1 == ~m_pc~0; 15062#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15063#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14959#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14960#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14545#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14546#L407-27 assume !(1 == ~t1_pc~0); 14945#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 14944#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14854#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14855#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 14826#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14462#L426-27 assume !(1 == ~t2_pc~0); 14464#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 14476#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14477#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14937#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15059#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14774#L445-27 assume 1 == ~t3_pc~0; 14746#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14314#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14315#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14775#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14866#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14571#L464-27 assume !(1 == ~t4_pc~0); 14312#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 14313#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14384#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14701#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14455#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14456#L483-27 assume 1 == ~t5_pc~0; 15016#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14367#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14368#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15029#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15030#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15107#L502-27 assume !(1 == ~t6_pc~0); 14802#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 14803#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15102#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14965#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14966#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14256#L521-27 assume 1 == ~t7_pc~0; 14257#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14610#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14557#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14310#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14311#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14816#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14962#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14702#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14703#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14764#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14757#L889-3 assume !(1 == ~T5_E~0); 14421#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14422#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14442#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14443#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14400#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14401#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14437#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14949#L929-3 assume !(1 == ~E_5~0); 14863#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14864#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14447#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14448#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14276#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15211#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 15209#L1209 assume !(0 == start_simulation_~tmp~3#1); 14796#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14797#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 15146#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15145#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 15144#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 15143#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15142#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 14500#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 14501#L1190-2 [2023-11-19 07:39:52,990 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:52,991 INFO L85 PathProgramCache]: Analyzing trace with hash -1207876549, now seen corresponding path program 1 times [2023-11-19 07:39:52,991 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:52,991 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1289000745] [2023-11-19 07:39:52,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:52,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:53,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:53,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:53,061 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:53,061 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1289000745] [2023-11-19 07:39:53,061 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1289000745] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:53,061 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:53,062 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:39:53,062 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [476534664] [2023-11-19 07:39:53,062 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:53,062 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:39:53,063 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:53,063 INFO L85 PathProgramCache]: Analyzing trace with hash -1171889826, now seen corresponding path program 1 times [2023-11-19 07:39:53,063 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:53,063 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1994554340] [2023-11-19 07:39:53,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:53,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:53,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:53,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:53,114 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:53,114 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1994554340] [2023-11-19 07:39:53,114 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1994554340] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:53,114 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:53,114 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:39:53,115 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1423407515] [2023-11-19 07:39:53,115 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:53,115 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:39:53,115 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:39:53,116 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:39:53,116 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:39:53,116 INFO L87 Difference]: Start difference. First operand 1525 states and 2254 transitions. cyclomatic complexity: 731 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:53,284 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:39:53,284 INFO L93 Difference]: Finished difference Result 2755 states and 4059 transitions. [2023-11-19 07:39:53,284 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2755 states and 4059 transitions. [2023-11-19 07:39:53,309 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2622 [2023-11-19 07:39:53,333 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2755 states to 2755 states and 4059 transitions. [2023-11-19 07:39:53,334 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2755 [2023-11-19 07:39:53,337 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2755 [2023-11-19 07:39:53,337 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2755 states and 4059 transitions. [2023-11-19 07:39:53,341 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:39:53,341 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2755 states and 4059 transitions. [2023-11-19 07:39:53,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2755 states and 4059 transitions. [2023-11-19 07:39:53,388 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2755 to 2753. [2023-11-19 07:39:53,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2753 states, 2753 states have (on average 1.473665092626226) internal successors, (4057), 2752 states have internal predecessors, (4057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:53,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2753 states to 2753 states and 4057 transitions. [2023-11-19 07:39:53,408 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2753 states and 4057 transitions. [2023-11-19 07:39:53,409 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:39:53,409 INFO L428 stractBuchiCegarLoop]: Abstraction has 2753 states and 4057 transitions. [2023-11-19 07:39:53,410 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-19 07:39:53,410 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2753 states and 4057 transitions. [2023-11-19 07:39:53,424 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2622 [2023-11-19 07:39:53,424 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:39:53,424 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:39:53,426 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:53,426 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:53,426 INFO L748 eck$LassoCheckResult]: Stem: 18788#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 18789#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 19365#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19366#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19415#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 18933#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18934#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19061#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19062#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18833#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18622#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 18623#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18796#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18797#L781 assume !(0 == ~M_E~0); 19290#L781-2 assume !(0 == ~T1_E~0); 19420#L786-1 assume !(0 == ~T2_E~0); 18585#L791-1 assume !(0 == ~T3_E~0); 18586#L796-1 assume !(0 == ~T4_E~0); 19135#L801-1 assume !(0 == ~T5_E~0); 19136#L806-1 assume !(0 == ~T6_E~0); 19167#L811-1 assume !(0 == ~T7_E~0); 18800#L816-1 assume !(0 == ~E_M~0); 18801#L821-1 assume !(0 == ~E_1~0); 18613#L826-1 assume !(0 == ~E_2~0); 18614#L831-1 assume !(0 == ~E_3~0); 18928#L836-1 assume !(0 == ~E_4~0); 18929#L841-1 assume !(0 == ~E_5~0); 18751#L846-1 assume !(0 == ~E_6~0); 18752#L851-1 assume !(0 == ~E_7~0); 18775#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18776#L388 assume !(1 == ~m_pc~0); 18769#L388-2 is_master_triggered_~__retres1~0#1 := 0; 18770#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19265#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18628#L967 assume !(0 != activate_threads_~tmp~1#1); 18629#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18558#L407 assume 1 == ~t1_pc~0; 18559#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18566#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18567#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18601#L975 assume !(0 != activate_threads_~tmp___0~0#1); 19363#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18888#L426 assume !(1 == ~t2_pc~0); 18889#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19385#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18910#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18911#L983 assume !(0 != activate_threads_~tmp___1~0#1); 19410#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18977#L445 assume 1 == ~t3_pc~0; 18978#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19300#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18556#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18557#L991 assume !(0 != activate_threads_~tmp___2~0#1); 19228#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19195#L464 assume !(1 == ~t4_pc~0); 18779#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18648#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18649#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18660#L999 assume !(0 != activate_threads_~tmp___3~0#1); 18955#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18956#L483 assume 1 == ~t5_pc~0; 19191#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19345#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19315#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19316#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 18871#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18872#L502 assume 1 == ~t6_pc~0; 19165#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18688#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18689#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18898#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 19102#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19325#L521 assume !(1 == ~t7_pc~0); 19360#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18624#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18625#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19354#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19332#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19257#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 19258#L869-2 assume !(1 == ~T1_E~0); 19591#L874-1 assume !(1 == ~T2_E~0); 19590#L879-1 assume !(1 == ~T3_E~0); 19589#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19588#L889-1 assume !(1 == ~T5_E~0); 19587#L894-1 assume !(1 == ~T6_E~0); 19585#L899-1 assume !(1 == ~T7_E~0); 19583#L904-1 assume !(1 == ~E_M~0); 19582#L909-1 assume !(1 == ~E_1~0); 19581#L914-1 assume !(1 == ~E_2~0); 19580#L919-1 assume !(1 == ~E_3~0); 19543#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 19541#L929-1 assume !(1 == ~E_5~0); 19540#L934-1 assume !(1 == ~E_6~0); 19537#L939-1 assume !(1 == ~E_7~0); 19450#L944-1 assume { :end_inline_reset_delta_events } true; 19444#L1190-2 [2023-11-19 07:39:53,427 INFO L750 eck$LassoCheckResult]: Loop: 19444#L1190-2 assume !false; 19440#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19439#L756-1 assume !false; 19438#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19437#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19429#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19428#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19426#L653 assume !(0 != eval_~tmp~0#1); 19425#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19424#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19422#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19423#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19997#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19996#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19995#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19994#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19993#L806-3 assume !(0 == ~T6_E~0); 19941#L811-3 assume !(0 == ~T7_E~0); 19939#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19937#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19935#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19934#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19932#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19930#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19928#L846-3 assume !(0 == ~E_6~0); 19927#L851-3 assume !(0 == ~E_7~0); 19926#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19925#L388-27 assume !(1 == ~m_pc~0); 19922#L388-29 is_master_triggered_~__retres1~0#1 := 0; 19920#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19918#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19916#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19915#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19913#L407-27 assume 1 == ~t1_pc~0; 19910#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19908#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19905#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19862#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 19859#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19857#L426-27 assume 1 == ~t2_pc~0; 19854#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19851#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19849#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19847#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19845#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19843#L445-27 assume !(1 == ~t3_pc~0); 19815#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 19813#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19770#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19768#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19766#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19764#L464-27 assume 1 == ~t4_pc~0; 19760#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19758#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19756#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19754#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19752#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19750#L483-27 assume !(1 == ~t5_pc~0); 19723#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 19721#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19719#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19717#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19715#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19714#L502-27 assume 1 == ~t6_pc~0; 19712#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19711#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19664#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19663#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19636#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19633#L521-27 assume !(1 == ~t7_pc~0); 19630#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 19628#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19626#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19607#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19593#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19550#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19390#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19546#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19544#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19529#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19526#L889-3 assume !(1 == ~T5_E~0); 19524#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18712#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19518#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19515#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19511#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19508#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19505#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19502#L929-3 assume !(1 == ~E_5~0); 19499#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19495#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19492#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19486#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19480#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19478#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 19476#L1209 assume !(0 == start_simulation_~tmp~3#1); 19103#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19469#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19463#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19461#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 19459#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 19455#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19453#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 19451#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 19444#L1190-2 [2023-11-19 07:39:53,428 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:53,428 INFO L85 PathProgramCache]: Analyzing trace with hash -253936391, now seen corresponding path program 1 times [2023-11-19 07:39:53,428 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:53,428 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [593704652] [2023-11-19 07:39:53,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:53,429 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:53,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:53,533 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:53,533 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:53,533 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [593704652] [2023-11-19 07:39:53,534 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [593704652] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:53,534 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:53,534 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:39:53,534 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1734200643] [2023-11-19 07:39:53,534 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:53,535 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:39:53,535 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:53,535 INFO L85 PathProgramCache]: Analyzing trace with hash 601568924, now seen corresponding path program 1 times [2023-11-19 07:39:53,535 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:53,536 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [106126293] [2023-11-19 07:39:53,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:53,536 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:53,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:53,585 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:53,585 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:53,586 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [106126293] [2023-11-19 07:39:53,586 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [106126293] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:53,586 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:53,586 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:39:53,586 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [841172057] [2023-11-19 07:39:53,586 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:53,587 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:39:53,587 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:39:53,587 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:39:53,588 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:39:53,588 INFO L87 Difference]: Start difference. First operand 2753 states and 4057 transitions. cyclomatic complexity: 1308 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:53,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:39:53,870 INFO L93 Difference]: Finished difference Result 7594 states and 11014 transitions. [2023-11-19 07:39:53,870 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7594 states and 11014 transitions. [2023-11-19 07:39:53,923 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7213 [2023-11-19 07:39:53,986 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7594 states to 7594 states and 11014 transitions. [2023-11-19 07:39:53,986 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7594 [2023-11-19 07:39:53,994 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7594 [2023-11-19 07:39:53,995 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7594 states and 11014 transitions. [2023-11-19 07:39:54,005 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:39:54,005 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7594 states and 11014 transitions. [2023-11-19 07:39:54,014 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7594 states and 11014 transitions. [2023-11-19 07:39:54,197 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7594 to 7162. [2023-11-19 07:39:54,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7162 states, 7162 states have (on average 1.4551801172856744) internal successors, (10422), 7161 states have internal predecessors, (10422), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:54,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7162 states to 7162 states and 10422 transitions. [2023-11-19 07:39:54,242 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7162 states and 10422 transitions. [2023-11-19 07:39:54,243 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:39:54,243 INFO L428 stractBuchiCegarLoop]: Abstraction has 7162 states and 10422 transitions. [2023-11-19 07:39:54,243 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-19 07:39:54,243 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7162 states and 10422 transitions. [2023-11-19 07:39:54,275 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7013 [2023-11-19 07:39:54,276 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:39:54,276 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:39:54,277 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:54,278 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:54,278 INFO L748 eck$LassoCheckResult]: Stem: 29149#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 29150#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 29817#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29818#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29918#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 29302#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29303#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29434#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29435#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29197#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28977#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 28978#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29154#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29155#L781 assume !(0 == ~M_E~0); 29717#L781-2 assume !(0 == ~T1_E~0); 29935#L786-1 assume !(0 == ~T2_E~0); 28937#L791-1 assume !(0 == ~T3_E~0); 28938#L796-1 assume !(0 == ~T4_E~0); 29520#L801-1 assume !(0 == ~T5_E~0); 29521#L806-1 assume !(0 == ~T6_E~0); 29560#L811-1 assume !(0 == ~T7_E~0); 29162#L816-1 assume !(0 == ~E_M~0); 29163#L821-1 assume !(0 == ~E_1~0); 28968#L826-1 assume !(0 == ~E_2~0); 28969#L831-1 assume !(0 == ~E_3~0); 29297#L836-1 assume !(0 == ~E_4~0); 29298#L841-1 assume !(0 == ~E_5~0); 29110#L846-1 assume !(0 == ~E_6~0); 29111#L851-1 assume !(0 == ~E_7~0); 29135#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29136#L388 assume !(1 == ~m_pc~0); 29129#L388-2 is_master_triggered_~__retres1~0#1 := 0; 29130#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29680#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 28983#L967 assume !(0 != activate_threads_~tmp~1#1); 28984#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28915#L407 assume !(1 == ~t1_pc~0); 28916#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28919#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28920#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28954#L975 assume !(0 != activate_threads_~tmp___0~0#1); 29815#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29255#L426 assume !(1 == ~t2_pc~0); 29256#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 29843#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29278#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29279#L983 assume !(0 != activate_threads_~tmp___1~0#1); 29898#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29345#L445 assume 1 == ~t3_pc~0; 29346#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29726#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28913#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28914#L991 assume !(0 != activate_threads_~tmp___2~0#1); 29631#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29590#L464 assume !(1 == ~t4_pc~0); 29139#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 29003#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29004#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29017#L999 assume !(0 != activate_threads_~tmp___3~0#1); 29322#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29323#L483 assume 1 == ~t5_pc~0; 29586#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29795#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29749#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29750#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 29237#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29238#L502 assume 1 == ~t6_pc~0; 29556#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29045#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29046#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29264#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 29477#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29768#L521 assume !(1 == ~t7_pc~0); 29812#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 28979#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28980#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29805#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29774#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29668#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 29669#L869-2 assume !(1 == ~T1_E~0); 33340#L874-1 assume !(1 == ~T2_E~0); 33339#L879-1 assume !(1 == ~T3_E~0); 33338#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33337#L889-1 assume !(1 == ~T5_E~0); 29170#L894-1 assume !(1 == ~T6_E~0); 29171#L899-1 assume !(1 == ~T7_E~0); 29614#L904-1 assume !(1 == ~E_M~0); 29342#L909-1 assume !(1 == ~E_1~0); 29343#L914-1 assume !(1 == ~E_2~0); 29541#L919-1 assume !(1 == ~E_3~0); 29253#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 29254#L929-1 assume !(1 == ~E_5~0); 34902#L934-1 assume !(1 == ~E_6~0); 29875#L939-1 assume !(1 == ~E_7~0); 34886#L944-1 assume { :end_inline_reset_delta_events } true; 34880#L1190-2 [2023-11-19 07:39:54,279 INFO L750 eck$LassoCheckResult]: Loop: 34880#L1190-2 assume !false; 34876#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34875#L756-1 assume !false; 34874#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 34873#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 34865#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 34864#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 34862#L653 assume !(0 != eval_~tmp~0#1); 34861#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34859#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34856#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34853#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34854#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34847#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34848#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31103#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 31104#L806-3 assume !(0 == ~T6_E~0); 31097#L811-3 assume !(0 == ~T7_E~0); 31094#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 31095#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35078#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35077#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35076#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 31082#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 31083#L846-3 assume !(0 == ~E_6~0); 31077#L851-3 assume !(0 == ~E_7~0); 31078#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29901#L388-27 assume !(1 == ~m_pc~0); 29902#L388-29 is_master_triggered_~__retres1~0#1 := 0; 35075#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29653#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 29654#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29878#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35073#L407-27 assume !(1 == ~t1_pc~0); 29867#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 29868#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29532#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 29533#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 35072#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35071#L426-27 assume 1 == ~t2_pc~0; 29862#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29127#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29128#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29876#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29877#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35069#L445-27 assume 1 == ~t3_pc~0; 29408#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29410#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29442#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29443#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29943#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35061#L464-27 assume 1 == ~t4_pc~0; 35059#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35058#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35057#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35056#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35055#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35054#L483-27 assume !(1 == ~t5_pc~0); 35052#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 35050#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35048#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35046#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 35044#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35042#L502-27 assume !(1 == ~t6_pc~0); 35040#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 35037#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35035#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35033#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35031#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35027#L521-27 assume !(1 == ~t7_pc~0); 35024#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 35021#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35019#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35017#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35015#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35013#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29852#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35009#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35007#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35005#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35003#L889-3 assume !(1 == ~T5_E~0); 35001#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33568#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34997#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 34995#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34993#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34991#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34989#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34987#L929-3 assume !(1 == ~E_5~0); 34984#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29544#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 34981#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 34969#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 34963#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 34961#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 34958#L1209 assume !(0 == start_simulation_~tmp~3#1); 31058#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 34943#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 34937#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 34935#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 34933#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 34903#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34894#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 34887#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 34880#L1190-2 [2023-11-19 07:39:54,280 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:54,280 INFO L85 PathProgramCache]: Analyzing trace with hash -1285267206, now seen corresponding path program 1 times [2023-11-19 07:39:54,280 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:54,280 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [985448375] [2023-11-19 07:39:54,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:54,281 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:54,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:54,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:54,347 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:54,347 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [985448375] [2023-11-19 07:39:54,347 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [985448375] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:54,347 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:54,348 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:39:54,348 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1992041912] [2023-11-19 07:39:54,348 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:54,348 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:39:54,349 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:54,349 INFO L85 PathProgramCache]: Analyzing trace with hash -807596195, now seen corresponding path program 1 times [2023-11-19 07:39:54,349 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:54,349 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [928858740] [2023-11-19 07:39:54,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:54,350 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:54,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:54,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:54,397 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:54,397 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [928858740] [2023-11-19 07:39:54,398 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [928858740] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:54,398 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:54,398 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:39:54,398 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [642208927] [2023-11-19 07:39:54,398 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:54,399 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:39:54,399 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:39:54,399 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:39:54,400 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:39:54,400 INFO L87 Difference]: Start difference. First operand 7162 states and 10422 transitions. cyclomatic complexity: 3268 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:54,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:39:54,850 INFO L93 Difference]: Finished difference Result 19967 states and 28719 transitions. [2023-11-19 07:39:54,850 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19967 states and 28719 transitions. [2023-11-19 07:39:54,979 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19263 [2023-11-19 07:39:55,073 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19967 states to 19967 states and 28719 transitions. [2023-11-19 07:39:55,073 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19967 [2023-11-19 07:39:55,094 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19967 [2023-11-19 07:39:55,094 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19967 states and 28719 transitions. [2023-11-19 07:39:55,203 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:39:55,203 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19967 states and 28719 transitions. [2023-11-19 07:39:55,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19967 states and 28719 transitions. [2023-11-19 07:39:55,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19967 to 19019. [2023-11-19 07:39:55,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19019 states, 19019 states have (on average 1.4429254955570745) internal successors, (27443), 19018 states have internal predecessors, (27443), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:55,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19019 states to 19019 states and 27443 transitions. [2023-11-19 07:39:55,653 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19019 states and 27443 transitions. [2023-11-19 07:39:55,653 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:39:55,654 INFO L428 stractBuchiCegarLoop]: Abstraction has 19019 states and 27443 transitions. [2023-11-19 07:39:55,654 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-19 07:39:55,654 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19019 states and 27443 transitions. [2023-11-19 07:39:55,721 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18831 [2023-11-19 07:39:55,721 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:39:55,721 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:39:55,723 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:55,723 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:55,723 INFO L748 eck$LassoCheckResult]: Stem: 56284#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 56285#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 56924#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 56925#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 57026#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 56434#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56435#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 56564#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56565#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56332#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 56114#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 56115#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 56289#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 56290#L781 assume !(0 == ~M_E~0); 56829#L781-2 assume !(0 == ~T1_E~0); 57048#L786-1 assume !(0 == ~T2_E~0); 56075#L791-1 assume !(0 == ~T3_E~0); 56076#L796-1 assume !(0 == ~T4_E~0); 56644#L801-1 assume !(0 == ~T5_E~0); 56645#L806-1 assume !(0 == ~T6_E~0); 56681#L811-1 assume !(0 == ~T7_E~0); 56296#L816-1 assume !(0 == ~E_M~0); 56297#L821-1 assume !(0 == ~E_1~0); 56106#L826-1 assume !(0 == ~E_2~0); 56107#L831-1 assume !(0 == ~E_3~0); 56429#L836-1 assume !(0 == ~E_4~0); 56430#L841-1 assume !(0 == ~E_5~0); 56246#L846-1 assume !(0 == ~E_6~0); 56247#L851-1 assume !(0 == ~E_7~0); 56270#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56271#L388 assume !(1 == ~m_pc~0); 56264#L388-2 is_master_triggered_~__retres1~0#1 := 0; 56265#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56797#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 56120#L967 assume !(0 != activate_threads_~tmp~1#1); 56121#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56054#L407 assume !(1 == ~t1_pc~0); 56055#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 56058#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56059#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 56092#L975 assume !(0 != activate_threads_~tmp___0~0#1); 56920#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56387#L426 assume !(1 == ~t2_pc~0); 56388#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 56947#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56409#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 56410#L983 assume !(0 != activate_threads_~tmp___1~0#1); 57009#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56476#L445 assume !(1 == ~t3_pc~0); 56477#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 56835#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56052#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 56053#L991 assume !(0 != activate_threads_~tmp___2~0#1); 56749#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56713#L464 assume !(1 == ~t4_pc~0); 56274#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 56140#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56141#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 56152#L999 assume !(0 != activate_threads_~tmp___3~0#1); 56455#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56456#L483 assume 1 == ~t5_pc~0; 56708#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56901#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56860#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56861#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 56369#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 56370#L502 assume 1 == ~t6_pc~0; 56678#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 56180#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 56181#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 56395#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 56605#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56877#L521 assume !(1 == ~t7_pc~0); 56917#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 56116#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 56117#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56910#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 56885#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56785#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 56447#L869-2 assume !(1 == ~T1_E~0); 56448#L874-1 assume !(1 == ~T2_E~0); 56966#L879-1 assume !(1 == ~T3_E~0); 56967#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56040#L889-1 assume !(1 == ~T5_E~0); 56041#L894-1 assume !(1 == ~T6_E~0); 57051#L899-1 assume !(1 == ~T7_E~0); 56734#L904-1 assume !(1 == ~E_M~0); 56473#L909-1 assume !(1 == ~E_1~0); 56474#L914-1 assume !(1 == ~E_2~0); 56664#L919-1 assume !(1 == ~E_3~0); 56386#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 56214#L929-1 assume !(1 == ~E_5~0); 56215#L934-1 assume !(1 == ~E_6~0); 60091#L939-1 assume !(1 == ~E_7~0); 60088#L944-1 assume { :end_inline_reset_delta_events } true; 60070#L1190-2 [2023-11-19 07:39:55,724 INFO L750 eck$LassoCheckResult]: Loop: 60070#L1190-2 assume !false; 60071#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 60029#L756-1 assume !false; 60030#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 59808#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 59798#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 59796#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 59793#L653 assume !(0 != eval_~tmp~0#1); 59794#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 61960#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 61959#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 61958#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 61957#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 61956#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 61955#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 61954#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 61953#L806-3 assume !(0 == ~T6_E~0); 61952#L811-3 assume !(0 == ~T7_E~0); 61951#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 61950#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 61949#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 61948#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 61947#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 61946#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 61945#L846-3 assume !(0 == ~E_6~0); 61944#L851-3 assume !(0 == ~E_7~0); 61943#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61942#L388-27 assume !(1 == ~m_pc~0); 61941#L388-29 is_master_triggered_~__retres1~0#1 := 0; 61940#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61939#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 61938#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 61937#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61936#L407-27 assume !(1 == ~t1_pc~0); 61935#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 61934#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61933#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 61932#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 61931#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61930#L426-27 assume 1 == ~t2_pc~0; 61928#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 61927#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61926#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 61925#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 61924#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61923#L445-27 assume !(1 == ~t3_pc~0); 61922#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 61921#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61920#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 61919#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 61918#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61917#L464-27 assume 1 == ~t4_pc~0; 61915#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 61914#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61913#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 61912#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 61911#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61909#L483-27 assume !(1 == ~t5_pc~0); 61907#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 61905#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 61903#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 61901#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 61899#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 61897#L502-27 assume 1 == ~t6_pc~0; 61894#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 61892#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 61890#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 61888#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 61886#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 61884#L521-27 assume !(1 == ~t7_pc~0); 61880#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 61878#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 61876#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 61874#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 61872#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61870#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 60628#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 61867#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 61865#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 61863#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 61861#L889-3 assume !(1 == ~T5_E~0); 61859#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 61856#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 61854#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 61852#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 61850#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 61848#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 61846#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 61843#L929-3 assume !(1 == ~E_5~0); 61840#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 60598#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 61835#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 61750#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 61744#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 61742#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 61739#L1209 assume !(0 == start_simulation_~tmp~3#1); 61735#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 60313#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 60306#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 60105#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 60100#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 60101#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 62202#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 62200#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 60070#L1190-2 [2023-11-19 07:39:55,724 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:55,725 INFO L85 PathProgramCache]: Analyzing trace with hash 1116257915, now seen corresponding path program 1 times [2023-11-19 07:39:55,725 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:55,725 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [585593974] [2023-11-19 07:39:55,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:55,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:55,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:55,900 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:55,900 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:55,900 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [585593974] [2023-11-19 07:39:55,900 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [585593974] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:55,901 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:55,901 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:39:55,901 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1997201602] [2023-11-19 07:39:55,901 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:55,902 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:39:55,902 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:55,902 INFO L85 PathProgramCache]: Analyzing trace with hash -1353752291, now seen corresponding path program 1 times [2023-11-19 07:39:55,902 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:55,903 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1110662687] [2023-11-19 07:39:55,903 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:55,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:55,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:55,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:55,950 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:55,951 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1110662687] [2023-11-19 07:39:55,951 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1110662687] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:55,951 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:55,951 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:39:55,951 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [488684873] [2023-11-19 07:39:55,952 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:55,952 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:39:55,952 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:39:55,952 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:39:55,953 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:39:55,953 INFO L87 Difference]: Start difference. First operand 19019 states and 27443 transitions. cyclomatic complexity: 8440 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:56,373 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:39:56,374 INFO L93 Difference]: Finished difference Result 36634 states and 52549 transitions. [2023-11-19 07:39:56,374 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36634 states and 52549 transitions. [2023-11-19 07:39:56,709 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36315 [2023-11-19 07:39:56,987 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36634 states to 36634 states and 52549 transitions. [2023-11-19 07:39:56,988 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 36634 [2023-11-19 07:39:57,090 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 36634 [2023-11-19 07:39:57,091 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36634 states and 52549 transitions. [2023-11-19 07:39:57,121 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:39:57,121 INFO L218 hiAutomatonCegarLoop]: Abstraction has 36634 states and 52549 transitions. [2023-11-19 07:39:57,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36634 states and 52549 transitions. [2023-11-19 07:39:57,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36634 to 36562. [2023-11-19 07:39:57,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36562 states, 36562 states have (on average 1.4352880039385154) internal successors, (52477), 36561 states have internal predecessors, (52477), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:57,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36562 states to 36562 states and 52477 transitions. [2023-11-19 07:39:57,776 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36562 states and 52477 transitions. [2023-11-19 07:39:57,776 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:39:57,778 INFO L428 stractBuchiCegarLoop]: Abstraction has 36562 states and 52477 transitions. [2023-11-19 07:39:57,778 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-19 07:39:57,778 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36562 states and 52477 transitions. [2023-11-19 07:39:58,087 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36243 [2023-11-19 07:39:58,087 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:39:58,088 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:39:58,090 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:58,090 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:39:58,090 INFO L748 eck$LassoCheckResult]: Stem: 111942#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 111943#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 112547#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 112548#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 112630#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 112085#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 112086#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 112215#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 112216#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 111987#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 111774#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 111775#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 111947#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 111948#L781 assume !(0 == ~M_E~0); 112464#L781-2 assume !(0 == ~T1_E~0); 112643#L786-1 assume !(0 == ~T2_E~0); 111735#L791-1 assume !(0 == ~T3_E~0); 111736#L796-1 assume !(0 == ~T4_E~0); 112290#L801-1 assume !(0 == ~T5_E~0); 112291#L806-1 assume !(0 == ~T6_E~0); 112331#L811-1 assume !(0 == ~T7_E~0); 111954#L816-1 assume !(0 == ~E_M~0); 111955#L821-1 assume !(0 == ~E_1~0); 111766#L826-1 assume !(0 == ~E_2~0); 111767#L831-1 assume !(0 == ~E_3~0); 112080#L836-1 assume !(0 == ~E_4~0); 112081#L841-1 assume !(0 == ~E_5~0); 111904#L846-1 assume !(0 == ~E_6~0); 111905#L851-1 assume !(0 == ~E_7~0); 111928#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 111929#L388 assume !(1 == ~m_pc~0); 111922#L388-2 is_master_triggered_~__retres1~0#1 := 0; 111923#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 112437#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 111780#L967 assume !(0 != activate_threads_~tmp~1#1); 111781#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 111714#L407 assume !(1 == ~t1_pc~0); 111715#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 111718#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 111719#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 111752#L975 assume !(0 != activate_threads_~tmp___0~0#1); 112544#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112041#L426 assume !(1 == ~t2_pc~0); 112042#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 112568#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 112063#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 112064#L983 assume !(0 != activate_threads_~tmp___1~0#1); 112617#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 112125#L445 assume !(1 == ~t3_pc~0); 112126#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 112471#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 111712#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 111713#L991 assume !(0 != activate_threads_~tmp___2~0#1); 112397#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 112363#L464 assume !(1 == ~t4_pc~0); 111932#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 111800#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 111801#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 111812#L999 assume !(0 != activate_threads_~tmp___3~0#1); 112104#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 112105#L483 assume !(1 == ~t5_pc~0); 112360#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 112525#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 112486#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 112487#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 112023#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 112024#L502 assume 1 == ~t6_pc~0; 112328#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 111840#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 111841#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 112049#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 112254#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 112501#L521 assume !(1 == ~t7_pc~0); 112541#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 111776#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 111777#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 112535#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 112507#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 112426#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 112427#L869-2 assume !(1 == ~T1_E~0); 112613#L874-1 assume !(1 == ~T2_E~0); 112614#L879-1 assume !(1 == ~T3_E~0); 112175#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 112176#L889-1 assume !(1 == ~T5_E~0); 111962#L894-1 assume !(1 == ~T6_E~0); 111963#L899-1 assume !(1 == ~T7_E~0); 112647#L904-1 assume !(1 == ~E_M~0); 112122#L909-1 assume !(1 == ~E_1~0); 112123#L914-1 assume !(1 == ~E_2~0); 112340#L919-1 assume !(1 == ~E_3~0); 112341#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 111874#L929-1 assume !(1 == ~E_5~0); 111875#L934-1 assume !(1 == ~E_6~0); 112593#L939-1 assume !(1 == ~E_7~0); 119107#L944-1 assume { :end_inline_reset_delta_events } true; 119108#L1190-2 [2023-11-19 07:39:58,091 INFO L750 eck$LassoCheckResult]: Loop: 119108#L1190-2 assume !false; 138348#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 138347#L756-1 assume !false; 138346#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 138345#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 138337#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 138336#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 138334#L653 assume !(0 != eval_~tmp~0#1); 138335#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 138648#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 138647#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 138646#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 138645#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 138644#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 138643#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 138642#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 138641#L806-3 assume !(0 == ~T6_E~0); 138640#L811-3 assume !(0 == ~T7_E~0); 138639#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 138638#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 138637#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 138636#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 138635#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 138634#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 138633#L846-3 assume !(0 == ~E_6~0); 138632#L851-3 assume !(0 == ~E_7~0); 138631#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 138630#L388-27 assume !(1 == ~m_pc~0); 138629#L388-29 is_master_triggered_~__retres1~0#1 := 0; 138628#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 138627#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 138626#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 138625#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 138624#L407-27 assume !(1 == ~t1_pc~0); 138623#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 138622#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 138621#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 138620#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 138619#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 138618#L426-27 assume 1 == ~t2_pc~0; 138616#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 138615#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 138614#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 138613#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 138612#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 138611#L445-27 assume !(1 == ~t3_pc~0); 138610#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 138609#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 138608#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 138607#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 138606#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 138605#L464-27 assume 1 == ~t4_pc~0; 138603#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 138602#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 138601#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 138600#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 138599#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 138598#L483-27 assume !(1 == ~t5_pc~0); 138597#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 138596#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 138595#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 138594#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 138593#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 138592#L502-27 assume 1 == ~t6_pc~0; 138590#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 138589#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 138588#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 138587#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 138586#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 138585#L521-27 assume !(1 == ~t7_pc~0); 138583#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 138582#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 138581#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 138580#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 138579#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 138578#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 132240#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 138577#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 138576#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 138575#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 138574#L889-3 assume !(1 == ~T5_E~0); 138573#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 136045#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 138572#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 138571#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 138570#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 138569#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 138568#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 138567#L929-3 assume !(1 == ~E_5~0); 138566#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 132223#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 138565#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 138561#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 138556#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 138555#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 138554#L1209 assume !(0 == start_simulation_~tmp~3#1); 138552#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 138548#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 138543#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 138542#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 138541#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 138540#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 138539#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 138538#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 119108#L1190-2 [2023-11-19 07:39:58,092 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:58,092 INFO L85 PathProgramCache]: Analyzing trace with hash -2127260292, now seen corresponding path program 1 times [2023-11-19 07:39:58,092 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:58,092 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [884392272] [2023-11-19 07:39:58,093 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:58,093 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:58,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:58,184 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:58,184 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:58,185 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [884392272] [2023-11-19 07:39:58,185 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [884392272] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:58,185 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:58,185 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:39:58,186 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1051324570] [2023-11-19 07:39:58,186 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:58,187 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:39:58,187 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:39:58,188 INFO L85 PathProgramCache]: Analyzing trace with hash -1353752291, now seen corresponding path program 2 times [2023-11-19 07:39:58,188 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:39:58,188 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1265832711] [2023-11-19 07:39:58,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:39:58,189 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:39:58,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:39:58,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:39:58,248 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:39:58,248 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1265832711] [2023-11-19 07:39:58,248 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1265832711] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:39:58,249 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:39:58,249 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:39:58,249 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1621716633] [2023-11-19 07:39:58,249 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:39:58,250 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:39:58,250 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:39:58,251 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:39:58,251 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:39:58,252 INFO L87 Difference]: Start difference. First operand 36562 states and 52477 transitions. cyclomatic complexity: 15947 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:39:59,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:39:59,028 INFO L93 Difference]: Finished difference Result 100975 states and 143760 transitions. [2023-11-19 07:39:59,028 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100975 states and 143760 transitions. [2023-11-19 07:39:59,967 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 98145 [2023-11-19 07:40:00,469 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100975 states to 100975 states and 143760 transitions. [2023-11-19 07:40:00,469 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 100975 [2023-11-19 07:40:00,579 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 100975 [2023-11-19 07:40:00,580 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100975 states and 143760 transitions. [2023-11-19 07:40:00,716 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:40:00,716 INFO L218 hiAutomatonCegarLoop]: Abstraction has 100975 states and 143760 transitions. [2023-11-19 07:40:00,807 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100975 states and 143760 transitions. [2023-11-19 07:40:02,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100975 to 97687. [2023-11-19 07:40:02,252 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97687 states, 97687 states have (on average 1.4282350773388475) internal successors, (139520), 97686 states have internal predecessors, (139520), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:40:02,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97687 states to 97687 states and 139520 transitions. [2023-11-19 07:40:02,832 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97687 states and 139520 transitions. [2023-11-19 07:40:02,832 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:40:02,833 INFO L428 stractBuchiCegarLoop]: Abstraction has 97687 states and 139520 transitions. [2023-11-19 07:40:02,833 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-19 07:40:02,833 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97687 states and 139520 transitions. [2023-11-19 07:40:03,337 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 97065 [2023-11-19 07:40:03,338 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:40:03,338 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:40:03,340 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:40:03,340 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:40:03,340 INFO L748 eck$LassoCheckResult]: Stem: 249488#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 249489#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 250152#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 250153#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 250251#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 249643#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 249644#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 249772#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 249773#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 249533#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 249321#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 249322#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 249493#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 249494#L781 assume !(0 == ~M_E~0); 250038#L781-2 assume !(0 == ~T1_E~0); 250272#L786-1 assume !(0 == ~T2_E~0); 249282#L791-1 assume !(0 == ~T3_E~0); 249283#L796-1 assume !(0 == ~T4_E~0); 249853#L801-1 assume !(0 == ~T5_E~0); 249854#L806-1 assume !(0 == ~T6_E~0); 249890#L811-1 assume !(0 == ~T7_E~0); 249500#L816-1 assume !(0 == ~E_M~0); 249501#L821-1 assume !(0 == ~E_1~0); 249313#L826-1 assume !(0 == ~E_2~0); 249314#L831-1 assume !(0 == ~E_3~0); 249638#L836-1 assume !(0 == ~E_4~0); 249639#L841-1 assume !(0 == ~E_5~0); 249450#L846-1 assume !(0 == ~E_6~0); 249451#L851-1 assume !(0 == ~E_7~0); 249474#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 249475#L388 assume !(1 == ~m_pc~0); 249468#L388-2 is_master_triggered_~__retres1~0#1 := 0; 249469#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 250006#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 249327#L967 assume !(0 != activate_threads_~tmp~1#1); 249328#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 249261#L407 assume !(1 == ~t1_pc~0); 249262#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 249265#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 249266#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 249299#L975 assume !(0 != activate_threads_~tmp___0~0#1); 250146#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 249591#L426 assume !(1 == ~t2_pc~0); 249592#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 250175#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 249617#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 249618#L983 assume !(0 != activate_threads_~tmp___1~0#1); 250229#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 249685#L445 assume !(1 == ~t3_pc~0); 249686#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 250046#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 249259#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 249260#L991 assume !(0 != activate_threads_~tmp___2~0#1); 249960#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 249920#L464 assume !(1 == ~t4_pc~0); 249478#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 249347#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 249348#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 249359#L999 assume !(0 != activate_threads_~tmp___3~0#1); 249664#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 249665#L483 assume !(1 == ~t5_pc~0); 249917#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 250124#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 250072#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 250073#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 249574#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 249575#L502 assume !(1 == ~t6_pc~0); 249428#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 249387#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 249388#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 249602#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 249814#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 250093#L521 assume !(1 == ~t7_pc~0); 250139#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 249323#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 249324#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 250133#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 250103#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 249994#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 249995#L869-2 assume !(1 == ~T1_E~0); 250223#L874-1 assume !(1 == ~T2_E~0); 250224#L879-1 assume !(1 == ~T3_E~0); 249735#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 249736#L889-1 assume !(1 == ~T5_E~0); 249508#L894-1 assume !(1 == ~T6_E~0); 249509#L899-1 assume !(1 == ~T7_E~0); 250279#L904-1 assume !(1 == ~E_M~0); 249682#L909-1 assume !(1 == ~E_1~0); 249683#L914-1 assume !(1 == ~E_2~0); 249900#L919-1 assume !(1 == ~E_3~0); 249901#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 249421#L929-1 assume !(1 == ~E_5~0); 249422#L934-1 assume !(1 == ~E_6~0); 249660#L939-1 assume !(1 == ~E_7~0); 249661#L944-1 assume { :end_inline_reset_delta_events } true; 297506#L1190-2 [2023-11-19 07:40:03,341 INFO L750 eck$LassoCheckResult]: Loop: 297506#L1190-2 assume !false; 297483#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 297480#L756-1 assume !false; 297477#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 297474#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 297466#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 297465#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 297463#L653 assume !(0 != eval_~tmp~0#1); 297464#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 297916#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 297914#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 297912#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 297910#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 297908#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 297906#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 297904#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 297902#L806-3 assume !(0 == ~T6_E~0); 297900#L811-3 assume !(0 == ~T7_E~0); 297898#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 297896#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 297894#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 297892#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 297890#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 297888#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 297886#L846-3 assume !(0 == ~E_6~0); 297884#L851-3 assume !(0 == ~E_7~0); 297882#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 297880#L388-27 assume !(1 == ~m_pc~0); 297878#L388-29 is_master_triggered_~__retres1~0#1 := 0; 297876#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 297874#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 297872#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 297869#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 297867#L407-27 assume !(1 == ~t1_pc~0); 297865#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 297863#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 297861#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 297859#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 297857#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 297855#L426-27 assume 1 == ~t2_pc~0; 297852#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 297850#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 297848#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 297846#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 297843#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 297841#L445-27 assume !(1 == ~t3_pc~0); 297839#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 297837#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 297835#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 297833#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 297831#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 297829#L464-27 assume 1 == ~t4_pc~0; 297826#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 297824#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 297822#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 297820#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 297819#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 297817#L483-27 assume !(1 == ~t5_pc~0); 297815#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 297813#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 297811#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 297809#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 297806#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 297804#L502-27 assume !(1 == ~t6_pc~0); 297802#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 297800#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 297798#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 297797#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 297796#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 297795#L521-27 assume !(1 == ~t7_pc~0); 297792#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 297790#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 297788#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 297786#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 297784#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 297783#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 292420#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 297778#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 297776#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 297774#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 297772#L889-3 assume !(1 == ~T5_E~0); 297770#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 292271#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 297769#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 297767#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 297765#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 297763#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 297761#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 297759#L929-3 assume !(1 == ~E_5~0); 297757#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 297752#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 297750#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 297609#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 297603#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 297600#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 297597#L1209 assume !(0 == start_simulation_~tmp~3#1); 297594#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 297573#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 297565#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 297560#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 297554#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 297551#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 297548#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 297507#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 297506#L1190-2 [2023-11-19 07:40:03,342 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:40:03,342 INFO L85 PathProgramCache]: Analyzing trace with hash 1196032317, now seen corresponding path program 1 times [2023-11-19 07:40:03,342 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:40:03,342 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [646151939] [2023-11-19 07:40:03,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:40:03,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:40:03,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:40:03,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:40:03,421 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:40:03,421 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [646151939] [2023-11-19 07:40:03,421 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [646151939] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:40:03,422 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:40:03,422 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:40:03,422 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1587383206] [2023-11-19 07:40:03,422 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:40:03,423 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:40:03,423 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:40:03,424 INFO L85 PathProgramCache]: Analyzing trace with hash -1838927010, now seen corresponding path program 1 times [2023-11-19 07:40:03,424 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:40:03,424 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2114135330] [2023-11-19 07:40:03,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:40:03,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:40:03,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:40:03,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:40:03,479 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:40:03,480 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2114135330] [2023-11-19 07:40:03,480 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2114135330] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:40:03,480 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:40:03,480 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:40:03,481 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1369619602] [2023-11-19 07:40:03,481 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:40:03,481 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:40:03,481 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:40:03,482 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 07:40:03,482 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 07:40:03,482 INFO L87 Difference]: Start difference. First operand 97687 states and 139520 transitions. cyclomatic complexity: 41897 Second operand has 5 states, 5 states have (on average 19.0) internal successors, (95), 5 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:40:04,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:40:04,541 INFO L93 Difference]: Finished difference Result 192794 states and 272676 transitions. [2023-11-19 07:40:04,541 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 192794 states and 272676 transitions. [2023-11-19 07:40:05,713 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 191626 [2023-11-19 07:40:07,033 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 192794 states to 192794 states and 272676 transitions. [2023-11-19 07:40:07,034 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 192794 [2023-11-19 07:40:07,115 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 192794 [2023-11-19 07:40:07,115 INFO L73 IsDeterministic]: Start isDeterministic. Operand 192794 states and 272676 transitions. [2023-11-19 07:40:07,243 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:40:07,243 INFO L218 hiAutomatonCegarLoop]: Abstraction has 192794 states and 272676 transitions. [2023-11-19 07:40:07,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 192794 states and 272676 transitions. [2023-11-19 07:40:08,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 192794 to 101446. [2023-11-19 07:40:08,635 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 101446 states, 101446 states have (on average 1.4123671707115115) internal successors, (143279), 101445 states have internal predecessors, (143279), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:40:09,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101446 states to 101446 states and 143279 transitions. [2023-11-19 07:40:09,340 INFO L240 hiAutomatonCegarLoop]: Abstraction has 101446 states and 143279 transitions. [2023-11-19 07:40:09,341 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-19 07:40:09,341 INFO L428 stractBuchiCegarLoop]: Abstraction has 101446 states and 143279 transitions. [2023-11-19 07:40:09,341 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-19 07:40:09,342 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 101446 states and 143279 transitions. [2023-11-19 07:40:09,590 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 100821 [2023-11-19 07:40:09,591 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:40:09,591 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:40:09,593 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:40:09,593 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:40:09,593 INFO L748 eck$LassoCheckResult]: Stem: 539981#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 539982#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 540645#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 540646#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 540753#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 540133#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 540134#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 540267#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 540268#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 540027#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 539815#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 539816#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 539989#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 539990#L781 assume !(0 == ~M_E~0); 540537#L781-2 assume !(0 == ~T1_E~0); 540776#L786-1 assume !(0 == ~T2_E~0); 539776#L791-1 assume !(0 == ~T3_E~0); 539777#L796-1 assume !(0 == ~T4_E~0); 540353#L801-1 assume !(0 == ~T5_E~0); 540354#L806-1 assume !(0 == ~T6_E~0); 540390#L811-1 assume !(0 == ~T7_E~0); 539993#L816-1 assume !(0 == ~E_M~0); 539994#L821-1 assume !(0 == ~E_1~0); 539807#L826-1 assume !(0 == ~E_2~0); 539808#L831-1 assume !(0 == ~E_3~0); 540128#L836-1 assume !(0 == ~E_4~0); 540129#L841-1 assume !(0 == ~E_5~0); 539943#L846-1 assume !(0 == ~E_6~0); 539944#L851-1 assume !(0 == ~E_7~0); 539967#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 539968#L388 assume !(1 == ~m_pc~0); 539961#L388-2 is_master_triggered_~__retres1~0#1 := 0; 539962#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 540509#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 539821#L967 assume !(0 != activate_threads_~tmp~1#1); 539822#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 539755#L407 assume !(1 == ~t1_pc~0); 539756#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 539762#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 539763#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 539793#L975 assume !(0 != activate_threads_~tmp___0~0#1); 540639#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 540082#L426 assume !(1 == ~t2_pc~0); 540083#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 540675#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 540109#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 540110#L983 assume !(0 != activate_threads_~tmp___1~0#1); 540733#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 540176#L445 assume !(1 == ~t3_pc~0); 540177#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 540546#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 539753#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 539754#L991 assume !(0 != activate_threads_~tmp___2~0#1); 540461#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 540422#L464 assume !(1 == ~t4_pc~0); 539971#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 539841#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 539842#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 539853#L999 assume !(0 != activate_threads_~tmp___3~0#1); 540155#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 540156#L483 assume !(1 == ~t5_pc~0); 540418#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 540615#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 540570#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 540571#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 540065#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 540066#L502 assume !(1 == ~t6_pc~0); 539922#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 539881#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 539882#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 540093#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 540309#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 540589#L521 assume !(1 == ~t7_pc~0); 540636#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 539817#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 539818#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 540629#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 540597#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 540498#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 540499#L869-2 assume !(1 == ~T1_E~0); 540725#L874-1 assume !(1 == ~T2_E~0); 540726#L879-1 assume !(1 == ~T3_E~0); 540226#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 540227#L889-1 assume !(1 == ~T5_E~0); 540004#L894-1 assume !(1 == ~T6_E~0); 540005#L899-1 assume !(1 == ~T7_E~0); 540450#L904-1 assume !(1 == ~E_M~0); 540451#L909-1 assume !(1 == ~E_1~0); 540372#L914-1 assume !(1 == ~E_2~0); 540373#L919-1 assume !(1 == ~E_3~0); 540080#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 540081#L929-1 assume !(1 == ~E_5~0); 540703#L934-1 assume !(1 == ~E_6~0); 540704#L939-1 assume !(1 == ~E_7~0); 540587#L944-1 assume { :end_inline_reset_delta_events } true; 540588#L1190-2 [2023-11-19 07:40:09,594 INFO L750 eck$LassoCheckResult]: Loop: 540588#L1190-2 assume !false; 620713#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 620706#L756-1 assume !false; 620700#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 620666#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 612617#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 612618#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 612560#L653 assume !(0 != eval_~tmp~0#1); 612562#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 623983#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 623982#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 623981#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 623980#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 623979#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 623978#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 623977#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 623976#L806-3 assume !(0 == ~T6_E~0); 623975#L811-3 assume !(0 == ~T7_E~0); 623974#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 623973#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 623972#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 623971#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 623970#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 623969#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 623968#L846-3 assume !(0 == ~E_6~0); 623967#L851-3 assume !(0 == ~E_7~0); 623966#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 623965#L388-27 assume !(1 == ~m_pc~0); 623964#L388-29 is_master_triggered_~__retres1~0#1 := 0; 623963#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 623962#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 623961#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 623960#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 623959#L407-27 assume !(1 == ~t1_pc~0); 623958#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 623957#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 623956#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 623955#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 623954#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 623953#L426-27 assume 1 == ~t2_pc~0; 623951#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 623950#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 623949#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 623948#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 623947#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 623946#L445-27 assume !(1 == ~t3_pc~0); 623945#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 623944#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 623943#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 623942#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 623941#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 623940#L464-27 assume !(1 == ~t4_pc~0); 623939#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 623937#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 623936#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 623935#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 623934#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 623933#L483-27 assume !(1 == ~t5_pc~0); 623932#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 623931#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 623930#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 623929#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 623928#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 623927#L502-27 assume !(1 == ~t6_pc~0); 623926#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 623925#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 623924#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 623923#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 623922#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 623921#L521-27 assume 1 == ~t7_pc~0; 623919#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 623917#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 623915#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 623913#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 622019#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 622015#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 578046#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 622008#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 622004#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 621999#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 621994#L889-3 assume !(1 == ~T5_E~0); 621981#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 578039#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 621976#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 621973#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 621970#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 621967#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 621964#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 621961#L929-3 assume !(1 == ~E_5~0); 621958#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 619725#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 621953#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 621947#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 621940#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 621937#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 621934#L1209 assume !(0 == start_simulation_~tmp~3#1); 621931#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 621864#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 621838#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 621654#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 620752#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 620750#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 620749#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 620748#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 540588#L1190-2 [2023-11-19 07:40:09,595 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:40:09,595 INFO L85 PathProgramCache]: Analyzing trace with hash -492911425, now seen corresponding path program 1 times [2023-11-19 07:40:09,595 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:40:09,595 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1110909407] [2023-11-19 07:40:09,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:40:09,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:40:09,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:40:09,683 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:40:09,683 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:40:09,684 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1110909407] [2023-11-19 07:40:09,684 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1110909407] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:40:09,684 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:40:09,684 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:40:09,685 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [772689954] [2023-11-19 07:40:09,685 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:40:09,685 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:40:09,686 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:40:09,686 INFO L85 PathProgramCache]: Analyzing trace with hash 1130812702, now seen corresponding path program 1 times [2023-11-19 07:40:09,686 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:40:09,686 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [914032607] [2023-11-19 07:40:09,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:40:09,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:40:09,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:40:09,739 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:40:09,739 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:40:09,740 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [914032607] [2023-11-19 07:40:09,740 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [914032607] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:40:09,740 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:40:09,740 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:40:09,740 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [460559270] [2023-11-19 07:40:09,740 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:40:09,741 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:40:09,741 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:40:09,741 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:40:09,742 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:40:09,742 INFO L87 Difference]: Start difference. First operand 101446 states and 143279 transitions. cyclomatic complexity: 41897 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:40:10,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:40:10,247 INFO L93 Difference]: Finished difference Result 127416 states and 180053 transitions. [2023-11-19 07:40:10,247 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 127416 states and 180053 transitions. [2023-11-19 07:40:11,405 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 126681 [2023-11-19 07:40:11,914 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 127416 states to 127416 states and 180053 transitions. [2023-11-19 07:40:11,916 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 127416 [2023-11-19 07:40:11,991 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 127416 [2023-11-19 07:40:11,991 INFO L73 IsDeterministic]: Start isDeterministic. Operand 127416 states and 180053 transitions. [2023-11-19 07:40:12,040 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:40:12,040 INFO L218 hiAutomatonCegarLoop]: Abstraction has 127416 states and 180053 transitions. [2023-11-19 07:40:12,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127416 states and 180053 transitions. [2023-11-19 07:40:12,776 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127416 to 55190. [2023-11-19 07:40:12,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55190 states, 55190 states have (on average 1.4188621127015764) internal successors, (78307), 55189 states have internal predecessors, (78307), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:40:13,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55190 states to 55190 states and 78307 transitions. [2023-11-19 07:40:13,610 INFO L240 hiAutomatonCegarLoop]: Abstraction has 55190 states and 78307 transitions. [2023-11-19 07:40:13,610 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:40:13,611 INFO L428 stractBuchiCegarLoop]: Abstraction has 55190 states and 78307 transitions. [2023-11-19 07:40:13,611 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-19 07:40:13,611 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55190 states and 78307 transitions. [2023-11-19 07:40:13,732 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 54841 [2023-11-19 07:40:13,732 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:40:13,732 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:40:13,733 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:40:13,734 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:40:13,734 INFO L748 eck$LassoCheckResult]: Stem: 768850#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 768851#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 769481#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 769482#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 769562#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 768998#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 768999#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 769125#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 769126#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 768897#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 768684#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 768685#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 768855#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 768856#L781 assume !(0 == ~M_E~0); 769385#L781-2 assume !(0 == ~T1_E~0); 769581#L786-1 assume !(0 == ~T2_E~0); 768645#L791-1 assume !(0 == ~T3_E~0); 768646#L796-1 assume !(0 == ~T4_E~0); 769204#L801-1 assume !(0 == ~T5_E~0); 769205#L806-1 assume !(0 == ~T6_E~0); 769239#L811-1 assume !(0 == ~T7_E~0); 768862#L816-1 assume !(0 == ~E_M~0); 768863#L821-1 assume !(0 == ~E_1~0); 768676#L826-1 assume !(0 == ~E_2~0); 768677#L831-1 assume !(0 == ~E_3~0); 768993#L836-1 assume !(0 == ~E_4~0); 768994#L841-1 assume !(0 == ~E_5~0); 768813#L846-1 assume !(0 == ~E_6~0); 768814#L851-1 assume !(0 == ~E_7~0); 768837#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 768838#L388 assume !(1 == ~m_pc~0); 768831#L388-2 is_master_triggered_~__retres1~0#1 := 0; 768832#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 769356#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 768690#L967 assume !(0 != activate_threads_~tmp~1#1); 768691#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 768624#L407 assume !(1 == ~t1_pc~0); 768625#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 768628#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 768629#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 768662#L975 assume !(0 != activate_threads_~tmp___0~0#1); 769475#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 768949#L426 assume !(1 == ~t2_pc~0); 768950#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 769500#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 768974#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 768975#L983 assume !(0 != activate_threads_~tmp___1~0#1); 769546#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 769038#L445 assume !(1 == ~t3_pc~0); 769039#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 769393#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 768622#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 768623#L991 assume !(0 != activate_threads_~tmp___2~0#1); 769311#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 769270#L464 assume !(1 == ~t4_pc~0); 768841#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 768710#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 768711#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 768722#L999 assume !(0 != activate_threads_~tmp___3~0#1); 769018#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 769019#L483 assume !(1 == ~t5_pc~0); 769266#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 769455#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 769412#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 769413#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 768934#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 768935#L502 assume !(1 == ~t6_pc~0); 768792#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 768751#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 768752#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 768960#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 769165#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 769430#L521 assume !(1 == ~t7_pc~0); 769471#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 769502#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 769592#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 769465#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 769437#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 769345#L869 assume !(1 == ~M_E~0); 769012#L869-2 assume !(1 == ~T1_E~0); 769013#L874-1 assume !(1 == ~T2_E~0); 769514#L879-1 assume !(1 == ~T3_E~0); 769085#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 768610#L889-1 assume !(1 == ~T5_E~0); 768611#L894-1 assume !(1 == ~T6_E~0); 768870#L899-1 assume !(1 == ~T7_E~0); 769297#L904-1 assume !(1 == ~E_M~0); 769035#L909-1 assume !(1 == ~E_1~0); 769036#L914-1 assume !(1 == ~E_2~0); 769223#L919-1 assume !(1 == ~E_3~0); 768948#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 768785#L929-1 assume !(1 == ~E_5~0); 768786#L934-1 assume !(1 == ~E_6~0); 769014#L939-1 assume !(1 == ~E_7~0); 769015#L944-1 assume { :end_inline_reset_delta_events } true; 769429#L1190-2 [2023-11-19 07:40:13,735 INFO L750 eck$LassoCheckResult]: Loop: 769429#L1190-2 assume !false; 802116#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 802114#L756-1 assume !false; 802113#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 802110#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 802102#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 802100#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 802098#L653 assume !(0 != eval_~tmp~0#1); 802099#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 802687#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 802685#L781-3 assume !(0 == ~M_E~0); 802683#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 802681#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 802679#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 802677#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 802675#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 802673#L806-3 assume !(0 == ~T6_E~0); 802671#L811-3 assume !(0 == ~T7_E~0); 802669#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 802667#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 802665#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 802663#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 802661#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 802659#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 802657#L846-3 assume !(0 == ~E_6~0); 802655#L851-3 assume !(0 == ~E_7~0); 802653#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 802651#L388-27 assume !(1 == ~m_pc~0); 802648#L388-29 is_master_triggered_~__retres1~0#1 := 0; 802647#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 802644#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 802642#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 802640#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 802618#L407-27 assume !(1 == ~t1_pc~0); 802616#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 802614#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 802612#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 802610#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 802608#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 802606#L426-27 assume 1 == ~t2_pc~0; 802601#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 802599#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 802597#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 802595#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 802592#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 802590#L445-27 assume !(1 == ~t3_pc~0); 802588#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 802587#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 802585#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 802583#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 802580#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 802578#L464-27 assume 1 == ~t4_pc~0; 802575#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 802573#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 802571#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 802569#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 802566#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 802564#L483-27 assume !(1 == ~t5_pc~0); 802562#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 802560#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 802558#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 802556#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 802554#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 802552#L502-27 assume !(1 == ~t6_pc~0); 802550#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 802548#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 802546#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 802542#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 802540#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 802538#L521-27 assume 1 == ~t7_pc~0; 802536#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 802537#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 802634#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 802526#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 802525#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 802523#L869-3 assume !(1 == ~M_E~0); 797091#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 802520#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 802518#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 802516#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 802514#L889-3 assume !(1 == ~T5_E~0); 802512#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 802510#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 802508#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 802506#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 802504#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 802502#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 802500#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 802498#L929-3 assume !(1 == ~E_5~0); 802496#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 802495#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 802494#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 798887#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 798881#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 798879#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 797180#L1209 assume !(0 == start_simulation_~tmp~3#1); 797181#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 802252#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 802247#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 802246#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 802245#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 802244#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 802243#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 802242#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 769429#L1190-2 [2023-11-19 07:40:13,735 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:40:13,736 INFO L85 PathProgramCache]: Analyzing trace with hash -2081259327, now seen corresponding path program 1 times [2023-11-19 07:40:13,736 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:40:13,736 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1359972879] [2023-11-19 07:40:13,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:40:13,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:40:13,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:40:13,800 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:40:13,800 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:40:13,800 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1359972879] [2023-11-19 07:40:13,800 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1359972879] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:40:13,800 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:40:13,801 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:40:13,801 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [779754034] [2023-11-19 07:40:13,801 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:40:13,801 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:40:13,802 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:40:13,802 INFO L85 PathProgramCache]: Analyzing trace with hash 1171819677, now seen corresponding path program 1 times [2023-11-19 07:40:13,802 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:40:13,802 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [542722858] [2023-11-19 07:40:13,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:40:13,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:40:13,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:40:13,845 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:40:13,845 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:40:13,845 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [542722858] [2023-11-19 07:40:13,845 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [542722858] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:40:13,845 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:40:13,846 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:40:13,846 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [624373626] [2023-11-19 07:40:13,846 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:40:13,846 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:40:13,846 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:40:13,847 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:40:13,847 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:40:13,847 INFO L87 Difference]: Start difference. First operand 55190 states and 78307 transitions. cyclomatic complexity: 23133 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:40:14,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:40:14,116 INFO L93 Difference]: Finished difference Result 88255 states and 124668 transitions. [2023-11-19 07:40:14,117 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88255 states and 124668 transitions. [2023-11-19 07:40:14,379 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 87699 [2023-11-19 07:40:14,550 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88255 states to 88255 states and 124668 transitions. [2023-11-19 07:40:14,550 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 88255 [2023-11-19 07:40:14,591 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 88255 [2023-11-19 07:40:14,591 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88255 states and 124668 transitions. [2023-11-19 07:40:14,625 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:40:14,625 INFO L218 hiAutomatonCegarLoop]: Abstraction has 88255 states and 124668 transitions. [2023-11-19 07:40:14,663 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88255 states and 124668 transitions. [2023-11-19 07:40:15,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88255 to 63123. [2023-11-19 07:40:15,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63123 states, 63123 states have (on average 1.4164092327677709) internal successors, (89408), 63122 states have internal predecessors, (89408), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:40:15,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63123 states to 63123 states and 89408 transitions. [2023-11-19 07:40:15,822 INFO L240 hiAutomatonCegarLoop]: Abstraction has 63123 states and 89408 transitions. [2023-11-19 07:40:15,822 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:40:15,823 INFO L428 stractBuchiCegarLoop]: Abstraction has 63123 states and 89408 transitions. [2023-11-19 07:40:15,823 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-19 07:40:15,823 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63123 states and 89408 transitions. [2023-11-19 07:40:15,973 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 62703 [2023-11-19 07:40:15,973 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:40:15,974 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:40:15,975 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:40:15,976 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:40:15,976 INFO L748 eck$LassoCheckResult]: Stem: 912309#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 912310#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 912949#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 912950#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 913054#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 912459#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 912460#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 912586#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 912587#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 912355#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 912140#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 912141#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 912314#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 912315#L781 assume !(0 == ~M_E~0); 912847#L781-2 assume !(0 == ~T1_E~0); 913074#L786-1 assume !(0 == ~T2_E~0); 912100#L791-1 assume !(0 == ~T3_E~0); 912101#L796-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 912665#L801-1 assume !(0 == ~T5_E~0); 912666#L806-1 assume !(0 == ~T6_E~0); 913040#L811-1 assume !(0 == ~T7_E~0); 913041#L816-1 assume !(0 == ~E_M~0); 912953#L821-1 assume !(0 == ~E_1~0); 912954#L826-1 assume !(0 == ~E_2~0); 912663#L831-1 assume !(0 == ~E_3~0); 912664#L836-1 assume !(0 == ~E_4~0); 913108#L841-1 assume !(0 == ~E_5~0); 912270#L846-1 assume !(0 == ~E_6~0); 912271#L851-1 assume !(0 == ~E_7~0); 913107#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 912975#L388 assume !(1 == ~m_pc~0); 912288#L388-2 is_master_triggered_~__retres1~0#1 := 0; 912289#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 912820#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 912146#L967 assume !(0 != activate_threads_~tmp~1#1); 912147#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 912079#L407 assume !(1 == ~t1_pc~0); 912080#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 913104#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 913103#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 912945#L975 assume !(0 != activate_threads_~tmp___0~0#1); 912946#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 912408#L426 assume !(1 == ~t2_pc~0); 912409#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 913034#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 913035#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 913030#L983 assume !(0 != activate_threads_~tmp___1~0#1); 913031#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 913102#L445 assume !(1 == ~t3_pc~0); 913075#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 912855#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 912856#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 913100#L991 assume !(0 != activate_threads_~tmp___2~0#1); 913099#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 912735#L464 assume !(1 == ~t4_pc~0); 912298#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 912299#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 913096#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 913095#L999 assume !(0 != activate_threads_~tmp___3~0#1); 913094#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 912731#L483 assume !(1 == ~t5_pc~0); 912732#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 912924#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 912925#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 913006#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 913007#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 913093#L502 assume !(1 == ~t6_pc~0); 912247#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 912248#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 912419#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 912420#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 912900#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 912901#L521 assume !(1 == ~t7_pc~0); 912942#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 912142#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 912143#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 913086#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 912909#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 912809#L869 assume !(1 == ~M_E~0); 912473#L869-2 assume !(1 == ~T1_E~0); 912474#L874-1 assume !(1 == ~T2_E~0); 912998#L879-1 assume !(1 == ~T3_E~0); 912999#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 912065#L889-1 assume !(1 == ~T5_E~0); 912066#L894-1 assume !(1 == ~T6_E~0); 912329#L899-1 assume !(1 == ~T7_E~0); 912762#L904-1 assume !(1 == ~E_M~0); 912496#L909-1 assume !(1 == ~E_1~0); 912497#L914-1 assume !(1 == ~E_2~0); 912687#L919-1 assume !(1 == ~E_3~0); 912407#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 912240#L929-1 assume !(1 == ~E_5~0); 912241#L934-1 assume !(1 == ~E_6~0); 912475#L939-1 assume !(1 == ~E_7~0); 912476#L944-1 assume { :end_inline_reset_delta_events } true; 912899#L1190-2 [2023-11-19 07:40:15,976 INFO L750 eck$LassoCheckResult]: Loop: 912899#L1190-2 assume !false; 940115#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 940107#L756-1 assume !false; 940099#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 940083#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 940068#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 940062#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 940051#L653 assume !(0 != eval_~tmp~0#1); 940052#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 943210#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 943193#L781-3 assume !(0 == ~M_E~0); 943184#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 943121#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 943114#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 943104#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 943103#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 943102#L806-3 assume !(0 == ~T6_E~0); 943101#L811-3 assume !(0 == ~T7_E~0); 943100#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 943099#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 943098#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 943097#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 943096#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 943095#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 943094#L846-3 assume !(0 == ~E_6~0); 943093#L851-3 assume !(0 == ~E_7~0); 943092#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 943091#L388-27 assume !(1 == ~m_pc~0); 943090#L388-29 is_master_triggered_~__retres1~0#1 := 0; 943089#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 943088#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 943087#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 943086#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 943085#L407-27 assume !(1 == ~t1_pc~0); 943084#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 943083#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 943082#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 943081#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 943080#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 943079#L426-27 assume !(1 == ~t2_pc~0); 943078#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 943076#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 943075#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 943074#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 943073#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 943072#L445-27 assume !(1 == ~t3_pc~0); 943071#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 943070#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 943069#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 943068#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 943067#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 943066#L464-27 assume 1 == ~t4_pc~0; 943064#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 943063#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 943062#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 943061#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 943060#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 943059#L483-27 assume !(1 == ~t5_pc~0); 943058#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 943057#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 943056#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 943055#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 943054#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 943053#L502-27 assume !(1 == ~t6_pc~0); 943052#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 943051#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 943050#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 943049#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 943048#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 943047#L521-27 assume !(1 == ~t7_pc~0); 943046#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 943044#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 943042#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 943040#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 943038#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 943037#L869-3 assume !(1 == ~M_E~0); 930057#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 943036#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 943035#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 943033#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 943025#L889-3 assume !(1 == ~T5_E~0); 942949#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 942943#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 942937#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 942931#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 942924#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 942917#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 942910#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 942904#L929-3 assume !(1 == ~E_5~0); 942898#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 942893#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 942834#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 942792#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 942780#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 942775#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 931912#L1209 assume !(0 == start_simulation_~tmp~3#1); 931913#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 940262#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 940255#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 940253#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 940251#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 940155#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 940142#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 940135#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 912899#L1190-2 [2023-11-19 07:40:15,977 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:40:15,977 INFO L85 PathProgramCache]: Analyzing trace with hash 1374674307, now seen corresponding path program 1 times [2023-11-19 07:40:15,977 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:40:15,977 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [413368073] [2023-11-19 07:40:15,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:40:15,978 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:40:15,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:40:16,034 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:40:16,034 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:40:16,034 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [413368073] [2023-11-19 07:40:16,034 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [413368073] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:40:16,034 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:40:16,035 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:40:16,035 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [22467297] [2023-11-19 07:40:16,035 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:40:16,035 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:40:16,036 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:40:16,036 INFO L85 PathProgramCache]: Analyzing trace with hash -992455839, now seen corresponding path program 1 times [2023-11-19 07:40:16,036 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:40:16,036 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1557421100] [2023-11-19 07:40:16,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:40:16,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:40:16,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:40:16,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:40:16,081 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:40:16,082 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1557421100] [2023-11-19 07:40:16,082 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1557421100] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:40:16,082 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:40:16,082 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:40:16,082 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [363400223] [2023-11-19 07:40:16,082 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:40:16,083 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:40:16,083 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:40:16,083 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:40:16,084 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:40:16,084 INFO L87 Difference]: Start difference. First operand 63123 states and 89408 transitions. cyclomatic complexity: 26301 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:40:16,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:40:16,913 INFO L93 Difference]: Finished difference Result 80310 states and 113164 transitions. [2023-11-19 07:40:16,913 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 80310 states and 113164 transitions. [2023-11-19 07:40:17,264 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 79837 [2023-11-19 07:40:17,441 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 80310 states to 80310 states and 113164 transitions. [2023-11-19 07:40:17,441 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 80310 [2023-11-19 07:40:17,475 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 80310 [2023-11-19 07:40:17,475 INFO L73 IsDeterministic]: Start isDeterministic. Operand 80310 states and 113164 transitions. [2023-11-19 07:40:17,510 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:40:17,510 INFO L218 hiAutomatonCegarLoop]: Abstraction has 80310 states and 113164 transitions. [2023-11-19 07:40:17,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80310 states and 113164 transitions. [2023-11-19 07:40:18,042 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80310 to 55190. [2023-11-19 07:40:18,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55190 states, 55190 states have (on average 1.412955245515492) internal successors, (77981), 55189 states have internal predecessors, (77981), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:40:18,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55190 states to 55190 states and 77981 transitions. [2023-11-19 07:40:18,192 INFO L240 hiAutomatonCegarLoop]: Abstraction has 55190 states and 77981 transitions. [2023-11-19 07:40:18,192 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:40:18,193 INFO L428 stractBuchiCegarLoop]: Abstraction has 55190 states and 77981 transitions. [2023-11-19 07:40:18,193 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-19 07:40:18,193 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55190 states and 77981 transitions. [2023-11-19 07:40:18,605 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 54841 [2023-11-19 07:40:18,605 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:40:18,605 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:40:18,607 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:40:18,607 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:40:18,607 INFO L748 eck$LassoCheckResult]: Stem: 1055748#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1055749#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1056374#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1056375#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1056459#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1055892#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1055893#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1056016#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1056017#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1055794#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1055582#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1055583#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1055753#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1055754#L781 assume !(0 == ~M_E~0); 1056274#L781-2 assume !(0 == ~T1_E~0); 1056485#L786-1 assume !(0 == ~T2_E~0); 1055543#L791-1 assume !(0 == ~T3_E~0); 1055544#L796-1 assume !(0 == ~T4_E~0); 1056093#L801-1 assume !(0 == ~T5_E~0); 1056094#L806-1 assume !(0 == ~T6_E~0); 1056131#L811-1 assume !(0 == ~T7_E~0); 1055760#L816-1 assume !(0 == ~E_M~0); 1055761#L821-1 assume !(0 == ~E_1~0); 1055574#L826-1 assume !(0 == ~E_2~0); 1055575#L831-1 assume !(0 == ~E_3~0); 1055887#L836-1 assume !(0 == ~E_4~0); 1055888#L841-1 assume !(0 == ~E_5~0); 1055710#L846-1 assume !(0 == ~E_6~0); 1055711#L851-1 assume !(0 == ~E_7~0); 1055734#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1055735#L388 assume !(1 == ~m_pc~0); 1055728#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1055729#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1056247#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1055588#L967 assume !(0 != activate_threads_~tmp~1#1); 1055589#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1055522#L407 assume !(1 == ~t1_pc~0); 1055523#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1055529#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1055530#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1055562#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1056368#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1055846#L426 assume !(1 == ~t2_pc~0); 1055847#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1056399#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1055870#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1055871#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1056445#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1055931#L445 assume !(1 == ~t3_pc~0); 1055932#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1056281#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1055520#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1055521#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1056201#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1056161#L464 assume !(1 == ~t4_pc~0); 1055738#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1055608#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1055609#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1055620#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1055911#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1055912#L483 assume !(1 == ~t5_pc~0); 1056157#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1056346#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1056307#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1056308#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1055831#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1055832#L502 assume !(1 == ~t6_pc~0); 1055689#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1055648#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1055649#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1055856#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1056056#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1056324#L521 assume !(1 == ~t7_pc~0); 1056364#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1055584#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1055585#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1056356#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1056330#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1056235#L869 assume !(1 == ~M_E~0); 1055905#L869-2 assume !(1 == ~T1_E~0); 1055906#L874-1 assume !(1 == ~T2_E~0); 1056415#L879-1 assume !(1 == ~T3_E~0); 1055979#L884-1 assume !(1 == ~T4_E~0); 1055508#L889-1 assume !(1 == ~T5_E~0); 1055509#L894-1 assume !(1 == ~T6_E~0); 1055768#L899-1 assume !(1 == ~T7_E~0); 1056188#L904-1 assume !(1 == ~E_M~0); 1055928#L909-1 assume !(1 == ~E_1~0); 1055929#L914-1 assume !(1 == ~E_2~0); 1056116#L919-1 assume !(1 == ~E_3~0); 1055845#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1055682#L929-1 assume !(1 == ~E_5~0); 1055683#L934-1 assume !(1 == ~E_6~0); 1055907#L939-1 assume !(1 == ~E_7~0); 1055908#L944-1 assume { :end_inline_reset_delta_events } true; 1056323#L1190-2 [2023-11-19 07:40:18,608 INFO L750 eck$LassoCheckResult]: Loop: 1056323#L1190-2 assume !false; 1070831#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1070819#L756-1 assume !false; 1070218#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1070144#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1070135#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1070132#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1070129#L653 assume !(0 != eval_~tmp~0#1); 1070127#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1070125#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1070123#L781-3 assume !(0 == ~M_E~0); 1070121#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1070119#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1070117#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1070115#L796-3 assume !(0 == ~T4_E~0); 1070113#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1070111#L806-3 assume !(0 == ~T6_E~0); 1070109#L811-3 assume !(0 == ~T7_E~0); 1070107#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1070104#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1070102#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1070100#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1070098#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1070096#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1070094#L846-3 assume !(0 == ~E_6~0); 1070092#L851-3 assume !(0 == ~E_7~0); 1070090#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1070088#L388-27 assume !(1 == ~m_pc~0); 1070086#L388-29 is_master_triggered_~__retres1~0#1 := 0; 1070084#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1070081#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1070080#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1070077#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1070075#L407-27 assume !(1 == ~t1_pc~0); 1070073#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1070071#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1070069#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1070065#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 1070063#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1070061#L426-27 assume 1 == ~t2_pc~0; 1070058#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1070055#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1070053#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1070051#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1070050#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1070048#L445-27 assume !(1 == ~t3_pc~0); 1070046#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1070044#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1070042#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1070040#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1070038#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1070036#L464-27 assume 1 == ~t4_pc~0; 1070033#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1070031#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1070029#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1070027#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1070025#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1070023#L483-27 assume !(1 == ~t5_pc~0); 1070021#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1070019#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1070018#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1070017#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1070016#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1070015#L502-27 assume !(1 == ~t6_pc~0); 1070014#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1070013#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1070011#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1070010#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1070009#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1069802#L521-27 assume !(1 == ~t7_pc~0); 1069798#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1069796#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1069794#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1069792#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 1069789#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1069625#L869-3 assume !(1 == ~M_E~0); 1063311#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1069622#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1069620#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1069617#L884-3 assume !(1 == ~T4_E~0); 1069615#L889-3 assume !(1 == ~T5_E~0); 1069614#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1069610#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1069608#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1069606#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1069605#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1069602#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1069601#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1069600#L929-3 assume !(1 == ~E_5~0); 1069597#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1069361#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1069351#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1067188#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1067175#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1067173#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1066652#L1209 assume !(0 == start_simulation_~tmp~3#1); 1066653#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1070882#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1070874#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1070870#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1070866#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1070864#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1070862#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1070861#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1056323#L1190-2 [2023-11-19 07:40:18,608 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:40:18,609 INFO L85 PathProgramCache]: Analyzing trace with hash 1626901955, now seen corresponding path program 1 times [2023-11-19 07:40:18,609 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:40:18,609 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1368712912] [2023-11-19 07:40:18,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:40:18,609 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:40:18,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:40:18,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:40:18,670 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:40:18,670 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1368712912] [2023-11-19 07:40:18,670 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1368712912] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:40:18,670 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:40:18,671 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:40:18,671 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [986327189] [2023-11-19 07:40:18,671 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:40:18,671 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:40:18,672 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:40:18,672 INFO L85 PathProgramCache]: Analyzing trace with hash 647513184, now seen corresponding path program 1 times [2023-11-19 07:40:18,672 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:40:18,672 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [97830941] [2023-11-19 07:40:18,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:40:18,672 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:40:18,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:40:18,710 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:40:18,710 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:40:18,711 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [97830941] [2023-11-19 07:40:18,711 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [97830941] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:40:18,711 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:40:18,711 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:40:18,711 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2143469705] [2023-11-19 07:40:18,711 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:40:18,712 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:40:18,712 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:40:18,712 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:40:18,712 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:40:18,713 INFO L87 Difference]: Start difference. First operand 55190 states and 77981 transitions. cyclomatic complexity: 22807 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:40:19,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:40:19,038 INFO L93 Difference]: Finished difference Result 88288 states and 123265 transitions. [2023-11-19 07:40:19,038 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88288 states and 123265 transitions. [2023-11-19 07:40:19,346 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 87682 [2023-11-19 07:40:19,530 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88288 states to 88288 states and 123265 transitions. [2023-11-19 07:40:19,530 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 88288 [2023-11-19 07:40:19,572 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 88288 [2023-11-19 07:40:19,572 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88288 states and 123265 transitions. [2023-11-19 07:40:19,608 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:40:19,608 INFO L218 hiAutomatonCegarLoop]: Abstraction has 88288 states and 123265 transitions. [2023-11-19 07:40:19,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88288 states and 123265 transitions. [2023-11-19 07:40:20,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88288 to 63123. [2023-11-19 07:40:20,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63123 states, 63123 states have (on average 1.4010265671783662) internal successors, (88437), 63122 states have internal predecessors, (88437), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:40:20,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63123 states to 63123 states and 88437 transitions. [2023-11-19 07:40:20,835 INFO L240 hiAutomatonCegarLoop]: Abstraction has 63123 states and 88437 transitions. [2023-11-19 07:40:20,835 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:40:20,836 INFO L428 stractBuchiCegarLoop]: Abstraction has 63123 states and 88437 transitions. [2023-11-19 07:40:20,836 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-19 07:40:20,836 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63123 states and 88437 transitions. [2023-11-19 07:40:20,986 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 62703 [2023-11-19 07:40:20,986 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:40:20,986 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:40:20,987 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:40:20,987 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:40:20,988 INFO L748 eck$LassoCheckResult]: Stem: 1199238#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1199239#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1199892#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1199893#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1199996#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1199386#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1199387#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1199520#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1199521#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1199284#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1199070#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1199071#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1199243#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1199244#L781 assume !(0 == ~M_E~0); 1199789#L781-2 assume !(0 == ~T1_E~0); 1200019#L786-1 assume !(0 == ~T2_E~0); 1199031#L791-1 assume !(0 == ~T3_E~0); 1199032#L796-1 assume !(0 == ~T4_E~0); 1199603#L801-1 assume !(0 == ~T5_E~0); 1199604#L806-1 assume !(0 == ~T6_E~0); 1199644#L811-1 assume !(0 == ~T7_E~0); 1199249#L816-1 assume !(0 == ~E_M~0); 1199250#L821-1 assume !(0 == ~E_1~0); 1199062#L826-1 assume !(0 == ~E_2~0); 1199063#L831-1 assume !(0 == ~E_3~0); 1199380#L836-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1199381#L841-1 assume !(0 == ~E_5~0); 1199791#L846-1 assume !(0 == ~E_6~0); 1200006#L851-1 assume !(0 == ~E_7~0); 1199224#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1199225#L388 assume !(1 == ~m_pc~0); 1200082#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1200081#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1199821#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1199822#L967 assume !(0 != activate_threads_~tmp~1#1); 1199988#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1199989#L407 assume !(1 == ~t1_pc~0); 1199995#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1199017#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1199018#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1199050#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1199909#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1199910#L426 assume !(1 == ~t2_pc~0); 1199918#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1199919#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1199360#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1199361#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1200077#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1200076#L445 assume !(1 == ~t3_pc~0); 1200075#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1200074#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1199008#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1199009#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1199715#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1199796#L464 assume !(1 == ~t4_pc~0); 1200070#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1200069#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1200068#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1200067#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1200066#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1200065#L483 assume !(1 == ~t5_pc~0); 1200064#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1200063#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1200062#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1200061#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1200060#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1200059#L502 assume !(1 == ~t6_pc~0); 1200058#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1200057#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1200056#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1200055#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1200054#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1200053#L521 assume !(1 == ~t7_pc~0); 1200051#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1200049#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1200047#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1200045#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1200044#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1200043#L869 assume !(1 == ~M_E~0); 1200042#L869-2 assume !(1 == ~T1_E~0); 1200041#L874-1 assume !(1 == ~T2_E~0); 1200040#L879-1 assume !(1 == ~T3_E~0); 1200039#L884-1 assume !(1 == ~T4_E~0); 1200038#L889-1 assume !(1 == ~T5_E~0); 1200037#L894-1 assume !(1 == ~T6_E~0); 1200036#L899-1 assume !(1 == ~T7_E~0); 1200035#L904-1 assume !(1 == ~E_M~0); 1200034#L909-1 assume !(1 == ~E_1~0); 1200033#L914-1 assume !(1 == ~E_2~0); 1200032#L919-1 assume !(1 == ~E_3~0); 1200031#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1199170#L929-1 assume !(1 == ~E_5~0); 1199171#L934-1 assume !(1 == ~E_6~0); 1199404#L939-1 assume !(1 == ~E_7~0); 1199405#L944-1 assume { :end_inline_reset_delta_events } true; 1199841#L1190-2 [2023-11-19 07:40:20,988 INFO L750 eck$LassoCheckResult]: Loop: 1199841#L1190-2 assume !false; 1208765#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1208766#L756-1 assume !false; 1208755#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1208756#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1208693#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1208694#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1208685#L653 assume !(0 != eval_~tmp~0#1); 1208687#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1209310#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1209307#L781-3 assume !(0 == ~M_E~0); 1209305#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1209303#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1209301#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1209299#L796-3 assume !(0 == ~T4_E~0); 1209297#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1209295#L806-3 assume !(0 == ~T6_E~0); 1209293#L811-3 assume !(0 == ~T7_E~0); 1209291#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1209276#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1209267#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1209258#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1209248#L836-3 assume !(0 == ~E_4~0); 1209250#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1209741#L846-3 assume !(0 == ~E_6~0); 1209735#L851-3 assume !(0 == ~E_7~0); 1209736#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1209729#L388-27 assume !(1 == ~m_pc~0); 1209730#L388-29 is_master_triggered_~__retres1~0#1 := 0; 1209721#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1209722#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1209709#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1209710#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1209695#L407-27 assume !(1 == ~t1_pc~0); 1209696#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1209682#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1209683#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1209670#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 1209671#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1209657#L426-27 assume 1 == ~t2_pc~0; 1209658#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1209644#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1209645#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1209631#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1209632#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1209618#L445-27 assume !(1 == ~t3_pc~0); 1209619#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1209605#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1209606#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1209447#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1209448#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1209404#L464-27 assume !(1 == ~t4_pc~0); 1209186#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1209400#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1209397#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1209395#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1209393#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1209391#L483-27 assume !(1 == ~t5_pc~0); 1209389#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1209387#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1209374#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1209368#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1209362#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1209327#L502-27 assume !(1 == ~t6_pc~0); 1209322#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1209321#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1209320#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1209319#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1209318#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1209317#L521-27 assume 1 == ~t7_pc~0; 1209315#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1209316#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1209314#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1209308#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1209306#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1209304#L869-3 assume !(1 == ~M_E~0); 1209302#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1209300#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1209298#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1209296#L884-3 assume !(1 == ~T4_E~0); 1209294#L889-3 assume !(1 == ~T5_E~0); 1209292#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1209290#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1209289#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1209274#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1209275#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1209256#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1209257#L924-3 assume !(1 == ~E_4~0); 1235110#L929-3 assume !(1 == ~E_5~0); 1235109#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1235108#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1235107#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1235103#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1235098#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1235097#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1215297#L1209 assume !(0 == start_simulation_~tmp~3#1); 1208873#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1208874#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1221602#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1221601#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1221600#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1221599#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1221598#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1208790#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1199841#L1190-2 [2023-11-19 07:40:20,989 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:40:20,989 INFO L85 PathProgramCache]: Analyzing trace with hash -281555835, now seen corresponding path program 1 times [2023-11-19 07:40:20,989 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:40:20,990 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1307745885] [2023-11-19 07:40:20,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:40:20,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:40:21,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:40:21,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:40:21,048 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:40:21,048 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1307745885] [2023-11-19 07:40:21,048 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1307745885] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:40:21,048 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:40:21,048 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:40:21,049 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [76847338] [2023-11-19 07:40:21,049 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:40:21,049 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:40:21,049 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:40:21,050 INFO L85 PathProgramCache]: Analyzing trace with hash -1400904226, now seen corresponding path program 1 times [2023-11-19 07:40:21,050 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:40:21,050 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [342110706] [2023-11-19 07:40:21,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:40:21,050 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:40:21,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:40:21,088 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:40:21,088 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:40:21,088 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [342110706] [2023-11-19 07:40:21,089 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [342110706] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:40:21,089 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:40:21,089 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:40:21,089 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1398737611] [2023-11-19 07:40:21,089 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:40:21,090 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:40:21,090 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:40:21,090 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:40:21,090 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:40:21,091 INFO L87 Difference]: Start difference. First operand 63123 states and 88437 transitions. cyclomatic complexity: 25330 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:40:21,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:40:21,376 INFO L93 Difference]: Finished difference Result 79273 states and 110407 transitions. [2023-11-19 07:40:21,377 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 79273 states and 110407 transitions. [2023-11-19 07:40:21,627 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 78782 [2023-11-19 07:40:22,427 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 79273 states to 79273 states and 110407 transitions. [2023-11-19 07:40:22,428 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 79273 [2023-11-19 07:40:22,463 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 79273 [2023-11-19 07:40:22,464 INFO L73 IsDeterministic]: Start isDeterministic. Operand 79273 states and 110407 transitions. [2023-11-19 07:40:22,492 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:40:22,492 INFO L218 hiAutomatonCegarLoop]: Abstraction has 79273 states and 110407 transitions. [2023-11-19 07:40:22,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79273 states and 110407 transitions. [2023-11-19 07:40:22,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79273 to 55190. [2023-11-19 07:40:22,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55190 states, 55190 states have (on average 1.395361478528719) internal successors, (77010), 55189 states have internal predecessors, (77010), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:40:23,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55190 states to 55190 states and 77010 transitions. [2023-11-19 07:40:23,028 INFO L240 hiAutomatonCegarLoop]: Abstraction has 55190 states and 77010 transitions. [2023-11-19 07:40:23,029 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:40:23,029 INFO L428 stractBuchiCegarLoop]: Abstraction has 55190 states and 77010 transitions. [2023-11-19 07:40:23,029 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-19 07:40:23,029 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55190 states and 77010 transitions. [2023-11-19 07:40:23,168 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 54841 [2023-11-19 07:40:23,168 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:40:23,168 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:40:23,169 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:40:23,169 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:40:23,170 INFO L748 eck$LassoCheckResult]: Stem: 1341643#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1341644#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1342280#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1342281#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1342364#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1341789#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1341790#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1341920#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1341921#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1341689#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1341477#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1341478#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1341648#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1341649#L781 assume !(0 == ~M_E~0); 1342182#L781-2 assume !(0 == ~T1_E~0); 1342387#L786-1 assume !(0 == ~T2_E~0); 1341441#L791-1 assume !(0 == ~T3_E~0); 1341442#L796-1 assume !(0 == ~T4_E~0); 1342000#L801-1 assume !(0 == ~T5_E~0); 1342001#L806-1 assume !(0 == ~T6_E~0); 1342038#L811-1 assume !(0 == ~T7_E~0); 1341654#L816-1 assume !(0 == ~E_M~0); 1341655#L821-1 assume !(0 == ~E_1~0); 1341469#L826-1 assume !(0 == ~E_2~0); 1341470#L831-1 assume !(0 == ~E_3~0); 1341784#L836-1 assume !(0 == ~E_4~0); 1341785#L841-1 assume !(0 == ~E_5~0); 1341605#L846-1 assume !(0 == ~E_6~0); 1341606#L851-1 assume !(0 == ~E_7~0); 1341629#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1341630#L388 assume !(1 == ~m_pc~0); 1341623#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1341624#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1342156#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1341483#L967 assume !(0 != activate_threads_~tmp~1#1); 1341484#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1341416#L407 assume !(1 == ~t1_pc~0); 1341417#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1341423#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1341424#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1341457#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1342277#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1341741#L426 assume !(1 == ~t2_pc~0); 1341742#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1342306#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1341764#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1341765#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1342342#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1341831#L445 assume !(1 == ~t3_pc~0); 1341832#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1342192#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1341414#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1341415#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1342111#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1342071#L464 assume !(1 == ~t4_pc~0); 1341635#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1341503#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1341504#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1341517#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1341809#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1341810#L483 assume !(1 == ~t5_pc~0); 1342068#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1342254#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1342215#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1342216#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1341728#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1341729#L502 assume !(1 == ~t6_pc~0); 1341584#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1341542#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1341543#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1341753#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1341961#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1342232#L521 assume !(1 == ~t7_pc~0); 1342274#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1341479#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1341480#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1342267#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1342238#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1342145#L869 assume !(1 == ~M_E~0); 1341803#L869-2 assume !(1 == ~T1_E~0); 1341804#L874-1 assume !(1 == ~T2_E~0); 1342318#L879-1 assume !(1 == ~T3_E~0); 1341882#L884-1 assume !(1 == ~T4_E~0); 1341402#L889-1 assume !(1 == ~T5_E~0); 1341403#L894-1 assume !(1 == ~T6_E~0); 1341665#L899-1 assume !(1 == ~T7_E~0); 1342097#L904-1 assume !(1 == ~E_M~0); 1341828#L909-1 assume !(1 == ~E_1~0); 1341829#L914-1 assume !(1 == ~E_2~0); 1342023#L919-1 assume !(1 == ~E_3~0); 1341740#L924-1 assume !(1 == ~E_4~0); 1341576#L929-1 assume !(1 == ~E_5~0); 1341577#L934-1 assume !(1 == ~E_6~0); 1341807#L939-1 assume !(1 == ~E_7~0); 1341808#L944-1 assume { :end_inline_reset_delta_events } true; 1342231#L1190-2 [2023-11-19 07:40:23,170 INFO L750 eck$LassoCheckResult]: Loop: 1342231#L1190-2 assume !false; 1364092#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1364091#L756-1 assume !false; 1364090#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1364089#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1364081#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1364080#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1364078#L653 assume !(0 != eval_~tmp~0#1); 1364077#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1364076#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1364074#L781-3 assume !(0 == ~M_E~0); 1364073#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1364072#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1364071#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1364070#L796-3 assume !(0 == ~T4_E~0); 1364068#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1364065#L806-3 assume !(0 == ~T6_E~0); 1364062#L811-3 assume !(0 == ~T7_E~0); 1364059#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1364056#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1364053#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1364050#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1364047#L836-3 assume !(0 == ~E_4~0); 1364044#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1364041#L846-3 assume !(0 == ~E_6~0); 1364038#L851-3 assume !(0 == ~E_7~0); 1364035#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1364032#L388-27 assume !(1 == ~m_pc~0); 1364029#L388-29 is_master_triggered_~__retres1~0#1 := 0; 1364026#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1364023#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1364020#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1364017#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1364014#L407-27 assume !(1 == ~t1_pc~0); 1364011#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1364008#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1364005#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1364002#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 1363999#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1363996#L426-27 assume 1 == ~t2_pc~0; 1363993#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1363991#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1363989#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1363987#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1363985#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1363983#L445-27 assume !(1 == ~t3_pc~0); 1363981#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1363979#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1363977#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1363975#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1363973#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1363971#L464-27 assume !(1 == ~t4_pc~0); 1363966#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1363964#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1363962#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1363960#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1363957#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1363955#L483-27 assume !(1 == ~t5_pc~0); 1363954#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1363950#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1363948#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1363946#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1363945#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1363942#L502-27 assume !(1 == ~t6_pc~0); 1363941#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1363940#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1363939#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1363938#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1363937#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1363936#L521-27 assume !(1 == ~t7_pc~0); 1363934#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1363932#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1363930#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1363929#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 1363927#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1363926#L869-3 assume !(1 == ~M_E~0); 1354113#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1363925#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1363923#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1363920#L884-3 assume !(1 == ~T4_E~0); 1363918#L889-3 assume !(1 == ~T5_E~0); 1363915#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1363912#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1363910#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1363906#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1363903#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1363901#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1363898#L924-3 assume !(1 == ~E_4~0); 1363895#L929-3 assume !(1 == ~E_5~0); 1363891#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1363890#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1363886#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1363871#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1363865#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1363863#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1361364#L1209 assume !(0 == start_simulation_~tmp~3#1); 1361365#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1364270#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1364264#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1364260#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1364258#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1364256#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1364254#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1364251#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1342231#L1190-2 [2023-11-19 07:40:23,170 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:40:23,171 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 1 times [2023-11-19 07:40:23,171 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:40:23,172 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1137566076] [2023-11-19 07:40:23,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:40:23,173 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:40:23,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:40:23,185 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:40:23,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:40:23,251 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:40:23,251 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:40:23,252 INFO L85 PathProgramCache]: Analyzing trace with hash 352144737, now seen corresponding path program 1 times [2023-11-19 07:40:23,252 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:40:23,252 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [680883062] [2023-11-19 07:40:23,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:40:23,252 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:40:23,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:40:23,295 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:40:23,297 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:40:23,297 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [680883062] [2023-11-19 07:40:23,297 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [680883062] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:40:23,297 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:40:23,297 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:40:23,297 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1763326383] [2023-11-19 07:40:23,298 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:40:23,298 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:40:23,298 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:40:23,298 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:40:23,299 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:40:23,299 INFO L87 Difference]: Start difference. First operand 55190 states and 77010 transitions. cyclomatic complexity: 21836 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:40:23,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:40:23,483 INFO L93 Difference]: Finished difference Result 63123 states and 87892 transitions. [2023-11-19 07:40:23,483 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63123 states and 87892 transitions. [2023-11-19 07:40:24,203 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 62703 [2023-11-19 07:40:24,346 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63123 states to 63123 states and 87892 transitions. [2023-11-19 07:40:24,347 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63123 [2023-11-19 07:40:24,376 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63123 [2023-11-19 07:40:24,376 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63123 states and 87892 transitions. [2023-11-19 07:40:24,404 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:40:24,404 INFO L218 hiAutomatonCegarLoop]: Abstraction has 63123 states and 87892 transitions. [2023-11-19 07:40:24,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63123 states and 87892 transitions. [2023-11-19 07:40:24,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63123 to 63123. [2023-11-19 07:40:24,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63123 states, 63123 states have (on average 1.3923926302615528) internal successors, (87892), 63122 states have internal predecessors, (87892), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:40:25,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63123 states to 63123 states and 87892 transitions. [2023-11-19 07:40:25,093 INFO L240 hiAutomatonCegarLoop]: Abstraction has 63123 states and 87892 transitions. [2023-11-19 07:40:25,093 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:40:25,094 INFO L428 stractBuchiCegarLoop]: Abstraction has 63123 states and 87892 transitions. [2023-11-19 07:40:25,094 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-19 07:40:25,094 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63123 states and 87892 transitions. [2023-11-19 07:40:25,271 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 62703 [2023-11-19 07:40:25,271 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:40:25,271 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:40:25,273 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:40:25,273 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:40:25,273 INFO L748 eck$LassoCheckResult]: Stem: 1459961#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1459962#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1460609#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1460610#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1460726#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1460105#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1460106#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1460237#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1460238#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1460008#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1459795#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1459796#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1459966#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1459967#L781 assume !(0 == ~M_E~0); 1460503#L781-2 assume !(0 == ~T1_E~0); 1460745#L786-1 assume !(0 == ~T2_E~0); 1459756#L791-1 assume !(0 == ~T3_E~0); 1459757#L796-1 assume !(0 == ~T4_E~0); 1460316#L801-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1460317#L806-1 assume !(0 == ~T6_E~0); 1460357#L811-1 assume !(0 == ~T7_E~0); 1459972#L816-1 assume !(0 == ~E_M~0); 1459973#L821-1 assume !(0 == ~E_1~0); 1459787#L826-1 assume !(0 == ~E_2~0); 1459788#L831-1 assume !(0 == ~E_3~0); 1460800#L836-1 assume !(0 == ~E_4~0); 1460799#L841-1 assume !(0 == ~E_5~0); 1460798#L846-1 assume !(0 == ~E_6~0); 1460797#L851-1 assume !(0 == ~E_7~0); 1460796#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1460634#L388 assume !(1 == ~m_pc~0); 1459941#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1459942#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1460476#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1459801#L967 assume !(0 != activate_threads_~tmp~1#1); 1459802#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1459735#L407 assume !(1 == ~t1_pc~0); 1459736#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1460793#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1460792#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1460604#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1460605#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1460060#L426 assume !(1 == ~t2_pc~0); 1460061#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1460705#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1460706#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1460700#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1460701#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1460148#L445 assume !(1 == ~t3_pc~0); 1460149#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1460789#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1459733#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1459734#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1460432#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1460510#L464 assume !(1 == ~t4_pc~0); 1460785#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1460784#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1460783#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1460782#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1460781#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1460386#L483 assume !(1 == ~t5_pc~0); 1460387#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1460581#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1460582#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1460779#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1460778#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1460777#L502 assume !(1 == ~t6_pc~0); 1460776#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1460775#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1460774#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1460773#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1460772#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1460771#L521 assume !(1 == ~t7_pc~0); 1460644#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1460645#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1460780#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1460766#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1460765#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1460764#L869 assume !(1 == ~M_E~0); 1460763#L869-2 assume !(1 == ~T1_E~0); 1460762#L874-1 assume !(1 == ~T2_E~0); 1460761#L879-1 assume !(1 == ~T3_E~0); 1460760#L884-1 assume !(1 == ~T4_E~0); 1459721#L889-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1459722#L894-1 assume !(1 == ~T6_E~0); 1459984#L899-1 assume !(1 == ~T7_E~0); 1460418#L904-1 assume !(1 == ~E_M~0); 1460145#L909-1 assume !(1 == ~E_1~0); 1460146#L914-1 assume !(1 == ~E_2~0); 1460340#L919-1 assume !(1 == ~E_3~0); 1460059#L924-1 assume !(1 == ~E_4~0); 1459894#L929-1 assume !(1 == ~E_5~0); 1459895#L934-1 assume !(1 == ~E_6~0); 1460124#L939-1 assume !(1 == ~E_7~0); 1460125#L944-1 assume { :end_inline_reset_delta_events } true; 1460558#L1190-2 [2023-11-19 07:40:25,274 INFO L750 eck$LassoCheckResult]: Loop: 1460558#L1190-2 assume !false; 1497301#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1497297#L756-1 assume !false; 1497293#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1497200#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1497188#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1497178#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1497168#L653 assume !(0 != eval_~tmp~0#1); 1497169#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1497914#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1497908#L781-3 assume !(0 == ~M_E~0); 1497900#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1497894#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1497891#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1497888#L796-3 assume !(0 == ~T4_E~0); 1497887#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1497886#L806-3 assume !(0 == ~T6_E~0); 1497884#L811-3 assume !(0 == ~T7_E~0); 1497882#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1497880#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1497878#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1497876#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1497865#L836-3 assume !(0 == ~E_4~0); 1497861#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1497857#L846-3 assume !(0 == ~E_6~0); 1497852#L851-3 assume !(0 == ~E_7~0); 1497848#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1497844#L388-27 assume !(1 == ~m_pc~0); 1497840#L388-29 is_master_triggered_~__retres1~0#1 := 0; 1497836#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1497832#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1497828#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1497824#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1497819#L407-27 assume !(1 == ~t1_pc~0); 1497815#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1497811#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1497807#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1497803#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 1497797#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1497791#L426-27 assume 1 == ~t2_pc~0; 1497784#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1497776#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1497771#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1497766#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1497761#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1497756#L445-27 assume !(1 == ~t3_pc~0); 1497751#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1497746#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1497741#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1497736#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1497731#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1497725#L464-27 assume !(1 == ~t4_pc~0); 1497722#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1497720#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1497718#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1497716#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1497714#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1497712#L483-27 assume !(1 == ~t5_pc~0); 1497709#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1497707#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1497659#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1497654#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1497649#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1497643#L502-27 assume !(1 == ~t6_pc~0); 1497639#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1497634#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1497629#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1497624#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1497619#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1497614#L521-27 assume 1 == ~t7_pc~0; 1497608#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1497599#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1497590#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1497581#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1497573#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1497568#L869-3 assume !(1 == ~M_E~0); 1497561#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1497558#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1497554#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1497550#L884-3 assume !(1 == ~T4_E~0); 1497546#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1497542#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1497539#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1497536#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1497533#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1497530#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1497527#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1497523#L924-3 assume !(1 == ~E_4~0); 1497519#L929-3 assume !(1 == ~E_5~0); 1497514#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1497510#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1497507#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1497419#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1497410#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1497404#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1497398#L1209 assume !(0 == start_simulation_~tmp~3#1); 1497395#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1497346#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1497337#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1497332#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1497328#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1497322#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1497317#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1497312#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1460558#L1190-2 [2023-11-19 07:40:25,275 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:40:25,275 INFO L85 PathProgramCache]: Analyzing trace with hash 1343517957, now seen corresponding path program 1 times [2023-11-19 07:40:25,275 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:40:25,275 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [689623319] [2023-11-19 07:40:25,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:40:25,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:40:25,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:40:25,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:40:25,337 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:40:25,337 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [689623319] [2023-11-19 07:40:25,337 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [689623319] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:40:25,337 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:40:25,337 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:40:25,338 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [94441044] [2023-11-19 07:40:25,338 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:40:25,338 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:40:25,338 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:40:25,339 INFO L85 PathProgramCache]: Analyzing trace with hash -1266890720, now seen corresponding path program 1 times [2023-11-19 07:40:25,339 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:40:25,339 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1527141095] [2023-11-19 07:40:25,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:40:25,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:40:25,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:40:25,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:40:25,386 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:40:25,387 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1527141095] [2023-11-19 07:40:25,387 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1527141095] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:40:25,387 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:40:25,387 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:40:25,387 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1830647702] [2023-11-19 07:40:25,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:40:25,388 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:40:25,388 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:40:25,389 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:40:25,389 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:40:25,389 INFO L87 Difference]: Start difference. First operand 63123 states and 87892 transitions. cyclomatic complexity: 24785 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:40:26,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:40:26,154 INFO L93 Difference]: Finished difference Result 80321 states and 111647 transitions. [2023-11-19 07:40:26,154 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 80321 states and 111647 transitions. [2023-11-19 07:40:26,420 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 79837 [2023-11-19 07:40:26,577 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 80321 states to 80321 states and 111647 transitions. [2023-11-19 07:40:26,577 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 80321 [2023-11-19 07:40:26,612 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 80321 [2023-11-19 07:40:26,612 INFO L73 IsDeterministic]: Start isDeterministic. Operand 80321 states and 111647 transitions. [2023-11-19 07:40:26,640 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:40:26,641 INFO L218 hiAutomatonCegarLoop]: Abstraction has 80321 states and 111647 transitions. [2023-11-19 07:40:26,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80321 states and 111647 transitions. [2023-11-19 07:40:27,075 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80321 to 55190. [2023-11-19 07:40:27,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55190 states, 55190 states have (on average 1.3933864830585252) internal successors, (76901), 55189 states have internal predecessors, (76901), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:40:27,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55190 states to 55190 states and 76901 transitions. [2023-11-19 07:40:27,200 INFO L240 hiAutomatonCegarLoop]: Abstraction has 55190 states and 76901 transitions. [2023-11-19 07:40:27,200 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:40:27,201 INFO L428 stractBuchiCegarLoop]: Abstraction has 55190 states and 76901 transitions. [2023-11-19 07:40:27,201 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-19 07:40:27,201 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55190 states and 76901 transitions. [2023-11-19 07:40:27,633 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 54841 [2023-11-19 07:40:27,633 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:40:27,633 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:40:27,634 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:40:27,635 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:40:27,635 INFO L748 eck$LassoCheckResult]: Stem: 1603417#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1603418#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1604059#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1604060#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1604150#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1603568#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1603569#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1603703#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1603704#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1603464#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1603250#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1603251#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1603425#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1603426#L781 assume !(0 == ~M_E~0); 1603966#L781-2 assume !(0 == ~T1_E~0); 1604173#L786-1 assume !(0 == ~T2_E~0); 1603213#L791-1 assume !(0 == ~T3_E~0); 1603214#L796-1 assume !(0 == ~T4_E~0); 1603784#L801-1 assume !(0 == ~T5_E~0); 1603785#L806-1 assume !(0 == ~T6_E~0); 1603821#L811-1 assume !(0 == ~T7_E~0); 1603429#L816-1 assume !(0 == ~E_M~0); 1603430#L821-1 assume !(0 == ~E_1~0); 1603242#L826-1 assume !(0 == ~E_2~0); 1603243#L831-1 assume !(0 == ~E_3~0); 1603563#L836-1 assume !(0 == ~E_4~0); 1603564#L841-1 assume !(0 == ~E_5~0); 1603379#L846-1 assume !(0 == ~E_6~0); 1603380#L851-1 assume !(0 == ~E_7~0); 1603403#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1603404#L388 assume !(1 == ~m_pc~0); 1603397#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1603398#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1603937#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1603256#L967 assume !(0 != activate_threads_~tmp~1#1); 1603257#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1603189#L407 assume !(1 == ~t1_pc~0); 1603190#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1603196#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1603197#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1603229#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1604053#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1603518#L426 assume !(1 == ~t2_pc~0); 1603519#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1604084#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1603543#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1603544#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1604133#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1603612#L445 assume !(1 == ~t3_pc~0); 1603613#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1603972#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1603187#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1603188#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1603891#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1603851#L464 assume !(1 == ~t4_pc~0); 1603409#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1603276#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1603277#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1603290#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1603591#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1603592#L483 assume !(1 == ~t5_pc~0); 1603846#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1604032#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1603994#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1603995#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1603504#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1603505#L502 assume !(1 == ~t6_pc~0); 1603356#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1603315#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1603316#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1603531#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1603744#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1604008#L521 assume !(1 == ~t7_pc~0); 1604049#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1604086#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1604185#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1604043#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1604015#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1603927#L869 assume !(1 == ~M_E~0); 1603584#L869-2 assume !(1 == ~T1_E~0); 1603585#L874-1 assume !(1 == ~T2_E~0); 1604102#L879-1 assume !(1 == ~T3_E~0); 1603664#L884-1 assume !(1 == ~T4_E~0); 1603175#L889-1 assume !(1 == ~T5_E~0); 1603176#L894-1 assume !(1 == ~T6_E~0); 1603440#L899-1 assume !(1 == ~T7_E~0); 1603881#L904-1 assume !(1 == ~E_M~0); 1603609#L909-1 assume !(1 == ~E_1~0); 1603610#L914-1 assume !(1 == ~E_2~0); 1603806#L919-1 assume !(1 == ~E_3~0); 1603517#L924-1 assume !(1 == ~E_4~0); 1603349#L929-1 assume !(1 == ~E_5~0); 1603350#L934-1 assume !(1 == ~E_6~0); 1603589#L939-1 assume !(1 == ~E_7~0); 1603590#L944-1 assume { :end_inline_reset_delta_events } true; 1604007#L1190-2 [2023-11-19 07:40:27,636 INFO L750 eck$LassoCheckResult]: Loop: 1604007#L1190-2 assume !false; 1638230#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1638228#L756-1 assume !false; 1638183#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1638130#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1638121#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1637798#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1637794#L653 assume !(0 != eval_~tmp~0#1); 1637795#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1640967#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1640965#L781-3 assume !(0 == ~M_E~0); 1640963#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1640961#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1640959#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1640957#L796-3 assume !(0 == ~T4_E~0); 1640955#L801-3 assume !(0 == ~T5_E~0); 1640953#L806-3 assume !(0 == ~T6_E~0); 1640951#L811-3 assume !(0 == ~T7_E~0); 1640949#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1640946#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1640944#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1640942#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1640940#L836-3 assume !(0 == ~E_4~0); 1640938#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1640936#L846-3 assume !(0 == ~E_6~0); 1640935#L851-3 assume !(0 == ~E_7~0); 1640933#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1640931#L388-27 assume !(1 == ~m_pc~0); 1640929#L388-29 is_master_triggered_~__retres1~0#1 := 0; 1640927#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1640924#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1640922#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1640920#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1640918#L407-27 assume !(1 == ~t1_pc~0); 1640916#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1640914#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1640912#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1640910#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 1640908#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1640906#L426-27 assume !(1 == ~t2_pc~0); 1640904#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1640901#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1640898#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1640897#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1640894#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1640874#L445-27 assume !(1 == ~t3_pc~0); 1640864#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1640855#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1640844#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1640817#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1640811#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1640739#L464-27 assume !(1 == ~t4_pc~0); 1640736#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1640734#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1640732#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1640730#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1640727#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1640725#L483-27 assume !(1 == ~t5_pc~0); 1640692#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1640685#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1640678#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1640670#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1640618#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1640608#L502-27 assume !(1 == ~t6_pc~0); 1640599#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1639777#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1639655#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1639381#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1639372#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1639369#L521-27 assume !(1 == ~t7_pc~0); 1639365#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1639363#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1639361#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1639359#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 1639355#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1639352#L869-3 assume !(1 == ~M_E~0); 1627810#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1639350#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1639347#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1639344#L884-3 assume !(1 == ~T4_E~0); 1639341#L889-3 assume !(1 == ~T5_E~0); 1639338#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1639335#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1639332#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1639329#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1639326#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1639323#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1639320#L924-3 assume !(1 == ~E_4~0); 1639314#L929-3 assume !(1 == ~E_5~0); 1639293#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1639290#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1639285#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1639279#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1639271#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1639266#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1627977#L1209 assume !(0 == start_simulation_~tmp~3#1); 1627978#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1638316#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1638310#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1638308#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1638306#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1638304#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1638302#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1638300#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1604007#L1190-2 [2023-11-19 07:40:27,636 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:40:27,636 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 2 times [2023-11-19 07:40:27,637 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:40:27,637 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1966281314] [2023-11-19 07:40:27,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:40:27,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:40:27,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:40:27,650 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:40:27,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:40:27,688 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:40:27,689 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:40:27,689 INFO L85 PathProgramCache]: Analyzing trace with hash -40946012, now seen corresponding path program 1 times [2023-11-19 07:40:27,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:40:27,689 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [342988870] [2023-11-19 07:40:27,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:40:27,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:40:27,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:40:27,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:40:27,727 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:40:27,727 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [342988870] [2023-11-19 07:40:27,727 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [342988870] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:40:27,727 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:40:27,728 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:40:27,728 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [875365274] [2023-11-19 07:40:27,728 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:40:27,728 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:40:27,728 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:40:27,729 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:40:27,729 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:40:27,729 INFO L87 Difference]: Start difference. First operand 55190 states and 76901 transitions. cyclomatic complexity: 21727 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:40:27,996 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:40:27,997 INFO L93 Difference]: Finished difference Result 82593 states and 114481 transitions. [2023-11-19 07:40:27,997 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 82593 states and 114481 transitions. [2023-11-19 07:40:28,269 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 82103 [2023-11-19 07:40:28,435 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 82593 states to 82593 states and 114481 transitions. [2023-11-19 07:40:28,435 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 82593 [2023-11-19 07:40:28,472 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 82593 [2023-11-19 07:40:28,473 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82593 states and 114481 transitions. [2023-11-19 07:40:28,504 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:40:28,504 INFO L218 hiAutomatonCegarLoop]: Abstraction has 82593 states and 114481 transitions. [2023-11-19 07:40:28,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82593 states and 114481 transitions. [2023-11-19 07:40:29,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82593 to 82539. [2023-11-19 07:40:29,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82539 states, 82539 states have (on average 1.3863385793382523) internal successors, (114427), 82538 states have internal predecessors, (114427), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:40:29,645 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82539 states to 82539 states and 114427 transitions. [2023-11-19 07:40:29,645 INFO L240 hiAutomatonCegarLoop]: Abstraction has 82539 states and 114427 transitions. [2023-11-19 07:40:29,645 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:40:29,646 INFO L428 stractBuchiCegarLoop]: Abstraction has 82539 states and 114427 transitions. [2023-11-19 07:40:29,646 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-19 07:40:29,646 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82539 states and 114427 transitions. [2023-11-19 07:40:29,829 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 82049 [2023-11-19 07:40:29,830 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:40:29,830 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:40:29,831 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:40:29,831 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:40:29,832 INFO L748 eck$LassoCheckResult]: Stem: 1741205#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1741206#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1741874#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1741875#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1742007#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1741355#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1741356#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1741491#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1741492#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1741253#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1741038#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1741039#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1741211#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1741212#L781 assume !(0 == ~M_E~0); 1741761#L781-2 assume !(0 == ~T1_E~0); 1742036#L786-1 assume !(0 == ~T2_E~0); 1741002#L791-1 assume !(0 == ~T3_E~0); 1741003#L796-1 assume !(0 == ~T4_E~0); 1741574#L801-1 assume !(0 == ~T5_E~0); 1741575#L806-1 assume !(0 == ~T6_E~0); 1741614#L811-1 assume !(0 == ~T7_E~0); 1741217#L816-1 assume !(0 == ~E_M~0); 1741218#L821-1 assume !(0 == ~E_1~0); 1741030#L826-1 assume !(0 == ~E_2~0); 1741031#L831-1 assume !(0 == ~E_3~0); 1741350#L836-1 assume !(0 == ~E_4~0); 1741351#L841-1 assume 0 == ~E_5~0;~E_5~0 := 1; 1741763#L846-1 assume !(0 == ~E_6~0); 1742020#L851-1 assume !(0 == ~E_7~0); 1741190#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1741191#L388 assume !(1 == ~m_pc~0); 1742080#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1742079#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1741793#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1741794#L967 assume !(0 != activate_threads_~tmp~1#1); 1741996#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1741997#L407 assume !(1 == ~t1_pc~0); 1742006#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1740985#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1740986#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1741018#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1741895#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1741896#L426 assume !(1 == ~t2_pc~0); 1741908#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1741909#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1742076#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1741981#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1741982#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1741399#L445 assume !(1 == ~t3_pc~0); 1741400#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1742073#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1740976#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1740977#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1741688#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1741647#L464 assume !(1 == ~t4_pc~0); 1741197#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1741198#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1742067#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1742066#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1742065#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1741643#L483 assume !(1 == ~t5_pc~0); 1741644#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1741841#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1741842#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1741940#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1741941#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1742064#L502 assume !(1 == ~t6_pc~0); 1741144#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1741145#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1741319#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1741320#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1741819#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1741820#L521 assume !(1 == ~t7_pc~0); 1741864#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1741040#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1741041#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1741855#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1741856#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1742062#L869 assume !(1 == ~M_E~0); 1742061#L869-2 assume !(1 == ~T1_E~0); 1741976#L874-1 assume !(1 == ~T2_E~0); 1741977#L879-1 assume !(1 == ~T3_E~0); 1741451#L884-1 assume !(1 == ~T4_E~0); 1741452#L889-1 assume !(1 == ~T5_E~0); 1741227#L894-1 assume !(1 == ~T6_E~0); 1741228#L899-1 assume !(1 == ~T7_E~0); 1741675#L904-1 assume !(1 == ~E_M~0); 1741396#L909-1 assume !(1 == ~E_1~0); 1741397#L914-1 assume !(1 == ~E_2~0); 1741624#L919-1 assume !(1 == ~E_3~0); 1741305#L924-1 assume !(1 == ~E_4~0); 1741137#L929-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1741138#L934-1 assume !(1 == ~E_6~0); 1741374#L939-1 assume !(1 == ~E_7~0); 1741375#L944-1 assume { :end_inline_reset_delta_events } true; 1741818#L1190-2 [2023-11-19 07:40:29,832 INFO L750 eck$LassoCheckResult]: Loop: 1741818#L1190-2 assume !false; 1788682#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1788680#L756-1 assume !false; 1788678#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1788676#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1788659#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1788651#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1788643#L653 assume !(0 != eval_~tmp~0#1); 1788644#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1788924#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1788923#L781-3 assume !(0 == ~M_E~0); 1788922#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1788921#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1788920#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1788919#L796-3 assume !(0 == ~T4_E~0); 1788918#L801-3 assume !(0 == ~T5_E~0); 1788916#L806-3 assume !(0 == ~T6_E~0); 1788914#L811-3 assume !(0 == ~T7_E~0); 1788912#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1788910#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1788908#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1788906#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1788904#L836-3 assume !(0 == ~E_4~0); 1788901#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1788899#L846-3 assume !(0 == ~E_6~0); 1788897#L851-3 assume !(0 == ~E_7~0); 1788895#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1788893#L388-27 assume !(1 == ~m_pc~0); 1788891#L388-29 is_master_triggered_~__retres1~0#1 := 0; 1788889#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1788887#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1788884#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1788882#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1788880#L407-27 assume !(1 == ~t1_pc~0); 1788878#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1788876#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1788874#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1788872#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 1788870#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1788868#L426-27 assume !(1 == ~t2_pc~0); 1788866#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1788863#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1788860#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1788858#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1788856#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1788854#L445-27 assume !(1 == ~t3_pc~0); 1788852#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1788850#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1788848#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1788846#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1788844#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1788842#L464-27 assume !(1 == ~t4_pc~0); 1788839#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1788837#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1788835#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1788833#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1788831#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1788829#L483-27 assume !(1 == ~t5_pc~0); 1788827#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1788825#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1788821#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1788819#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1788817#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1788815#L502-27 assume !(1 == ~t6_pc~0); 1788812#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1788810#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1788806#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1788804#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1788802#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1788800#L521-27 assume 1 == ~t7_pc~0; 1788798#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1788799#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1788937#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1788789#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1788787#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1788785#L869-3 assume !(1 == ~M_E~0); 1788781#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1788779#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1788777#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1788776#L884-3 assume !(1 == ~T4_E~0); 1788775#L889-3 assume !(1 == ~T5_E~0); 1788773#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1788771#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1788769#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1788767#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1788765#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1788763#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1788761#L924-3 assume !(1 == ~E_4~0); 1788759#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1788756#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1788753#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1788751#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1788739#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1788733#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1788731#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1788727#L1209 assume !(0 == start_simulation_~tmp~3#1); 1788725#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1788712#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1788706#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1788704#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1788702#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1788700#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1788698#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1788695#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1741818#L1190-2 [2023-11-19 07:40:29,832 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:40:29,833 INFO L85 PathProgramCache]: Analyzing trace with hash 2121315589, now seen corresponding path program 1 times [2023-11-19 07:40:29,835 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:40:29,835 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1498668656] [2023-11-19 07:40:29,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:40:29,836 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:40:29,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:40:29,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:40:29,893 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:40:29,893 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1498668656] [2023-11-19 07:40:29,893 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1498668656] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:40:29,894 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:40:29,894 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:40:29,894 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [627148291] [2023-11-19 07:40:29,894 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:40:29,894 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:40:29,895 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:40:29,895 INFO L85 PathProgramCache]: Analyzing trace with hash -772926621, now seen corresponding path program 1 times [2023-11-19 07:40:29,895 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:40:29,895 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2137013248] [2023-11-19 07:40:29,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:40:29,896 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:40:29,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:40:29,952 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:40:29,952 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:40:29,952 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2137013248] [2023-11-19 07:40:29,952 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2137013248] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:40:29,953 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:40:29,953 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:40:29,953 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1795352805] [2023-11-19 07:40:29,953 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:40:29,953 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:40:29,953 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:40:29,954 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:40:29,954 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:40:29,954 INFO L87 Difference]: Start difference. First operand 82539 states and 114427 transitions. cyclomatic complexity: 31904 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:40:30,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:40:30,328 INFO L93 Difference]: Finished difference Result 111668 states and 154603 transitions. [2023-11-19 07:40:30,328 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 111668 states and 154603 transitions. [2023-11-19 07:40:31,497 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 108622 [2023-11-19 07:40:31,811 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 111668 states to 111668 states and 154603 transitions. [2023-11-19 07:40:31,811 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 111668 [2023-11-19 07:40:31,869 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 111668 [2023-11-19 07:40:31,870 INFO L73 IsDeterministic]: Start isDeterministic. Operand 111668 states and 154603 transitions. [2023-11-19 07:40:31,925 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:40:31,926 INFO L218 hiAutomatonCegarLoop]: Abstraction has 111668 states and 154603 transitions. [2023-11-19 07:40:31,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111668 states and 154603 transitions. [2023-11-19 07:40:32,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111668 to 78564. [2023-11-19 07:40:32,785 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 78564 states, 78564 states have (on average 1.385570999439947) internal successors, (108856), 78563 states have internal predecessors, (108856), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:40:32,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78564 states to 78564 states and 108856 transitions. [2023-11-19 07:40:32,906 INFO L240 hiAutomatonCegarLoop]: Abstraction has 78564 states and 108856 transitions. [2023-11-19 07:40:32,907 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:40:32,907 INFO L428 stractBuchiCegarLoop]: Abstraction has 78564 states and 108856 transitions. [2023-11-19 07:40:32,907 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-19 07:40:32,907 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 78564 states and 108856 transitions.