./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.08.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 9bd2c7ff Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a0047f3-36d2-47c3-92db-95d2bceba819/bin/uautomizer-verify-uCwYo4JHxu/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a0047f3-36d2-47c3-92db-95d2bceba819/bin/uautomizer-verify-uCwYo4JHxu/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a0047f3-36d2-47c3-92db-95d2bceba819/bin/uautomizer-verify-uCwYo4JHxu/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a0047f3-36d2-47c3-92db-95d2bceba819/bin/uautomizer-verify-uCwYo4JHxu/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.08.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a0047f3-36d2-47c3-92db-95d2bceba819/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a0047f3-36d2-47c3-92db-95d2bceba819/bin/uautomizer-verify-uCwYo4JHxu --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 19daebdfafed51668fa57cd9e9dbb1892c2070de71da48d425d8df389215d260 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-9bd2c7f [2023-11-19 07:58:53,282 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-19 07:58:53,356 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a0047f3-36d2-47c3-92db-95d2bceba819/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-19 07:58:53,362 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-19 07:58:53,363 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-19 07:58:53,390 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-19 07:58:53,390 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-19 07:58:53,391 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-19 07:58:53,392 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-19 07:58:53,393 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-19 07:58:53,393 INFO L153 SettingsManager]: * Use SBE=true [2023-11-19 07:58:53,394 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-19 07:58:53,394 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-19 07:58:53,395 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-19 07:58:53,396 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-19 07:58:53,396 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-19 07:58:53,397 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-19 07:58:53,397 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-19 07:58:53,398 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-19 07:58:53,399 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-19 07:58:53,399 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-19 07:58:53,400 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-19 07:58:53,401 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-19 07:58:53,401 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-19 07:58:53,402 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-19 07:58:53,402 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-19 07:58:53,403 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-19 07:58:53,403 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-19 07:58:53,404 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-19 07:58:53,404 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-19 07:58:53,405 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-19 07:58:53,405 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-19 07:58:53,406 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-19 07:58:53,406 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-19 07:58:53,407 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-19 07:58:53,408 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-19 07:58:53,408 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a0047f3-36d2-47c3-92db-95d2bceba819/bin/uautomizer-verify-uCwYo4JHxu/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a0047f3-36d2-47c3-92db-95d2bceba819/bin/uautomizer-verify-uCwYo4JHxu Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 19daebdfafed51668fa57cd9e9dbb1892c2070de71da48d425d8df389215d260 [2023-11-19 07:58:53,686 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-19 07:58:53,721 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-19 07:58:53,724 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-19 07:58:53,727 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-19 07:58:53,728 INFO L274 PluginConnector]: CDTParser initialized [2023-11-19 07:58:53,729 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a0047f3-36d2-47c3-92db-95d2bceba819/bin/uautomizer-verify-uCwYo4JHxu/../../sv-benchmarks/c/systemc/token_ring.08.cil-2.c [2023-11-19 07:58:56,949 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-19 07:58:57,262 INFO L384 CDTParser]: Found 1 translation units. [2023-11-19 07:58:57,263 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a0047f3-36d2-47c3-92db-95d2bceba819/sv-benchmarks/c/systemc/token_ring.08.cil-2.c [2023-11-19 07:58:57,287 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a0047f3-36d2-47c3-92db-95d2bceba819/bin/uautomizer-verify-uCwYo4JHxu/data/085e3ccf1/110678d2c9ce4da8a00a96b080f3949d/FLAGd385d02b4 [2023-11-19 07:58:57,301 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a0047f3-36d2-47c3-92db-95d2bceba819/bin/uautomizer-verify-uCwYo4JHxu/data/085e3ccf1/110678d2c9ce4da8a00a96b080f3949d [2023-11-19 07:58:57,303 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-19 07:58:57,305 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-19 07:58:57,306 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-19 07:58:57,307 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-19 07:58:57,320 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-19 07:58:57,321 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:58:57" (1/1) ... [2023-11-19 07:58:57,325 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@643d86dc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:57, skipping insertion in model container [2023-11-19 07:58:57,325 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:58:57" (1/1) ... [2023-11-19 07:58:57,400 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-19 07:58:57,636 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:58:57,652 INFO L202 MainTranslator]: Completed pre-run [2023-11-19 07:58:57,743 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:58:57,773 INFO L206 MainTranslator]: Completed translation [2023-11-19 07:58:57,773 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:57 WrapperNode [2023-11-19 07:58:57,774 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-19 07:58:57,775 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-19 07:58:57,775 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-19 07:58:57,775 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-19 07:58:57,782 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:57" (1/1) ... [2023-11-19 07:58:57,794 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:57" (1/1) ... [2023-11-19 07:58:57,903 INFO L138 Inliner]: procedures = 44, calls = 57, calls flagged for inlining = 52, calls inlined = 160, statements flattened = 2391 [2023-11-19 07:58:57,904 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-19 07:58:57,904 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-19 07:58:57,905 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-19 07:58:57,905 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-19 07:58:57,915 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:57" (1/1) ... [2023-11-19 07:58:57,915 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:57" (1/1) ... [2023-11-19 07:58:57,924 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:57" (1/1) ... [2023-11-19 07:58:57,924 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:57" (1/1) ... [2023-11-19 07:58:57,962 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:57" (1/1) ... [2023-11-19 07:58:58,022 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:57" (1/1) ... [2023-11-19 07:58:58,027 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:57" (1/1) ... [2023-11-19 07:58:58,047 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:57" (1/1) ... [2023-11-19 07:58:58,062 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-19 07:58:58,063 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-19 07:58:58,064 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-19 07:58:58,064 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-19 07:58:58,065 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:57" (1/1) ... [2023-11-19 07:58:58,071 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 07:58:58,084 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a0047f3-36d2-47c3-92db-95d2bceba819/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:58:58,097 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a0047f3-36d2-47c3-92db-95d2bceba819/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 07:58:58,121 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a0047f3-36d2-47c3-92db-95d2bceba819/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-19 07:58:58,154 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-19 07:58:58,154 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-19 07:58:58,154 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-19 07:58:58,154 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-19 07:58:58,316 INFO L236 CfgBuilder]: Building ICFG [2023-11-19 07:58:58,319 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-19 07:59:00,139 INFO L277 CfgBuilder]: Performing block encoding [2023-11-19 07:59:00,165 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-19 07:59:00,165 INFO L302 CfgBuilder]: Removed 11 assume(true) statements. [2023-11-19 07:59:00,178 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:59:00 BoogieIcfgContainer [2023-11-19 07:59:00,178 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-19 07:59:00,179 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-19 07:59:00,181 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-19 07:59:00,185 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-19 07:59:00,186 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:59:00,186 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 07:58:57" (1/3) ... [2023-11-19 07:59:00,187 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@71776ba3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:59:00, skipping insertion in model container [2023-11-19 07:59:00,187 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:59:00,188 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:57" (2/3) ... [2023-11-19 07:59:00,189 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@71776ba3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:59:00, skipping insertion in model container [2023-11-19 07:59:00,190 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:59:00,190 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:59:00" (3/3) ... [2023-11-19 07:59:00,191 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.08.cil-2.c [2023-11-19 07:59:00,284 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-19 07:59:00,284 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-19 07:59:00,285 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-19 07:59:00,285 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-19 07:59:00,285 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-19 07:59:00,285 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-19 07:59:00,285 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-19 07:59:00,285 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-19 07:59:00,295 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1017 states, 1016 states have (on average 1.5098425196850394) internal successors, (1534), 1016 states have internal predecessors, (1534), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:00,373 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 898 [2023-11-19 07:59:00,374 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:00,374 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:00,389 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:00,389 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:00,389 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-19 07:59:00,393 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1017 states, 1016 states have (on average 1.5098425196850394) internal successors, (1534), 1016 states have internal predecessors, (1534), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:00,411 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 898 [2023-11-19 07:59:00,411 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:00,411 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:00,421 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:00,422 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:00,440 INFO L748 eck$LassoCheckResult]: Stem: 124#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 936#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 760#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 934#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 318#L609true assume !(1 == ~m_i~0);~m_st~0 := 2; 1016#L609-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 59#L614-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 104#L619-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 735#L624-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 978#L629-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 43#L634-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 289#L639-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 874#L644-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 310#L649-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 107#L866true assume !(0 == ~M_E~0); 982#L866-2true assume !(0 == ~T1_E~0); 457#L871-1true assume !(0 == ~T2_E~0); 857#L876-1true assume !(0 == ~T3_E~0); 850#L881-1true assume !(0 == ~T4_E~0); 472#L886-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 283#L891-1true assume !(0 == ~T6_E~0); 462#L896-1true assume !(0 == ~T7_E~0); 595#L901-1true assume !(0 == ~T8_E~0); 485#L906-1true assume !(0 == ~E_M~0); 871#L911-1true assume !(0 == ~E_1~0); 316#L916-1true assume !(0 == ~E_2~0); 597#L921-1true assume !(0 == ~E_3~0); 756#L926-1true assume 0 == ~E_4~0;~E_4~0 := 1; 878#L931-1true assume !(0 == ~E_5~0); 903#L936-1true assume !(0 == ~E_6~0); 992#L941-1true assume !(0 == ~E_7~0); 319#L946-1true assume !(0 == ~E_8~0); 796#L951-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 907#L430true assume !(1 == ~m_pc~0); 699#L430-2true is_master_triggered_~__retres1~0#1 := 0; 16#L441true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 651#is_master_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 405#L1073true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 833#L1073-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 575#L449true assume 1 == ~t1_pc~0; 600#L450true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 828#L460true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 912#L1081true assume !(0 != activate_threads_~tmp___0~0#1); 497#L1081-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 358#L468true assume !(1 == ~t2_pc~0); 228#L468-2true is_transmit2_triggered_~__retres1~2#1 := 0; 445#L479true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 223#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 220#L1089true assume !(0 != activate_threads_~tmp___1~0#1); 17#L1089-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 905#L487true assume 1 == ~t3_pc~0; 836#L488true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 62#L498true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 654#L1097true assume !(0 != activate_threads_~tmp___2~0#1); 271#L1097-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 354#L506true assume !(1 == ~t4_pc~0); 867#L506-2true is_transmit4_triggered_~__retres1~4#1 := 0; 983#L517true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 837#L1105true assume !(0 != activate_threads_~tmp___3~0#1); 348#L1105-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 229#L525true assume 1 == ~t5_pc~0; 185#L526true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 721#L536true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 656#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 969#L1113true assume !(0 != activate_threads_~tmp___4~0#1); 141#L1113-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 346#L544true assume !(1 == ~t6_pc~0); 230#L544-2true is_transmit6_triggered_~__retres1~6#1 := 0; 512#L555true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 211#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26#L1121true assume !(0 != activate_threads_~tmp___5~0#1); 810#L1121-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 715#L563true assume 1 == ~t7_pc~0; 528#L564true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38#L574true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 950#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 284#L1129true assume !(0 != activate_threads_~tmp___6~0#1); 113#L1129-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 513#L582true assume 1 == ~t8_pc~0; 71#L583true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 840#L593true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 583#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 262#L1137true assume !(0 != activate_threads_~tmp___7~0#1); 187#L1137-2true havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 579#L964true assume 1 == ~M_E~0;~M_E~0 := 2; 832#L964-2true assume !(1 == ~T1_E~0); 142#L969-1true assume !(1 == ~T2_E~0); 766#L974-1true assume !(1 == ~T3_E~0); 623#L979-1true assume !(1 == ~T4_E~0); 964#L984-1true assume !(1 == ~T5_E~0); 233#L989-1true assume !(1 == ~T6_E~0); 466#L994-1true assume !(1 == ~T7_E~0); 160#L999-1true assume 1 == ~T8_E~0;~T8_E~0 := 2; 584#L1004-1true assume !(1 == ~E_M~0); 27#L1009-1true assume !(1 == ~E_1~0); 154#L1014-1true assume !(1 == ~E_2~0); 565#L1019-1true assume !(1 == ~E_3~0); 809#L1024-1true assume !(1 == ~E_4~0); 122#L1029-1true assume !(1 == ~E_5~0); 169#L1034-1true assume !(1 == ~E_6~0); 994#L1039-1true assume 1 == ~E_7~0;~E_7~0 := 2; 781#L1044-1true assume !(1 == ~E_8~0); 295#L1049-1true assume { :end_inline_reset_delta_events } true; 103#L1315-2true [2023-11-19 07:59:00,447 INFO L750 eck$LassoCheckResult]: Loop: 103#L1315-2true assume !false; 885#L1316true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 608#L841-1true assume !true; 593#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 355#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19#L866-3true assume 0 == ~M_E~0;~M_E~0 := 1; 845#L866-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 173#L871-3true assume !(0 == ~T2_E~0); 274#L876-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 182#L881-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 688#L886-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 335#L891-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 469#L896-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 245#L901-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 337#L906-3true assume 0 == ~E_M~0;~E_M~0 := 1; 609#L911-3true assume !(0 == ~E_1~0); 520#L916-3true assume 0 == ~E_2~0;~E_2~0 := 1; 196#L921-3true assume 0 == ~E_3~0;~E_3~0 := 1; 504#L926-3true assume 0 == ~E_4~0;~E_4~0 := 1; 603#L931-3true assume 0 == ~E_5~0;~E_5~0 := 1; 251#L936-3true assume 0 == ~E_6~0;~E_6~0 := 1; 347#L941-3true assume 0 == ~E_7~0;~E_7~0 := 1; 606#L946-3true assume 0 == ~E_8~0;~E_8~0 := 1; 174#L951-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 879#L430-30true assume !(1 == ~m_pc~0); 648#L430-32true is_master_triggered_~__retres1~0#1 := 0; 259#L441-10true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 236#is_master_triggered_returnLabel#11true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 545#L1073-30true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 927#L1073-32true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 555#L449-30true assume 1 == ~t1_pc~0; 189#L450-10true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25#L460-10true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 387#is_transmit1_triggered_returnLabel#11true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 232#L1081-30true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 68#L1081-32true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 397#L468-30true assume 1 == ~t2_pc~0; 120#L469-10true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 617#L479-10true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 172#is_transmit2_triggered_returnLabel#11true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 330#L1089-30true assume !(0 != activate_threads_~tmp___1~0#1); 795#L1089-32true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 224#L487-30true assume !(1 == ~t3_pc~0); 106#L487-32true is_transmit3_triggered_~__retres1~3#1 := 0; 862#L498-10true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 375#is_transmit3_triggered_returnLabel#11true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 821#L1097-30true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 573#L1097-32true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 280#L506-30true assume !(1 == ~t4_pc~0); 535#L506-32true is_transmit4_triggered_~__retres1~4#1 := 0; 297#L517-10true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 849#is_transmit4_triggered_returnLabel#11true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 638#L1105-30true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 225#L1105-32true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 985#L525-30true assume 1 == ~t5_pc~0; 709#L526-10true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 930#L536-10true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 477#is_transmit5_triggered_returnLabel#11true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 694#L1113-30true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 227#L1113-32true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 94#L544-30true assume 1 == ~t6_pc~0; 4#L545-10true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 881#L555-10true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58#is_transmit6_triggered_returnLabel#11true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 723#L1121-30true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1004#L1121-32true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 685#L563-30true assume !(1 == ~t7_pc~0); 162#L563-32true is_transmit7_triggered_~__retres1~7#1 := 0; 88#L574-10true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 540#is_transmit7_triggered_returnLabel#11true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 290#L1129-30true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 920#L1129-32true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 666#L582-30true assume !(1 == ~t8_pc~0); 135#L582-32true is_transmit8_triggered_~__retres1~8#1 := 0; 281#L593-10true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 989#is_transmit8_triggered_returnLabel#11true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1002#L1137-30true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 914#L1137-32true havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32#L964-3true assume 1 == ~M_E~0;~M_E~0 := 2; 101#L964-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 208#L969-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 96#L974-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 932#L979-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 363#L984-3true assume !(1 == ~T5_E~0); 996#L989-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 125#L994-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 843#L999-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 494#L1004-3true assume 1 == ~E_M~0;~E_M~0 := 2; 51#L1009-3true assume 1 == ~E_1~0;~E_1~0 := 2; 558#L1014-3true assume 1 == ~E_2~0;~E_2~0 := 2; 343#L1019-3true assume 1 == ~E_3~0;~E_3~0 := 2; 980#L1024-3true assume !(1 == ~E_4~0); 331#L1029-3true assume 1 == ~E_5~0;~E_5~0 := 2; 313#L1034-3true assume 1 == ~E_6~0;~E_6~0 := 2; 564#L1039-3true assume 1 == ~E_7~0;~E_7~0 := 2; 598#L1044-3true assume 1 == ~E_8~0;~E_8~0 := 2; 119#L1049-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 470#L662-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 706#L709-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 190#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 138#L1334true assume !(0 == start_simulation_~tmp~3#1); 827#L1334-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 144#L662-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2#L709-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 28#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 928#L1289true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 758#L1296true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 371#stop_simulation_returnLabel#1true start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 734#L1347true assume !(0 != start_simulation_~tmp___0~1#1); 103#L1315-2true [2023-11-19 07:59:00,464 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:00,464 INFO L85 PathProgramCache]: Analyzing trace with hash -1103313420, now seen corresponding path program 1 times [2023-11-19 07:59:00,471 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:00,472 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [13760796] [2023-11-19 07:59:00,472 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:00,473 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:00,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:00,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:00,818 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:00,819 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [13760796] [2023-11-19 07:59:00,819 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [13760796] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:00,820 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:00,820 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:00,823 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1446016331] [2023-11-19 07:59:00,823 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:00,830 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:00,831 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:00,831 INFO L85 PathProgramCache]: Analyzing trace with hash -1219078109, now seen corresponding path program 1 times [2023-11-19 07:59:00,832 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:00,832 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [28002752] [2023-11-19 07:59:00,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:00,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:00,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:00,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:00,951 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:00,951 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [28002752] [2023-11-19 07:59:00,952 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [28002752] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:00,952 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:00,952 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:59:00,952 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1429418454] [2023-11-19 07:59:00,953 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:00,954 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:00,955 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:01,015 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:59:01,015 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:59:01,019 INFO L87 Difference]: Start difference. First operand has 1017 states, 1016 states have (on average 1.5098425196850394) internal successors, (1534), 1016 states have internal predecessors, (1534), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:01,118 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:01,118 INFO L93 Difference]: Finished difference Result 1013 states and 1505 transitions. [2023-11-19 07:59:01,120 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1013 states and 1505 transitions. [2023-11-19 07:59:01,134 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-19 07:59:01,150 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1013 states to 1007 states and 1499 transitions. [2023-11-19 07:59:01,151 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1007 [2023-11-19 07:59:01,154 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1007 [2023-11-19 07:59:01,155 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1007 states and 1499 transitions. [2023-11-19 07:59:01,168 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:01,168 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1499 transitions. [2023-11-19 07:59:01,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states and 1499 transitions. [2023-11-19 07:59:01,254 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1007. [2023-11-19 07:59:01,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.4885799404170805) internal successors, (1499), 1006 states have internal predecessors, (1499), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:01,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1499 transitions. [2023-11-19 07:59:01,263 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1499 transitions. [2023-11-19 07:59:01,265 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:59:01,268 INFO L428 stractBuchiCegarLoop]: Abstraction has 1007 states and 1499 transitions. [2023-11-19 07:59:01,269 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-19 07:59:01,269 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1499 transitions. [2023-11-19 07:59:01,277 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-19 07:59:01,278 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:01,278 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:01,280 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:01,281 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:01,281 INFO L748 eck$LassoCheckResult]: Stem: 2287#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2288#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 3001#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3002#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2601#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 2602#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2159#L614-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2160#L619-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2251#L624-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2987#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2127#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2128#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2556#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2588#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2255#L866 assume !(0 == ~M_E~0); 2256#L866-2 assume !(0 == ~T1_E~0); 2786#L871-1 assume !(0 == ~T2_E~0); 2787#L876-1 assume !(0 == ~T3_E~0); 3027#L881-1 assume !(0 == ~T4_E~0); 2800#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2545#L891-1 assume !(0 == ~T6_E~0); 2546#L896-1 assume !(0 == ~T7_E~0); 2794#L901-1 assume !(0 == ~T8_E~0); 2815#L906-1 assume !(0 == ~E_M~0); 2816#L911-1 assume !(0 == ~E_1~0); 2598#L916-1 assume !(0 == ~E_2~0); 2599#L921-1 assume !(0 == ~E_3~0); 2908#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2998#L931-1 assume !(0 == ~E_5~0); 3030#L936-1 assume !(0 == ~E_6~0); 3034#L941-1 assume !(0 == ~E_7~0); 2603#L946-1 assume !(0 == ~E_8~0); 2604#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3015#L430 assume !(1 == ~m_pc~0); 2445#L430-2 is_master_triggered_~__retres1~0#1 := 0; 2074#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2075#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2720#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2721#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2889#L449 assume 1 == ~t1_pc~0; 2890#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2262#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2101#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2102#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 2830#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2660#L468 assume !(1 == ~t2_pc~0); 2062#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2061#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2455#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2450#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 2076#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2077#L487 assume 1 == ~t3_pc~0; 3025#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2165#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2058#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2059#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 2523#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2524#L506 assume !(1 == ~t4_pc~0); 2655#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2705#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2151#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2152#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 2649#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2462#L525 assume 1 == ~t5_pc~0; 2396#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2115#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2946#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2947#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 2319#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2320#L544 assume !(1 == ~t6_pc~0); 2463#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2464#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2435#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2096#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 2097#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2979#L563 assume 1 == ~t7_pc~0; 2853#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2119#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2120#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2547#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 2263#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2264#L582 assume 1 == ~t8_pc~0; 2183#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2184#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2895#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2511#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 2400#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2401#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 2893#L964-2 assume !(1 == ~T1_E~0); 2321#L969-1 assume !(1 == ~T2_E~0); 2322#L974-1 assume !(1 == ~T3_E~0); 2926#L979-1 assume !(1 == ~T4_E~0); 2927#L984-1 assume !(1 == ~T5_E~0); 2469#L989-1 assume !(1 == ~T6_E~0); 2470#L994-1 assume !(1 == ~T7_E~0); 2352#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2353#L1004-1 assume !(1 == ~E_M~0); 2098#L1009-1 assume !(1 == ~E_1~0); 2099#L1014-1 assume !(1 == ~E_2~0); 2341#L1019-1 assume !(1 == ~E_3~0); 2881#L1024-1 assume !(1 == ~E_4~0); 2284#L1029-1 assume !(1 == ~E_5~0); 2285#L1034-1 assume !(1 == ~E_6~0); 2368#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 3011#L1044-1 assume !(1 == ~E_8~0); 2567#L1049-1 assume { :end_inline_reset_delta_events } true; 2249#L1315-2 [2023-11-19 07:59:01,282 INFO L750 eck$LassoCheckResult]: Loop: 2249#L1315-2 assume !false; 2250#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2663#L841-1 assume !false; 2917#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2314#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2315#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2496#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2071#L724 assume !(0 != eval_~tmp~0#1); 2073#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2657#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2080#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2081#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2373#L871-3 assume !(0 == ~T2_E~0); 2374#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2390#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2391#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2631#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2632#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2489#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2490#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2633#L911-3 assume !(0 == ~E_1~0); 2847#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2417#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2418#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2836#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2497#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2498#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2648#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2375#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2376#L430-30 assume 1 == ~m_pc~0; 2402#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2403#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2474#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2475#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2864#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2870#L449-30 assume 1 == ~t1_pc~0; 2405#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2094#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2095#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2468#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2179#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2180#L468-30 assume 1 == ~t2_pc~0; 2279#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2280#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2371#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2372#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 2623#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2456#L487-30 assume 1 == ~t3_pc~0; 2434#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2254#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2685#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2686#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2888#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2540#L506-30 assume !(1 == ~t4_pc~0); 2541#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2570#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2571#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2934#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2457#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2458#L525-30 assume !(1 == ~t5_pc~0); 2977#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 2976#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2804#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2805#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2461#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2231#L544-30 assume 1 == ~t6_pc~0; 2043#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2044#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2157#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2158#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2982#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2965#L563-30 assume 1 == ~t7_pc~0; 2198#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2199#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2220#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2557#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2558#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2955#L582-30 assume 1 == ~t8_pc~0; 2915#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2308#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2543#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3045#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3035#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2106#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2107#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2245#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2234#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2235#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2669#L984-3 assume !(1 == ~T5_E~0); 2670#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2289#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2290#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2828#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2142#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2143#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2645#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2646#L1024-3 assume !(1 == ~E_4~0); 2624#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2593#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2594#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2880#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2277#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2278#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2398#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2407#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2311#L1334 assume !(0 == start_simulation_~tmp~3#1); 2312#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2325#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2039#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2040#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2100#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3000#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2679#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2680#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 2249#L1315-2 [2023-11-19 07:59:01,283 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:01,284 INFO L85 PathProgramCache]: Analyzing trace with hash 763395254, now seen corresponding path program 1 times [2023-11-19 07:59:01,284 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:01,285 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [277510260] [2023-11-19 07:59:01,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:01,285 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:01,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:01,362 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:01,362 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:01,363 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [277510260] [2023-11-19 07:59:01,363 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [277510260] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:01,363 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:01,363 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:01,364 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [946163781] [2023-11-19 07:59:01,364 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:01,365 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:01,365 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:01,365 INFO L85 PathProgramCache]: Analyzing trace with hash 13135423, now seen corresponding path program 1 times [2023-11-19 07:59:01,366 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:01,366 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1313426591] [2023-11-19 07:59:01,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:01,366 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:01,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:01,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:01,510 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:01,511 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1313426591] [2023-11-19 07:59:01,511 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1313426591] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:01,512 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:01,512 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:01,512 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [176995482] [2023-11-19 07:59:01,512 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:01,514 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:01,516 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:01,516 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:59:01,516 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:59:01,517 INFO L87 Difference]: Start difference. First operand 1007 states and 1499 transitions. cyclomatic complexity: 493 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:01,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:01,565 INFO L93 Difference]: Finished difference Result 1007 states and 1498 transitions. [2023-11-19 07:59:01,565 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1498 transitions. [2023-11-19 07:59:01,575 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-19 07:59:01,584 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1007 states and 1498 transitions. [2023-11-19 07:59:01,585 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1007 [2023-11-19 07:59:01,587 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1007 [2023-11-19 07:59:01,587 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1007 states and 1498 transitions. [2023-11-19 07:59:01,590 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:01,590 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1498 transitions. [2023-11-19 07:59:01,593 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states and 1498 transitions. [2023-11-19 07:59:01,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1007. [2023-11-19 07:59:01,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.4875868917576962) internal successors, (1498), 1006 states have internal predecessors, (1498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:01,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1498 transitions. [2023-11-19 07:59:01,659 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1498 transitions. [2023-11-19 07:59:01,660 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:59:01,661 INFO L428 stractBuchiCegarLoop]: Abstraction has 1007 states and 1498 transitions. [2023-11-19 07:59:01,663 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-19 07:59:01,663 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1498 transitions. [2023-11-19 07:59:01,671 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-19 07:59:01,672 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:01,672 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:01,676 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:01,682 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:01,684 INFO L748 eck$LassoCheckResult]: Stem: 4308#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 4309#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 5022#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5023#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4622#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 4623#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4180#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4181#L619-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4272#L624-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5008#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4148#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4149#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4577#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4609#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4276#L866 assume !(0 == ~M_E~0); 4277#L866-2 assume !(0 == ~T1_E~0); 4807#L871-1 assume !(0 == ~T2_E~0); 4808#L876-1 assume !(0 == ~T3_E~0); 5048#L881-1 assume !(0 == ~T4_E~0); 4821#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4566#L891-1 assume !(0 == ~T6_E~0); 4567#L896-1 assume !(0 == ~T7_E~0); 4815#L901-1 assume !(0 == ~T8_E~0); 4836#L906-1 assume !(0 == ~E_M~0); 4837#L911-1 assume !(0 == ~E_1~0); 4619#L916-1 assume !(0 == ~E_2~0); 4620#L921-1 assume !(0 == ~E_3~0); 4929#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 5019#L931-1 assume !(0 == ~E_5~0); 5051#L936-1 assume !(0 == ~E_6~0); 5055#L941-1 assume !(0 == ~E_7~0); 4624#L946-1 assume !(0 == ~E_8~0); 4625#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5036#L430 assume !(1 == ~m_pc~0); 4466#L430-2 is_master_triggered_~__retres1~0#1 := 0; 4095#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4096#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4741#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4742#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4910#L449 assume 1 == ~t1_pc~0; 4911#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4283#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4122#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4123#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 4851#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4681#L468 assume !(1 == ~t2_pc~0); 4083#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4082#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4476#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4471#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 4097#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4098#L487 assume 1 == ~t3_pc~0; 5046#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4186#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4079#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4080#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 4544#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4545#L506 assume !(1 == ~t4_pc~0); 4676#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4726#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4172#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4173#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 4670#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4483#L525 assume 1 == ~t5_pc~0; 4417#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4136#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4967#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4968#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 4340#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4341#L544 assume !(1 == ~t6_pc~0); 4484#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4485#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4456#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4117#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 4118#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5000#L563 assume 1 == ~t7_pc~0; 4874#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4140#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4141#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4568#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 4284#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4285#L582 assume 1 == ~t8_pc~0; 4204#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4205#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4916#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4532#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 4421#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4422#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 4914#L964-2 assume !(1 == ~T1_E~0); 4342#L969-1 assume !(1 == ~T2_E~0); 4343#L974-1 assume !(1 == ~T3_E~0); 4947#L979-1 assume !(1 == ~T4_E~0); 4948#L984-1 assume !(1 == ~T5_E~0); 4490#L989-1 assume !(1 == ~T6_E~0); 4491#L994-1 assume !(1 == ~T7_E~0); 4373#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4374#L1004-1 assume !(1 == ~E_M~0); 4119#L1009-1 assume !(1 == ~E_1~0); 4120#L1014-1 assume !(1 == ~E_2~0); 4362#L1019-1 assume !(1 == ~E_3~0); 4902#L1024-1 assume !(1 == ~E_4~0); 4305#L1029-1 assume !(1 == ~E_5~0); 4306#L1034-1 assume !(1 == ~E_6~0); 4389#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 5032#L1044-1 assume !(1 == ~E_8~0); 4588#L1049-1 assume { :end_inline_reset_delta_events } true; 4270#L1315-2 [2023-11-19 07:59:01,685 INFO L750 eck$LassoCheckResult]: Loop: 4270#L1315-2 assume !false; 4271#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4684#L841-1 assume !false; 4938#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4335#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4336#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4517#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4092#L724 assume !(0 != eval_~tmp~0#1); 4094#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4678#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4101#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4102#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4394#L871-3 assume !(0 == ~T2_E~0); 4395#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4411#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4412#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4652#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4653#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4510#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4511#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4654#L911-3 assume !(0 == ~E_1~0); 4868#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4438#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4439#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4857#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4518#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4519#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4669#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4396#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4397#L430-30 assume 1 == ~m_pc~0; 4423#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4424#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4495#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4496#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4885#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4891#L449-30 assume 1 == ~t1_pc~0; 4426#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4115#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4116#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4489#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4200#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4201#L468-30 assume 1 == ~t2_pc~0; 4300#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4301#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4392#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4393#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 4644#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4477#L487-30 assume !(1 == ~t3_pc~0); 4274#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 4275#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4706#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4707#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4909#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4561#L506-30 assume !(1 == ~t4_pc~0); 4562#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 4591#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4592#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4955#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4478#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4479#L525-30 assume 1 == ~t5_pc~0; 4996#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4997#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4825#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4826#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4482#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4252#L544-30 assume 1 == ~t6_pc~0; 4064#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4065#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4178#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4179#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5003#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4986#L563-30 assume 1 == ~t7_pc~0; 4219#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4220#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4241#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4578#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4579#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4976#L582-30 assume 1 == ~t8_pc~0; 4936#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4329#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4564#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5066#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5056#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4127#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4128#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4266#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4255#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4256#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4690#L984-3 assume !(1 == ~T5_E~0); 4691#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4310#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4311#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4849#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4163#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4164#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4666#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4667#L1024-3 assume !(1 == ~E_4~0); 4645#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4614#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4615#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4901#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4298#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4299#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4419#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4428#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 4332#L1334 assume !(0 == start_simulation_~tmp~3#1); 4333#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4346#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4060#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4061#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 4121#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5021#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4700#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 4701#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 4270#L1315-2 [2023-11-19 07:59:01,687 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:01,687 INFO L85 PathProgramCache]: Analyzing trace with hash -1134101512, now seen corresponding path program 1 times [2023-11-19 07:59:01,688 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:01,688 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1361694428] [2023-11-19 07:59:01,688 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:01,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:01,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:01,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:01,788 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:01,788 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1361694428] [2023-11-19 07:59:01,788 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1361694428] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:01,789 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:01,789 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:01,789 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1202928914] [2023-11-19 07:59:01,789 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:01,790 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:01,790 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:01,790 INFO L85 PathProgramCache]: Analyzing trace with hash -1036208961, now seen corresponding path program 1 times [2023-11-19 07:59:01,791 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:01,791 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1120340694] [2023-11-19 07:59:01,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:01,791 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:01,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:01,860 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:01,861 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:01,861 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1120340694] [2023-11-19 07:59:01,861 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1120340694] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:01,861 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:01,862 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:01,862 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [653536380] [2023-11-19 07:59:01,862 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:01,863 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:01,863 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:01,863 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:59:01,864 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:59:01,864 INFO L87 Difference]: Start difference. First operand 1007 states and 1498 transitions. cyclomatic complexity: 492 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:01,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:01,890 INFO L93 Difference]: Finished difference Result 1007 states and 1497 transitions. [2023-11-19 07:59:01,891 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1497 transitions. [2023-11-19 07:59:01,900 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-19 07:59:01,908 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1007 states and 1497 transitions. [2023-11-19 07:59:01,909 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1007 [2023-11-19 07:59:01,910 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1007 [2023-11-19 07:59:01,910 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1007 states and 1497 transitions. [2023-11-19 07:59:01,912 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:01,913 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1497 transitions. [2023-11-19 07:59:01,915 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states and 1497 transitions. [2023-11-19 07:59:01,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1007. [2023-11-19 07:59:01,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.4865938430983119) internal successors, (1497), 1006 states have internal predecessors, (1497), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:01,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1497 transitions. [2023-11-19 07:59:01,937 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1497 transitions. [2023-11-19 07:59:01,937 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:59:01,939 INFO L428 stractBuchiCegarLoop]: Abstraction has 1007 states and 1497 transitions. [2023-11-19 07:59:01,940 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-19 07:59:01,940 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1497 transitions. [2023-11-19 07:59:01,947 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-19 07:59:01,947 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:01,947 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:01,955 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:01,955 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:01,955 INFO L748 eck$LassoCheckResult]: Stem: 6329#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 6330#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 7043#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7044#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6643#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 6644#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6201#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6202#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6293#L624-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7029#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6169#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6170#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6598#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6630#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6297#L866 assume !(0 == ~M_E~0); 6298#L866-2 assume !(0 == ~T1_E~0); 6828#L871-1 assume !(0 == ~T2_E~0); 6829#L876-1 assume !(0 == ~T3_E~0); 7069#L881-1 assume !(0 == ~T4_E~0); 6842#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6587#L891-1 assume !(0 == ~T6_E~0); 6588#L896-1 assume !(0 == ~T7_E~0); 6836#L901-1 assume !(0 == ~T8_E~0); 6857#L906-1 assume !(0 == ~E_M~0); 6858#L911-1 assume !(0 == ~E_1~0); 6640#L916-1 assume !(0 == ~E_2~0); 6641#L921-1 assume !(0 == ~E_3~0); 6950#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 7040#L931-1 assume !(0 == ~E_5~0); 7072#L936-1 assume !(0 == ~E_6~0); 7076#L941-1 assume !(0 == ~E_7~0); 6645#L946-1 assume !(0 == ~E_8~0); 6646#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7057#L430 assume !(1 == ~m_pc~0); 6487#L430-2 is_master_triggered_~__retres1~0#1 := 0; 6116#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6117#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6762#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6763#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6931#L449 assume 1 == ~t1_pc~0; 6932#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6304#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6143#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6144#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 6872#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6702#L468 assume !(1 == ~t2_pc~0); 6104#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6103#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6497#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6492#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 6118#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6119#L487 assume 1 == ~t3_pc~0; 7067#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6207#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6100#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6101#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 6565#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6566#L506 assume !(1 == ~t4_pc~0); 6697#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6747#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6193#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6194#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 6691#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6504#L525 assume 1 == ~t5_pc~0; 6438#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6157#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6988#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6989#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 6361#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6362#L544 assume !(1 == ~t6_pc~0); 6505#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6506#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6477#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6138#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 6139#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7021#L563 assume 1 == ~t7_pc~0; 6895#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6161#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6162#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6589#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 6305#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6306#L582 assume 1 == ~t8_pc~0; 6225#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6226#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6937#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6553#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 6442#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6443#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 6935#L964-2 assume !(1 == ~T1_E~0); 6363#L969-1 assume !(1 == ~T2_E~0); 6364#L974-1 assume !(1 == ~T3_E~0); 6968#L979-1 assume !(1 == ~T4_E~0); 6969#L984-1 assume !(1 == ~T5_E~0); 6511#L989-1 assume !(1 == ~T6_E~0); 6512#L994-1 assume !(1 == ~T7_E~0); 6394#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6395#L1004-1 assume !(1 == ~E_M~0); 6140#L1009-1 assume !(1 == ~E_1~0); 6141#L1014-1 assume !(1 == ~E_2~0); 6383#L1019-1 assume !(1 == ~E_3~0); 6923#L1024-1 assume !(1 == ~E_4~0); 6326#L1029-1 assume !(1 == ~E_5~0); 6327#L1034-1 assume !(1 == ~E_6~0); 6410#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7053#L1044-1 assume !(1 == ~E_8~0); 6609#L1049-1 assume { :end_inline_reset_delta_events } true; 6291#L1315-2 [2023-11-19 07:59:01,956 INFO L750 eck$LassoCheckResult]: Loop: 6291#L1315-2 assume !false; 6292#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6705#L841-1 assume !false; 6959#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6356#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6357#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6538#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6113#L724 assume !(0 != eval_~tmp~0#1); 6115#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6699#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6122#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6123#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6415#L871-3 assume !(0 == ~T2_E~0); 6416#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6432#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6433#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6673#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6674#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6531#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6532#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6675#L911-3 assume !(0 == ~E_1~0); 6889#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6459#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6460#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6878#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6539#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6540#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6690#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6417#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6418#L430-30 assume 1 == ~m_pc~0; 6444#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6445#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6516#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6517#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6906#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6912#L449-30 assume !(1 == ~t1_pc~0); 6448#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 6136#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6137#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6510#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6221#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6222#L468-30 assume 1 == ~t2_pc~0; 6321#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6322#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6413#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6414#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 6665#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6498#L487-30 assume !(1 == ~t3_pc~0); 6295#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 6296#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6727#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6728#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6930#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6582#L506-30 assume !(1 == ~t4_pc~0); 6583#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 6612#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6613#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6976#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6499#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6500#L525-30 assume 1 == ~t5_pc~0; 7017#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7018#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6846#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6847#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6503#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6273#L544-30 assume 1 == ~t6_pc~0; 6085#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6086#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6199#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6200#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7024#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7007#L563-30 assume 1 == ~t7_pc~0; 6240#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6241#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6262#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6599#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6600#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6997#L582-30 assume 1 == ~t8_pc~0; 6957#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6350#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6585#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7087#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7077#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6148#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6149#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6287#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6276#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6277#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6711#L984-3 assume !(1 == ~T5_E~0); 6712#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6331#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6332#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6870#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6184#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6185#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6687#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6688#L1024-3 assume !(1 == ~E_4~0); 6666#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6635#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6636#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6922#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6319#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6320#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6440#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6449#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 6353#L1334 assume !(0 == start_simulation_~tmp~3#1); 6354#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6367#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6081#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6082#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 6142#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7042#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6721#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 6722#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 6291#L1315-2 [2023-11-19 07:59:01,958 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:01,958 INFO L85 PathProgramCache]: Analyzing trace with hash 2129824886, now seen corresponding path program 1 times [2023-11-19 07:59:01,960 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:01,960 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1072770580] [2023-11-19 07:59:01,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:01,960 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:01,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:02,031 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:02,032 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:02,032 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1072770580] [2023-11-19 07:59:02,032 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1072770580] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:02,032 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:02,032 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:02,033 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [348419716] [2023-11-19 07:59:02,033 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:02,033 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:02,034 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:02,034 INFO L85 PathProgramCache]: Analyzing trace with hash -1973236160, now seen corresponding path program 1 times [2023-11-19 07:59:02,034 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:02,034 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2044969341] [2023-11-19 07:59:02,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:02,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:02,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:02,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:02,145 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:02,146 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2044969341] [2023-11-19 07:59:02,146 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2044969341] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:02,146 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:02,146 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:02,147 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [599407286] [2023-11-19 07:59:02,147 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:02,148 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:02,148 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:02,149 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:59:02,149 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:59:02,149 INFO L87 Difference]: Start difference. First operand 1007 states and 1497 transitions. cyclomatic complexity: 491 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:02,182 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:02,182 INFO L93 Difference]: Finished difference Result 1007 states and 1496 transitions. [2023-11-19 07:59:02,183 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1496 transitions. [2023-11-19 07:59:02,194 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-19 07:59:02,204 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1007 states and 1496 transitions. [2023-11-19 07:59:02,204 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1007 [2023-11-19 07:59:02,205 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1007 [2023-11-19 07:59:02,206 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1007 states and 1496 transitions. [2023-11-19 07:59:02,208 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:02,208 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1496 transitions. [2023-11-19 07:59:02,211 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states and 1496 transitions. [2023-11-19 07:59:02,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1007. [2023-11-19 07:59:02,232 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.4856007944389276) internal successors, (1496), 1006 states have internal predecessors, (1496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:02,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1496 transitions. [2023-11-19 07:59:02,238 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1496 transitions. [2023-11-19 07:59:02,238 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:59:02,241 INFO L428 stractBuchiCegarLoop]: Abstraction has 1007 states and 1496 transitions. [2023-11-19 07:59:02,246 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-19 07:59:02,247 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1496 transitions. [2023-11-19 07:59:02,255 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-19 07:59:02,256 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:02,256 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:02,258 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:02,258 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:02,259 INFO L748 eck$LassoCheckResult]: Stem: 8350#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 8351#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 9064#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9065#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8664#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 8665#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8222#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8223#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8314#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9050#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8190#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8191#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8619#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8651#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8318#L866 assume !(0 == ~M_E~0); 8319#L866-2 assume !(0 == ~T1_E~0); 8849#L871-1 assume !(0 == ~T2_E~0); 8850#L876-1 assume !(0 == ~T3_E~0); 9090#L881-1 assume !(0 == ~T4_E~0); 8863#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8608#L891-1 assume !(0 == ~T6_E~0); 8609#L896-1 assume !(0 == ~T7_E~0); 8857#L901-1 assume !(0 == ~T8_E~0); 8878#L906-1 assume !(0 == ~E_M~0); 8879#L911-1 assume !(0 == ~E_1~0); 8661#L916-1 assume !(0 == ~E_2~0); 8662#L921-1 assume !(0 == ~E_3~0); 8971#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 9061#L931-1 assume !(0 == ~E_5~0); 9093#L936-1 assume !(0 == ~E_6~0); 9097#L941-1 assume !(0 == ~E_7~0); 8666#L946-1 assume !(0 == ~E_8~0); 8667#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9078#L430 assume !(1 == ~m_pc~0); 8508#L430-2 is_master_triggered_~__retres1~0#1 := 0; 8137#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8138#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8783#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8784#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8952#L449 assume 1 == ~t1_pc~0; 8953#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8325#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8164#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8165#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 8893#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8723#L468 assume !(1 == ~t2_pc~0); 8125#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8124#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8518#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8513#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 8139#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8140#L487 assume 1 == ~t3_pc~0; 9088#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8228#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8121#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8122#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 8586#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8587#L506 assume !(1 == ~t4_pc~0); 8718#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8768#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8214#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8215#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 8712#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8525#L525 assume 1 == ~t5_pc~0; 8459#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8178#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9009#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9010#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 8382#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8383#L544 assume !(1 == ~t6_pc~0); 8526#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8527#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8498#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8159#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 8160#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9042#L563 assume 1 == ~t7_pc~0; 8916#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8182#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8183#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8610#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 8326#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8327#L582 assume 1 == ~t8_pc~0; 8246#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8247#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8958#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8574#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 8463#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8464#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 8956#L964-2 assume !(1 == ~T1_E~0); 8384#L969-1 assume !(1 == ~T2_E~0); 8385#L974-1 assume !(1 == ~T3_E~0); 8989#L979-1 assume !(1 == ~T4_E~0); 8990#L984-1 assume !(1 == ~T5_E~0); 8532#L989-1 assume !(1 == ~T6_E~0); 8533#L994-1 assume !(1 == ~T7_E~0); 8415#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8416#L1004-1 assume !(1 == ~E_M~0); 8161#L1009-1 assume !(1 == ~E_1~0); 8162#L1014-1 assume !(1 == ~E_2~0); 8404#L1019-1 assume !(1 == ~E_3~0); 8944#L1024-1 assume !(1 == ~E_4~0); 8347#L1029-1 assume !(1 == ~E_5~0); 8348#L1034-1 assume !(1 == ~E_6~0); 8431#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 9074#L1044-1 assume !(1 == ~E_8~0); 8630#L1049-1 assume { :end_inline_reset_delta_events } true; 8312#L1315-2 [2023-11-19 07:59:02,260 INFO L750 eck$LassoCheckResult]: Loop: 8312#L1315-2 assume !false; 8313#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8726#L841-1 assume !false; 8980#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8377#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8378#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8559#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8134#L724 assume !(0 != eval_~tmp~0#1); 8136#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8720#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8143#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8144#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8436#L871-3 assume !(0 == ~T2_E~0); 8437#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8453#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8454#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8694#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8695#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8552#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8553#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8696#L911-3 assume !(0 == ~E_1~0); 8910#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8480#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8481#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8899#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8560#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8561#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8711#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8438#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8439#L430-30 assume 1 == ~m_pc~0; 8465#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8466#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8537#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8538#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8927#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8933#L449-30 assume 1 == ~t1_pc~0; 8468#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8157#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8158#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8531#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8242#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8243#L468-30 assume 1 == ~t2_pc~0; 8342#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8343#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8434#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8435#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 8686#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8519#L487-30 assume 1 == ~t3_pc~0; 8497#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8317#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8748#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8749#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8951#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8603#L506-30 assume !(1 == ~t4_pc~0); 8604#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 8633#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8634#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8997#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8520#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8521#L525-30 assume !(1 == ~t5_pc~0); 9040#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 9039#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8867#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8868#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8524#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8294#L544-30 assume 1 == ~t6_pc~0; 8106#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8107#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8220#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8221#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9045#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9028#L563-30 assume 1 == ~t7_pc~0; 8261#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8262#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8283#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8620#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8621#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9018#L582-30 assume 1 == ~t8_pc~0; 8978#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8371#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8606#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9108#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9098#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8169#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8170#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8308#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8297#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8298#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8732#L984-3 assume !(1 == ~T5_E~0); 8733#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8352#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8353#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8891#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8205#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8206#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8708#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8709#L1024-3 assume !(1 == ~E_4~0); 8687#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8656#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8657#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8943#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8340#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8341#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8461#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8470#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 8374#L1334 assume !(0 == start_simulation_~tmp~3#1); 8375#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8388#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8102#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8103#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 8163#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9063#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8742#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 8743#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 8312#L1315-2 [2023-11-19 07:59:02,262 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:02,262 INFO L85 PathProgramCache]: Analyzing trace with hash -258739144, now seen corresponding path program 1 times [2023-11-19 07:59:02,263 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:02,263 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1822954051] [2023-11-19 07:59:02,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:02,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:02,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:02,328 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:02,329 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:02,329 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1822954051] [2023-11-19 07:59:02,329 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1822954051] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:02,329 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:02,330 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:02,330 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [952597480] [2023-11-19 07:59:02,330 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:02,331 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:02,331 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:02,331 INFO L85 PathProgramCache]: Analyzing trace with hash 13135423, now seen corresponding path program 2 times [2023-11-19 07:59:02,332 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:02,332 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1533870965] [2023-11-19 07:59:02,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:02,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:02,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:02,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:02,401 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:02,401 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1533870965] [2023-11-19 07:59:02,401 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1533870965] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:02,401 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:02,401 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:02,402 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1435720197] [2023-11-19 07:59:02,402 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:02,402 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:02,402 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:02,403 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:59:02,403 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:59:02,403 INFO L87 Difference]: Start difference. First operand 1007 states and 1496 transitions. cyclomatic complexity: 490 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:02,429 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:02,430 INFO L93 Difference]: Finished difference Result 1007 states and 1495 transitions. [2023-11-19 07:59:02,430 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1495 transitions. [2023-11-19 07:59:02,438 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-19 07:59:02,446 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1007 states and 1495 transitions. [2023-11-19 07:59:02,447 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1007 [2023-11-19 07:59:02,448 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1007 [2023-11-19 07:59:02,448 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1007 states and 1495 transitions. [2023-11-19 07:59:02,450 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:02,450 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1495 transitions. [2023-11-19 07:59:02,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states and 1495 transitions. [2023-11-19 07:59:02,467 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1007. [2023-11-19 07:59:02,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.4846077457795432) internal successors, (1495), 1006 states have internal predecessors, (1495), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:02,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1495 transitions. [2023-11-19 07:59:02,474 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1495 transitions. [2023-11-19 07:59:02,474 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:59:02,477 INFO L428 stractBuchiCegarLoop]: Abstraction has 1007 states and 1495 transitions. [2023-11-19 07:59:02,477 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-19 07:59:02,477 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1495 transitions. [2023-11-19 07:59:02,483 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-19 07:59:02,483 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:02,483 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:02,485 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:02,485 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:02,486 INFO L748 eck$LassoCheckResult]: Stem: 10371#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 10372#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 11085#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11086#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10685#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 10686#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10243#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10244#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10335#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11071#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10211#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10212#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10640#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10672#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10339#L866 assume !(0 == ~M_E~0); 10340#L866-2 assume !(0 == ~T1_E~0); 10870#L871-1 assume !(0 == ~T2_E~0); 10871#L876-1 assume !(0 == ~T3_E~0); 11111#L881-1 assume !(0 == ~T4_E~0); 10884#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10629#L891-1 assume !(0 == ~T6_E~0); 10630#L896-1 assume !(0 == ~T7_E~0); 10878#L901-1 assume !(0 == ~T8_E~0); 10899#L906-1 assume !(0 == ~E_M~0); 10900#L911-1 assume !(0 == ~E_1~0); 10682#L916-1 assume !(0 == ~E_2~0); 10683#L921-1 assume !(0 == ~E_3~0); 10992#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 11082#L931-1 assume !(0 == ~E_5~0); 11114#L936-1 assume !(0 == ~E_6~0); 11118#L941-1 assume !(0 == ~E_7~0); 10687#L946-1 assume !(0 == ~E_8~0); 10688#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11099#L430 assume !(1 == ~m_pc~0); 10529#L430-2 is_master_triggered_~__retres1~0#1 := 0; 10158#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10159#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10804#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10805#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10973#L449 assume 1 == ~t1_pc~0; 10974#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10346#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10185#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10186#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 10914#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10744#L468 assume !(1 == ~t2_pc~0); 10146#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10145#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10539#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10534#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 10160#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10161#L487 assume 1 == ~t3_pc~0; 11109#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10249#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10142#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10143#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 10607#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10608#L506 assume !(1 == ~t4_pc~0); 10739#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10789#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10235#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10236#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 10733#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10546#L525 assume 1 == ~t5_pc~0; 10480#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10199#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11030#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11031#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 10403#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10404#L544 assume !(1 == ~t6_pc~0); 10547#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10548#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10519#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10180#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 10181#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11063#L563 assume 1 == ~t7_pc~0; 10937#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10203#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10204#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10631#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 10347#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10348#L582 assume 1 == ~t8_pc~0; 10267#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10268#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10979#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10595#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 10484#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10485#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 10977#L964-2 assume !(1 == ~T1_E~0); 10405#L969-1 assume !(1 == ~T2_E~0); 10406#L974-1 assume !(1 == ~T3_E~0); 11010#L979-1 assume !(1 == ~T4_E~0); 11011#L984-1 assume !(1 == ~T5_E~0); 10553#L989-1 assume !(1 == ~T6_E~0); 10554#L994-1 assume !(1 == ~T7_E~0); 10436#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10437#L1004-1 assume !(1 == ~E_M~0); 10182#L1009-1 assume !(1 == ~E_1~0); 10183#L1014-1 assume !(1 == ~E_2~0); 10425#L1019-1 assume !(1 == ~E_3~0); 10965#L1024-1 assume !(1 == ~E_4~0); 10368#L1029-1 assume !(1 == ~E_5~0); 10369#L1034-1 assume !(1 == ~E_6~0); 10452#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 11095#L1044-1 assume !(1 == ~E_8~0); 10651#L1049-1 assume { :end_inline_reset_delta_events } true; 10333#L1315-2 [2023-11-19 07:59:02,486 INFO L750 eck$LassoCheckResult]: Loop: 10333#L1315-2 assume !false; 10334#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10747#L841-1 assume !false; 11001#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10398#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10399#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10580#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10155#L724 assume !(0 != eval_~tmp~0#1); 10157#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10741#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10164#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10165#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10457#L871-3 assume !(0 == ~T2_E~0); 10458#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10474#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10475#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10715#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10716#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10573#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10574#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10717#L911-3 assume !(0 == ~E_1~0); 10931#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10501#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10502#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10920#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10581#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10582#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10732#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10459#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10460#L430-30 assume 1 == ~m_pc~0; 10486#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10487#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10558#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10559#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10948#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10954#L449-30 assume 1 == ~t1_pc~0; 10489#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10178#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10179#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10552#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10263#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10264#L468-30 assume 1 == ~t2_pc~0; 10363#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10364#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10455#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10456#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 10707#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10540#L487-30 assume !(1 == ~t3_pc~0); 10337#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 10338#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10769#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10770#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10972#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10624#L506-30 assume !(1 == ~t4_pc~0); 10625#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 10654#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10655#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11018#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10541#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10542#L525-30 assume 1 == ~t5_pc~0; 11059#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11060#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10888#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10889#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10545#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10315#L544-30 assume !(1 == ~t6_pc~0); 10129#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 10128#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10241#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10242#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11066#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11049#L563-30 assume 1 == ~t7_pc~0; 10282#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10283#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10304#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10641#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10642#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11039#L582-30 assume 1 == ~t8_pc~0; 10999#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10392#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10627#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11129#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11119#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10190#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10191#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10329#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10318#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10319#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10753#L984-3 assume !(1 == ~T5_E~0); 10754#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10373#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10374#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10912#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10226#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10227#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10729#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10730#L1024-3 assume !(1 == ~E_4~0); 10708#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10677#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10678#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10964#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10361#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10362#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10482#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10491#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 10395#L1334 assume !(0 == start_simulation_~tmp~3#1); 10396#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10409#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10123#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10124#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 10184#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11084#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10763#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 10764#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 10333#L1315-2 [2023-11-19 07:59:02,487 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:02,488 INFO L85 PathProgramCache]: Analyzing trace with hash -1859810250, now seen corresponding path program 1 times [2023-11-19 07:59:02,488 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:02,488 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1955496721] [2023-11-19 07:59:02,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:02,488 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:02,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:02,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:02,536 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:02,536 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1955496721] [2023-11-19 07:59:02,536 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1955496721] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:02,536 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:02,537 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:02,537 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1704788845] [2023-11-19 07:59:02,537 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:02,537 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:02,538 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:02,538 INFO L85 PathProgramCache]: Analyzing trace with hash 431994368, now seen corresponding path program 1 times [2023-11-19 07:59:02,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:02,543 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1087730563] [2023-11-19 07:59:02,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:02,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:02,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:02,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:02,615 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:02,615 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1087730563] [2023-11-19 07:59:02,615 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1087730563] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:02,615 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:02,615 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:02,616 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1059651755] [2023-11-19 07:59:02,616 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:02,617 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:02,617 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:02,617 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:59:02,618 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:59:02,618 INFO L87 Difference]: Start difference. First operand 1007 states and 1495 transitions. cyclomatic complexity: 489 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:02,674 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:02,674 INFO L93 Difference]: Finished difference Result 1007 states and 1494 transitions. [2023-11-19 07:59:02,675 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1494 transitions. [2023-11-19 07:59:02,685 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-19 07:59:02,694 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1007 states and 1494 transitions. [2023-11-19 07:59:02,694 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1007 [2023-11-19 07:59:02,695 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1007 [2023-11-19 07:59:02,695 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1007 states and 1494 transitions. [2023-11-19 07:59:02,697 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:02,697 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1494 transitions. [2023-11-19 07:59:02,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states and 1494 transitions. [2023-11-19 07:59:02,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1007. [2023-11-19 07:59:02,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.483614697120159) internal successors, (1494), 1006 states have internal predecessors, (1494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:02,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1494 transitions. [2023-11-19 07:59:02,721 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1494 transitions. [2023-11-19 07:59:02,723 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:59:02,725 INFO L428 stractBuchiCegarLoop]: Abstraction has 1007 states and 1494 transitions. [2023-11-19 07:59:02,726 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-19 07:59:02,726 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1494 transitions. [2023-11-19 07:59:02,732 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-19 07:59:02,732 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:02,733 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:02,734 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:02,735 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:02,735 INFO L748 eck$LassoCheckResult]: Stem: 12392#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 12393#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 13106#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13107#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12706#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 12707#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12264#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12265#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12356#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13092#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12232#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12233#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12661#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12693#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12360#L866 assume !(0 == ~M_E~0); 12361#L866-2 assume !(0 == ~T1_E~0); 12891#L871-1 assume !(0 == ~T2_E~0); 12892#L876-1 assume !(0 == ~T3_E~0); 13132#L881-1 assume !(0 == ~T4_E~0); 12905#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12650#L891-1 assume !(0 == ~T6_E~0); 12651#L896-1 assume !(0 == ~T7_E~0); 12899#L901-1 assume !(0 == ~T8_E~0); 12920#L906-1 assume !(0 == ~E_M~0); 12921#L911-1 assume !(0 == ~E_1~0); 12703#L916-1 assume !(0 == ~E_2~0); 12704#L921-1 assume !(0 == ~E_3~0); 13013#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 13103#L931-1 assume !(0 == ~E_5~0); 13135#L936-1 assume !(0 == ~E_6~0); 13139#L941-1 assume !(0 == ~E_7~0); 12708#L946-1 assume !(0 == ~E_8~0); 12709#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13120#L430 assume !(1 == ~m_pc~0); 12550#L430-2 is_master_triggered_~__retres1~0#1 := 0; 12179#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12180#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12825#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12826#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12994#L449 assume 1 == ~t1_pc~0; 12995#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12367#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12206#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12207#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 12935#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12765#L468 assume !(1 == ~t2_pc~0); 12167#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12166#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12560#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12555#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 12181#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12182#L487 assume 1 == ~t3_pc~0; 13130#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12270#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12163#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12164#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 12628#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12629#L506 assume !(1 == ~t4_pc~0); 12760#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12810#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12256#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12257#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 12754#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12567#L525 assume 1 == ~t5_pc~0; 12501#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12220#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13051#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13052#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 12424#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12425#L544 assume !(1 == ~t6_pc~0); 12568#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12569#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12540#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12201#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 12202#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13084#L563 assume 1 == ~t7_pc~0; 12958#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12224#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12225#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12652#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 12368#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12369#L582 assume 1 == ~t8_pc~0; 12288#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12289#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13000#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12616#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 12505#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12506#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 12998#L964-2 assume !(1 == ~T1_E~0); 12426#L969-1 assume !(1 == ~T2_E~0); 12427#L974-1 assume !(1 == ~T3_E~0); 13031#L979-1 assume !(1 == ~T4_E~0); 13032#L984-1 assume !(1 == ~T5_E~0); 12574#L989-1 assume !(1 == ~T6_E~0); 12575#L994-1 assume !(1 == ~T7_E~0); 12457#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12458#L1004-1 assume !(1 == ~E_M~0); 12203#L1009-1 assume !(1 == ~E_1~0); 12204#L1014-1 assume !(1 == ~E_2~0); 12446#L1019-1 assume !(1 == ~E_3~0); 12986#L1024-1 assume !(1 == ~E_4~0); 12389#L1029-1 assume !(1 == ~E_5~0); 12390#L1034-1 assume !(1 == ~E_6~0); 12473#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 13116#L1044-1 assume !(1 == ~E_8~0); 12672#L1049-1 assume { :end_inline_reset_delta_events } true; 12354#L1315-2 [2023-11-19 07:59:02,736 INFO L750 eck$LassoCheckResult]: Loop: 12354#L1315-2 assume !false; 12355#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12768#L841-1 assume !false; 13022#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12419#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12420#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12601#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12176#L724 assume !(0 != eval_~tmp~0#1); 12178#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12762#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12185#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12186#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12478#L871-3 assume !(0 == ~T2_E~0); 12479#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12495#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12496#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12736#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12737#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12594#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12595#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12738#L911-3 assume !(0 == ~E_1~0); 12952#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12522#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12523#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12941#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12602#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12603#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12753#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12480#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12481#L430-30 assume 1 == ~m_pc~0; 12507#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12508#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12579#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12580#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12969#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12975#L449-30 assume 1 == ~t1_pc~0; 12510#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12199#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12200#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12573#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12284#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12285#L468-30 assume 1 == ~t2_pc~0; 12384#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12385#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12476#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12477#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 12728#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12561#L487-30 assume !(1 == ~t3_pc~0); 12358#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 12359#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12790#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12791#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12993#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12645#L506-30 assume !(1 == ~t4_pc~0); 12646#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 12675#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12676#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13039#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12562#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12563#L525-30 assume 1 == ~t5_pc~0; 13080#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13081#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12909#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12910#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12566#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12336#L544-30 assume 1 == ~t6_pc~0; 12148#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12149#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12262#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12263#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13087#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13070#L563-30 assume !(1 == ~t7_pc~0); 12305#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 12304#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12325#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12662#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12663#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13060#L582-30 assume 1 == ~t8_pc~0; 13020#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12413#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12648#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13150#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13140#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12211#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12212#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12350#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12339#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12340#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12774#L984-3 assume !(1 == ~T5_E~0); 12775#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12394#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12395#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12933#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12247#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12248#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12750#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12751#L1024-3 assume !(1 == ~E_4~0); 12729#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12698#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12699#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12985#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12382#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12383#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12503#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12512#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 12416#L1334 assume !(0 == start_simulation_~tmp~3#1); 12417#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12430#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12144#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12145#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 12205#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13105#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12784#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 12785#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 12354#L1315-2 [2023-11-19 07:59:02,736 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:02,736 INFO L85 PathProgramCache]: Analyzing trace with hash -803079048, now seen corresponding path program 1 times [2023-11-19 07:59:02,737 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:02,737 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1804654191] [2023-11-19 07:59:02,737 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:02,737 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:02,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:02,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:02,780 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:02,781 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1804654191] [2023-11-19 07:59:02,781 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1804654191] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:02,782 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:02,782 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:02,782 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1511717163] [2023-11-19 07:59:02,782 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:02,783 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:02,783 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:02,784 INFO L85 PathProgramCache]: Analyzing trace with hash 862321344, now seen corresponding path program 1 times [2023-11-19 07:59:02,784 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:02,784 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2023429196] [2023-11-19 07:59:02,784 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:02,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:02,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:02,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:02,856 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:02,856 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2023429196] [2023-11-19 07:59:02,856 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2023429196] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:02,856 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:02,856 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:02,857 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1727422132] [2023-11-19 07:59:02,857 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:02,857 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:02,858 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:02,858 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:59:02,858 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:59:02,858 INFO L87 Difference]: Start difference. First operand 1007 states and 1494 transitions. cyclomatic complexity: 488 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:02,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:02,886 INFO L93 Difference]: Finished difference Result 1007 states and 1493 transitions. [2023-11-19 07:59:02,887 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1493 transitions. [2023-11-19 07:59:02,896 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-19 07:59:02,905 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1007 states and 1493 transitions. [2023-11-19 07:59:02,906 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1007 [2023-11-19 07:59:02,907 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1007 [2023-11-19 07:59:02,907 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1007 states and 1493 transitions. [2023-11-19 07:59:02,909 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:02,910 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1493 transitions. [2023-11-19 07:59:02,912 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states and 1493 transitions. [2023-11-19 07:59:02,927 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1007. [2023-11-19 07:59:02,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.4826216484607746) internal successors, (1493), 1006 states have internal predecessors, (1493), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:02,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1493 transitions. [2023-11-19 07:59:02,935 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1493 transitions. [2023-11-19 07:59:02,935 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:59:02,937 INFO L428 stractBuchiCegarLoop]: Abstraction has 1007 states and 1493 transitions. [2023-11-19 07:59:02,938 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-19 07:59:02,938 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1493 transitions. [2023-11-19 07:59:02,944 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-19 07:59:02,944 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:02,945 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:02,946 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:02,947 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:02,947 INFO L748 eck$LassoCheckResult]: Stem: 14413#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 14414#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 15127#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15128#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14727#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 14728#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14285#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14286#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14377#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15113#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14253#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14254#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14682#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14714#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14381#L866 assume !(0 == ~M_E~0); 14382#L866-2 assume !(0 == ~T1_E~0); 14912#L871-1 assume !(0 == ~T2_E~0); 14913#L876-1 assume !(0 == ~T3_E~0); 15153#L881-1 assume !(0 == ~T4_E~0); 14926#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14671#L891-1 assume !(0 == ~T6_E~0); 14672#L896-1 assume !(0 == ~T7_E~0); 14920#L901-1 assume !(0 == ~T8_E~0); 14941#L906-1 assume !(0 == ~E_M~0); 14942#L911-1 assume !(0 == ~E_1~0); 14724#L916-1 assume !(0 == ~E_2~0); 14725#L921-1 assume !(0 == ~E_3~0); 15034#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 15124#L931-1 assume !(0 == ~E_5~0); 15156#L936-1 assume !(0 == ~E_6~0); 15160#L941-1 assume !(0 == ~E_7~0); 14729#L946-1 assume !(0 == ~E_8~0); 14730#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15141#L430 assume !(1 == ~m_pc~0); 14571#L430-2 is_master_triggered_~__retres1~0#1 := 0; 14200#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14201#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14846#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14847#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15015#L449 assume 1 == ~t1_pc~0; 15016#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14388#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14227#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14228#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 14956#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14786#L468 assume !(1 == ~t2_pc~0); 14188#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14187#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14581#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14576#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 14202#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14203#L487 assume 1 == ~t3_pc~0; 15151#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14291#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14184#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14185#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 14649#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14650#L506 assume !(1 == ~t4_pc~0); 14781#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14831#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14277#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14278#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 14775#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14588#L525 assume 1 == ~t5_pc~0; 14522#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14241#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15072#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15073#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 14445#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14446#L544 assume !(1 == ~t6_pc~0); 14589#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14590#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14561#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14222#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 14223#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15105#L563 assume 1 == ~t7_pc~0; 14979#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14245#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14246#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14673#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 14389#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14390#L582 assume 1 == ~t8_pc~0; 14309#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14310#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15021#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14637#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 14526#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14527#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 15019#L964-2 assume !(1 == ~T1_E~0); 14447#L969-1 assume !(1 == ~T2_E~0); 14448#L974-1 assume !(1 == ~T3_E~0); 15052#L979-1 assume !(1 == ~T4_E~0); 15053#L984-1 assume !(1 == ~T5_E~0); 14595#L989-1 assume !(1 == ~T6_E~0); 14596#L994-1 assume !(1 == ~T7_E~0); 14478#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14479#L1004-1 assume !(1 == ~E_M~0); 14224#L1009-1 assume !(1 == ~E_1~0); 14225#L1014-1 assume !(1 == ~E_2~0); 14467#L1019-1 assume !(1 == ~E_3~0); 15007#L1024-1 assume !(1 == ~E_4~0); 14410#L1029-1 assume !(1 == ~E_5~0); 14411#L1034-1 assume !(1 == ~E_6~0); 14494#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 15137#L1044-1 assume !(1 == ~E_8~0); 14693#L1049-1 assume { :end_inline_reset_delta_events } true; 14375#L1315-2 [2023-11-19 07:59:02,948 INFO L750 eck$LassoCheckResult]: Loop: 14375#L1315-2 assume !false; 14376#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14789#L841-1 assume !false; 15043#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14440#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14441#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14622#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14197#L724 assume !(0 != eval_~tmp~0#1); 14199#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14783#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14206#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14207#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14499#L871-3 assume !(0 == ~T2_E~0); 14500#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14516#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14517#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14757#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14758#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14615#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14616#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14759#L911-3 assume !(0 == ~E_1~0); 14973#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14543#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14544#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14962#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14623#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14624#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14774#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14501#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14502#L430-30 assume 1 == ~m_pc~0; 14528#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14529#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14600#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14601#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14990#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14996#L449-30 assume 1 == ~t1_pc~0; 14531#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14220#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14221#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14594#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14305#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14306#L468-30 assume 1 == ~t2_pc~0; 14405#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14406#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14497#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14498#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 14749#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14582#L487-30 assume 1 == ~t3_pc~0; 14560#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14380#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14811#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14812#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15014#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14666#L506-30 assume !(1 == ~t4_pc~0); 14667#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 14696#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14697#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15060#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14583#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14584#L525-30 assume 1 == ~t5_pc~0; 15101#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15102#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14930#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14931#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14587#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14357#L544-30 assume 1 == ~t6_pc~0; 14169#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14170#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14283#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14284#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15108#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15091#L563-30 assume 1 == ~t7_pc~0; 14324#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14325#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14346#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14683#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14684#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15081#L582-30 assume 1 == ~t8_pc~0; 15041#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14434#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14669#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15171#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15161#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14232#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14233#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14371#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14360#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14361#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14795#L984-3 assume !(1 == ~T5_E~0); 14796#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14415#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14416#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14954#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14268#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14269#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14771#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14772#L1024-3 assume !(1 == ~E_4~0); 14750#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14719#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14720#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15006#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14403#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14404#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14524#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14533#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 14437#L1334 assume !(0 == start_simulation_~tmp~3#1); 14438#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14451#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14165#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14166#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 14226#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15126#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14805#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 14806#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 14375#L1315-2 [2023-11-19 07:59:02,949 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:02,949 INFO L85 PathProgramCache]: Analyzing trace with hash 2140503030, now seen corresponding path program 1 times [2023-11-19 07:59:02,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:02,949 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1709337156] [2023-11-19 07:59:02,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:02,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:02,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:03,004 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:03,005 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:03,006 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1709337156] [2023-11-19 07:59:03,006 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1709337156] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:03,007 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:03,007 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:03,012 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [840140749] [2023-11-19 07:59:03,012 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:03,013 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:03,013 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:03,013 INFO L85 PathProgramCache]: Analyzing trace with hash 1121264062, now seen corresponding path program 1 times [2023-11-19 07:59:03,014 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:03,016 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1911714877] [2023-11-19 07:59:03,016 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:03,016 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:03,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:03,096 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:03,096 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:03,096 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1911714877] [2023-11-19 07:59:03,096 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1911714877] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:03,100 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:03,100 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:03,100 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [905662003] [2023-11-19 07:59:03,100 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:03,101 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:03,101 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:03,101 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:59:03,102 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:59:03,102 INFO L87 Difference]: Start difference. First operand 1007 states and 1493 transitions. cyclomatic complexity: 487 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:03,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:03,128 INFO L93 Difference]: Finished difference Result 1007 states and 1492 transitions. [2023-11-19 07:59:03,128 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1492 transitions. [2023-11-19 07:59:03,137 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-19 07:59:03,146 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1007 states and 1492 transitions. [2023-11-19 07:59:03,147 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1007 [2023-11-19 07:59:03,148 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1007 [2023-11-19 07:59:03,148 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1007 states and 1492 transitions. [2023-11-19 07:59:03,150 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:03,150 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1492 transitions. [2023-11-19 07:59:03,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states and 1492 transitions. [2023-11-19 07:59:03,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1007. [2023-11-19 07:59:03,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.4816285998013903) internal successors, (1492), 1006 states have internal predecessors, (1492), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:03,176 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1492 transitions. [2023-11-19 07:59:03,176 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1492 transitions. [2023-11-19 07:59:03,176 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:59:03,178 INFO L428 stractBuchiCegarLoop]: Abstraction has 1007 states and 1492 transitions. [2023-11-19 07:59:03,178 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-19 07:59:03,179 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1492 transitions. [2023-11-19 07:59:03,185 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-19 07:59:03,185 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:03,185 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:03,187 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:03,188 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:03,188 INFO L748 eck$LassoCheckResult]: Stem: 16434#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 16435#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 17148#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17149#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16748#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 16749#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16306#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16307#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16398#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17134#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16274#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16275#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16703#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 16735#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16402#L866 assume !(0 == ~M_E~0); 16403#L866-2 assume !(0 == ~T1_E~0); 16933#L871-1 assume !(0 == ~T2_E~0); 16934#L876-1 assume !(0 == ~T3_E~0); 17174#L881-1 assume !(0 == ~T4_E~0); 16947#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16692#L891-1 assume !(0 == ~T6_E~0); 16693#L896-1 assume !(0 == ~T7_E~0); 16941#L901-1 assume !(0 == ~T8_E~0); 16962#L906-1 assume !(0 == ~E_M~0); 16963#L911-1 assume !(0 == ~E_1~0); 16745#L916-1 assume !(0 == ~E_2~0); 16746#L921-1 assume !(0 == ~E_3~0); 17055#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 17145#L931-1 assume !(0 == ~E_5~0); 17177#L936-1 assume !(0 == ~E_6~0); 17181#L941-1 assume !(0 == ~E_7~0); 16750#L946-1 assume !(0 == ~E_8~0); 16751#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17162#L430 assume !(1 == ~m_pc~0); 16592#L430-2 is_master_triggered_~__retres1~0#1 := 0; 16221#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16222#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16867#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16868#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17036#L449 assume 1 == ~t1_pc~0; 17037#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16409#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16248#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16249#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 16977#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16807#L468 assume !(1 == ~t2_pc~0); 16209#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16208#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16602#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16597#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 16223#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16224#L487 assume 1 == ~t3_pc~0; 17172#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16312#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16205#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16206#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 16670#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16671#L506 assume !(1 == ~t4_pc~0); 16802#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16852#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16298#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16299#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 16796#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16609#L525 assume 1 == ~t5_pc~0; 16543#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16262#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17093#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17094#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 16466#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16467#L544 assume !(1 == ~t6_pc~0); 16610#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16611#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16582#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16243#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 16244#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17126#L563 assume 1 == ~t7_pc~0; 17000#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16266#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16267#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16694#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 16410#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16411#L582 assume 1 == ~t8_pc~0; 16330#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16331#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17042#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16658#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 16547#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16548#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 17040#L964-2 assume !(1 == ~T1_E~0); 16468#L969-1 assume !(1 == ~T2_E~0); 16469#L974-1 assume !(1 == ~T3_E~0); 17073#L979-1 assume !(1 == ~T4_E~0); 17074#L984-1 assume !(1 == ~T5_E~0); 16616#L989-1 assume !(1 == ~T6_E~0); 16617#L994-1 assume !(1 == ~T7_E~0); 16499#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16500#L1004-1 assume !(1 == ~E_M~0); 16245#L1009-1 assume !(1 == ~E_1~0); 16246#L1014-1 assume !(1 == ~E_2~0); 16488#L1019-1 assume !(1 == ~E_3~0); 17028#L1024-1 assume !(1 == ~E_4~0); 16431#L1029-1 assume !(1 == ~E_5~0); 16432#L1034-1 assume !(1 == ~E_6~0); 16515#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 17158#L1044-1 assume !(1 == ~E_8~0); 16714#L1049-1 assume { :end_inline_reset_delta_events } true; 16396#L1315-2 [2023-11-19 07:59:03,189 INFO L750 eck$LassoCheckResult]: Loop: 16396#L1315-2 assume !false; 16397#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16810#L841-1 assume !false; 17064#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16461#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16462#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16643#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16218#L724 assume !(0 != eval_~tmp~0#1); 16220#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16804#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16227#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16228#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16520#L871-3 assume !(0 == ~T2_E~0); 16521#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16537#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16538#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16778#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16779#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16636#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16637#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16780#L911-3 assume !(0 == ~E_1~0); 16994#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16564#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16565#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16983#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16644#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16645#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16795#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16522#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16523#L430-30 assume 1 == ~m_pc~0; 16549#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16550#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16621#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16622#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17011#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17017#L449-30 assume 1 == ~t1_pc~0; 16552#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16241#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16242#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16615#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16326#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16327#L468-30 assume 1 == ~t2_pc~0; 16426#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16427#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16518#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16519#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 16770#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16603#L487-30 assume !(1 == ~t3_pc~0); 16400#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 16401#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16832#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16833#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17035#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16687#L506-30 assume !(1 == ~t4_pc~0); 16688#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 16717#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16718#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17081#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16604#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16605#L525-30 assume 1 == ~t5_pc~0; 17122#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17123#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16951#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16952#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16608#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16378#L544-30 assume !(1 == ~t6_pc~0); 16192#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 16191#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16304#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16305#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17129#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17112#L563-30 assume 1 == ~t7_pc~0; 16345#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16346#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16367#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16704#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16705#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17102#L582-30 assume 1 == ~t8_pc~0; 17062#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16455#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16690#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17192#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17182#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16253#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16254#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16392#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16381#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16382#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16816#L984-3 assume !(1 == ~T5_E~0); 16817#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16436#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16437#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16975#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16289#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16290#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16792#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16793#L1024-3 assume !(1 == ~E_4~0); 16771#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16740#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16741#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17027#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16424#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16425#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16545#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16554#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 16458#L1334 assume !(0 == start_simulation_~tmp~3#1); 16459#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16472#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16186#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16187#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 16247#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17147#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16826#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 16827#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 16396#L1315-2 [2023-11-19 07:59:03,189 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:03,189 INFO L85 PathProgramCache]: Analyzing trace with hash -535489352, now seen corresponding path program 1 times [2023-11-19 07:59:03,190 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:03,190 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [567431870] [2023-11-19 07:59:03,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:03,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:03,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:03,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:03,301 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:03,302 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [567431870] [2023-11-19 07:59:03,302 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [567431870] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:03,302 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:03,302 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:03,302 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1929899617] [2023-11-19 07:59:03,302 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:03,303 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:03,303 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:03,304 INFO L85 PathProgramCache]: Analyzing trace with hash 431994368, now seen corresponding path program 2 times [2023-11-19 07:59:03,304 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:03,304 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [331067236] [2023-11-19 07:59:03,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:03,305 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:03,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:03,361 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:03,361 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:03,361 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [331067236] [2023-11-19 07:59:03,362 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [331067236] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:03,362 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:03,362 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:03,362 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [221717135] [2023-11-19 07:59:03,362 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:03,363 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:03,363 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:03,363 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:59:03,364 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:59:03,364 INFO L87 Difference]: Start difference. First operand 1007 states and 1492 transitions. cyclomatic complexity: 486 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:03,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:03,517 INFO L93 Difference]: Finished difference Result 1834 states and 2707 transitions. [2023-11-19 07:59:03,517 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1834 states and 2707 transitions. [2023-11-19 07:59:03,533 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1701 [2023-11-19 07:59:03,548 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1834 states to 1834 states and 2707 transitions. [2023-11-19 07:59:03,549 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1834 [2023-11-19 07:59:03,551 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1834 [2023-11-19 07:59:03,551 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1834 states and 2707 transitions. [2023-11-19 07:59:03,555 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:03,555 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1834 states and 2707 transitions. [2023-11-19 07:59:03,558 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1834 states and 2707 transitions. [2023-11-19 07:59:03,595 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1834 to 1834. [2023-11-19 07:59:03,600 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1834 states, 1834 states have (on average 1.4760087241003272) internal successors, (2707), 1833 states have internal predecessors, (2707), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:03,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1834 states to 1834 states and 2707 transitions. [2023-11-19 07:59:03,608 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1834 states and 2707 transitions. [2023-11-19 07:59:03,609 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:59:03,610 INFO L428 stractBuchiCegarLoop]: Abstraction has 1834 states and 2707 transitions. [2023-11-19 07:59:03,610 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-19 07:59:03,611 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1834 states and 2707 transitions. [2023-11-19 07:59:03,620 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1701 [2023-11-19 07:59:03,620 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:03,620 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:03,622 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:03,623 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:03,623 INFO L748 eck$LassoCheckResult]: Stem: 19286#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 19287#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 20088#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20089#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19617#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 19618#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19157#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19158#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19250#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20066#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19125#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19126#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19570#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 19604#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19254#L866 assume !(0 == ~M_E~0); 19255#L866-2 assume !(0 == ~T1_E~0); 19816#L871-1 assume !(0 == ~T2_E~0); 19817#L876-1 assume !(0 == ~T3_E~0); 20138#L881-1 assume !(0 == ~T4_E~0); 19830#L886-1 assume !(0 == ~T5_E~0); 19559#L891-1 assume !(0 == ~T6_E~0); 19560#L896-1 assume !(0 == ~T7_E~0); 19824#L901-1 assume !(0 == ~T8_E~0); 19845#L906-1 assume !(0 == ~E_M~0); 19846#L911-1 assume !(0 == ~E_1~0); 19614#L916-1 assume !(0 == ~E_2~0); 19615#L921-1 assume !(0 == ~E_3~0); 19955#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 20084#L931-1 assume !(0 == ~E_5~0); 20144#L936-1 assume !(0 == ~E_6~0); 20156#L941-1 assume !(0 == ~E_7~0); 19619#L946-1 assume !(0 == ~E_8~0); 19620#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20111#L430 assume !(1 == ~m_pc~0); 19455#L430-2 is_master_triggered_~__retres1~0#1 := 0; 19072#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19073#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19745#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19746#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19931#L449 assume 1 == ~t1_pc~0; 19932#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19261#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19099#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19100#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 19862#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19679#L468 assume !(1 == ~t2_pc~0); 19060#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19059#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19465#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19460#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 19074#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19075#L487 assume 1 == ~t3_pc~0; 20133#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19163#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19056#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19057#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 19537#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19538#L506 assume !(1 == ~t4_pc~0); 19673#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19729#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19149#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19150#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 19666#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19472#L525 assume 1 == ~t5_pc~0; 19403#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19113#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20006#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20007#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 19319#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19320#L544 assume !(1 == ~t6_pc~0); 19473#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19474#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19444#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19094#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 19095#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20054#L563 assume 1 == ~t7_pc~0; 19888#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19117#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19118#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19561#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 19262#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19263#L582 assume 1 == ~t8_pc~0; 19181#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19182#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19939#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19523#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 19407#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19408#L964 assume !(1 == ~M_E~0); 19935#L964-2 assume !(1 == ~T1_E~0); 19321#L969-1 assume !(1 == ~T2_E~0); 19322#L974-1 assume !(1 == ~T3_E~0); 19977#L979-1 assume !(1 == ~T4_E~0); 19978#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20176#L989-1 assume !(1 == ~T6_E~0); 20723#L994-1 assume !(1 == ~T7_E~0); 20722#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 20721#L1004-1 assume !(1 == ~E_M~0); 20720#L1009-1 assume !(1 == ~E_1~0); 20719#L1014-1 assume !(1 == ~E_2~0); 20718#L1019-1 assume !(1 == ~E_3~0); 20717#L1024-1 assume !(1 == ~E_4~0); 19283#L1029-1 assume !(1 == ~E_5~0); 19284#L1034-1 assume !(1 == ~E_6~0); 19371#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 20180#L1044-1 assume !(1 == ~E_8~0); 19581#L1049-1 assume { :end_inline_reset_delta_events } true; 19248#L1315-2 [2023-11-19 07:59:03,624 INFO L750 eck$LassoCheckResult]: Loop: 19248#L1315-2 assume !false; 19249#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19682#L841-1 assume !false; 20113#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20114#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19980#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19507#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19069#L724 assume !(0 != eval_~tmp~0#1); 19071#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19675#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19676#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20136#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19377#L871-3 assume !(0 == ~T2_E~0); 19378#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19397#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19398#L886-3 assume !(0 == ~T5_E~0); 19648#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19649#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19500#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19501#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19650#L911-3 assume !(0 == ~E_1~0); 19881#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19424#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19425#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19869#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19508#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19509#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19665#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19379#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19380#L430-30 assume 1 == ~m_pc~0; 19409#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19410#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19484#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19485#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19903#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19911#L449-30 assume 1 == ~t1_pc~0; 19412#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19092#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19093#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19478#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19177#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19178#L468-30 assume !(1 == ~t2_pc~0); 19280#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 19279#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19375#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19376#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 19640#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19466#L487-30 assume 1 == ~t3_pc~0; 19443#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19253#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19705#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19706#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19930#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19554#L506-30 assume !(1 == ~t4_pc~0); 19555#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 19584#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19585#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19991#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19467#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19468#L525-30 assume 1 == ~t5_pc~0; 20049#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20050#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19834#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19835#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19471#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19229#L544-30 assume 1 == ~t6_pc~0; 19041#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19042#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19155#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19156#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20059#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20033#L563-30 assume 1 == ~t7_pc~0; 19196#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19197#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19218#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19571#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19572#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20017#L582-30 assume 1 == ~t8_pc~0; 19962#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19308#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19557#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20179#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20158#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19104#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19105#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19244#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19232#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19233#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19689#L984-3 assume !(1 == ~T5_E~0); 19690#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19288#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19289#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19860#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19140#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19141#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19662#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19663#L1024-3 assume !(1 == ~E_4~0); 19641#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19609#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19610#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19922#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19276#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19277#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19405#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 20762#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 20761#L1334 assume !(0 == start_simulation_~tmp~3#1); 20027#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20758#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 20751#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 20750#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 20749#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20086#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20087#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 20065#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 19248#L1315-2 [2023-11-19 07:59:03,624 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:03,625 INFO L85 PathProgramCache]: Analyzing trace with hash -1799592066, now seen corresponding path program 1 times [2023-11-19 07:59:03,625 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:03,625 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1700846622] [2023-11-19 07:59:03,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:03,626 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:03,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:03,705 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:03,706 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:03,706 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1700846622] [2023-11-19 07:59:03,706 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1700846622] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:03,706 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:03,706 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:03,707 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [784830929] [2023-11-19 07:59:03,707 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:03,708 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:03,708 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:03,709 INFO L85 PathProgramCache]: Analyzing trace with hash -10674303, now seen corresponding path program 1 times [2023-11-19 07:59:03,709 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:03,709 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [659311669] [2023-11-19 07:59:03,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:03,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:03,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:03,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:03,766 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:03,766 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [659311669] [2023-11-19 07:59:03,767 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [659311669] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:03,767 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:03,767 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:03,767 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1550503855] [2023-11-19 07:59:03,767 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:03,768 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:03,768 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:03,768 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:59:03,768 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:59:03,768 INFO L87 Difference]: Start difference. First operand 1834 states and 2707 transitions. cyclomatic complexity: 875 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:03,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:03,978 INFO L93 Difference]: Finished difference Result 3342 states and 4920 transitions. [2023-11-19 07:59:03,978 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3342 states and 4920 transitions. [2023-11-19 07:59:04,025 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3189 [2023-11-19 07:59:04,052 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3342 states to 3342 states and 4920 transitions. [2023-11-19 07:59:04,053 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3342 [2023-11-19 07:59:04,056 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3342 [2023-11-19 07:59:04,057 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3342 states and 4920 transitions. [2023-11-19 07:59:04,062 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:04,063 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3342 states and 4920 transitions. [2023-11-19 07:59:04,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3342 states and 4920 transitions. [2023-11-19 07:59:04,127 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3342 to 3340. [2023-11-19 07:59:04,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3340 states, 3340 states have (on average 1.4724550898203592) internal successors, (4918), 3339 states have internal predecessors, (4918), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:04,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3340 states to 3340 states and 4918 transitions. [2023-11-19 07:59:04,148 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3340 states and 4918 transitions. [2023-11-19 07:59:04,149 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:59:04,149 INFO L428 stractBuchiCegarLoop]: Abstraction has 3340 states and 4918 transitions. [2023-11-19 07:59:04,150 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-19 07:59:04,150 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3340 states and 4918 transitions. [2023-11-19 07:59:04,166 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3189 [2023-11-19 07:59:04,166 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:04,166 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:04,168 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:04,168 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:04,169 INFO L748 eck$LassoCheckResult]: Stem: 24475#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 24476#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 25231#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25232#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24799#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 24800#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24345#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24346#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24439#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25214#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24312#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24313#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24753#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24786#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24443#L866 assume !(0 == ~M_E~0); 24444#L866-2 assume !(0 == ~T1_E~0); 24993#L871-1 assume !(0 == ~T2_E~0); 24994#L876-1 assume !(0 == ~T3_E~0); 25272#L881-1 assume !(0 == ~T4_E~0); 25008#L886-1 assume !(0 == ~T5_E~0); 24742#L891-1 assume !(0 == ~T6_E~0); 24743#L896-1 assume !(0 == ~T7_E~0); 25001#L901-1 assume !(0 == ~T8_E~0); 25024#L906-1 assume !(0 == ~E_M~0); 25025#L911-1 assume !(0 == ~E_1~0); 24796#L916-1 assume !(0 == ~E_2~0); 24797#L921-1 assume !(0 == ~E_3~0); 25125#L926-1 assume !(0 == ~E_4~0); 25228#L931-1 assume !(0 == ~E_5~0); 25280#L936-1 assume !(0 == ~E_6~0); 25286#L941-1 assume !(0 == ~E_7~0); 24801#L946-1 assume !(0 == ~E_8~0); 24802#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25252#L430 assume !(1 == ~m_pc~0); 24640#L430-2 is_master_triggered_~__retres1~0#1 := 0; 24258#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24259#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24925#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24926#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25101#L449 assume 1 == ~t1_pc~0; 25102#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24450#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24285#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24286#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 25039#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24863#L468 assume !(1 == ~t2_pc~0); 24246#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24245#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24650#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24645#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 24260#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24261#L487 assume 1 == ~t3_pc~0; 25269#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24351#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24242#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24243#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 24720#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24721#L506 assume !(1 == ~t4_pc~0); 24858#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24910#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24337#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24338#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 24850#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24657#L525 assume 1 == ~t5_pc~0; 24586#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24300#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25166#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25167#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 24507#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24508#L544 assume !(1 == ~t6_pc~0); 24658#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24659#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24629#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24280#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 24281#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25203#L563 assume 1 == ~t7_pc~0; 25064#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24304#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24305#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24744#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 24451#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24452#L582 assume 1 == ~t8_pc~0; 24369#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24370#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25108#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24707#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 24590#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24591#L964 assume !(1 == ~M_E~0); 25105#L964-2 assume !(1 == ~T1_E~0); 25488#L969-1 assume !(1 == ~T2_E~0); 25486#L974-1 assume !(1 == ~T3_E~0); 25143#L979-1 assume !(1 == ~T4_E~0); 25144#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25300#L989-1 assume !(1 == ~T6_E~0); 25439#L994-1 assume !(1 == ~T7_E~0); 25437#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25435#L1004-1 assume !(1 == ~E_M~0); 24282#L1009-1 assume !(1 == ~E_1~0); 24283#L1014-1 assume !(1 == ~E_2~0); 25405#L1019-1 assume !(1 == ~E_3~0); 25383#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 25381#L1029-1 assume !(1 == ~E_5~0); 25380#L1034-1 assume !(1 == ~E_6~0); 25360#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 25351#L1044-1 assume !(1 == ~E_8~0); 25343#L1049-1 assume { :end_inline_reset_delta_events } true; 25336#L1315-2 [2023-11-19 07:59:04,169 INFO L750 eck$LassoCheckResult]: Loop: 25336#L1315-2 assume !false; 25332#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25331#L841-1 assume !false; 25330#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25325#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25320#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25319#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25317#L724 assume !(0 != eval_~tmp~0#1); 25316#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25315#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25313#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25314#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25881#L871-3 assume !(0 == ~T2_E~0); 25878#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25876#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25874#L886-3 assume !(0 == ~T5_E~0); 25872#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25870#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25868#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25865#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25863#L911-3 assume !(0 == ~E_1~0); 25861#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25859#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25858#L926-3 assume !(0 == ~E_4~0); 25857#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25855#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25852#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25850#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25848#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25846#L430-30 assume 1 == ~m_pc~0; 25842#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25839#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25837#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25835#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25833#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25831#L449-30 assume !(1 == ~t1_pc~0); 25828#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 25825#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25823#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25821#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25819#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25817#L468-30 assume 1 == ~t2_pc~0; 25814#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25811#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25809#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25807#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 25805#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25803#L487-30 assume 1 == ~t3_pc~0; 25800#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25797#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25795#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25793#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25791#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25789#L506-30 assume !(1 == ~t4_pc~0); 25786#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 25783#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25781#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25780#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25779#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25778#L525-30 assume 1 == ~t5_pc~0; 25776#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25775#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25774#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25773#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25772#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25771#L544-30 assume !(1 == ~t6_pc~0); 25769#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 25768#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25767#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25766#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25765#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25764#L563-30 assume 1 == ~t7_pc~0; 25760#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25758#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25756#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25755#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25754#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25753#L582-30 assume !(1 == ~t8_pc~0); 25731#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 25704#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25701#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25699#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25697#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25696#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24291#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25662#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25661#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25659#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25641#L984-3 assume !(1 == ~T5_E~0); 25640#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 25637#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25635#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25634#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25609#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25597#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25593#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25582#L1024-3 assume !(1 == ~E_4~0); 25549#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25523#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25513#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25507#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25506#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25474#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25465#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25464#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 25460#L1334 assume !(0 == start_simulation_~tmp~3#1); 25185#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25430#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25397#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25379#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 25375#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25359#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25350#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 25342#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 25336#L1315-2 [2023-11-19 07:59:04,171 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:04,171 INFO L85 PathProgramCache]: Analyzing trace with hash -1616610622, now seen corresponding path program 1 times [2023-11-19 07:59:04,171 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:04,171 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1238692126] [2023-11-19 07:59:04,171 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:04,172 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:04,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:04,258 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:04,258 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:04,258 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1238692126] [2023-11-19 07:59:04,258 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1238692126] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:04,259 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:04,259 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:59:04,259 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [901613197] [2023-11-19 07:59:04,260 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:04,260 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:04,260 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:04,261 INFO L85 PathProgramCache]: Analyzing trace with hash 1868159045, now seen corresponding path program 1 times [2023-11-19 07:59:04,261 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:04,261 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [642821292] [2023-11-19 07:59:04,261 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:04,261 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:04,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:04,340 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:04,341 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:04,341 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [642821292] [2023-11-19 07:59:04,341 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [642821292] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:04,341 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:04,341 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:59:04,341 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1717954234] [2023-11-19 07:59:04,342 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:04,342 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:04,342 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:04,343 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 07:59:04,343 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 07:59:04,343 INFO L87 Difference]: Start difference. First operand 3340 states and 4918 transitions. cyclomatic complexity: 1582 Second operand has 5 states, 5 states have (on average 21.2) internal successors, (106), 5 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:04,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:04,795 INFO L93 Difference]: Finished difference Result 8807 states and 12787 transitions. [2023-11-19 07:59:04,796 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8807 states and 12787 transitions. [2023-11-19 07:59:04,859 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8484 [2023-11-19 07:59:04,927 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8807 states to 8807 states and 12787 transitions. [2023-11-19 07:59:04,927 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8807 [2023-11-19 07:59:04,937 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8807 [2023-11-19 07:59:04,937 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8807 states and 12787 transitions. [2023-11-19 07:59:04,954 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:04,954 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8807 states and 12787 transitions. [2023-11-19 07:59:04,965 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8807 states and 12787 transitions. [2023-11-19 07:59:05,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8807 to 3460. [2023-11-19 07:59:05,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3460 states, 3460 states have (on average 1.4560693641618496) internal successors, (5038), 3459 states have internal predecessors, (5038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:05,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3460 states to 3460 states and 5038 transitions. [2023-11-19 07:59:05,071 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3460 states and 5038 transitions. [2023-11-19 07:59:05,071 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-19 07:59:05,072 INFO L428 stractBuchiCegarLoop]: Abstraction has 3460 states and 5038 transitions. [2023-11-19 07:59:05,072 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-19 07:59:05,072 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3460 states and 5038 transitions. [2023-11-19 07:59:05,088 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3306 [2023-11-19 07:59:05,088 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:05,089 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:05,090 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:05,091 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:05,091 INFO L748 eck$LassoCheckResult]: Stem: 36635#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 36636#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 37419#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37420#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36958#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 36959#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36508#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36509#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36599#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37401#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36474#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36475#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36915#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36945#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36604#L866 assume !(0 == ~M_E~0); 36605#L866-2 assume !(0 == ~T1_E~0); 37157#L871-1 assume !(0 == ~T2_E~0); 37158#L876-1 assume !(0 == ~T3_E~0); 37463#L881-1 assume !(0 == ~T4_E~0); 37172#L886-1 assume !(0 == ~T5_E~0); 36902#L891-1 assume !(0 == ~T6_E~0); 36903#L896-1 assume !(0 == ~T7_E~0); 37165#L901-1 assume !(0 == ~T8_E~0); 37188#L906-1 assume !(0 == ~E_M~0); 37189#L911-1 assume !(0 == ~E_1~0); 36955#L916-1 assume !(0 == ~E_2~0); 36956#L921-1 assume !(0 == ~E_3~0); 37296#L926-1 assume !(0 == ~E_4~0); 37416#L931-1 assume !(0 == ~E_5~0); 37468#L936-1 assume !(0 == ~E_6~0); 37481#L941-1 assume !(0 == ~E_7~0); 36961#L946-1 assume !(0 == ~E_8~0); 36962#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37445#L430 assume !(1 == ~m_pc~0); 36802#L430-2 is_master_triggered_~__retres1~0#1 := 0; 36422#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36423#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 37088#L1073 assume !(0 != activate_threads_~tmp~1#1); 37089#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37274#L449 assume 1 == ~t1_pc~0; 37275#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36610#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36450#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36451#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 37203#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37024#L468 assume !(1 == ~t2_pc~0); 36408#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 36407#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36810#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36807#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 36424#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36425#L487 assume 1 == ~t3_pc~0; 37461#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36512#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36404#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36405#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 36880#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36881#L506 assume !(1 == ~t4_pc~0); 37017#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 37071#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36498#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36499#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 37010#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36817#L525 assume 1 == ~t5_pc~0; 36752#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36462#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37349#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37350#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 36667#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36668#L544 assume !(1 == ~t6_pc~0); 36818#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36819#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36788#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36442#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 36443#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37390#L563 assume 1 == ~t7_pc~0; 37228#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36466#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36467#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36906#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 36613#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36614#L582 assume 1 == ~t8_pc~0; 36530#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36531#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37281#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36867#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 36753#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36754#L964 assume !(1 == ~M_E~0); 37279#L964-2 assume !(1 == ~T1_E~0); 36669#L969-1 assume !(1 == ~T2_E~0); 36670#L974-1 assume !(1 == ~T3_E~0); 37320#L979-1 assume !(1 == ~T4_E~0); 37321#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37650#L989-1 assume !(1 == ~T6_E~0); 37648#L994-1 assume !(1 == ~T7_E~0); 37643#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37642#L1004-1 assume !(1 == ~E_M~0); 37631#L1009-1 assume !(1 == ~E_1~0); 36693#L1014-1 assume !(1 == ~E_2~0); 36694#L1019-1 assume !(1 == ~E_3~0); 37594#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 37579#L1029-1 assume !(1 == ~E_5~0); 37577#L1034-1 assume !(1 == ~E_6~0); 37565#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 37556#L1044-1 assume !(1 == ~E_8~0); 37548#L1049-1 assume { :end_inline_reset_delta_events } true; 37541#L1315-2 [2023-11-19 07:59:05,092 INFO L750 eck$LassoCheckResult]: Loop: 37541#L1315-2 assume !false; 37537#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37536#L841-1 assume !false; 37535#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 37530#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 37525#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 37524#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37522#L724 assume !(0 != eval_~tmp~0#1); 37521#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37520#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37518#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37519#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38307#L871-3 assume !(0 == ~T2_E~0); 38306#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38305#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38304#L886-3 assume !(0 == ~T5_E~0); 38303#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38302#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 38301#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 38300#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 38299#L911-3 assume !(0 == ~E_1~0); 38298#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38297#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38296#L926-3 assume !(0 == ~E_4~0); 38295#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38294#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38293#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38292#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 38291#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38290#L430-30 assume 1 == ~m_pc~0; 38288#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 38286#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38284#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 38282#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38280#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38278#L449-30 assume !(1 == ~t1_pc~0); 38275#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 38273#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38270#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38268#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38266#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38264#L468-30 assume 1 == ~t2_pc~0; 38261#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38259#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38256#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38254#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 38252#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38250#L487-30 assume 1 == ~t3_pc~0; 38247#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38245#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38244#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38241#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38239#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38237#L506-30 assume !(1 == ~t4_pc~0); 38234#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 38232#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38229#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38227#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38225#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38223#L525-30 assume 1 == ~t5_pc~0; 38220#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38218#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38215#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38213#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38211#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38209#L544-30 assume !(1 == ~t6_pc~0); 38206#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 38204#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38201#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38199#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38197#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37854#L563-30 assume 1 == ~t7_pc~0; 37852#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37850#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37849#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37848#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 37752#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37749#L582-30 assume !(1 == ~t8_pc~0); 37746#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 37744#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37742#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37740#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37726#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37723#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36448#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37718#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37715#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37712#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37709#L984-3 assume !(1 == ~T5_E~0); 37708#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37706#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37704#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37702#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37700#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37698#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37696#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37693#L1024-3 assume !(1 == ~E_4~0); 37692#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37691#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37690#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37689#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37688#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 37687#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 37665#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 37664#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 37659#L1334 assume !(0 == start_simulation_~tmp~3#1); 37365#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 37602#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 37580#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 37578#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 37576#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37564#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37555#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 37547#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 37541#L1315-2 [2023-11-19 07:59:05,093 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:05,093 INFO L85 PathProgramCache]: Analyzing trace with hash -2109236796, now seen corresponding path program 1 times [2023-11-19 07:59:05,093 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:05,093 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1697606331] [2023-11-19 07:59:05,094 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:05,094 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:05,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:05,160 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:05,161 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:05,161 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1697606331] [2023-11-19 07:59:05,161 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1697606331] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:05,161 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:05,161 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:05,162 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1517109142] [2023-11-19 07:59:05,162 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:05,162 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:05,162 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:05,163 INFO L85 PathProgramCache]: Analyzing trace with hash 1868159045, now seen corresponding path program 2 times [2023-11-19 07:59:05,163 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:05,163 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1977394099] [2023-11-19 07:59:05,163 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:05,163 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:05,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:05,235 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:05,235 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:05,236 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1977394099] [2023-11-19 07:59:05,236 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1977394099] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:05,236 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:05,236 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:59:05,236 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1910147908] [2023-11-19 07:59:05,236 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:05,237 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:05,237 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:05,237 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:59:05,238 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:59:05,238 INFO L87 Difference]: Start difference. First operand 3460 states and 5038 transitions. cyclomatic complexity: 1582 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:05,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:05,555 INFO L93 Difference]: Finished difference Result 9497 states and 13637 transitions. [2023-11-19 07:59:05,555 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9497 states and 13637 transitions. [2023-11-19 07:59:05,611 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9068 [2023-11-19 07:59:05,657 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9497 states to 9497 states and 13637 transitions. [2023-11-19 07:59:05,657 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9497 [2023-11-19 07:59:05,667 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9497 [2023-11-19 07:59:05,667 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9497 states and 13637 transitions. [2023-11-19 07:59:05,683 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:05,683 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9497 states and 13637 transitions. [2023-11-19 07:59:05,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9497 states and 13637 transitions. [2023-11-19 07:59:05,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9497 to 9009. [2023-11-19 07:59:05,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9009 states, 9009 states have (on average 1.4395604395604396) internal successors, (12969), 9008 states have internal predecessors, (12969), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:05,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9009 states to 9009 states and 12969 transitions. [2023-11-19 07:59:05,897 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9009 states and 12969 transitions. [2023-11-19 07:59:05,898 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:59:05,898 INFO L428 stractBuchiCegarLoop]: Abstraction has 9009 states and 12969 transitions. [2023-11-19 07:59:05,899 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-19 07:59:05,899 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9009 states and 12969 transitions. [2023-11-19 07:59:05,941 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8840 [2023-11-19 07:59:05,942 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:05,942 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:05,944 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:05,944 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:05,944 INFO L748 eck$LassoCheckResult]: Stem: 49606#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 49607#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 50439#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50440#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49933#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 49934#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49478#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49479#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49570#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50420#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49443#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49444#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49887#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49920#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49574#L866 assume !(0 == ~M_E~0); 49575#L866-2 assume !(0 == ~T1_E~0); 50139#L871-1 assume !(0 == ~T2_E~0); 50140#L876-1 assume !(0 == ~T3_E~0); 50487#L881-1 assume !(0 == ~T4_E~0); 50154#L886-1 assume !(0 == ~T5_E~0); 49876#L891-1 assume !(0 == ~T6_E~0); 49877#L896-1 assume !(0 == ~T7_E~0); 50147#L901-1 assume !(0 == ~T8_E~0); 50170#L906-1 assume !(0 == ~E_M~0); 50171#L911-1 assume !(0 == ~E_1~0); 49930#L916-1 assume !(0 == ~E_2~0); 49931#L921-1 assume !(0 == ~E_3~0); 50293#L926-1 assume !(0 == ~E_4~0); 50435#L931-1 assume !(0 == ~E_5~0); 50498#L936-1 assume !(0 == ~E_6~0); 50510#L941-1 assume !(0 == ~E_7~0); 49936#L946-1 assume !(0 == ~E_8~0); 49937#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50465#L430 assume !(1 == ~m_pc~0); 50383#L430-2 is_master_triggered_~__retres1~0#1 := 0; 49389#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49390#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 50065#L1073 assume !(0 != activate_threads_~tmp~1#1); 50066#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50270#L449 assume !(1 == ~t1_pc~0); 49580#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 49581#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49416#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49417#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 50187#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49994#L468 assume !(1 == ~t2_pc~0); 49377#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 49376#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49782#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49777#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 49391#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49392#L487 assume 1 == ~t3_pc~0; 50484#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49482#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49373#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49374#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 49855#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49856#L506 assume !(1 == ~t4_pc~0); 49988#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 50045#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49468#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49469#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 49982#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49789#L525 assume 1 == ~t5_pc~0; 49720#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49430#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50348#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50349#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 49638#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49639#L544 assume !(1 == ~t6_pc~0); 49790#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 49791#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49763#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49411#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 49412#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50399#L563 assume 1 == ~t7_pc~0; 50215#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49434#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49435#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49878#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 49582#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49583#L582 assume 1 == ~t8_pc~0; 49500#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49501#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50277#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49842#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 49724#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49725#L964 assume !(1 == ~M_E~0); 50275#L964-2 assume !(1 == ~T1_E~0); 49640#L969-1 assume !(1 == ~T2_E~0); 49641#L974-1 assume !(1 == ~T3_E~0); 50320#L979-1 assume !(1 == ~T4_E~0); 50321#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 55100#L989-1 assume !(1 == ~T6_E~0); 55356#L994-1 assume !(1 == ~T7_E~0); 55355#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 55354#L1004-1 assume !(1 == ~E_M~0); 49413#L1009-1 assume !(1 == ~E_1~0); 49414#L1014-1 assume !(1 == ~E_2~0); 49665#L1019-1 assume !(1 == ~E_3~0); 50258#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 49603#L1029-1 assume !(1 == ~E_5~0); 49604#L1034-1 assume !(1 == ~E_6~0); 55338#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 55334#L1044-1 assume !(1 == ~E_8~0); 55333#L1049-1 assume { :end_inline_reset_delta_events } true; 55329#L1315-2 [2023-11-19 07:59:05,945 INFO L750 eck$LassoCheckResult]: Loop: 55329#L1315-2 assume !false; 55325#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 54700#L841-1 assume !false; 54701#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 54693#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 54689#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 55274#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 49386#L724 assume !(0 != eval_~tmp~0#1); 49388#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 56462#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 56461#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 56460#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 56459#L871-3 assume !(0 == ~T2_E~0); 56458#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 56457#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 56456#L886-3 assume !(0 == ~T5_E~0); 56455#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 56454#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 56453#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 56452#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 56451#L911-3 assume !(0 == ~E_1~0); 56450#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 56449#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 56448#L926-3 assume !(0 == ~E_4~0); 56446#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 56444#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 56442#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 56440#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 56438#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56436#L430-30 assume !(1 == ~m_pc~0); 56434#L430-32 is_master_triggered_~__retres1~0#1 := 0; 56432#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56430#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 56428#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 56426#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56424#L449-30 assume !(1 == ~t1_pc~0); 56422#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 56420#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56418#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 56416#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 56414#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56412#L468-30 assume 1 == ~t2_pc~0; 56409#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 56407#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56405#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 56403#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 56401#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56399#L487-30 assume 1 == ~t3_pc~0; 56396#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 56394#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56392#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 56390#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 56388#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56386#L506-30 assume 1 == ~t4_pc~0; 56384#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 56381#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56379#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56376#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 56374#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56372#L525-30 assume 1 == ~t5_pc~0; 56369#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56367#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56365#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 56362#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 56360#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 56358#L544-30 assume !(1 == ~t6_pc~0); 56355#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 56353#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 56351#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56348#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 56346#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56344#L563-30 assume 1 == ~t7_pc~0; 56341#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 56339#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 56337#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 56334#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 56332#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 56330#L582-30 assume !(1 == ~t8_pc~0); 56327#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 56325#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 56323#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 56320#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 56318#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56316#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 55172#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 56312#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 56310#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 56307#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56277#L984-3 assume !(1 == ~T5_E~0); 56275#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 56272#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 56270#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 56268#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 56266#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 56264#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 56262#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 56172#L1024-3 assume !(1 == ~E_4~0); 56170#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 56168#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 56166#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 56164#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 56162#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 55878#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 55869#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 55868#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 55867#L1334 assume !(0 == start_simulation_~tmp~3#1); 55120#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 55857#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 55849#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 55847#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 55845#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 55842#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 55514#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 55332#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 55329#L1315-2 [2023-11-19 07:59:05,945 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:05,946 INFO L85 PathProgramCache]: Analyzing trace with hash 28257477, now seen corresponding path program 1 times [2023-11-19 07:59:05,946 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:05,946 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1139998107] [2023-11-19 07:59:05,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:05,946 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:05,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:06,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:06,021 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:06,021 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1139998107] [2023-11-19 07:59:06,021 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1139998107] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:06,022 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:06,022 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:06,022 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [151626713] [2023-11-19 07:59:06,022 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:06,022 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:06,023 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:06,023 INFO L85 PathProgramCache]: Analyzing trace with hash -1435397817, now seen corresponding path program 1 times [2023-11-19 07:59:06,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:06,023 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [367769081] [2023-11-19 07:59:06,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:06,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:06,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:06,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:06,116 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:06,116 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [367769081] [2023-11-19 07:59:06,116 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [367769081] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:06,116 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:06,116 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:06,117 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1366684340] [2023-11-19 07:59:06,117 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:06,117 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:06,117 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:06,118 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:59:06,118 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:59:06,119 INFO L87 Difference]: Start difference. First operand 9009 states and 12969 transitions. cyclomatic complexity: 3968 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:06,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:06,504 INFO L93 Difference]: Finished difference Result 25612 states and 36442 transitions. [2023-11-19 07:59:06,505 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25612 states and 36442 transitions. [2023-11-19 07:59:06,654 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24832 [2023-11-19 07:59:06,914 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25612 states to 25612 states and 36442 transitions. [2023-11-19 07:59:06,914 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25612 [2023-11-19 07:59:06,939 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25612 [2023-11-19 07:59:06,940 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25612 states and 36442 transitions. [2023-11-19 07:59:06,969 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:06,969 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25612 states and 36442 transitions. [2023-11-19 07:59:06,997 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25612 states and 36442 transitions. [2023-11-19 07:59:07,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25612 to 24782. [2023-11-19 07:59:07,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24782 states, 24782 states have (on average 1.425550803002179) internal successors, (35328), 24781 states have internal predecessors, (35328), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:07,596 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24782 states to 24782 states and 35328 transitions. [2023-11-19 07:59:07,596 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24782 states and 35328 transitions. [2023-11-19 07:59:07,597 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:59:07,598 INFO L428 stractBuchiCegarLoop]: Abstraction has 24782 states and 35328 transitions. [2023-11-19 07:59:07,598 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-19 07:59:07,598 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24782 states and 35328 transitions. [2023-11-19 07:59:07,719 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24574 [2023-11-19 07:59:07,719 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:07,720 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:07,722 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:07,722 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:07,723 INFO L748 eck$LassoCheckResult]: Stem: 84236#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 84237#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 85112#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 85113#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 84571#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 84572#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 84106#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 84107#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 84197#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 85091#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 84073#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 84074#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 84527#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 84558#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 84204#L866 assume !(0 == ~M_E~0); 84205#L866-2 assume !(0 == ~T1_E~0); 84787#L871-1 assume !(0 == ~T2_E~0); 84788#L876-1 assume !(0 == ~T3_E~0); 85175#L881-1 assume !(0 == ~T4_E~0); 84804#L886-1 assume !(0 == ~T5_E~0); 84514#L891-1 assume !(0 == ~T6_E~0); 84515#L896-1 assume !(0 == ~T7_E~0); 84795#L901-1 assume !(0 == ~T8_E~0); 84821#L906-1 assume !(0 == ~E_M~0); 84822#L911-1 assume !(0 == ~E_1~0); 84568#L916-1 assume !(0 == ~E_2~0); 84569#L921-1 assume !(0 == ~E_3~0); 84956#L926-1 assume !(0 == ~E_4~0); 85107#L931-1 assume !(0 == ~E_5~0); 85191#L936-1 assume !(0 == ~E_6~0); 85208#L941-1 assume !(0 == ~E_7~0); 84575#L946-1 assume !(0 == ~E_8~0); 84576#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85145#L430 assume !(1 == ~m_pc~0); 85061#L430-2 is_master_triggered_~__retres1~0#1 := 0; 84022#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84023#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 84711#L1073 assume !(0 != activate_threads_~tmp~1#1); 84712#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84932#L449 assume !(1 == ~t1_pc~0); 84209#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 84210#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 84052#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 84053#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 84837#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84640#L468 assume !(1 == ~t2_pc~0); 84008#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 84007#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 84416#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 84412#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 84024#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 84025#L487 assume !(1 == ~t3_pc~0); 84139#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 84110#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 84004#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 84005#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 84492#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 84493#L506 assume !(1 == ~t4_pc~0); 84630#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 84693#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84096#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 84097#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 84624#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 84423#L525 assume 1 == ~t5_pc~0; 84354#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 84060#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 85017#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 85018#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 84268#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 84269#L544 assume !(1 == ~t6_pc~0); 84424#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 84425#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 84395#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 84042#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 84043#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 85073#L563 assume 1 == ~t7_pc~0; 84867#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 84064#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 84065#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 84521#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 84213#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 84214#L582 assume 1 == ~t8_pc~0; 84128#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 84129#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 84942#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 84480#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 84355#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84356#L964 assume !(1 == ~M_E~0); 84939#L964-2 assume !(1 == ~T1_E~0); 106248#L969-1 assume !(1 == ~T2_E~0); 106246#L974-1 assume !(1 == ~T3_E~0); 84981#L979-1 assume !(1 == ~T4_E~0); 84982#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 84430#L989-1 assume !(1 == ~T6_E~0); 84431#L994-1 assume !(1 == ~T7_E~0); 84306#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 84307#L1004-1 assume !(1 == ~E_M~0); 84045#L1009-1 assume !(1 == ~E_1~0); 84046#L1014-1 assume !(1 == ~E_2~0); 84296#L1019-1 assume !(1 == ~E_3~0); 84917#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 85158#L1029-1 assume !(1 == ~E_5~0); 106844#L1034-1 assume !(1 == ~E_6~0); 106843#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 85135#L1044-1 assume !(1 == ~E_8~0); 84535#L1049-1 assume { :end_inline_reset_delta_events } true; 84195#L1315-2 [2023-11-19 07:59:07,723 INFO L750 eck$LassoCheckResult]: Loop: 84195#L1315-2 assume !false; 84196#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 107754#L841-1 assume !false; 106646#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 106647#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 107744#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 107743#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 107742#L724 assume !(0 != eval_~tmp~0#1); 84952#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 84632#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 84026#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 84027#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 108360#L871-3 assume !(0 == ~T2_E~0); 108356#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 108355#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 108354#L886-3 assume !(0 == ~T5_E~0); 108353#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 108352#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 108351#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 108350#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 108349#L911-3 assume !(0 == ~E_1~0); 108348#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 108347#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 108346#L926-3 assume !(0 == ~E_4~0); 108345#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 108344#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 108343#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 108342#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 108341#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 108340#L430-30 assume !(1 == ~m_pc~0); 108339#L430-32 is_master_triggered_~__retres1~0#1 := 0; 108338#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 108337#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 108336#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 108335#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 108334#L449-30 assume !(1 == ~t1_pc~0); 108333#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 108332#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 108331#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 108330#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 108329#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 108328#L468-30 assume !(1 == ~t2_pc~0); 108327#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 108324#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 108322#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 108321#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 108319#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 108317#L487-30 assume !(1 == ~t3_pc~0); 108315#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 108313#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 108311#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 108310#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 108307#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 108305#L506-30 assume 1 == ~t4_pc~0; 108303#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 108300#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 108298#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 108296#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 108294#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 108292#L525-30 assume 1 == ~t5_pc~0; 108289#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 108287#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 108285#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 108283#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 84422#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 84176#L544-30 assume 1 == ~t6_pc~0; 83989#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 83990#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 84100#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 84101#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 85076#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 85047#L563-30 assume !(1 == ~t7_pc~0); 85049#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 108183#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 108181#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 108179#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 108177#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 108175#L582-30 assume !(1 == ~t8_pc~0); 108171#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 108169#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 108167#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 108165#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 108163#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 108162#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 106348#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 108160#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 108159#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 108158#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 108157#L984-3 assume !(1 == ~T5_E~0); 106340#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 108156#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 108155#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 108154#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 108153#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 108152#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 108151#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 108150#L1024-3 assume !(1 == ~E_4~0); 107395#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 108149#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 107390#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 107389#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 106729#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 106730#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 108134#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 108133#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 108098#L1334 assume !(0 == start_simulation_~tmp~3#1); 108096#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 108084#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 108075#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 107896#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 85219#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 85109#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 84660#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 84661#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 84195#L1315-2 [2023-11-19 07:59:07,724 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:07,724 INFO L85 PathProgramCache]: Analyzing trace with hash -1079871162, now seen corresponding path program 1 times [2023-11-19 07:59:07,725 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:07,725 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [960160384] [2023-11-19 07:59:07,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:07,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:07,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:07,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:07,822 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:07,823 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [960160384] [2023-11-19 07:59:07,823 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [960160384] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:07,824 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:07,824 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:59:07,824 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1725132226] [2023-11-19 07:59:07,824 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:07,825 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:07,827 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:07,827 INFO L85 PathProgramCache]: Analyzing trace with hash -1030555831, now seen corresponding path program 1 times [2023-11-19 07:59:07,828 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:07,828 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1462004725] [2023-11-19 07:59:07,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:07,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:07,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:07,998 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:07,998 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:07,999 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1462004725] [2023-11-19 07:59:07,999 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1462004725] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:07,999 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:07,999 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:08,000 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [81754159] [2023-11-19 07:59:08,000 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:08,000 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:08,001 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:08,001 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:59:08,001 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:59:08,001 INFO L87 Difference]: Start difference. First operand 24782 states and 35328 transitions. cyclomatic complexity: 10562 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:08,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:08,407 INFO L93 Difference]: Finished difference Result 46800 states and 66433 transitions. [2023-11-19 07:59:08,407 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 46800 states and 66433 transitions. [2023-11-19 07:59:08,769 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 46461 [2023-11-19 07:59:08,982 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 46800 states to 46800 states and 66433 transitions. [2023-11-19 07:59:08,983 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46800 [2023-11-19 07:59:09,033 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46800 [2023-11-19 07:59:09,033 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46800 states and 66433 transitions. [2023-11-19 07:59:09,201 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:09,219 INFO L218 hiAutomatonCegarLoop]: Abstraction has 46800 states and 66433 transitions. [2023-11-19 07:59:09,281 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46800 states and 66433 transitions. [2023-11-19 07:59:10,115 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46800 to 46728. [2023-11-19 07:59:10,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46728 states, 46728 states have (on average 1.4201549392227357) internal successors, (66361), 46727 states have internal predecessors, (66361), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:10,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46728 states to 46728 states and 66361 transitions. [2023-11-19 07:59:10,577 INFO L240 hiAutomatonCegarLoop]: Abstraction has 46728 states and 66361 transitions. [2023-11-19 07:59:10,578 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:59:10,578 INFO L428 stractBuchiCegarLoop]: Abstraction has 46728 states and 66361 transitions. [2023-11-19 07:59:10,579 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-19 07:59:10,579 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46728 states and 66361 transitions. [2023-11-19 07:59:10,755 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 46389 [2023-11-19 07:59:10,756 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:10,756 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:10,758 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:10,758 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:10,758 INFO L748 eck$LassoCheckResult]: Stem: 155824#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 155825#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 156658#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 156659#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 156153#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 156154#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 155695#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 155696#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 155786#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 156632#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 155662#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 155663#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 156108#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 156139#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 155793#L866 assume !(0 == ~M_E~0); 155794#L866-2 assume !(0 == ~T1_E~0); 156357#L871-1 assume !(0 == ~T2_E~0); 156358#L876-1 assume !(0 == ~T3_E~0); 156713#L881-1 assume !(0 == ~T4_E~0); 156374#L886-1 assume !(0 == ~T5_E~0); 156095#L891-1 assume !(0 == ~T6_E~0); 156096#L896-1 assume !(0 == ~T7_E~0); 156365#L901-1 assume !(0 == ~T8_E~0); 156390#L906-1 assume !(0 == ~E_M~0); 156391#L911-1 assume !(0 == ~E_1~0); 156149#L916-1 assume !(0 == ~E_2~0); 156150#L921-1 assume !(0 == ~E_3~0); 156512#L926-1 assume !(0 == ~E_4~0); 156654#L931-1 assume !(0 == ~E_5~0); 156725#L936-1 assume !(0 == ~E_6~0); 156742#L941-1 assume !(0 == ~E_7~0); 156156#L946-1 assume !(0 == ~E_8~0); 156157#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 156689#L430 assume !(1 == ~m_pc~0); 156608#L430-2 is_master_triggered_~__retres1~0#1 := 0; 155611#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 155612#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 156284#L1073 assume !(0 != activate_threads_~tmp~1#1); 156285#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 156488#L449 assume !(1 == ~t1_pc~0); 155798#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 155799#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 155640#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 155641#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 156405#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 156220#L468 assume !(1 == ~t2_pc~0); 155597#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 155596#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 156002#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 155997#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 155613#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 155614#L487 assume !(1 == ~t3_pc~0); 155728#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 155699#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 155593#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 155594#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 156074#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 156075#L506 assume !(1 == ~t4_pc~0); 156211#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 156268#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 155685#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 155686#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 156207#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 156008#L525 assume !(1 == ~t5_pc~0); 155648#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 155649#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 156567#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 156568#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 155856#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 155857#L544 assume !(1 == ~t6_pc~0); 156009#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 156010#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 155981#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 155631#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 155632#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 156620#L563 assume 1 == ~t7_pc~0; 156431#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 155653#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 155654#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 156102#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 155802#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 155803#L582 assume 1 == ~t8_pc~0; 155717#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 155718#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 156497#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 156062#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 155942#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 155943#L964 assume !(1 == ~M_E~0); 156493#L964-2 assume !(1 == ~T1_E~0); 155858#L969-1 assume !(1 == ~T2_E~0); 155859#L974-1 assume !(1 == ~T3_E~0); 156536#L979-1 assume !(1 == ~T4_E~0); 156537#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 156765#L989-1 assume !(1 == ~T6_E~0); 193326#L994-1 assume !(1 == ~T7_E~0); 193324#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 193322#L1004-1 assume !(1 == ~E_M~0); 193320#L1009-1 assume !(1 == ~E_1~0); 193318#L1014-1 assume !(1 == ~E_2~0); 193316#L1019-1 assume !(1 == ~E_3~0); 193314#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 155821#L1029-1 assume !(1 == ~E_5~0); 155822#L1034-1 assume !(1 == ~E_6~0); 155909#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 156682#L1044-1 assume !(1 == ~E_8~0); 156116#L1049-1 assume { :end_inline_reset_delta_events } true; 156117#L1315-2 [2023-11-19 07:59:10,759 INFO L750 eck$LassoCheckResult]: Loop: 156117#L1315-2 assume !false; 193871#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 193870#L841-1 assume !false; 193869#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 193864#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 193859#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 193858#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 193856#L724 assume !(0 != eval_~tmp~0#1); 193857#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 194404#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 194402#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 194400#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 194399#L871-3 assume !(0 == ~T2_E~0); 194397#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 194395#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 194393#L886-3 assume !(0 == ~T5_E~0); 194391#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 194389#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 194386#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 194384#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 194382#L911-3 assume !(0 == ~E_1~0); 194380#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 194378#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 194376#L926-3 assume !(0 == ~E_4~0); 194374#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 194372#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 194370#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 194368#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 194366#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 194364#L430-30 assume !(1 == ~m_pc~0); 194361#L430-32 is_master_triggered_~__retres1~0#1 := 0; 194359#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 194357#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 194355#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 194353#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 194351#L449-30 assume !(1 == ~t1_pc~0); 194349#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 194347#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 194345#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 194343#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 194341#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 194339#L468-30 assume !(1 == ~t2_pc~0); 194336#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 194333#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 194331#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 194329#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 194327#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 194325#L487-30 assume !(1 == ~t3_pc~0); 194322#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 194320#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 194318#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 194316#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 194314#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 194312#L506-30 assume !(1 == ~t4_pc~0); 194308#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 194306#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 194304#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 194302#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 194300#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 194299#L525-30 assume !(1 == ~t5_pc~0); 194298#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 194297#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 194296#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 194295#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 194294#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 194293#L544-30 assume !(1 == ~t6_pc~0); 194291#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 194290#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 194289#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 194288#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 194287#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 194286#L563-30 assume 1 == ~t7_pc~0; 194284#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 194283#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 194282#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 194281#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 194280#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 194279#L582-30 assume 1 == ~t8_pc~0; 194278#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 194276#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 194275#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 194274#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 194273#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 194272#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 183995#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 194270#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 194268#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 194266#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 194264#L984-3 assume !(1 == ~T5_E~0); 184393#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 194261#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 194259#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 194257#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 194255#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 194253#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 194251#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 194249#L1024-3 assume !(1 == ~E_4~0); 193361#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 194245#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 194243#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 194241#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 194239#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 194237#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 194227#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 194225#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 194121#L1334 assume !(0 == start_simulation_~tmp~3#1); 194118#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 194110#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 194101#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 194099#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 194097#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 194095#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 194093#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 194092#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 156117#L1315-2 [2023-11-19 07:59:10,760 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:10,760 INFO L85 PathProgramCache]: Analyzing trace with hash 818659143, now seen corresponding path program 1 times [2023-11-19 07:59:10,760 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:10,760 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [592245489] [2023-11-19 07:59:10,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:10,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:10,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:10,954 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:10,954 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:10,955 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [592245489] [2023-11-19 07:59:10,955 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [592245489] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:10,955 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:10,955 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:10,956 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1256257140] [2023-11-19 07:59:10,956 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:10,956 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:10,957 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:10,957 INFO L85 PathProgramCache]: Analyzing trace with hash 1629228042, now seen corresponding path program 1 times [2023-11-19 07:59:10,957 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:10,957 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [214110586] [2023-11-19 07:59:10,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:10,958 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:10,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:11,053 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:11,053 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:11,054 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [214110586] [2023-11-19 07:59:11,054 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [214110586] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:11,054 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:11,054 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:59:11,054 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1030339254] [2023-11-19 07:59:11,055 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:11,055 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:11,056 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:11,057 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:59:11,057 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:59:11,057 INFO L87 Difference]: Start difference. First operand 46728 states and 66361 transitions. cyclomatic complexity: 19665 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:12,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:12,127 INFO L93 Difference]: Finished difference Result 129325 states and 182268 transitions. [2023-11-19 07:59:12,127 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 129325 states and 182268 transitions. [2023-11-19 07:59:13,082 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 126251 [2023-11-19 07:59:14,005 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 129325 states to 129325 states and 182268 transitions. [2023-11-19 07:59:14,005 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 129325 [2023-11-19 07:59:14,128 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 129325 [2023-11-19 07:59:14,129 INFO L73 IsDeterministic]: Start isDeterministic. Operand 129325 states and 182268 transitions. [2023-11-19 07:59:14,241 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:14,241 INFO L218 hiAutomatonCegarLoop]: Abstraction has 129325 states and 182268 transitions. [2023-11-19 07:59:14,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129325 states and 182268 transitions. [2023-11-19 07:59:16,452 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129325 to 125813. [2023-11-19 07:59:16,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 125813 states, 125813 states have (on average 1.412731593714481) internal successors, (177740), 125812 states have internal predecessors, (177740), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:17,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125813 states to 125813 states and 177740 transitions. [2023-11-19 07:59:17,065 INFO L240 hiAutomatonCegarLoop]: Abstraction has 125813 states and 177740 transitions. [2023-11-19 07:59:17,066 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:59:17,066 INFO L428 stractBuchiCegarLoop]: Abstraction has 125813 states and 177740 transitions. [2023-11-19 07:59:17,066 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-19 07:59:17,067 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 125813 states and 177740 transitions. [2023-11-19 07:59:17,907 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 125171 [2023-11-19 07:59:17,907 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:17,907 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:17,910 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:17,910 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:17,910 INFO L748 eck$LassoCheckResult]: Stem: 331893#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 331894#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 332788#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 332789#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 332223#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 332224#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 331761#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 331762#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 331853#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 332767#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 331727#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 331728#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 332179#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 332210#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 331860#L866 assume !(0 == ~M_E~0); 331861#L866-2 assume !(0 == ~T1_E~0); 332438#L871-1 assume !(0 == ~T2_E~0); 332439#L876-1 assume !(0 == ~T3_E~0); 332853#L881-1 assume !(0 == ~T4_E~0); 332456#L886-1 assume !(0 == ~T5_E~0); 332165#L891-1 assume !(0 == ~T6_E~0); 332166#L896-1 assume !(0 == ~T7_E~0); 332446#L901-1 assume !(0 == ~T8_E~0); 332478#L906-1 assume !(0 == ~E_M~0); 332479#L911-1 assume !(0 == ~E_1~0); 332220#L916-1 assume !(0 == ~E_2~0); 332221#L921-1 assume !(0 == ~E_3~0); 332609#L926-1 assume !(0 == ~E_4~0); 332784#L931-1 assume !(0 == ~E_5~0); 332866#L936-1 assume !(0 == ~E_6~0); 332878#L941-1 assume !(0 == ~E_7~0); 332226#L946-1 assume !(0 == ~E_8~0); 332227#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 332826#L430 assume !(1 == ~m_pc~0); 332737#L430-2 is_master_triggered_~__retres1~0#1 := 0; 331675#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 331676#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 332360#L1073 assume !(0 != activate_threads_~tmp~1#1); 332361#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 332583#L449 assume !(1 == ~t1_pc~0); 331866#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 331867#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 331706#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 331707#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 332495#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 332291#L468 assume !(1 == ~t2_pc~0); 331661#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 331660#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 332073#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 332069#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 331677#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 331678#L487 assume !(1 == ~t3_pc~0); 331794#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 331765#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 331657#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 331658#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 332143#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 332144#L506 assume !(1 == ~t4_pc~0); 332281#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 332342#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 331751#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 331752#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 332276#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 332079#L525 assume !(1 == ~t5_pc~0); 331713#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 331714#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 332684#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 332685#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 331926#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 331927#L544 assume !(1 == ~t6_pc~0); 332080#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 332081#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 332054#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 331695#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 331696#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 332752#L563 assume !(1 == ~t7_pc~0); 332511#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 331718#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 331719#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 332172#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 331870#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 331871#L582 assume 1 == ~t8_pc~0; 331783#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 331784#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 332592#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 332131#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 332014#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 332015#L964 assume !(1 == ~M_E~0); 332589#L964-2 assume !(1 == ~T1_E~0); 331928#L969-1 assume !(1 == ~T2_E~0); 331929#L974-1 assume !(1 == ~T3_E~0); 332642#L979-1 assume !(1 == ~T4_E~0); 332643#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 332086#L989-1 assume !(1 == ~T6_E~0); 332087#L994-1 assume !(1 == ~T7_E~0); 331965#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 331966#L1004-1 assume !(1 == ~E_M~0); 331698#L1009-1 assume !(1 == ~E_1~0); 331699#L1014-1 assume !(1 == ~E_2~0); 332571#L1019-1 assume !(1 == ~E_3~0); 332572#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 332834#L1029-1 assume !(1 == ~E_5~0); 331978#L1034-1 assume !(1 == ~E_6~0); 331979#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 332809#L1044-1 assume !(1 == ~E_8~0); 332810#L1049-1 assume { :end_inline_reset_delta_events } true; 351640#L1315-2 [2023-11-19 07:59:17,911 INFO L750 eck$LassoCheckResult]: Loop: 351640#L1315-2 assume !false; 351634#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 351630#L841-1 assume !false; 351626#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 351627#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 389875#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 389874#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 389873#L724 assume !(0 != eval_~tmp~0#1); 369996#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 369995#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 369994#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 369993#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 369992#L871-3 assume !(0 == ~T2_E~0); 369991#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 369990#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 369989#L886-3 assume !(0 == ~T5_E~0); 369988#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 369987#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 369986#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 369985#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 369984#L911-3 assume !(0 == ~E_1~0); 369983#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 369982#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 369981#L926-3 assume !(0 == ~E_4~0); 369980#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 369979#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 369978#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 369977#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 369976#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 369975#L430-30 assume !(1 == ~m_pc~0); 369974#L430-32 is_master_triggered_~__retres1~0#1 := 0; 369973#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 369972#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 369971#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 369970#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 369969#L449-30 assume !(1 == ~t1_pc~0); 369968#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 369967#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 369966#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 369965#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 369964#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 369963#L468-30 assume 1 == ~t2_pc~0; 369961#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 369960#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 369959#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 369958#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 369957#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 369956#L487-30 assume !(1 == ~t3_pc~0); 369955#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 369954#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 369953#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 369952#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 369951#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 369950#L506-30 assume 1 == ~t4_pc~0; 369949#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 369947#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 369946#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 369945#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 369944#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 369943#L525-30 assume !(1 == ~t5_pc~0); 369942#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 369941#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 369940#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 369939#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 369938#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 369937#L544-30 assume 1 == ~t6_pc~0; 369936#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 369934#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 369933#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 369932#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 369931#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 369930#L563-30 assume !(1 == ~t7_pc~0); 369929#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 369928#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 369927#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 369926#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 369925#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 369924#L582-30 assume 1 == ~t8_pc~0; 369923#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 369921#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 369920#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 369919#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 369918#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 369917#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 351243#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 369916#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 369915#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 369914#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 369913#L984-3 assume !(1 == ~T5_E~0); 351776#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 369912#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 369911#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 369910#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 369909#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 369908#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 369907#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 369906#L1024-3 assume !(1 == ~E_4~0); 369687#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 369905#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 369904#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 369903#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 369902#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 369901#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 369892#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 369891#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 369578#L1334 assume !(0 == start_simulation_~tmp~3#1); 369577#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 369480#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 369472#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 351681#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 351676#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 351665#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 351658#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 351651#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 351640#L1315-2 [2023-11-19 07:59:17,912 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:17,912 INFO L85 PathProgramCache]: Analyzing trace with hash -952811832, now seen corresponding path program 1 times [2023-11-19 07:59:17,912 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:17,912 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1106450656] [2023-11-19 07:59:17,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:17,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:17,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:17,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:17,976 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:17,976 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1106450656] [2023-11-19 07:59:17,976 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1106450656] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:17,976 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:17,976 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:59:17,977 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [528987176] [2023-11-19 07:59:17,977 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:17,977 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:17,978 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:17,978 INFO L85 PathProgramCache]: Analyzing trace with hash -1100965176, now seen corresponding path program 1 times [2023-11-19 07:59:17,978 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:17,978 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [808252273] [2023-11-19 07:59:17,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:17,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:17,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:18,028 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:18,028 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:18,028 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [808252273] [2023-11-19 07:59:18,029 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [808252273] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:18,029 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:18,029 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:18,029 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2119519857] [2023-11-19 07:59:18,029 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:18,030 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:18,030 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:18,030 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:59:18,031 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:59:18,031 INFO L87 Difference]: Start difference. First operand 125813 states and 177740 transitions. cyclomatic complexity: 51991 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:19,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:19,596 INFO L93 Difference]: Finished difference Result 236453 states and 333170 transitions. [2023-11-19 07:59:19,596 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 236453 states and 333170 transitions. [2023-11-19 07:59:20,918 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 234884 [2023-11-19 07:59:22,426 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 236453 states to 236453 states and 333170 transitions. [2023-11-19 07:59:22,426 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 236453 [2023-11-19 07:59:22,687 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 236453 [2023-11-19 07:59:22,687 INFO L73 IsDeterministic]: Start isDeterministic. Operand 236453 states and 333170 transitions. [2023-11-19 07:59:22,846 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:22,846 INFO L218 hiAutomatonCegarLoop]: Abstraction has 236453 states and 333170 transitions. [2023-11-19 07:59:22,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236453 states and 333170 transitions. [2023-11-19 07:59:25,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236453 to 236021. [2023-11-19 07:59:25,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 236021 states, 236021 states have (on average 1.4097813330169773) internal successors, (332738), 236020 states have internal predecessors, (332738), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:27,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 236021 states to 236021 states and 332738 transitions. [2023-11-19 07:59:27,610 INFO L240 hiAutomatonCegarLoop]: Abstraction has 236021 states and 332738 transitions. [2023-11-19 07:59:27,611 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:59:27,612 INFO L428 stractBuchiCegarLoop]: Abstraction has 236021 states and 332738 transitions. [2023-11-19 07:59:27,612 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-19 07:59:27,612 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 236021 states and 332738 transitions. [2023-11-19 07:59:28,322 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 234452 [2023-11-19 07:59:28,322 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:28,322 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:28,325 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:28,325 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:28,326 INFO L748 eck$LassoCheckResult]: Stem: 694158#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 694159#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 695012#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 695013#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 694483#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 694484#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 694031#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 694032#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 694120#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 694993#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 693999#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 694000#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 694440#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 694470#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 694127#L866 assume !(0 == ~M_E~0); 694128#L866-2 assume !(0 == ~T1_E~0); 694695#L871-1 assume !(0 == ~T2_E~0); 694696#L876-1 assume !(0 == ~T3_E~0); 695068#L881-1 assume !(0 == ~T4_E~0); 694711#L886-1 assume !(0 == ~T5_E~0); 694427#L891-1 assume !(0 == ~T6_E~0); 694428#L896-1 assume !(0 == ~T7_E~0); 694703#L901-1 assume !(0 == ~T8_E~0); 694731#L906-1 assume !(0 == ~E_M~0); 694732#L911-1 assume !(0 == ~E_1~0); 694480#L916-1 assume !(0 == ~E_2~0); 694481#L921-1 assume !(0 == ~E_3~0); 694856#L926-1 assume !(0 == ~E_4~0); 695008#L931-1 assume !(0 == ~E_5~0); 695079#L936-1 assume !(0 == ~E_6~0); 695091#L941-1 assume !(0 == ~E_7~0); 694486#L946-1 assume !(0 == ~E_8~0); 694487#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 695040#L430 assume !(1 == ~m_pc~0); 694966#L430-2 is_master_triggered_~__retres1~0#1 := 0; 693948#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 693949#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 694618#L1073 assume !(0 != activate_threads_~tmp~1#1); 694619#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 694830#L449 assume !(1 == ~t1_pc~0); 694132#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 694133#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 693978#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 693979#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 694748#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 694552#L468 assume !(1 == ~t2_pc~0); 693934#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 693933#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 694335#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 694330#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 693950#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 693951#L487 assume !(1 == ~t3_pc~0); 694061#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 694035#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 693930#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 693931#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 694406#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 694407#L506 assume !(1 == ~t4_pc~0); 694542#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 694601#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 694021#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 694022#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 694537#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 694341#L525 assume !(1 == ~t5_pc~0); 693985#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 693986#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 694921#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 694922#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 694190#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 694191#L544 assume !(1 == ~t6_pc~0); 694342#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 694343#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 694314#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 693968#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 693969#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 694979#L563 assume !(1 == ~t7_pc~0); 694762#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 693990#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 693991#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 694434#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 694136#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 694137#L582 assume !(1 == ~t8_pc~0); 694766#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 695063#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 694839#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 694395#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 694276#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 694277#L964 assume !(1 == ~M_E~0); 694834#L964-2 assume !(1 == ~T1_E~0); 694192#L969-1 assume !(1 == ~T2_E~0); 694193#L974-1 assume !(1 == ~T3_E~0); 694884#L979-1 assume !(1 == ~T4_E~0); 694885#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 694348#L989-1 assume !(1 == ~T6_E~0); 694349#L994-1 assume !(1 == ~T7_E~0); 694230#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 694231#L1004-1 assume !(1 == ~E_M~0); 693971#L1009-1 assume !(1 == ~E_1~0); 693972#L1014-1 assume !(1 == ~E_2~0); 694818#L1019-1 assume !(1 == ~E_3~0); 694819#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 695047#L1029-1 assume !(1 == ~E_5~0); 694243#L1034-1 assume !(1 == ~E_6~0); 694244#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 695033#L1044-1 assume !(1 == ~E_8~0); 695034#L1049-1 assume { :end_inline_reset_delta_events } true; 728053#L1315-2 [2023-11-19 07:59:28,327 INFO L750 eck$LassoCheckResult]: Loop: 728053#L1315-2 assume !false; 816542#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 816541#L841-1 assume !false; 816540#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 816535#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 816530#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 816529#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 816527#L724 assume !(0 != eval_~tmp~0#1); 816528#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 816953#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 816952#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 816951#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 816950#L871-3 assume !(0 == ~T2_E~0); 816949#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 816948#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 816947#L886-3 assume !(0 == ~T5_E~0); 816946#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 816945#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 816944#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 816943#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 816942#L911-3 assume !(0 == ~E_1~0); 816941#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 816940#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 816939#L926-3 assume !(0 == ~E_4~0); 816938#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 816937#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 816936#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 816935#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 816934#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 816933#L430-30 assume !(1 == ~m_pc~0); 816932#L430-32 is_master_triggered_~__retres1~0#1 := 0; 816931#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 816930#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 816929#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 816928#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 816927#L449-30 assume !(1 == ~t1_pc~0); 816926#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 816925#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 816924#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 816923#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 816922#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 816921#L468-30 assume !(1 == ~t2_pc~0); 816920#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 816918#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 816917#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 816916#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 816915#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 816914#L487-30 assume !(1 == ~t3_pc~0); 816913#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 816912#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 816911#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 816910#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 816909#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 816908#L506-30 assume !(1 == ~t4_pc~0); 816906#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 816905#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 816904#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 816903#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 816902#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 816901#L525-30 assume !(1 == ~t5_pc~0); 816900#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 816899#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 816898#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 816897#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 816896#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 816895#L544-30 assume !(1 == ~t6_pc~0); 816893#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 816892#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 816891#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 816890#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 816889#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 816888#L563-30 assume !(1 == ~t7_pc~0); 816887#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 816886#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 816885#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 816884#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 816883#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 816882#L582-30 assume !(1 == ~t8_pc~0); 816881#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 816880#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 816879#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 816878#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 816877#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 816876#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 755546#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 816875#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 816874#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 816873#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 816872#L984-3 assume !(1 == ~T5_E~0); 760043#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 816871#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 816870#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 816869#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 816868#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 816867#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 816866#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 816865#L1024-3 assume !(1 == ~E_4~0); 815760#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 816864#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 816863#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 816862#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 816861#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 816860#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 816851#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 816850#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 816773#L1334 assume !(0 == start_simulation_~tmp~3#1); 816772#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 816769#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 816762#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 816761#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 816760#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 816759#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 816758#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 816757#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 728053#L1315-2 [2023-11-19 07:59:28,327 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:28,328 INFO L85 PathProgramCache]: Analyzing trace with hash 1284551433, now seen corresponding path program 1 times [2023-11-19 07:59:28,328 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:28,328 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1964450657] [2023-11-19 07:59:28,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:28,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:28,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:28,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:28,423 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:28,424 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1964450657] [2023-11-19 07:59:28,424 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1964450657] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:28,424 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:28,424 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:28,424 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1152176837] [2023-11-19 07:59:28,425 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:28,425 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:28,426 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:28,426 INFO L85 PathProgramCache]: Analyzing trace with hash 358051020, now seen corresponding path program 1 times [2023-11-19 07:59:28,426 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:28,426 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1956907750] [2023-11-19 07:59:28,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:28,427 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:28,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:28,502 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:28,503 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:28,503 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1956907750] [2023-11-19 07:59:28,503 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1956907750] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:28,503 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:28,504 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:59:28,504 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1949373184] [2023-11-19 07:59:28,504 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:28,505 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:28,505 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:28,505 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:59:28,505 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:59:28,506 INFO L87 Difference]: Start difference. First operand 236021 states and 332738 transitions. cyclomatic complexity: 96845 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:30,109 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:30,109 INFO L93 Difference]: Finished difference Result 180328 states and 253602 transitions. [2023-11-19 07:59:30,109 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 180328 states and 253602 transitions. [2023-11-19 07:59:30,792 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 179146 [2023-11-19 07:59:32,121 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 180328 states to 180328 states and 253602 transitions. [2023-11-19 07:59:32,121 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 180328 [2023-11-19 07:59:32,235 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 180328 [2023-11-19 07:59:32,235 INFO L73 IsDeterministic]: Start isDeterministic. Operand 180328 states and 253602 transitions. [2023-11-19 07:59:32,304 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:32,304 INFO L218 hiAutomatonCegarLoop]: Abstraction has 180328 states and 253602 transitions. [2023-11-19 07:59:32,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 180328 states and 253602 transitions. [2023-11-19 07:59:33,941 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 180328 to 124661. [2023-11-19 07:59:34,013 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 124661 states, 124661 states have (on average 1.4068794570876215) internal successors, (175383), 124660 states have internal predecessors, (175383), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:34,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124661 states to 124661 states and 175383 transitions. [2023-11-19 07:59:34,253 INFO L240 hiAutomatonCegarLoop]: Abstraction has 124661 states and 175383 transitions. [2023-11-19 07:59:34,254 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:59:34,255 INFO L428 stractBuchiCegarLoop]: Abstraction has 124661 states and 175383 transitions. [2023-11-19 07:59:34,255 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-19 07:59:34,255 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 124661 states and 175383 transitions. [2023-11-19 07:59:34,579 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 123840 [2023-11-19 07:59:34,579 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:34,579 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:34,581 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:34,581 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:34,582 INFO L748 eck$LassoCheckResult]: Stem: 1110521#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1110522#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1111373#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1111374#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1110848#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 1110849#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1110391#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1110392#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1110483#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1111349#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1110361#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1110362#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1110803#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1110833#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1110490#L866 assume !(0 == ~M_E~0); 1110491#L866-2 assume !(0 == ~T1_E~0); 1111058#L871-1 assume !(0 == ~T2_E~0); 1111059#L876-1 assume !(0 == ~T3_E~0); 1111419#L881-1 assume !(0 == ~T4_E~0); 1111073#L886-1 assume !(0 == ~T5_E~0); 1110789#L891-1 assume !(0 == ~T6_E~0); 1110790#L896-1 assume !(0 == ~T7_E~0); 1111066#L901-1 assume !(0 == ~T8_E~0); 1111092#L906-1 assume !(0 == ~E_M~0); 1111093#L911-1 assume !(0 == ~E_1~0); 1110844#L916-1 assume !(0 == ~E_2~0); 1110845#L921-1 assume !(0 == ~E_3~0); 1111213#L926-1 assume !(0 == ~E_4~0); 1111369#L931-1 assume !(0 == ~E_5~0); 1111427#L936-1 assume !(0 == ~E_6~0); 1111435#L941-1 assume !(0 == ~E_7~0); 1110851#L946-1 assume !(0 == ~E_8~0); 1110852#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1111398#L430 assume !(1 == ~m_pc~0); 1111323#L430-2 is_master_triggered_~__retres1~0#1 := 0; 1110310#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1110311#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1110981#L1073 assume !(0 != activate_threads_~tmp~1#1); 1110982#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1111187#L449 assume !(1 == ~t1_pc~0); 1110495#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1110496#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1110340#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1110341#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 1111108#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1110915#L468 assume !(1 == ~t2_pc~0); 1110296#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1110295#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1110699#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1110695#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 1110312#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1110313#L487 assume !(1 == ~t3_pc~0); 1110423#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1110397#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1110292#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1110293#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 1110769#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1110770#L506 assume !(1 == ~t4_pc~0); 1110905#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1110964#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1110383#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1110384#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 1110901#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1110705#L525 assume !(1 == ~t5_pc~0); 1110347#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1110348#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1111275#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1111276#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 1110553#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1110554#L544 assume !(1 == ~t6_pc~0); 1110706#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1110707#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1110680#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1110330#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 1110331#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1111337#L563 assume !(1 == ~t7_pc~0); 1111119#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1110352#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1110353#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1110796#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 1110499#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1110500#L582 assume !(1 == ~t8_pc~0); 1111123#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1111415#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1111198#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1110757#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 1110639#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1110640#L964 assume !(1 == ~M_E~0); 1111193#L964-2 assume !(1 == ~T1_E~0); 1110555#L969-1 assume !(1 == ~T2_E~0); 1110556#L974-1 assume !(1 == ~T3_E~0); 1111240#L979-1 assume !(1 == ~T4_E~0); 1111241#L984-1 assume !(1 == ~T5_E~0); 1110712#L989-1 assume !(1 == ~T6_E~0); 1110713#L994-1 assume !(1 == ~T7_E~0); 1110592#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1110593#L1004-1 assume !(1 == ~E_M~0); 1110333#L1009-1 assume !(1 == ~E_1~0); 1110334#L1014-1 assume !(1 == ~E_2~0); 1110578#L1019-1 assume !(1 == ~E_3~0); 1111176#L1024-1 assume !(1 == ~E_4~0); 1110518#L1029-1 assume !(1 == ~E_5~0); 1110519#L1034-1 assume !(1 == ~E_6~0); 1110606#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1111389#L1044-1 assume !(1 == ~E_8~0); 1110813#L1049-1 assume { :end_inline_reset_delta_events } true; 1110814#L1315-2 [2023-11-19 07:59:34,582 INFO L750 eck$LassoCheckResult]: Loop: 1110814#L1315-2 assume !false; 1182784#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1182783#L841-1 assume !false; 1182782#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1181893#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1181887#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1181885#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1181882#L724 assume !(0 != eval_~tmp~0#1); 1181883#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1200752#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1200750#L866-3 assume !(0 == ~M_E~0); 1200747#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1200745#L871-3 assume !(0 == ~T2_E~0); 1200743#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1200741#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1200739#L886-3 assume !(0 == ~T5_E~0); 1200737#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1200736#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1200734#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1200732#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1200730#L911-3 assume !(0 == ~E_1~0); 1200728#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1200726#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1200724#L926-3 assume !(0 == ~E_4~0); 1200722#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1200720#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1200718#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1200716#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1200714#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1200712#L430-30 assume !(1 == ~m_pc~0); 1200710#L430-32 is_master_triggered_~__retres1~0#1 := 0; 1200708#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1200706#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1200704#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 1200702#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1200700#L449-30 assume !(1 == ~t1_pc~0); 1200698#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1200696#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1200694#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1200692#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1200690#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1200688#L468-30 assume !(1 == ~t2_pc~0); 1200686#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1200683#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1200681#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1200679#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 1200677#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1200667#L487-30 assume !(1 == ~t3_pc~0); 1200665#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1200663#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1200662#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1200660#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1200657#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1200655#L506-30 assume !(1 == ~t4_pc~0); 1200652#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1200650#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1200648#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1200646#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1200644#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1200642#L525-30 assume !(1 == ~t5_pc~0); 1200640#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1200638#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1200636#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1200634#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1200631#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1200629#L544-30 assume !(1 == ~t6_pc~0); 1200626#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1200624#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1200622#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1200620#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1200618#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1200616#L563-30 assume !(1 == ~t7_pc~0); 1200614#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1200612#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1200610#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1200608#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1200606#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1200604#L582-30 assume !(1 == ~t8_pc~0); 1200602#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1200600#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1200598#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1200596#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1200594#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1200592#L964-3 assume !(1 == ~M_E~0); 1200590#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1200588#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1200586#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1200584#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1200583#L984-3 assume !(1 == ~T5_E~0); 1200582#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1200581#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1200580#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1200579#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1200578#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1200577#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1200576#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1200575#L1024-3 assume !(1 == ~E_4~0); 1200573#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1200570#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1200567#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1200564#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1200561#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1200558#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1200547#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1200545#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1122926#L1334 assume !(0 == start_simulation_~tmp~3#1); 1122927#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1182814#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1182806#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1182804#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1182802#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1182800#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1182798#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1182796#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 1110814#L1315-2 [2023-11-19 07:59:34,583 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:34,583 INFO L85 PathProgramCache]: Analyzing trace with hash 330692485, now seen corresponding path program 1 times [2023-11-19 07:59:34,583 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:34,583 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1746099816] [2023-11-19 07:59:34,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:34,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:34,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:34,652 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:34,652 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:34,653 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1746099816] [2023-11-19 07:59:34,653 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1746099816] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:34,653 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:34,653 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:34,653 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [576099760] [2023-11-19 07:59:34,653 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:34,654 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:34,654 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:34,654 INFO L85 PathProgramCache]: Analyzing trace with hash -1846022388, now seen corresponding path program 1 times [2023-11-19 07:59:34,655 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:34,655 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1275066521] [2023-11-19 07:59:34,655 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:34,655 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:34,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:34,717 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:34,717 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:34,718 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1275066521] [2023-11-19 07:59:34,718 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1275066521] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:34,718 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:34,718 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:59:34,718 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1518818019] [2023-11-19 07:59:34,718 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:34,719 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:34,719 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:34,719 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:59:34,720 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:59:34,720 INFO L87 Difference]: Start difference. First operand 124661 states and 175383 transitions. cyclomatic complexity: 50786 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:36,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:36,264 INFO L93 Difference]: Finished difference Result 199797 states and 280844 transitions. [2023-11-19 07:59:36,264 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 199797 states and 280844 transitions. [2023-11-19 07:59:37,251 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 198534 [2023-11-19 07:59:37,794 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 199797 states to 199797 states and 280844 transitions. [2023-11-19 07:59:37,794 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 199797 [2023-11-19 07:59:37,909 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 199797 [2023-11-19 07:59:37,909 INFO L73 IsDeterministic]: Start isDeterministic. Operand 199797 states and 280844 transitions. [2023-11-19 07:59:38,861 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:38,861 INFO L218 hiAutomatonCegarLoop]: Abstraction has 199797 states and 280844 transitions. [2023-11-19 07:59:39,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 199797 states and 280844 transitions. [2023-11-19 07:59:39,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 199797 to 141841. [2023-11-19 07:59:40,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 141841 states, 141841 states have (on average 1.4078792450701842) internal successors, (199695), 141840 states have internal predecessors, (199695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)