./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.09.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 9bd2c7ff Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d3bf88c9-0ed5-4ed9-b9ee-2eaaec6ba036/bin/uautomizer-verify-uCwYo4JHxu/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d3bf88c9-0ed5-4ed9-b9ee-2eaaec6ba036/bin/uautomizer-verify-uCwYo4JHxu/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d3bf88c9-0ed5-4ed9-b9ee-2eaaec6ba036/bin/uautomizer-verify-uCwYo4JHxu/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d3bf88c9-0ed5-4ed9-b9ee-2eaaec6ba036/bin/uautomizer-verify-uCwYo4JHxu/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.09.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d3bf88c9-0ed5-4ed9-b9ee-2eaaec6ba036/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d3bf88c9-0ed5-4ed9-b9ee-2eaaec6ba036/bin/uautomizer-verify-uCwYo4JHxu --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 834ccc2d6e5ce947bfece9c1e11f57131346eaac8927553a9495d7568350ac6e --- Real Ultimate output --- This is Ultimate 0.2.3-dev-9bd2c7f [2023-11-19 07:59:04,919 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-19 07:59:05,052 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d3bf88c9-0ed5-4ed9-b9ee-2eaaec6ba036/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-19 07:59:05,061 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-19 07:59:05,062 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-19 07:59:05,100 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-19 07:59:05,104 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-19 07:59:05,105 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-19 07:59:05,106 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-19 07:59:05,112 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-19 07:59:05,114 INFO L153 SettingsManager]: * Use SBE=true [2023-11-19 07:59:05,115 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-19 07:59:05,115 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-19 07:59:05,118 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-19 07:59:05,118 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-19 07:59:05,119 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-19 07:59:05,119 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-19 07:59:05,120 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-19 07:59:05,121 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-19 07:59:05,123 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-19 07:59:05,124 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-19 07:59:05,125 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-19 07:59:05,125 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-19 07:59:05,126 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-19 07:59:05,127 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-19 07:59:05,127 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-19 07:59:05,128 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-19 07:59:05,128 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-19 07:59:05,129 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-19 07:59:05,130 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-19 07:59:05,131 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-19 07:59:05,132 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-19 07:59:05,132 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-19 07:59:05,132 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-19 07:59:05,133 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-19 07:59:05,134 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-19 07:59:05,134 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d3bf88c9-0ed5-4ed9-b9ee-2eaaec6ba036/bin/uautomizer-verify-uCwYo4JHxu/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d3bf88c9-0ed5-4ed9-b9ee-2eaaec6ba036/bin/uautomizer-verify-uCwYo4JHxu Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 834ccc2d6e5ce947bfece9c1e11f57131346eaac8927553a9495d7568350ac6e [2023-11-19 07:59:05,530 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-19 07:59:05,574 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-19 07:59:05,577 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-19 07:59:05,580 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-19 07:59:05,581 INFO L274 PluginConnector]: CDTParser initialized [2023-11-19 07:59:05,583 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d3bf88c9-0ed5-4ed9-b9ee-2eaaec6ba036/bin/uautomizer-verify-uCwYo4JHxu/../../sv-benchmarks/c/systemc/token_ring.09.cil-1.c [2023-11-19 07:59:08,924 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-19 07:59:09,285 INFO L384 CDTParser]: Found 1 translation units. [2023-11-19 07:59:09,289 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d3bf88c9-0ed5-4ed9-b9ee-2eaaec6ba036/sv-benchmarks/c/systemc/token_ring.09.cil-1.c [2023-11-19 07:59:09,312 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d3bf88c9-0ed5-4ed9-b9ee-2eaaec6ba036/bin/uautomizer-verify-uCwYo4JHxu/data/22d9ea84f/11d1b5a73748482eb55a087591118fe6/FLAG38b80abb0 [2023-11-19 07:59:09,332 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d3bf88c9-0ed5-4ed9-b9ee-2eaaec6ba036/bin/uautomizer-verify-uCwYo4JHxu/data/22d9ea84f/11d1b5a73748482eb55a087591118fe6 [2023-11-19 07:59:09,340 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-19 07:59:09,344 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-19 07:59:09,349 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-19 07:59:09,350 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-19 07:59:09,357 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-19 07:59:09,358 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:59:09" (1/1) ... [2023-11-19 07:59:09,359 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5b4a9530 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:59:09, skipping insertion in model container [2023-11-19 07:59:09,359 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:59:09" (1/1) ... [2023-11-19 07:59:09,432 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-19 07:59:09,848 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:59:09,865 INFO L202 MainTranslator]: Completed pre-run [2023-11-19 07:59:09,963 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:59:10,003 INFO L206 MainTranslator]: Completed translation [2023-11-19 07:59:10,003 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:59:10 WrapperNode [2023-11-19 07:59:10,004 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-19 07:59:10,005 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-19 07:59:10,005 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-19 07:59:10,006 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-19 07:59:10,019 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:59:10" (1/1) ... [2023-11-19 07:59:10,054 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:59:10" (1/1) ... [2023-11-19 07:59:10,171 INFO L138 Inliner]: procedures = 46, calls = 59, calls flagged for inlining = 54, calls inlined = 183, statements flattened = 2778 [2023-11-19 07:59:10,171 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-19 07:59:10,172 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-19 07:59:10,172 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-19 07:59:10,172 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-19 07:59:10,183 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:59:10" (1/1) ... [2023-11-19 07:59:10,184 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:59:10" (1/1) ... [2023-11-19 07:59:10,196 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:59:10" (1/1) ... [2023-11-19 07:59:10,196 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:59:10" (1/1) ... [2023-11-19 07:59:10,245 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:59:10" (1/1) ... [2023-11-19 07:59:10,292 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:59:10" (1/1) ... [2023-11-19 07:59:10,298 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:59:10" (1/1) ... [2023-11-19 07:59:10,318 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:59:10" (1/1) ... [2023-11-19 07:59:10,339 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-19 07:59:10,342 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-19 07:59:10,342 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-19 07:59:10,342 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-19 07:59:10,343 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:59:10" (1/1) ... [2023-11-19 07:59:10,350 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 07:59:10,362 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d3bf88c9-0ed5-4ed9-b9ee-2eaaec6ba036/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:59:10,382 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d3bf88c9-0ed5-4ed9-b9ee-2eaaec6ba036/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 07:59:10,406 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d3bf88c9-0ed5-4ed9-b9ee-2eaaec6ba036/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-19 07:59:10,430 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-19 07:59:10,430 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-19 07:59:10,430 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-19 07:59:10,432 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-19 07:59:10,581 INFO L236 CfgBuilder]: Building ICFG [2023-11-19 07:59:10,583 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-19 07:59:12,644 INFO L277 CfgBuilder]: Performing block encoding [2023-11-19 07:59:12,675 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-19 07:59:12,676 INFO L302 CfgBuilder]: Removed 12 assume(true) statements. [2023-11-19 07:59:12,690 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:59:12 BoogieIcfgContainer [2023-11-19 07:59:12,691 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-19 07:59:12,693 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-19 07:59:12,693 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-19 07:59:12,697 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-19 07:59:12,697 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:59:12,698 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 07:59:09" (1/3) ... [2023-11-19 07:59:12,700 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5523aa72 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:59:12, skipping insertion in model container [2023-11-19 07:59:12,700 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:59:12,700 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:59:10" (2/3) ... [2023-11-19 07:59:12,701 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5523aa72 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:59:12, skipping insertion in model container [2023-11-19 07:59:12,701 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:59:12,701 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:59:12" (3/3) ... [2023-11-19 07:59:12,702 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.09.cil-1.c [2023-11-19 07:59:12,803 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-19 07:59:12,803 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-19 07:59:12,803 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-19 07:59:12,803 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-19 07:59:12,803 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-19 07:59:12,804 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-19 07:59:12,804 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-19 07:59:12,804 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-19 07:59:12,814 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1187 states, 1186 states have (on average 1.5050590219224282) internal successors, (1785), 1186 states have internal predecessors, (1785), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:12,909 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1056 [2023-11-19 07:59:12,909 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:12,909 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:12,935 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:12,936 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:12,936 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-19 07:59:12,940 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1187 states, 1186 states have (on average 1.5050590219224282) internal successors, (1785), 1186 states have internal predecessors, (1785), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:12,958 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1056 [2023-11-19 07:59:12,959 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:12,959 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:12,963 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:12,964 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:13,020 INFO L748 eck$LassoCheckResult]: Stem: 169#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1075#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 887#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1071#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 763#L658true assume !(1 == ~m_i~0);~m_st~0 := 2; 407#L658-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 786#L663-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 726#L668-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 268#L673-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 827#L678-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 633#L683-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1045#L688-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8#L693-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 103#L698-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 336#L703-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1036#L939true assume !(0 == ~M_E~0); 538#L939-2true assume !(0 == ~T1_E~0); 758#L944-1true assume !(0 == ~T2_E~0); 361#L949-1true assume !(0 == ~T3_E~0); 359#L954-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1082#L959-1true assume !(0 == ~T5_E~0); 787#L964-1true assume !(0 == ~T6_E~0); 183#L969-1true assume !(0 == ~T7_E~0); 898#L974-1true assume !(0 == ~T8_E~0); 713#L979-1true assume !(0 == ~T9_E~0); 1108#L984-1true assume !(0 == ~E_M~0); 275#L989-1true assume !(0 == ~E_1~0); 518#L994-1true assume 0 == ~E_2~0;~E_2~0 := 1; 210#L999-1true assume !(0 == ~E_3~0); 676#L1004-1true assume !(0 == ~E_4~0); 37#L1009-1true assume !(0 == ~E_5~0); 206#L1014-1true assume !(0 == ~E_6~0); 639#L1019-1true assume !(0 == ~E_7~0); 952#L1024-1true assume !(0 == ~E_8~0); 166#L1029-1true assume !(0 == ~E_9~0); 213#L1034-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 966#L460true assume 1 == ~m_pc~0; 2#L461true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 603#L471true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 743#is_master_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1040#L1167true assume !(0 != activate_threads_~tmp~1#1); 350#L1167-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 502#L479true assume 1 == ~t1_pc~0; 337#L480true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1054#L490true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 173#L1175true assume !(0 != activate_threads_~tmp___0~0#1); 393#L1175-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 93#L498true assume !(1 == ~t2_pc~0); 648#L498-2true is_transmit2_triggered_~__retres1~2#1 := 0; 335#L509true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 270#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 677#L1183true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 595#L1183-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1131#L517true assume 1 == ~t3_pc~0; 911#L518true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1077#L528true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 192#L1191true assume !(0 != activate_threads_~tmp___2~0#1); 650#L1191-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 828#L536true assume !(1 == ~t4_pc~0); 1110#L536-2true is_transmit4_triggered_~__retres1~4#1 := 0; 776#L547true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 376#L1199true assume !(0 != activate_threads_~tmp___3~0#1); 1100#L1199-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 569#L555true assume 1 == ~t5_pc~0; 1176#L556true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 709#L566true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 746#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 167#L1207true assume !(0 != activate_threads_~tmp___4~0#1); 107#L1207-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 56#L574true assume !(1 == ~t6_pc~0); 641#L574-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1113#L585true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 264#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 672#L1215true assume !(0 != activate_threads_~tmp___5~0#1); 1105#L1215-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 986#L593true assume 1 == ~t7_pc~0; 1152#L594true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 791#L604true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1094#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1093#L1223true assume !(0 != activate_threads_~tmp___6~0#1); 915#L1223-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 273#L612true assume !(1 == ~t8_pc~0); 1034#L612-2true is_transmit8_triggered_~__retres1~8#1 := 0; 901#L623true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 678#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 822#L1231true assume !(0 != activate_threads_~tmp___7~0#1); 450#L1231-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 506#L631true assume 1 == ~t9_pc~0; 461#L632true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52#L642true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 301#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 338#L1239true assume !(0 != activate_threads_~tmp___8~0#1); 1063#L1239-2true havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 653#L1047true assume !(1 == ~M_E~0); 23#L1047-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 444#L1052-1true assume !(1 == ~T2_E~0); 15#L1057-1true assume !(1 == ~T3_E~0); 158#L1062-1true assume !(1 == ~T4_E~0); 788#L1067-1true assume !(1 == ~T5_E~0); 352#L1072-1true assume !(1 == ~T6_E~0); 621#L1077-1true assume !(1 == ~T7_E~0); 100#L1082-1true assume !(1 == ~T8_E~0); 426#L1087-1true assume 1 == ~T9_E~0;~T9_E~0 := 2; 5#L1092-1true assume !(1 == ~E_M~0); 16#L1097-1true assume !(1 == ~E_1~0); 957#L1102-1true assume !(1 == ~E_2~0); 503#L1107-1true assume !(1 == ~E_3~0); 446#L1112-1true assume !(1 == ~E_4~0); 481#L1117-1true assume !(1 == ~E_5~0); 1165#L1122-1true assume !(1 == ~E_6~0); 389#L1127-1true assume 1 == ~E_7~0;~E_7~0 := 2; 216#L1132-1true assume !(1 == ~E_8~0); 960#L1137-1true assume !(1 == ~E_9~0); 156#L1142-1true assume { :end_inline_reset_delta_events } true; 81#L1428-2true [2023-11-19 07:59:13,023 INFO L750 eck$LassoCheckResult]: Loop: 81#L1428-2true assume !false; 443#L1429true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 490#L914-1true assume false; 686#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 413#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 773#L939-3true assume 0 == ~M_E~0;~M_E~0 := 1; 114#L939-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 141#L944-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 4#L949-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 730#L954-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 364#L959-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 40#L964-3true assume !(0 == ~T6_E~0); 261#L969-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 140#L974-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1068#L979-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 421#L984-3true assume 0 == ~E_M~0;~E_M~0 := 1; 1155#L989-3true assume 0 == ~E_1~0;~E_1~0 := 1; 171#L994-3true assume 0 == ~E_2~0;~E_2~0 := 1; 987#L999-3true assume 0 == ~E_3~0;~E_3~0 := 1; 545#L1004-3true assume !(0 == ~E_4~0); 76#L1009-3true assume 0 == ~E_5~0;~E_5~0 := 1; 627#L1014-3true assume 0 == ~E_6~0;~E_6~0 := 1; 408#L1019-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1124#L1024-3true assume 0 == ~E_8~0;~E_8~0 := 1; 396#L1029-3true assume 0 == ~E_9~0;~E_9~0 := 1; 366#L1034-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 936#L460-33true assume 1 == ~m_pc~0; 390#L461-11true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 558#L471-11true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 701#is_master_triggered_returnLabel#12true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7#L1167-33true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 507#L1167-35true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 186#L479-33true assume !(1 == ~t1_pc~0); 717#L479-35true is_transmit1_triggered_~__retres1~1#1 := 0; 168#L490-11true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1062#is_transmit1_triggered_returnLabel#12true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 877#L1175-33true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1007#L1175-35true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 191#L498-33true assume !(1 == ~t2_pc~0); 58#L498-35true is_transmit2_triggered_~__retres1~2#1 := 0; 322#L509-11true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 646#is_transmit2_triggered_returnLabel#12true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 435#L1183-33true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 115#L1183-35true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1016#L517-33true assume !(1 == ~t3_pc~0); 1122#L517-35true is_transmit3_triggered_~__retres1~3#1 := 0; 750#L528-11true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 92#is_transmit3_triggered_returnLabel#12true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 532#L1191-33true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 673#L1191-35true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 241#L536-33true assume !(1 == ~t4_pc~0); 1027#L536-35true is_transmit4_triggered_~__retres1~4#1 := 0; 286#L547-11true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 949#is_transmit4_triggered_returnLabel#12true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 719#L1199-33true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 829#L1199-35true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27#L555-33true assume !(1 == ~t5_pc~0); 813#L555-35true is_transmit5_triggered_~__retres1~5#1 := 0; 476#L566-11true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1012#is_transmit5_triggered_returnLabel#12true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 499#L1207-33true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1049#L1207-35true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14#L574-33true assume 1 == ~t6_pc~0; 733#L575-11true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 857#L585-11true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 345#is_transmit6_triggered_returnLabel#12true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 582#L1215-33true assume !(0 != activate_threads_~tmp___5~0#1); 331#L1215-35true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49#L593-33true assume 1 == ~t7_pc~0; 405#L594-11true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 970#L604-11true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 771#is_transmit7_triggered_returnLabel#12true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 557#L1223-33true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 704#L1223-35true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1130#L612-33true assume 1 == ~t8_pc~0; 934#L613-11true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 863#L623-11true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 484#is_transmit8_triggered_returnLabel#12true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 620#L1231-33true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 98#L1231-35true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1174#L631-33true assume 1 == ~t9_pc~0; 784#L632-11true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 69#L642-11true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 655#is_transmit9_triggered_returnLabel#12true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 205#L1239-33true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 129#L1239-35true havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 219#L1047-3true assume 1 == ~M_E~0;~M_E~0 := 2; 785#L1047-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1183#L1052-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 684#L1057-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1178#L1062-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 73#L1067-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1041#L1072-3true assume !(1 == ~T6_E~0); 296#L1077-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 196#L1082-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 238#L1087-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 440#L1092-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1188#L1097-3true assume 1 == ~E_1~0;~E_1~0 := 2; 388#L1102-3true assume 1 == ~E_2~0;~E_2~0 := 2; 965#L1107-3true assume 1 == ~E_3~0;~E_3~0 := 2; 738#L1112-3true assume !(1 == ~E_4~0); 193#L1117-3true assume 1 == ~E_5~0;~E_5~0 := 2; 748#L1122-3true assume 1 == ~E_6~0;~E_6~0 := 2; 220#L1127-3true assume 1 == ~E_7~0;~E_7~0 := 2; 517#L1132-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1096#L1137-3true assume 1 == ~E_9~0;~E_9~0 := 2; 493#L1142-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 131#L716-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 501#L768-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 239#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 311#L1447true assume !(0 == start_simulation_~tmp~3#1); 712#L1447-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1154#L716-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 742#L768-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 38#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 209#L1402true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 78#L1409true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 429#stop_simulation_returnLabel#1true start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 354#L1460true assume !(0 != start_simulation_~tmp___0~1#1); 81#L1428-2true [2023-11-19 07:59:13,031 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:13,031 INFO L85 PathProgramCache]: Analyzing trace with hash -986421749, now seen corresponding path program 1 times [2023-11-19 07:59:13,046 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:13,052 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [824311335] [2023-11-19 07:59:13,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:13,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:13,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:13,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:13,402 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:13,403 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [824311335] [2023-11-19 07:59:13,404 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [824311335] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:13,404 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:13,404 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:13,406 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1675803591] [2023-11-19 07:59:13,407 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:13,413 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:13,416 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:13,416 INFO L85 PathProgramCache]: Analyzing trace with hash 1305754084, now seen corresponding path program 1 times [2023-11-19 07:59:13,417 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:13,417 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1000586372] [2023-11-19 07:59:13,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:13,417 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:13,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:13,485 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:13,486 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:13,486 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1000586372] [2023-11-19 07:59:13,486 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1000586372] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:13,486 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:13,487 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:59:13,487 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [114013634] [2023-11-19 07:59:13,487 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:13,488 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:13,489 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:13,531 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:59:13,532 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:59:13,537 INFO L87 Difference]: Start difference. First operand has 1187 states, 1186 states have (on average 1.5050590219224282) internal successors, (1785), 1186 states have internal predecessors, (1785), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:13,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:13,644 INFO L93 Difference]: Finished difference Result 1185 states and 1757 transitions. [2023-11-19 07:59:13,645 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1185 states and 1757 transitions. [2023-11-19 07:59:13,661 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-19 07:59:13,678 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1185 states to 1180 states and 1752 transitions. [2023-11-19 07:59:13,679 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2023-11-19 07:59:13,682 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2023-11-19 07:59:13,683 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1752 transitions. [2023-11-19 07:59:13,690 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:13,690 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1752 transitions. [2023-11-19 07:59:13,713 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1752 transitions. [2023-11-19 07:59:13,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2023-11-19 07:59:13,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1180 states, 1180 states have (on average 1.4847457627118643) internal successors, (1752), 1179 states have internal predecessors, (1752), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:13,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1752 transitions. [2023-11-19 07:59:13,779 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1752 transitions. [2023-11-19 07:59:13,784 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:59:13,788 INFO L428 stractBuchiCegarLoop]: Abstraction has 1180 states and 1752 transitions. [2023-11-19 07:59:13,789 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-19 07:59:13,789 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1752 transitions. [2023-11-19 07:59:13,798 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-19 07:59:13,799 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:13,799 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:13,804 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:13,804 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:13,806 INFO L748 eck$LassoCheckResult]: Stem: 2723#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 2724#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3504#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3505#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3439#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 3103#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3104#L663-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3415#L668-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2891#L673-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2892#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3342#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3343#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2395#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2396#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2599#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2993#L939 assume !(0 == ~M_E~0); 3248#L939-2 assume !(0 == ~T1_E~0); 3249#L944-1 assume !(0 == ~T2_E~0); 3031#L949-1 assume !(0 == ~T3_E~0); 3029#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3030#L959-1 assume !(0 == ~T5_E~0); 3451#L964-1 assume !(0 == ~T6_E~0); 2744#L969-1 assume !(0 == ~T7_E~0); 2745#L974-1 assume !(0 == ~T8_E~0); 3400#L979-1 assume !(0 == ~T9_E~0); 3401#L984-1 assume !(0 == ~E_M~0); 2905#L989-1 assume !(0 == ~E_1~0); 2906#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 2795#L999-1 assume !(0 == ~E_3~0); 2796#L1004-1 assume !(0 == ~E_4~0); 2463#L1009-1 assume !(0 == ~E_5~0); 2464#L1014-1 assume !(0 == ~E_6~0); 2792#L1019-1 assume !(0 == ~E_7~0); 3347#L1024-1 assume !(0 == ~E_8~0); 2716#L1029-1 assume !(0 == ~E_9~0); 2717#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2801#L460 assume 1 == ~m_pc~0; 2381#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2382#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3312#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3425#L1167 assume !(0 != activate_threads_~tmp~1#1); 3014#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3015#L479 assume 1 == ~t1_pc~0; 2994#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2995#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2465#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2466#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 2729#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2578#L498 assume !(1 == ~t2_pc~0); 2579#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2992#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2895#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2896#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3302#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3303#L517 assume 1 == ~t3_pc~0; 3512#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3513#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2402#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2403#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 2765#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3354#L536 assume !(1 == ~t4_pc~0); 3059#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3058#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2561#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2562#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 3052#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3282#L555 assume 1 == ~t5_pc~0; 3283#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3348#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3398#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2718#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 2602#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2501#L574 assume !(1 == ~t6_pc~0); 2502#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3158#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2885#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2886#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 3371#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3537#L593 assume 1 == ~t7_pc~0; 3538#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2737#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3454#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3554#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 3516#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2900#L612 assume !(1 == ~t8_pc~0); 2901#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3330#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3374#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3375#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 3160#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3161#L631 assume 1 == ~t9_pc~0; 3174#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2493#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2494#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2945#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 2997#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3355#L1047 assume !(1 == ~M_E~0); 2429#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2430#L1052-1 assume !(1 == ~T2_E~0); 2412#L1057-1 assume !(1 == ~T3_E~0); 2413#L1062-1 assume !(1 == ~T4_E~0); 2702#L1067-1 assume !(1 == ~T5_E~0); 3018#L1072-1 assume !(1 == ~T6_E~0); 3019#L1077-1 assume !(1 == ~T7_E~0); 2593#L1082-1 assume !(1 == ~T8_E~0); 2594#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2391#L1092-1 assume !(1 == ~E_M~0); 2392#L1097-1 assume !(1 == ~E_1~0); 2414#L1102-1 assume !(1 == ~E_2~0); 3218#L1107-1 assume !(1 == ~E_3~0); 3156#L1112-1 assume !(1 == ~E_4~0); 3157#L1117-1 assume !(1 == ~E_5~0); 3192#L1122-1 assume !(1 == ~E_6~0); 3074#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2807#L1132-1 assume !(1 == ~E_8~0); 2808#L1137-1 assume !(1 == ~E_9~0); 2699#L1142-1 assume { :end_inline_reset_delta_events } true; 2552#L1428-2 [2023-11-19 07:59:13,809 INFO L750 eck$LassoCheckResult]: Loop: 2552#L1428-2 assume !false; 2553#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2924#L914-1 assume !false; 3152#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3153#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2400#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2401#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2923#L783 assume !(0 != eval_~tmp~0#1); 3372#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3111#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3112#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2617#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2618#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2387#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2388#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3036#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2467#L964-3 assume !(0 == ~T6_E~0); 2468#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2670#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2671#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3123#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3124#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2725#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2726#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3257#L1004-3 assume !(0 == ~E_4~0); 2544#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2545#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3105#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3106#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3084#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3037#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3038#L460-33 assume 1 == ~m_pc~0; 3075#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3076#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3272#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2393#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2394#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2753#L479-33 assume !(1 == ~t1_pc~0); 2754#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2719#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2720#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3492#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3493#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2763#L498-33 assume !(1 == ~t2_pc~0); 2507#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 2508#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2975#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3146#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2619#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2620#L517-33 assume !(1 == ~t3_pc~0); 3546#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 3431#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2576#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2577#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3242#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2843#L536-33 assume 1 == ~t4_pc~0; 2844#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2921#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2922#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3406#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3407#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2438#L555-33 assume 1 == ~t5_pc~0; 2439#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3184#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3185#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3214#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3215#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2404#L574-33 assume !(1 == ~t6_pc~0); 2405#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 3419#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3006#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3007#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 2985#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2482#L593-33 assume 1 == ~t7_pc~0; 2483#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2949#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3442#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3270#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3271#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3393#L612-33 assume 1 == ~t8_pc~0; 3524#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3485#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3195#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3196#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2587#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2588#L631-33 assume !(1 == ~t9_pc~0); 3221#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 2528#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2529#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2787#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2645#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2646#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2811#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3450#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3379#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3380#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2538#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2539#L1072-3 assume !(1 == ~T6_E~0); 2935#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2771#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2772#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2837#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3151#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3070#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3071#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3420#L1112-3 assume !(1 == ~E_4~0); 2766#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2767#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2812#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2813#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3231#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3209#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2647#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2524#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2838#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2839#L1447 assume !(0 == start_simulation_~tmp~3#1); 2955#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3399#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2678#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2461#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 2462#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2546#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2547#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 3022#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 2552#L1428-2 [2023-11-19 07:59:13,810 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:13,810 INFO L85 PathProgramCache]: Analyzing trace with hash 1581400585, now seen corresponding path program 1 times [2023-11-19 07:59:13,811 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:13,811 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800928928] [2023-11-19 07:59:13,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:13,812 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:13,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:13,908 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:13,908 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:13,909 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1800928928] [2023-11-19 07:59:13,909 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1800928928] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:13,909 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:13,909 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:13,910 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2124571567] [2023-11-19 07:59:13,910 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:13,910 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:13,911 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:13,911 INFO L85 PathProgramCache]: Analyzing trace with hash 1780472913, now seen corresponding path program 1 times [2023-11-19 07:59:13,911 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:13,912 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2113354847] [2023-11-19 07:59:13,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:13,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:14,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:14,194 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:14,195 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:14,195 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2113354847] [2023-11-19 07:59:14,195 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2113354847] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:14,195 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:14,196 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:14,196 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1562996442] [2023-11-19 07:59:14,196 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:14,196 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:14,197 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:14,197 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:59:14,197 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:59:14,198 INFO L87 Difference]: Start difference. First operand 1180 states and 1752 transitions. cyclomatic complexity: 573 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:14,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:14,240 INFO L93 Difference]: Finished difference Result 1180 states and 1751 transitions. [2023-11-19 07:59:14,240 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1751 transitions. [2023-11-19 07:59:14,252 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-19 07:59:14,266 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1751 transitions. [2023-11-19 07:59:14,267 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2023-11-19 07:59:14,269 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2023-11-19 07:59:14,269 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1751 transitions. [2023-11-19 07:59:14,272 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:14,272 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1751 transitions. [2023-11-19 07:59:14,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1751 transitions. [2023-11-19 07:59:14,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2023-11-19 07:59:14,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1180 states, 1180 states have (on average 1.4838983050847459) internal successors, (1751), 1179 states have internal predecessors, (1751), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:14,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1751 transitions. [2023-11-19 07:59:14,310 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1751 transitions. [2023-11-19 07:59:14,312 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:59:14,313 INFO L428 stractBuchiCegarLoop]: Abstraction has 1180 states and 1751 transitions. [2023-11-19 07:59:14,313 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-19 07:59:14,314 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1751 transitions. [2023-11-19 07:59:14,325 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-19 07:59:14,326 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:14,326 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:14,335 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:14,339 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:14,339 INFO L748 eck$LassoCheckResult]: Stem: 5090#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 5091#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 5871#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5872#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5806#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 5470#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5471#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5782#L668-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5258#L673-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5259#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5709#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5710#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4762#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4763#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4966#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5360#L939 assume !(0 == ~M_E~0); 5615#L939-2 assume !(0 == ~T1_E~0); 5616#L944-1 assume !(0 == ~T2_E~0); 5398#L949-1 assume !(0 == ~T3_E~0); 5396#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5397#L959-1 assume !(0 == ~T5_E~0); 5818#L964-1 assume !(0 == ~T6_E~0); 5111#L969-1 assume !(0 == ~T7_E~0); 5112#L974-1 assume !(0 == ~T8_E~0); 5769#L979-1 assume !(0 == ~T9_E~0); 5770#L984-1 assume !(0 == ~E_M~0); 5272#L989-1 assume !(0 == ~E_1~0); 5273#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5162#L999-1 assume !(0 == ~E_3~0); 5163#L1004-1 assume !(0 == ~E_4~0); 4830#L1009-1 assume !(0 == ~E_5~0); 4831#L1014-1 assume !(0 == ~E_6~0); 5159#L1019-1 assume !(0 == ~E_7~0); 5714#L1024-1 assume !(0 == ~E_8~0); 5083#L1029-1 assume !(0 == ~E_9~0); 5084#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5168#L460 assume 1 == ~m_pc~0; 4751#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4752#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5679#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5792#L1167 assume !(0 != activate_threads_~tmp~1#1); 5381#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5382#L479 assume 1 == ~t1_pc~0; 5361#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5362#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4834#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4835#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 5096#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4945#L498 assume !(1 == ~t2_pc~0); 4946#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5359#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5262#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5263#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5669#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5670#L517 assume 1 == ~t3_pc~0; 5879#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5880#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4769#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4770#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 5132#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5721#L536 assume !(1 == ~t4_pc~0); 5426#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5425#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4931#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4932#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 5419#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5649#L555 assume 1 == ~t5_pc~0; 5650#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5715#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5765#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5085#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 4969#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4868#L574 assume !(1 == ~t6_pc~0); 4869#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5525#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5252#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5253#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 5738#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5904#L593 assume 1 == ~t7_pc~0; 5905#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5104#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5821#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5921#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 5883#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5267#L612 assume !(1 == ~t8_pc~0); 5268#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5697#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5741#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5742#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 5527#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5528#L631 assume 1 == ~t9_pc~0; 5541#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4860#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4861#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5312#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 5364#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5722#L1047 assume !(1 == ~M_E~0); 4796#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4797#L1052-1 assume !(1 == ~T2_E~0); 4779#L1057-1 assume !(1 == ~T3_E~0); 4780#L1062-1 assume !(1 == ~T4_E~0); 5069#L1067-1 assume !(1 == ~T5_E~0); 5385#L1072-1 assume !(1 == ~T6_E~0); 5386#L1077-1 assume !(1 == ~T7_E~0); 4960#L1082-1 assume !(1 == ~T8_E~0); 4961#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4758#L1092-1 assume !(1 == ~E_M~0); 4759#L1097-1 assume !(1 == ~E_1~0); 4781#L1102-1 assume !(1 == ~E_2~0); 5585#L1107-1 assume !(1 == ~E_3~0); 5523#L1112-1 assume !(1 == ~E_4~0); 5524#L1117-1 assume !(1 == ~E_5~0); 5560#L1122-1 assume !(1 == ~E_6~0); 5441#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 5174#L1132-1 assume !(1 == ~E_8~0); 5175#L1137-1 assume !(1 == ~E_9~0); 5066#L1142-1 assume { :end_inline_reset_delta_events } true; 4922#L1428-2 [2023-11-19 07:59:14,340 INFO L750 eck$LassoCheckResult]: Loop: 4922#L1428-2 assume !false; 4923#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5291#L914-1 assume !false; 5519#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5520#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4767#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4768#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5290#L783 assume !(0 != eval_~tmp~0#1); 5739#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5479#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5480#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4986#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4987#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4754#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4755#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5403#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4836#L964-3 assume !(0 == ~T6_E~0); 4837#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5037#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5038#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5490#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5491#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5092#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5093#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5624#L1004-3 assume !(0 == ~E_4~0); 4911#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4912#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5472#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5473#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5451#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5407#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5408#L460-33 assume 1 == ~m_pc~0; 5443#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5444#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5639#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4760#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4761#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5120#L479-33 assume !(1 == ~t1_pc~0); 5121#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 5086#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5087#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5859#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5860#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5125#L498-33 assume 1 == ~t2_pc~0; 5126#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4872#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5342#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5513#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4984#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4985#L517-33 assume !(1 == ~t3_pc~0); 5913#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 5798#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4943#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4944#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5609#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5207#L536-33 assume 1 == ~t4_pc~0; 5208#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5288#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5289#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5773#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5774#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4805#L555-33 assume 1 == ~t5_pc~0; 4806#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5551#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5552#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5581#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5582#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4774#L574-33 assume !(1 == ~t6_pc~0); 4775#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 5786#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5373#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5374#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 5352#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4852#L593-33 assume 1 == ~t7_pc~0; 4853#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5317#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5809#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5637#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5638#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5760#L612-33 assume 1 == ~t8_pc~0; 5891#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5852#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5562#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5563#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4954#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4955#L631-33 assume !(1 == ~t9_pc~0); 5588#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 4897#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4898#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5154#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5012#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5013#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5178#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5817#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5746#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5747#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4905#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4906#L1072-3 assume !(1 == ~T6_E~0); 5302#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5138#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5139#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5204#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5518#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5437#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5438#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5787#L1112-3 assume !(1 == ~E_4~0); 5133#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5134#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5179#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5180#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5598#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5576#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5017#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4891#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5205#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 5206#L1447 assume !(0 == start_simulation_~tmp~3#1); 5322#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5766#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5045#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4828#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 4829#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4913#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4914#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 5389#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 4922#L1428-2 [2023-11-19 07:59:14,341 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:14,341 INFO L85 PathProgramCache]: Analyzing trace with hash -1066203769, now seen corresponding path program 1 times [2023-11-19 07:59:14,341 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:14,341 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1012397187] [2023-11-19 07:59:14,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:14,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:14,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:14,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:14,464 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:14,464 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1012397187] [2023-11-19 07:59:14,464 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1012397187] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:14,464 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:14,464 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:14,465 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1502773053] [2023-11-19 07:59:14,465 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:14,465 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:14,466 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:14,466 INFO L85 PathProgramCache]: Analyzing trace with hash 320478992, now seen corresponding path program 1 times [2023-11-19 07:59:14,466 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:14,466 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1917638897] [2023-11-19 07:59:14,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:14,467 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:14,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:14,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:14,541 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:14,541 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1917638897] [2023-11-19 07:59:14,542 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1917638897] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:14,542 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:14,542 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:14,542 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [802533999] [2023-11-19 07:59:14,543 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:14,543 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:14,543 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:14,544 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:59:14,544 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:59:14,544 INFO L87 Difference]: Start difference. First operand 1180 states and 1751 transitions. cyclomatic complexity: 572 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:14,580 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:14,580 INFO L93 Difference]: Finished difference Result 1180 states and 1750 transitions. [2023-11-19 07:59:14,580 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1750 transitions. [2023-11-19 07:59:14,593 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-19 07:59:14,635 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1750 transitions. [2023-11-19 07:59:14,636 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2023-11-19 07:59:14,637 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2023-11-19 07:59:14,637 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1750 transitions. [2023-11-19 07:59:14,640 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:14,640 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1750 transitions. [2023-11-19 07:59:14,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1750 transitions. [2023-11-19 07:59:14,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2023-11-19 07:59:14,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1180 states, 1180 states have (on average 1.4830508474576272) internal successors, (1750), 1179 states have internal predecessors, (1750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:14,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1750 transitions. [2023-11-19 07:59:14,674 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1750 transitions. [2023-11-19 07:59:14,675 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:59:14,677 INFO L428 stractBuchiCegarLoop]: Abstraction has 1180 states and 1750 transitions. [2023-11-19 07:59:14,678 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-19 07:59:14,678 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1750 transitions. [2023-11-19 07:59:14,689 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-19 07:59:14,689 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:14,690 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:14,692 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:14,692 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:14,693 INFO L748 eck$LassoCheckResult]: Stem: 7457#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 7458#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 8238#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8239#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8173#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 7839#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7840#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8149#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7627#L673-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7628#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8076#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8077#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7129#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7130#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7333#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7727#L939 assume !(0 == ~M_E~0); 7982#L939-2 assume !(0 == ~T1_E~0); 7983#L944-1 assume !(0 == ~T2_E~0); 7765#L949-1 assume !(0 == ~T3_E~0); 7763#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7764#L959-1 assume !(0 == ~T5_E~0); 8185#L964-1 assume !(0 == ~T6_E~0); 7478#L969-1 assume !(0 == ~T7_E~0); 7479#L974-1 assume !(0 == ~T8_E~0); 8136#L979-1 assume !(0 == ~T9_E~0); 8137#L984-1 assume !(0 == ~E_M~0); 7641#L989-1 assume !(0 == ~E_1~0); 7642#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7529#L999-1 assume !(0 == ~E_3~0); 7530#L1004-1 assume !(0 == ~E_4~0); 7197#L1009-1 assume !(0 == ~E_5~0); 7198#L1014-1 assume !(0 == ~E_6~0); 7526#L1019-1 assume !(0 == ~E_7~0); 8081#L1024-1 assume !(0 == ~E_8~0); 7450#L1029-1 assume !(0 == ~E_9~0); 7451#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7537#L460 assume 1 == ~m_pc~0; 7118#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7119#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8046#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8160#L1167 assume !(0 != activate_threads_~tmp~1#1); 7748#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7749#L479 assume 1 == ~t1_pc~0; 7728#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7729#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7201#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7202#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 7464#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7312#L498 assume !(1 == ~t2_pc~0); 7313#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7726#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7629#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7630#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8036#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8037#L517 assume 1 == ~t3_pc~0; 8247#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8248#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7136#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7137#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 7499#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8088#L536 assume !(1 == ~t4_pc~0); 7793#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7792#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7298#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7299#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 7786#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8018#L555 assume 1 == ~t5_pc~0; 8019#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8082#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8132#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7454#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 7338#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7235#L574 assume !(1 == ~t6_pc~0); 7236#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7892#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7619#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7620#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 8105#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8271#L593 assume 1 == ~t7_pc~0; 8272#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7471#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8190#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8288#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 8250#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7634#L612 assume !(1 == ~t8_pc~0); 7635#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8064#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8110#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8111#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 7894#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7895#L631 assume 1 == ~t9_pc~0; 7908#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7227#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7228#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7679#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 7731#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8089#L1047 assume !(1 == ~M_E~0); 7165#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7166#L1052-1 assume !(1 == ~T2_E~0); 7146#L1057-1 assume !(1 == ~T3_E~0); 7147#L1062-1 assume !(1 == ~T4_E~0); 7436#L1067-1 assume !(1 == ~T5_E~0); 7752#L1072-1 assume !(1 == ~T6_E~0); 7753#L1077-1 assume !(1 == ~T7_E~0); 7327#L1082-1 assume !(1 == ~T8_E~0); 7328#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7125#L1092-1 assume !(1 == ~E_M~0); 7126#L1097-1 assume !(1 == ~E_1~0); 7148#L1102-1 assume !(1 == ~E_2~0); 7952#L1107-1 assume !(1 == ~E_3~0); 7890#L1112-1 assume !(1 == ~E_4~0); 7891#L1117-1 assume !(1 == ~E_5~0); 7927#L1122-1 assume !(1 == ~E_6~0); 7808#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7541#L1132-1 assume !(1 == ~E_8~0); 7542#L1137-1 assume !(1 == ~E_9~0); 7435#L1142-1 assume { :end_inline_reset_delta_events } true; 7289#L1428-2 [2023-11-19 07:59:14,694 INFO L750 eck$LassoCheckResult]: Loop: 7289#L1428-2 assume !false; 7290#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7657#L914-1 assume !false; 7886#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7887#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7134#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7135#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7658#L783 assume !(0 != eval_~tmp~0#1); 8106#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7846#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7847#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7353#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7354#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7121#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7122#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7770#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7203#L964-3 assume !(0 == ~T6_E~0); 7204#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7404#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7405#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7857#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7858#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7459#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7460#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7991#L1004-3 assume !(0 == ~E_4~0); 7278#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7279#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7837#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7838#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7818#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 7771#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7772#L460-33 assume 1 == ~m_pc~0; 7809#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7810#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8006#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7127#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7128#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7485#L479-33 assume !(1 == ~t1_pc~0); 7486#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 7452#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7453#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8226#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8227#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7495#L498-33 assume 1 == ~t2_pc~0; 7496#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7242#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7709#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7880#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7351#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7352#L517-33 assume !(1 == ~t3_pc~0); 8280#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 8165#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7310#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7311#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7976#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7577#L536-33 assume 1 == ~t4_pc~0; 7578#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7655#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7656#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8140#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8141#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7172#L555-33 assume 1 == ~t5_pc~0; 7173#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7918#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7919#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7948#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7949#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7143#L574-33 assume !(1 == ~t6_pc~0); 7144#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 8153#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7740#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7741#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 7719#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7221#L593-33 assume 1 == ~t7_pc~0; 7222#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7687#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8177#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8004#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8005#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8127#L612-33 assume 1 == ~t8_pc~0; 8258#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8219#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7929#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7930#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7323#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7324#L631-33 assume !(1 == ~t9_pc~0); 7955#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 7264#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7265#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7523#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7379#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7380#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7545#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8184#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8113#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8114#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7272#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7273#L1072-3 assume !(1 == ~T6_E~0); 7669#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7505#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7506#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7571#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7885#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7804#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7805#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8154#L1112-3 assume !(1 == ~E_4~0); 7500#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7501#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7546#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7547#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7965#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7943#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7384#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7261#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7572#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 7573#L1447 assume !(0 == start_simulation_~tmp~3#1); 7689#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 8133#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7412#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7195#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 7196#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7280#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7281#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 7756#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 7289#L1428-2 [2023-11-19 07:59:14,694 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:14,695 INFO L85 PathProgramCache]: Analyzing trace with hash 1065146953, now seen corresponding path program 1 times [2023-11-19 07:59:14,695 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:14,696 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [39855173] [2023-11-19 07:59:14,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:14,696 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:14,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:14,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:14,801 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:14,802 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [39855173] [2023-11-19 07:59:14,803 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [39855173] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:14,803 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:14,803 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:14,804 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1398904977] [2023-11-19 07:59:14,804 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:14,806 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:14,806 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:14,806 INFO L85 PathProgramCache]: Analyzing trace with hash 320478992, now seen corresponding path program 2 times [2023-11-19 07:59:14,807 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:14,812 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1266792709] [2023-11-19 07:59:14,813 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:14,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:14,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:14,933 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:14,934 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:14,934 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1266792709] [2023-11-19 07:59:14,934 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1266792709] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:14,934 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:14,935 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:14,935 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [893675156] [2023-11-19 07:59:14,935 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:14,937 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:14,937 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:14,937 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:59:14,938 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:59:14,938 INFO L87 Difference]: Start difference. First operand 1180 states and 1750 transitions. cyclomatic complexity: 571 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:14,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:14,982 INFO L93 Difference]: Finished difference Result 1180 states and 1749 transitions. [2023-11-19 07:59:14,982 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1749 transitions. [2023-11-19 07:59:14,998 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-19 07:59:15,011 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1749 transitions. [2023-11-19 07:59:15,011 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2023-11-19 07:59:15,013 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2023-11-19 07:59:15,014 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1749 transitions. [2023-11-19 07:59:15,016 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:15,017 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1749 transitions. [2023-11-19 07:59:15,020 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1749 transitions. [2023-11-19 07:59:15,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2023-11-19 07:59:15,044 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1180 states, 1180 states have (on average 1.4822033898305085) internal successors, (1749), 1179 states have internal predecessors, (1749), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:15,050 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1749 transitions. [2023-11-19 07:59:15,051 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1749 transitions. [2023-11-19 07:59:15,051 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:59:15,054 INFO L428 stractBuchiCegarLoop]: Abstraction has 1180 states and 1749 transitions. [2023-11-19 07:59:15,059 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-19 07:59:15,059 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1749 transitions. [2023-11-19 07:59:15,070 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-19 07:59:15,070 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:15,070 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:15,073 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:15,073 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:15,073 INFO L748 eck$LassoCheckResult]: Stem: 9822#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 9823#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 10605#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10606#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10540#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 10204#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10205#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10514#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9992#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9993#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10441#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10442#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9496#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9497#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9700#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10094#L939 assume !(0 == ~M_E~0); 10349#L939-2 assume !(0 == ~T1_E~0); 10350#L944-1 assume !(0 == ~T2_E~0); 10132#L949-1 assume !(0 == ~T3_E~0); 10130#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10131#L959-1 assume !(0 == ~T5_E~0); 10552#L964-1 assume !(0 == ~T6_E~0); 9845#L969-1 assume !(0 == ~T7_E~0); 9846#L974-1 assume !(0 == ~T8_E~0); 10501#L979-1 assume !(0 == ~T9_E~0); 10502#L984-1 assume !(0 == ~E_M~0); 10006#L989-1 assume !(0 == ~E_1~0); 10007#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 9896#L999-1 assume !(0 == ~E_3~0); 9897#L1004-1 assume !(0 == ~E_4~0); 9562#L1009-1 assume !(0 == ~E_5~0); 9563#L1014-1 assume !(0 == ~E_6~0); 9891#L1019-1 assume !(0 == ~E_7~0); 10448#L1024-1 assume !(0 == ~E_8~0); 9817#L1029-1 assume !(0 == ~E_9~0); 9818#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9902#L460 assume 1 == ~m_pc~0; 9482#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9483#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10413#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10526#L1167 assume !(0 != activate_threads_~tmp~1#1); 10115#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10116#L479 assume 1 == ~t1_pc~0; 10095#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10096#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9566#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9567#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 9830#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9679#L498 assume !(1 == ~t2_pc~0); 9680#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10093#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9996#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9997#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10403#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10404#L517 assume 1 == ~t3_pc~0; 10611#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10612#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9503#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9504#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 9866#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10453#L536 assume !(1 == ~t4_pc~0); 10160#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10159#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9660#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9661#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 10153#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10381#L555 assume 1 == ~t5_pc~0; 10382#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10449#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10499#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9819#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 9703#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9602#L574 assume !(1 == ~t6_pc~0); 9603#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10259#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9986#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9987#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 10470#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10638#L593 assume 1 == ~t7_pc~0; 10639#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9838#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10555#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10655#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 10617#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10001#L612 assume !(1 == ~t8_pc~0); 10002#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10431#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10475#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10476#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 10261#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10262#L631 assume 1 == ~t9_pc~0; 10275#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9594#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9595#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10046#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 10098#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10456#L1047 assume !(1 == ~M_E~0); 9530#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9531#L1052-1 assume !(1 == ~T2_E~0); 9513#L1057-1 assume !(1 == ~T3_E~0); 9514#L1062-1 assume !(1 == ~T4_E~0); 9803#L1067-1 assume !(1 == ~T5_E~0); 10119#L1072-1 assume !(1 == ~T6_E~0); 10120#L1077-1 assume !(1 == ~T7_E~0); 9694#L1082-1 assume !(1 == ~T8_E~0); 9695#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9490#L1092-1 assume !(1 == ~E_M~0); 9491#L1097-1 assume !(1 == ~E_1~0); 9515#L1102-1 assume !(1 == ~E_2~0); 10319#L1107-1 assume !(1 == ~E_3~0); 10257#L1112-1 assume !(1 == ~E_4~0); 10258#L1117-1 assume !(1 == ~E_5~0); 10293#L1122-1 assume !(1 == ~E_6~0); 10175#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 9906#L1132-1 assume !(1 == ~E_8~0); 9907#L1137-1 assume !(1 == ~E_9~0); 9800#L1142-1 assume { :end_inline_reset_delta_events } true; 9653#L1428-2 [2023-11-19 07:59:15,074 INFO L750 eck$LassoCheckResult]: Loop: 9653#L1428-2 assume !false; 9654#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10025#L914-1 assume !false; 10253#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10254#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9501#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9502#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10024#L783 assume !(0 != eval_~tmp~0#1); 10473#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10212#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10213#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9718#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9719#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9488#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9489#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10136#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9568#L964-3 assume !(0 == ~T6_E~0); 9569#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9771#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9772#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10224#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10225#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9826#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9827#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10358#L1004-3 assume !(0 == ~E_4~0); 9645#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9646#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10206#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10207#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10185#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 10138#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10139#L460-33 assume 1 == ~m_pc~0; 10176#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10177#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10373#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9494#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9495#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9852#L479-33 assume !(1 == ~t1_pc~0); 9853#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 9820#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9821#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10593#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10594#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9864#L498-33 assume !(1 == ~t2_pc~0); 9608#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 9609#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10076#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10247#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9720#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9721#L517-33 assume !(1 == ~t3_pc~0); 10647#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 10532#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9677#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9678#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10343#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9944#L536-33 assume 1 == ~t4_pc~0; 9945#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10022#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10023#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10507#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10508#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9539#L555-33 assume 1 == ~t5_pc~0; 9540#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10285#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10286#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10315#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10316#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9510#L574-33 assume !(1 == ~t6_pc~0); 9511#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 10520#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10107#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10108#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 10086#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9588#L593-33 assume 1 == ~t7_pc~0; 9589#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10054#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10544#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10371#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10372#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10495#L612-33 assume 1 == ~t8_pc~0; 10625#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10586#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10296#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10297#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9690#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9691#L631-33 assume !(1 == ~t9_pc~0); 10322#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 9631#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9632#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9890#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9746#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9747#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9912#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10551#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10480#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10481#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9639#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9640#L1072-3 assume !(1 == ~T6_E~0); 10036#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9872#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9873#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9938#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10252#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10173#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10174#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10521#L1112-3 assume !(1 == ~E_4~0); 9867#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9868#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9913#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9914#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10332#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10310#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9751#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9628#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9939#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 9940#L1447 assume !(0 == start_simulation_~tmp~3#1); 10056#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10500#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9779#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9564#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 9565#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9647#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9648#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 10123#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 9653#L1428-2 [2023-11-19 07:59:15,075 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:15,077 INFO L85 PathProgramCache]: Analyzing trace with hash 2103731527, now seen corresponding path program 1 times [2023-11-19 07:59:15,077 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:15,078 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1094695765] [2023-11-19 07:59:15,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:15,078 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:15,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:15,152 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:15,152 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:15,153 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1094695765] [2023-11-19 07:59:15,153 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1094695765] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:15,153 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:15,153 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:15,153 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1235931952] [2023-11-19 07:59:15,153 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:15,154 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:15,154 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:15,154 INFO L85 PathProgramCache]: Analyzing trace with hash 1780472913, now seen corresponding path program 2 times [2023-11-19 07:59:15,155 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:15,155 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1008510321] [2023-11-19 07:59:15,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:15,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:15,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:15,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:15,238 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:15,238 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1008510321] [2023-11-19 07:59:15,238 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1008510321] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:15,239 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:15,239 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:15,239 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [209480068] [2023-11-19 07:59:15,239 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:15,240 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:15,240 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:15,240 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:59:15,240 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:59:15,241 INFO L87 Difference]: Start difference. First operand 1180 states and 1749 transitions. cyclomatic complexity: 570 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:15,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:15,295 INFO L93 Difference]: Finished difference Result 1180 states and 1748 transitions. [2023-11-19 07:59:15,296 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1748 transitions. [2023-11-19 07:59:15,308 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-19 07:59:15,320 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1748 transitions. [2023-11-19 07:59:15,320 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2023-11-19 07:59:15,322 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2023-11-19 07:59:15,322 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1748 transitions. [2023-11-19 07:59:15,324 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:15,325 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1748 transitions. [2023-11-19 07:59:15,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1748 transitions. [2023-11-19 07:59:15,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2023-11-19 07:59:15,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1180 states, 1180 states have (on average 1.4813559322033898) internal successors, (1748), 1179 states have internal predecessors, (1748), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:15,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1748 transitions. [2023-11-19 07:59:15,356 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1748 transitions. [2023-11-19 07:59:15,356 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:59:15,359 INFO L428 stractBuchiCegarLoop]: Abstraction has 1180 states and 1748 transitions. [2023-11-19 07:59:15,359 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-19 07:59:15,359 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1748 transitions. [2023-11-19 07:59:15,368 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-19 07:59:15,368 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:15,369 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:15,371 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:15,371 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:15,371 INFO L748 eck$LassoCheckResult]: Stem: 12189#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 12190#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 12972#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12973#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12907#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 12571#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12572#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12881#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12359#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12360#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12808#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12809#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11863#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11864#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12067#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12461#L939 assume !(0 == ~M_E~0); 12716#L939-2 assume !(0 == ~T1_E~0); 12717#L944-1 assume !(0 == ~T2_E~0); 12499#L949-1 assume !(0 == ~T3_E~0); 12497#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12498#L959-1 assume !(0 == ~T5_E~0); 12919#L964-1 assume !(0 == ~T6_E~0); 12212#L969-1 assume !(0 == ~T7_E~0); 12213#L974-1 assume !(0 == ~T8_E~0); 12868#L979-1 assume !(0 == ~T9_E~0); 12869#L984-1 assume !(0 == ~E_M~0); 12373#L989-1 assume !(0 == ~E_1~0); 12374#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 12263#L999-1 assume !(0 == ~E_3~0); 12264#L1004-1 assume !(0 == ~E_4~0); 11929#L1009-1 assume !(0 == ~E_5~0); 11930#L1014-1 assume !(0 == ~E_6~0); 12258#L1019-1 assume !(0 == ~E_7~0); 12815#L1024-1 assume !(0 == ~E_8~0); 12184#L1029-1 assume !(0 == ~E_9~0); 12185#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12269#L460 assume 1 == ~m_pc~0; 11849#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11850#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12780#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12893#L1167 assume !(0 != activate_threads_~tmp~1#1); 12482#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12483#L479 assume 1 == ~t1_pc~0; 12462#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12463#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11933#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11934#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 12197#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12046#L498 assume !(1 == ~t2_pc~0); 12047#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12460#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12363#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12364#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12770#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12771#L517 assume 1 == ~t3_pc~0; 12978#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12979#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11870#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11871#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 12233#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12820#L536 assume !(1 == ~t4_pc~0); 12527#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12526#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12027#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12028#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 12520#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12748#L555 assume 1 == ~t5_pc~0; 12749#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12816#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12866#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12186#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 12070#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11969#L574 assume !(1 == ~t6_pc~0); 11970#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12626#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12353#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12354#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 12837#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13005#L593 assume 1 == ~t7_pc~0; 13006#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12205#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12922#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13022#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 12984#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12368#L612 assume !(1 == ~t8_pc~0); 12369#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12798#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12842#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12843#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 12628#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12629#L631 assume 1 == ~t9_pc~0; 12642#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11961#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11962#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12413#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 12465#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12823#L1047 assume !(1 == ~M_E~0); 11897#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11898#L1052-1 assume !(1 == ~T2_E~0); 11880#L1057-1 assume !(1 == ~T3_E~0); 11881#L1062-1 assume !(1 == ~T4_E~0); 12170#L1067-1 assume !(1 == ~T5_E~0); 12486#L1072-1 assume !(1 == ~T6_E~0); 12487#L1077-1 assume !(1 == ~T7_E~0); 12061#L1082-1 assume !(1 == ~T8_E~0); 12062#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11857#L1092-1 assume !(1 == ~E_M~0); 11858#L1097-1 assume !(1 == ~E_1~0); 11882#L1102-1 assume !(1 == ~E_2~0); 12686#L1107-1 assume !(1 == ~E_3~0); 12624#L1112-1 assume !(1 == ~E_4~0); 12625#L1117-1 assume !(1 == ~E_5~0); 12660#L1122-1 assume !(1 == ~E_6~0); 12542#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 12273#L1132-1 assume !(1 == ~E_8~0); 12274#L1137-1 assume !(1 == ~E_9~0); 12167#L1142-1 assume { :end_inline_reset_delta_events } true; 12020#L1428-2 [2023-11-19 07:59:15,372 INFO L750 eck$LassoCheckResult]: Loop: 12020#L1428-2 assume !false; 12021#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12392#L914-1 assume !false; 12620#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12621#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11868#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11869#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12391#L783 assume !(0 != eval_~tmp~0#1); 12840#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12579#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12580#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12085#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12086#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11855#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11856#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12503#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11935#L964-3 assume !(0 == ~T6_E~0); 11936#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12138#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12139#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12591#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12592#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12193#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12194#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12725#L1004-3 assume !(0 == ~E_4~0); 12012#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12013#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12573#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12574#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12552#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12505#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12506#L460-33 assume !(1 == ~m_pc~0); 12545#L460-35 is_master_triggered_~__retres1~0#1 := 0; 12544#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12740#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11861#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11862#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12219#L479-33 assume !(1 == ~t1_pc~0); 12220#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 12187#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12188#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12960#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12961#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12231#L498-33 assume !(1 == ~t2_pc~0); 11975#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 11976#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12443#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12614#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12087#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12088#L517-33 assume !(1 == ~t3_pc~0); 13014#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 12899#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12044#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12045#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12710#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12311#L536-33 assume 1 == ~t4_pc~0; 12312#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12389#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12390#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12874#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12875#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11906#L555-33 assume 1 == ~t5_pc~0; 11907#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12652#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12653#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12682#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12683#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11877#L574-33 assume !(1 == ~t6_pc~0); 11878#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 12887#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12474#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12475#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 12453#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11955#L593-33 assume 1 == ~t7_pc~0; 11956#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12421#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12911#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12738#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12739#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12862#L612-33 assume 1 == ~t8_pc~0; 12992#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12953#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12663#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12664#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12057#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12058#L631-33 assume !(1 == ~t9_pc~0); 12689#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 11998#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11999#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12257#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12113#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12114#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12279#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12918#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12847#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12848#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12006#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12007#L1072-3 assume !(1 == ~T6_E~0); 12403#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12239#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12240#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12305#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12619#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12540#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12541#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12888#L1112-3 assume !(1 == ~E_4~0); 12234#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12235#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12280#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12281#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12699#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12677#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12118#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11995#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12306#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 12307#L1447 assume !(0 == start_simulation_~tmp~3#1); 12423#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12867#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12146#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11931#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 11932#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12014#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12015#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 12490#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 12020#L1428-2 [2023-11-19 07:59:15,373 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:15,373 INFO L85 PathProgramCache]: Analyzing trace with hash -218070391, now seen corresponding path program 1 times [2023-11-19 07:59:15,373 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:15,374 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1424376980] [2023-11-19 07:59:15,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:15,374 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:15,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:15,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:15,439 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:15,439 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1424376980] [2023-11-19 07:59:15,439 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1424376980] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:15,439 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:15,440 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:15,440 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1669248946] [2023-11-19 07:59:15,440 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:15,440 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:15,441 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:15,441 INFO L85 PathProgramCache]: Analyzing trace with hash -1397309422, now seen corresponding path program 1 times [2023-11-19 07:59:15,447 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:15,447 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [811719072] [2023-11-19 07:59:15,448 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:15,448 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:15,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:15,532 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:15,532 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:15,533 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [811719072] [2023-11-19 07:59:15,533 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [811719072] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:15,533 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:15,533 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:15,533 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1779798689] [2023-11-19 07:59:15,534 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:15,534 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:15,534 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:15,535 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:59:15,535 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:59:15,535 INFO L87 Difference]: Start difference. First operand 1180 states and 1748 transitions. cyclomatic complexity: 569 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:15,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:15,571 INFO L93 Difference]: Finished difference Result 1180 states and 1747 transitions. [2023-11-19 07:59:15,572 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1747 transitions. [2023-11-19 07:59:15,584 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-19 07:59:15,596 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1747 transitions. [2023-11-19 07:59:15,596 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2023-11-19 07:59:15,598 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2023-11-19 07:59:15,598 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1747 transitions. [2023-11-19 07:59:15,600 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:15,601 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1747 transitions. [2023-11-19 07:59:15,603 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1747 transitions. [2023-11-19 07:59:15,622 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2023-11-19 07:59:15,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1180 states, 1180 states have (on average 1.480508474576271) internal successors, (1747), 1179 states have internal predecessors, (1747), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:15,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1747 transitions. [2023-11-19 07:59:15,631 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1747 transitions. [2023-11-19 07:59:15,632 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:59:15,634 INFO L428 stractBuchiCegarLoop]: Abstraction has 1180 states and 1747 transitions. [2023-11-19 07:59:15,634 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-19 07:59:15,634 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1747 transitions. [2023-11-19 07:59:15,643 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-19 07:59:15,643 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:15,643 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:15,645 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:15,646 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:15,646 INFO L748 eck$LassoCheckResult]: Stem: 14556#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 14557#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 15339#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15340#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15274#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 14938#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14939#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15248#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14726#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14727#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15175#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 15176#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14230#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14231#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14434#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14828#L939 assume !(0 == ~M_E~0); 15083#L939-2 assume !(0 == ~T1_E~0); 15084#L944-1 assume !(0 == ~T2_E~0); 14866#L949-1 assume !(0 == ~T3_E~0); 14864#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14865#L959-1 assume !(0 == ~T5_E~0); 15286#L964-1 assume !(0 == ~T6_E~0); 14579#L969-1 assume !(0 == ~T7_E~0); 14580#L974-1 assume !(0 == ~T8_E~0); 15235#L979-1 assume !(0 == ~T9_E~0); 15236#L984-1 assume !(0 == ~E_M~0); 14740#L989-1 assume !(0 == ~E_1~0); 14741#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 14630#L999-1 assume !(0 == ~E_3~0); 14631#L1004-1 assume !(0 == ~E_4~0); 14296#L1009-1 assume !(0 == ~E_5~0); 14297#L1014-1 assume !(0 == ~E_6~0); 14625#L1019-1 assume !(0 == ~E_7~0); 15182#L1024-1 assume !(0 == ~E_8~0); 14551#L1029-1 assume !(0 == ~E_9~0); 14552#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14636#L460 assume 1 == ~m_pc~0; 14216#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14217#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15147#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15260#L1167 assume !(0 != activate_threads_~tmp~1#1); 14849#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14850#L479 assume 1 == ~t1_pc~0; 14829#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14830#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14300#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14301#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 14564#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14413#L498 assume !(1 == ~t2_pc~0); 14414#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14827#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14730#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14731#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15137#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15138#L517 assume 1 == ~t3_pc~0; 15345#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15346#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14237#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14238#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 14600#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15187#L536 assume !(1 == ~t4_pc~0); 14894#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14893#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14394#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14395#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 14887#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15115#L555 assume 1 == ~t5_pc~0; 15116#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15183#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15233#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14553#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 14437#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14336#L574 assume !(1 == ~t6_pc~0); 14337#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14993#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14720#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14721#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 15204#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15372#L593 assume 1 == ~t7_pc~0; 15373#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14572#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15289#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15389#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 15351#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14735#L612 assume !(1 == ~t8_pc~0); 14736#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 15165#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15209#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15210#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 14995#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14996#L631 assume 1 == ~t9_pc~0; 15009#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14328#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14329#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14780#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 14832#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15190#L1047 assume !(1 == ~M_E~0); 14264#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14265#L1052-1 assume !(1 == ~T2_E~0); 14247#L1057-1 assume !(1 == ~T3_E~0); 14248#L1062-1 assume !(1 == ~T4_E~0); 14537#L1067-1 assume !(1 == ~T5_E~0); 14853#L1072-1 assume !(1 == ~T6_E~0); 14854#L1077-1 assume !(1 == ~T7_E~0); 14428#L1082-1 assume !(1 == ~T8_E~0); 14429#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14224#L1092-1 assume !(1 == ~E_M~0); 14225#L1097-1 assume !(1 == ~E_1~0); 14249#L1102-1 assume !(1 == ~E_2~0); 15053#L1107-1 assume !(1 == ~E_3~0); 14991#L1112-1 assume !(1 == ~E_4~0); 14992#L1117-1 assume !(1 == ~E_5~0); 15027#L1122-1 assume !(1 == ~E_6~0); 14909#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14640#L1132-1 assume !(1 == ~E_8~0); 14641#L1137-1 assume !(1 == ~E_9~0); 14534#L1142-1 assume { :end_inline_reset_delta_events } true; 14387#L1428-2 [2023-11-19 07:59:15,646 INFO L750 eck$LassoCheckResult]: Loop: 14387#L1428-2 assume !false; 14388#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14759#L914-1 assume !false; 14987#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14988#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14235#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14236#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14758#L783 assume !(0 != eval_~tmp~0#1); 15207#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14946#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14947#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14452#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14453#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14222#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14223#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14870#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14302#L964-3 assume !(0 == ~T6_E~0); 14303#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14505#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14506#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14958#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14959#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14560#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14561#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15092#L1004-3 assume !(0 == ~E_4~0); 14379#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14380#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14940#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14941#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14919#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 14872#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14873#L460-33 assume !(1 == ~m_pc~0); 14912#L460-35 is_master_triggered_~__retres1~0#1 := 0; 14911#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15107#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14228#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14229#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14586#L479-33 assume !(1 == ~t1_pc~0); 14587#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 14554#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14555#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15327#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15328#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14598#L498-33 assume !(1 == ~t2_pc~0); 14342#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 14343#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14810#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14981#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14454#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14455#L517-33 assume !(1 == ~t3_pc~0); 15381#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 15266#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14411#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14412#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15077#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14678#L536-33 assume 1 == ~t4_pc~0; 14679#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14756#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14757#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15241#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15242#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14273#L555-33 assume 1 == ~t5_pc~0; 14274#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15019#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15020#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15049#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15050#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14244#L574-33 assume !(1 == ~t6_pc~0); 14245#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 15254#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14841#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14842#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 14820#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14322#L593-33 assume 1 == ~t7_pc~0; 14323#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14788#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15278#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15105#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15106#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15229#L612-33 assume !(1 == ~t8_pc~0); 15360#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 15320#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15030#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15031#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14424#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14425#L631-33 assume !(1 == ~t9_pc~0); 15056#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 14365#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14366#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14624#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14480#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14481#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14646#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15285#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15214#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15215#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14373#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14374#L1072-3 assume !(1 == ~T6_E~0); 14770#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14606#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14607#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14672#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14986#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14907#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14908#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15255#L1112-3 assume !(1 == ~E_4~0); 14601#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14602#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14647#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14648#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15066#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15044#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14485#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14362#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14673#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 14674#L1447 assume !(0 == start_simulation_~tmp~3#1); 14790#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 15234#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14513#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14298#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 14299#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14381#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14382#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 14857#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 14387#L1428-2 [2023-11-19 07:59:15,647 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:15,647 INFO L85 PathProgramCache]: Analyzing trace with hash 1923790087, now seen corresponding path program 1 times [2023-11-19 07:59:15,647 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:15,648 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1194859722] [2023-11-19 07:59:15,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:15,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:15,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:15,701 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:15,701 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:15,701 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1194859722] [2023-11-19 07:59:15,701 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1194859722] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:15,702 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:15,702 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:15,702 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [923459082] [2023-11-19 07:59:15,702 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:15,703 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:15,703 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:15,703 INFO L85 PathProgramCache]: Analyzing trace with hash 2024180179, now seen corresponding path program 1 times [2023-11-19 07:59:15,703 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:15,704 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1292316795] [2023-11-19 07:59:15,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:15,704 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:15,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:15,790 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:15,790 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:15,790 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1292316795] [2023-11-19 07:59:15,790 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1292316795] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:15,790 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:15,791 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:15,791 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1416655852] [2023-11-19 07:59:15,791 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:15,791 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:15,791 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:15,792 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:59:15,792 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:59:15,792 INFO L87 Difference]: Start difference. First operand 1180 states and 1747 transitions. cyclomatic complexity: 568 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:15,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:15,826 INFO L93 Difference]: Finished difference Result 1180 states and 1746 transitions. [2023-11-19 07:59:15,826 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1746 transitions. [2023-11-19 07:59:15,837 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-19 07:59:15,848 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1746 transitions. [2023-11-19 07:59:15,848 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2023-11-19 07:59:15,850 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2023-11-19 07:59:15,850 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1746 transitions. [2023-11-19 07:59:15,852 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:15,852 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1746 transitions. [2023-11-19 07:59:15,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1746 transitions. [2023-11-19 07:59:15,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2023-11-19 07:59:15,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1180 states, 1180 states have (on average 1.4796610169491526) internal successors, (1746), 1179 states have internal predecessors, (1746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:15,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1746 transitions. [2023-11-19 07:59:15,882 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1746 transitions. [2023-11-19 07:59:15,882 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:59:15,885 INFO L428 stractBuchiCegarLoop]: Abstraction has 1180 states and 1746 transitions. [2023-11-19 07:59:15,885 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-19 07:59:15,885 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1746 transitions. [2023-11-19 07:59:15,895 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-19 07:59:15,895 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:15,896 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:15,898 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:15,898 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:15,906 INFO L748 eck$LassoCheckResult]: Stem: 16923#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 16924#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 17706#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17707#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17641#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 17305#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17306#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17617#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17093#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17094#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17544#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17545#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16597#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16598#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16801#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17195#L939 assume !(0 == ~M_E~0); 17450#L939-2 assume !(0 == ~T1_E~0); 17451#L944-1 assume !(0 == ~T2_E~0); 17233#L949-1 assume !(0 == ~T3_E~0); 17231#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17232#L959-1 assume !(0 == ~T5_E~0); 17653#L964-1 assume !(0 == ~T6_E~0); 16946#L969-1 assume !(0 == ~T7_E~0); 16947#L974-1 assume !(0 == ~T8_E~0); 17602#L979-1 assume !(0 == ~T9_E~0); 17603#L984-1 assume !(0 == ~E_M~0); 17107#L989-1 assume !(0 == ~E_1~0); 17108#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 16997#L999-1 assume !(0 == ~E_3~0); 16998#L1004-1 assume !(0 == ~E_4~0); 16665#L1009-1 assume !(0 == ~E_5~0); 16666#L1014-1 assume !(0 == ~E_6~0); 16994#L1019-1 assume !(0 == ~E_7~0); 17549#L1024-1 assume !(0 == ~E_8~0); 16918#L1029-1 assume !(0 == ~E_9~0); 16919#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17003#L460 assume 1 == ~m_pc~0; 16583#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16584#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17514#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17627#L1167 assume !(0 != activate_threads_~tmp~1#1); 17216#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17217#L479 assume 1 == ~t1_pc~0; 17196#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17197#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16667#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16668#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 16931#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16780#L498 assume !(1 == ~t2_pc~0); 16781#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17194#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17097#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17098#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17504#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17505#L517 assume 1 == ~t3_pc~0; 17714#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17715#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16604#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16605#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 16967#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17554#L536 assume !(1 == ~t4_pc~0); 17261#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 17260#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16761#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16762#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 17254#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17484#L555 assume 1 == ~t5_pc~0; 17485#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17550#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17600#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16920#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 16804#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16703#L574 assume !(1 == ~t6_pc~0); 16704#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17360#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17087#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17088#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 17571#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17739#L593 assume 1 == ~t7_pc~0; 17740#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16939#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17656#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17756#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 17718#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17102#L612 assume !(1 == ~t8_pc~0); 17103#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17532#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17576#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17577#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 17362#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17363#L631 assume 1 == ~t9_pc~0; 17376#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16695#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16696#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17147#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 17199#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17557#L1047 assume !(1 == ~M_E~0); 16631#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16632#L1052-1 assume !(1 == ~T2_E~0); 16614#L1057-1 assume !(1 == ~T3_E~0); 16615#L1062-1 assume !(1 == ~T4_E~0); 16904#L1067-1 assume !(1 == ~T5_E~0); 17220#L1072-1 assume !(1 == ~T6_E~0); 17221#L1077-1 assume !(1 == ~T7_E~0); 16795#L1082-1 assume !(1 == ~T8_E~0); 16796#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16591#L1092-1 assume !(1 == ~E_M~0); 16592#L1097-1 assume !(1 == ~E_1~0); 16616#L1102-1 assume !(1 == ~E_2~0); 17420#L1107-1 assume !(1 == ~E_3~0); 17358#L1112-1 assume !(1 == ~E_4~0); 17359#L1117-1 assume !(1 == ~E_5~0); 17394#L1122-1 assume !(1 == ~E_6~0); 17276#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 17007#L1132-1 assume !(1 == ~E_8~0); 17008#L1137-1 assume !(1 == ~E_9~0); 16901#L1142-1 assume { :end_inline_reset_delta_events } true; 16754#L1428-2 [2023-11-19 07:59:15,906 INFO L750 eck$LassoCheckResult]: Loop: 16754#L1428-2 assume !false; 16755#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17126#L914-1 assume !false; 17354#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17355#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16602#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16603#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17125#L783 assume !(0 != eval_~tmp~0#1); 17574#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17313#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17314#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16819#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16820#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16589#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16590#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17237#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16669#L964-3 assume !(0 == ~T6_E~0); 16670#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16872#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16873#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17325#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17326#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16927#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16928#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17459#L1004-3 assume !(0 == ~E_4~0); 16746#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16747#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17307#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17308#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17286#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17239#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17240#L460-33 assume 1 == ~m_pc~0; 17277#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17278#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17474#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16595#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16596#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16955#L479-33 assume !(1 == ~t1_pc~0); 16956#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 16921#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16922#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17694#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17695#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16965#L498-33 assume !(1 == ~t2_pc~0); 16709#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 16710#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17177#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17348#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16821#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16822#L517-33 assume !(1 == ~t3_pc~0); 17748#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 17633#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16778#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16779#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17444#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17045#L536-33 assume 1 == ~t4_pc~0; 17046#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17123#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17124#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17608#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17609#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16640#L555-33 assume 1 == ~t5_pc~0; 16641#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17386#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17387#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17416#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17417#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16611#L574-33 assume !(1 == ~t6_pc~0); 16612#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 17621#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17208#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17209#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 17187#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16689#L593-33 assume 1 == ~t7_pc~0; 16690#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17156#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17644#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17472#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17473#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17595#L612-33 assume 1 == ~t8_pc~0; 17726#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17687#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17397#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17398#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16786#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16787#L631-33 assume 1 == ~t9_pc~0; 17651#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16730#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16731#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16989#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16847#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16848#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17013#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17652#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17581#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17582#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16740#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16741#L1072-3 assume !(1 == ~T6_E~0); 17137#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16973#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16974#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17039#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17353#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17272#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17273#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17622#L1112-3 assume !(1 == ~E_4~0); 16968#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16969#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17014#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17015#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17433#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17411#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16849#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16726#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17040#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 17041#L1447 assume !(0 == start_simulation_~tmp~3#1); 17157#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17601#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16880#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16663#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 16664#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16748#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16749#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 17224#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 16754#L1428-2 [2023-11-19 07:59:15,907 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:15,907 INFO L85 PathProgramCache]: Analyzing trace with hash -1747895607, now seen corresponding path program 1 times [2023-11-19 07:59:15,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:15,907 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1611712636] [2023-11-19 07:59:15,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:15,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:15,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:15,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:15,961 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:15,962 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1611712636] [2023-11-19 07:59:15,963 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1611712636] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:15,963 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:15,963 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:15,963 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [988802406] [2023-11-19 07:59:15,963 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:15,964 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:15,968 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:15,968 INFO L85 PathProgramCache]: Analyzing trace with hash -1557566000, now seen corresponding path program 1 times [2023-11-19 07:59:15,968 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:15,970 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1379303185] [2023-11-19 07:59:15,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:15,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:15,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:16,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:16,032 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:16,032 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1379303185] [2023-11-19 07:59:16,034 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1379303185] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:16,034 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:16,035 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:16,035 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [545959296] [2023-11-19 07:59:16,035 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:16,035 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:16,036 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:16,036 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:59:16,036 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:59:16,037 INFO L87 Difference]: Start difference. First operand 1180 states and 1746 transitions. cyclomatic complexity: 567 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:16,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:16,072 INFO L93 Difference]: Finished difference Result 1180 states and 1745 transitions. [2023-11-19 07:59:16,072 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1745 transitions. [2023-11-19 07:59:16,082 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-19 07:59:16,092 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1745 transitions. [2023-11-19 07:59:16,093 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2023-11-19 07:59:16,094 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2023-11-19 07:59:16,094 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1745 transitions. [2023-11-19 07:59:16,096 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:16,097 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1745 transitions. [2023-11-19 07:59:16,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1745 transitions. [2023-11-19 07:59:16,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2023-11-19 07:59:16,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1180 states, 1180 states have (on average 1.478813559322034) internal successors, (1745), 1179 states have internal predecessors, (1745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:16,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1745 transitions. [2023-11-19 07:59:16,128 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1745 transitions. [2023-11-19 07:59:16,128 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:59:16,130 INFO L428 stractBuchiCegarLoop]: Abstraction has 1180 states and 1745 transitions. [2023-11-19 07:59:16,130 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-19 07:59:16,130 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1745 transitions. [2023-11-19 07:59:16,137 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-19 07:59:16,137 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:16,137 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:16,140 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:16,140 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:16,140 INFO L748 eck$LassoCheckResult]: Stem: 19292#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 19293#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 20073#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20074#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20008#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 19672#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19673#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19984#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19460#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19461#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19911#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19912#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18964#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 18965#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19168#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19562#L939 assume !(0 == ~M_E~0); 19817#L939-2 assume !(0 == ~T1_E~0); 19818#L944-1 assume !(0 == ~T2_E~0); 19600#L949-1 assume !(0 == ~T3_E~0); 19598#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19599#L959-1 assume !(0 == ~T5_E~0); 20020#L964-1 assume !(0 == ~T6_E~0); 19313#L969-1 assume !(0 == ~T7_E~0); 19314#L974-1 assume !(0 == ~T8_E~0); 19971#L979-1 assume !(0 == ~T9_E~0); 19972#L984-1 assume !(0 == ~E_M~0); 19474#L989-1 assume !(0 == ~E_1~0); 19475#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 19364#L999-1 assume !(0 == ~E_3~0); 19365#L1004-1 assume !(0 == ~E_4~0); 19032#L1009-1 assume !(0 == ~E_5~0); 19033#L1014-1 assume !(0 == ~E_6~0); 19361#L1019-1 assume !(0 == ~E_7~0); 19916#L1024-1 assume !(0 == ~E_8~0); 19285#L1029-1 assume !(0 == ~E_9~0); 19286#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19370#L460 assume 1 == ~m_pc~0; 18953#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18954#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19881#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19994#L1167 assume !(0 != activate_threads_~tmp~1#1); 19583#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19584#L479 assume 1 == ~t1_pc~0; 19563#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19564#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19034#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19035#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 19298#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19147#L498 assume !(1 == ~t2_pc~0); 19148#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19561#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19464#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19465#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19871#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19872#L517 assume 1 == ~t3_pc~0; 20081#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20082#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18971#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18972#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 19334#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19923#L536 assume !(1 == ~t4_pc~0); 19628#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19627#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19133#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19134#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 19621#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19851#L555 assume 1 == ~t5_pc~0; 19852#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19917#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19967#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19287#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 19171#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19070#L574 assume !(1 == ~t6_pc~0); 19071#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19727#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19454#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19455#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 19940#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20106#L593 assume 1 == ~t7_pc~0; 20107#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19306#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20023#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20123#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 20085#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19469#L612 assume !(1 == ~t8_pc~0); 19470#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19899#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19943#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19944#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 19729#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19730#L631 assume 1 == ~t9_pc~0; 19743#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19062#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19063#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19514#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 19566#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19924#L1047 assume !(1 == ~M_E~0); 18998#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18999#L1052-1 assume !(1 == ~T2_E~0); 18981#L1057-1 assume !(1 == ~T3_E~0); 18982#L1062-1 assume !(1 == ~T4_E~0); 19271#L1067-1 assume !(1 == ~T5_E~0); 19587#L1072-1 assume !(1 == ~T6_E~0); 19588#L1077-1 assume !(1 == ~T7_E~0); 19162#L1082-1 assume !(1 == ~T8_E~0); 19163#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18960#L1092-1 assume !(1 == ~E_M~0); 18961#L1097-1 assume !(1 == ~E_1~0); 18983#L1102-1 assume !(1 == ~E_2~0); 19787#L1107-1 assume !(1 == ~E_3~0); 19725#L1112-1 assume !(1 == ~E_4~0); 19726#L1117-1 assume !(1 == ~E_5~0); 19761#L1122-1 assume !(1 == ~E_6~0); 19643#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19376#L1132-1 assume !(1 == ~E_8~0); 19377#L1137-1 assume !(1 == ~E_9~0); 19268#L1142-1 assume { :end_inline_reset_delta_events } true; 19121#L1428-2 [2023-11-19 07:59:16,141 INFO L750 eck$LassoCheckResult]: Loop: 19121#L1428-2 assume !false; 19122#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19493#L914-1 assume !false; 19721#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19722#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 18969#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 18970#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19492#L783 assume !(0 != eval_~tmp~0#1); 19941#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19681#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19682#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19186#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19187#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18956#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18957#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19605#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19036#L964-3 assume !(0 == ~T6_E~0); 19037#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19239#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19240#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19692#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19693#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19294#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19295#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19826#L1004-3 assume !(0 == ~E_4~0); 19113#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19114#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19674#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19675#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19653#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19606#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19607#L460-33 assume 1 == ~m_pc~0; 19645#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19646#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19841#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18962#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18963#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19322#L479-33 assume !(1 == ~t1_pc~0); 19323#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 19288#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19289#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20061#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20062#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19332#L498-33 assume !(1 == ~t2_pc~0); 19076#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 19077#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19544#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19715#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19188#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19189#L517-33 assume !(1 == ~t3_pc~0); 20115#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 20000#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19145#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19146#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19811#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19409#L536-33 assume 1 == ~t4_pc~0; 19410#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19490#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19491#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19975#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19976#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19004#L555-33 assume 1 == ~t5_pc~0; 19005#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19753#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19754#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19783#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19784#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18976#L574-33 assume !(1 == ~t6_pc~0); 18977#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 19988#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19575#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19576#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 19554#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19054#L593-33 assume !(1 == ~t7_pc~0); 19056#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 19519#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20011#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19839#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19840#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19962#L612-33 assume 1 == ~t8_pc~0; 20093#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20054#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19764#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19765#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19156#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19157#L631-33 assume 1 == ~t9_pc~0; 20018#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19099#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19100#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19356#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19214#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19215#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19380#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20019#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19948#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19949#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19107#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19108#L1072-3 assume !(1 == ~T6_E~0); 19504#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19340#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19341#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19406#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19720#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19639#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19640#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19989#L1112-3 assume !(1 == ~E_4~0); 19335#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19336#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19381#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19382#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19800#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19778#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19216#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19093#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19407#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 19408#L1447 assume !(0 == start_simulation_~tmp~3#1); 19524#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19968#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19247#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19030#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 19031#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19115#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19116#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 19591#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 19121#L1428-2 [2023-11-19 07:59:16,141 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:16,141 INFO L85 PathProgramCache]: Analyzing trace with hash -1866337081, now seen corresponding path program 1 times [2023-11-19 07:59:16,142 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:16,142 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1940366980] [2023-11-19 07:59:16,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:16,142 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:16,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:16,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:16,249 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:16,250 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1940366980] [2023-11-19 07:59:16,250 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1940366980] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:16,250 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:16,250 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:16,250 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [189789557] [2023-11-19 07:59:16,250 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:16,251 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:16,251 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:16,251 INFO L85 PathProgramCache]: Analyzing trace with hash 636560081, now seen corresponding path program 1 times [2023-11-19 07:59:16,252 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:16,252 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1824905037] [2023-11-19 07:59:16,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:16,252 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:16,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:16,328 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:16,329 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:16,329 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1824905037] [2023-11-19 07:59:16,329 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1824905037] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:16,329 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:16,329 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:16,329 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [901170409] [2023-11-19 07:59:16,329 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:16,330 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:16,330 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:16,330 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:59:16,330 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:59:16,331 INFO L87 Difference]: Start difference. First operand 1180 states and 1745 transitions. cyclomatic complexity: 566 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:16,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:16,572 INFO L93 Difference]: Finished difference Result 2161 states and 3183 transitions. [2023-11-19 07:59:16,572 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2161 states and 3183 transitions. [2023-11-19 07:59:16,586 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2014 [2023-11-19 07:59:16,603 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2161 states to 2161 states and 3183 transitions. [2023-11-19 07:59:16,603 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2161 [2023-11-19 07:59:16,606 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2161 [2023-11-19 07:59:16,606 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2161 states and 3183 transitions. [2023-11-19 07:59:16,610 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:16,610 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2161 states and 3183 transitions. [2023-11-19 07:59:16,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2161 states and 3183 transitions. [2023-11-19 07:59:16,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2161 to 2161. [2023-11-19 07:59:16,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2161 states, 2161 states have (on average 1.4729291994447016) internal successors, (3183), 2160 states have internal predecessors, (3183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:16,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2161 states to 2161 states and 3183 transitions. [2023-11-19 07:59:16,671 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2161 states and 3183 transitions. [2023-11-19 07:59:16,672 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:59:16,673 INFO L428 stractBuchiCegarLoop]: Abstraction has 2161 states and 3183 transitions. [2023-11-19 07:59:16,673 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-19 07:59:16,674 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2161 states and 3183 transitions. [2023-11-19 07:59:16,683 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2014 [2023-11-19 07:59:16,683 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:16,684 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:16,686 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:16,686 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:16,686 INFO L748 eck$LassoCheckResult]: Stem: 22644#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 22645#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 23494#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23495#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23416#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 23036#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23037#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23387#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22819#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22820#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23300#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23301#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22315#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22316#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22519#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22921#L939 assume !(0 == ~M_E~0); 23190#L939-2 assume !(0 == ~T1_E~0); 23191#L944-1 assume !(0 == ~T2_E~0); 22959#L949-1 assume !(0 == ~T3_E~0); 22957#L954-1 assume !(0 == ~T4_E~0); 22958#L959-1 assume !(0 == ~T5_E~0); 23432#L964-1 assume !(0 == ~T6_E~0); 22665#L969-1 assume !(0 == ~T7_E~0); 22666#L974-1 assume !(0 == ~T8_E~0); 23372#L979-1 assume !(0 == ~T9_E~0); 23373#L984-1 assume !(0 == ~E_M~0); 22833#L989-1 assume !(0 == ~E_1~0); 22834#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 22716#L999-1 assume !(0 == ~E_3~0); 22717#L1004-1 assume !(0 == ~E_4~0); 22383#L1009-1 assume !(0 == ~E_5~0); 22384#L1014-1 assume !(0 == ~E_6~0); 22713#L1019-1 assume !(0 == ~E_7~0); 23305#L1024-1 assume !(0 == ~E_8~0); 22637#L1029-1 assume !(0 == ~E_9~0); 22638#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22724#L460 assume 1 == ~m_pc~0; 22304#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22305#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23266#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23400#L1167 assume !(0 != activate_threads_~tmp~1#1); 22942#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22943#L479 assume 1 == ~t1_pc~0; 22922#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22923#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22387#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22388#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 22651#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22498#L498 assume !(1 == ~t2_pc~0); 22499#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 22920#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22821#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22822#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23255#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23256#L517 assume 1 == ~t3_pc~0; 23506#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23507#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22322#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22323#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 22686#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23315#L536 assume !(1 == ~t4_pc~0); 22988#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22987#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22484#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22485#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 22981#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23233#L555 assume 1 == ~t5_pc~0; 23234#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23306#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23368#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22641#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 22524#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22421#L574 assume !(1 == ~t6_pc~0); 22422#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 23089#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22809#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22810#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 23335#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23539#L593 assume 1 == ~t7_pc~0; 23540#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22658#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23437#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23565#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 23510#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22826#L612 assume !(1 == ~t8_pc~0); 22827#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 23285#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23341#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23342#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 23091#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23092#L631 assume 1 == ~t9_pc~0; 23106#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22413#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22414#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22872#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 22925#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23317#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 22351#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22352#L1052-1 assume !(1 == ~T2_E~0); 22332#L1057-1 assume !(1 == ~T3_E~0); 22333#L1062-1 assume !(1 == ~T4_E~0); 22623#L1067-1 assume !(1 == ~T5_E~0); 22946#L1072-1 assume !(1 == ~T6_E~0); 22947#L1077-1 assume !(1 == ~T7_E~0); 22513#L1082-1 assume !(1 == ~T8_E~0); 22514#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22311#L1092-1 assume !(1 == ~E_M~0); 22312#L1097-1 assume !(1 == ~E_1~0); 22334#L1102-1 assume !(1 == ~E_2~0); 23158#L1107-1 assume !(1 == ~E_3~0); 23087#L1112-1 assume !(1 == ~E_4~0); 23088#L1117-1 assume !(1 == ~E_5~0); 23605#L1122-1 assume !(1 == ~E_6~0); 23603#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 23602#L1132-1 assume !(1 == ~E_8~0); 23601#L1137-1 assume !(1 == ~E_9~0); 23600#L1142-1 assume { :end_inline_reset_delta_events } true; 23595#L1428-2 [2023-11-19 07:59:16,687 INFO L750 eck$LassoCheckResult]: Loop: 23595#L1428-2 assume !false; 23592#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23148#L914-1 assume !false; 23083#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23084#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 23581#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 23580#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 23336#L783 assume !(0 != eval_~tmp~0#1); 23337#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23043#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23044#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22539#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22540#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22307#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22308#L954-3 assume !(0 == ~T4_E~0); 22965#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22389#L964-3 assume !(0 == ~T6_E~0); 22390#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22591#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22592#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23054#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23055#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22646#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22647#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23201#L1004-3 assume !(0 == ~E_4~0); 22464#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22465#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23034#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23035#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23015#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22966#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22967#L460-33 assume 1 == ~m_pc~0; 23005#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23006#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23220#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22313#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22314#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22672#L479-33 assume !(1 == ~t1_pc~0); 22673#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 23375#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24388#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24387#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24386#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24385#L498-33 assume !(1 == ~t2_pc~0); 24384#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 24382#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24381#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24380#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24379#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24378#L517-33 assume !(1 == ~t3_pc~0); 24376#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 24375#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24374#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24373#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24372#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24371#L536-33 assume 1 == ~t4_pc~0; 24369#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24368#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24367#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24366#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24365#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24364#L555-33 assume !(1 == ~t5_pc~0); 24362#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 24361#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24360#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24359#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24358#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24357#L574-33 assume 1 == ~t6_pc~0; 24355#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24354#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24353#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24352#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 24351#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24350#L593-33 assume 1 == ~t7_pc~0; 24348#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24347#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24346#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24345#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24344#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24343#L612-33 assume !(1 == ~t8_pc~0); 24341#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 24340#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24339#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24338#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24337#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24336#L631-33 assume 1 == ~t9_pc~0; 24334#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24333#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24332#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24331#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24330#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24329#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22732#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24328#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24327#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24326#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23578#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24325#L1072-3 assume !(1 == ~T6_E~0); 24324#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22692#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22693#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22759#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23082#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23000#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23001#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23394#L1112-3 assume !(1 == ~E_4~0); 22687#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22688#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22734#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22735#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23171#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 23149#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22571#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 22444#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 22761#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 22762#L1447 assume !(0 == start_simulation_~tmp~3#1); 22882#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23369#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 23649#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 23646#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 23644#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23611#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23610#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 23599#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 23595#L1428-2 [2023-11-19 07:59:16,687 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:16,687 INFO L85 PathProgramCache]: Analyzing trace with hash 99525123, now seen corresponding path program 1 times [2023-11-19 07:59:16,688 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:16,688 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1959354487] [2023-11-19 07:59:16,688 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:16,688 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:16,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:16,757 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:16,758 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:16,758 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1959354487] [2023-11-19 07:59:16,758 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1959354487] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:16,758 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:16,758 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:59:16,758 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [53549837] [2023-11-19 07:59:16,759 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:16,760 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:16,760 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:16,761 INFO L85 PathProgramCache]: Analyzing trace with hash 69234191, now seen corresponding path program 1 times [2023-11-19 07:59:16,761 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:16,761 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1109127578] [2023-11-19 07:59:16,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:16,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:16,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:16,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:16,819 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:16,819 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1109127578] [2023-11-19 07:59:16,819 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1109127578] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:16,819 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:16,819 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:16,820 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1577501203] [2023-11-19 07:59:16,820 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:16,820 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:16,820 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:16,821 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:59:16,821 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:59:16,821 INFO L87 Difference]: Start difference. First operand 2161 states and 3183 transitions. cyclomatic complexity: 1024 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:16,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:16,937 INFO L93 Difference]: Finished difference Result 2161 states and 3153 transitions. [2023-11-19 07:59:16,937 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2161 states and 3153 transitions. [2023-11-19 07:59:16,952 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2014 [2023-11-19 07:59:16,970 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2161 states to 2161 states and 3153 transitions. [2023-11-19 07:59:16,970 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2161 [2023-11-19 07:59:16,972 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2161 [2023-11-19 07:59:16,973 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2161 states and 3153 transitions. [2023-11-19 07:59:16,977 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:16,977 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2161 states and 3153 transitions. [2023-11-19 07:59:16,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2161 states and 3153 transitions. [2023-11-19 07:59:17,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2161 to 2161. [2023-11-19 07:59:17,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2161 states, 2161 states have (on average 1.4590467376214715) internal successors, (3153), 2160 states have internal predecessors, (3153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:17,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2161 states to 2161 states and 3153 transitions. [2023-11-19 07:59:17,044 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2161 states and 3153 transitions. [2023-11-19 07:59:17,044 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:59:17,045 INFO L428 stractBuchiCegarLoop]: Abstraction has 2161 states and 3153 transitions. [2023-11-19 07:59:17,045 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-19 07:59:17,046 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2161 states and 3153 transitions. [2023-11-19 07:59:17,057 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2014 [2023-11-19 07:59:17,058 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:17,058 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:17,060 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:17,061 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:17,061 INFO L748 eck$LassoCheckResult]: Stem: 26973#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 26974#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 27800#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27801#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27732#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 27365#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27366#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27705#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27145#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27146#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27624#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27625#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26644#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 26645#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26847#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27249#L939 assume !(0 == ~M_E~0); 27524#L939-2 assume !(0 == ~T1_E~0); 27525#L944-1 assume !(0 == ~T2_E~0); 27287#L949-1 assume !(0 == ~T3_E~0); 27285#L954-1 assume !(0 == ~T4_E~0); 27286#L959-1 assume !(0 == ~T5_E~0); 27746#L964-1 assume !(0 == ~T6_E~0); 26994#L969-1 assume !(0 == ~T7_E~0); 26995#L974-1 assume !(0 == ~T8_E~0); 27691#L979-1 assume !(0 == ~T9_E~0); 27692#L984-1 assume !(0 == ~E_M~0); 27159#L989-1 assume !(0 == ~E_1~0); 27160#L994-1 assume !(0 == ~E_2~0); 27046#L999-1 assume !(0 == ~E_3~0); 27047#L1004-1 assume !(0 == ~E_4~0); 26712#L1009-1 assume !(0 == ~E_5~0); 26713#L1014-1 assume !(0 == ~E_6~0); 27043#L1019-1 assume !(0 == ~E_7~0); 27629#L1024-1 assume !(0 == ~E_8~0); 26966#L1029-1 assume !(0 == ~E_9~0); 26967#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27055#L460 assume 1 == ~m_pc~0; 26633#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26634#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27590#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27718#L1167 assume !(0 != activate_threads_~tmp~1#1); 27270#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27271#L479 assume 1 == ~t1_pc~0; 27250#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27251#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26718#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26719#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 26981#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26826#L498 assume !(1 == ~t2_pc~0); 26827#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27248#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27147#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27148#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27579#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27580#L517 assume 1 == ~t3_pc~0; 27809#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27810#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26651#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26652#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 27015#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27638#L536 assume !(1 == ~t4_pc~0); 27315#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27314#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26812#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26813#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 27309#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27560#L555 assume 1 == ~t5_pc~0; 27561#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27630#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27687#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26970#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 26852#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26750#L574 assume !(1 == ~t6_pc~0); 26751#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27421#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27137#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27138#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 27657#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27839#L593 assume 1 == ~t7_pc~0; 27840#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26987#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27751#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27858#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 27813#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27152#L612 assume !(1 == ~t8_pc~0); 27153#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27610#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27663#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27664#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 27423#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27424#L631 assume 1 == ~t9_pc~0; 27437#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26742#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26743#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27199#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 27253#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27639#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 27640#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28107#L1052-1 assume !(1 == ~T2_E~0); 28106#L1057-1 assume !(1 == ~T3_E~0); 28105#L1062-1 assume !(1 == ~T4_E~0); 26951#L1067-1 assume !(1 == ~T5_E~0); 28104#L1072-1 assume !(1 == ~T6_E~0); 28103#L1077-1 assume !(1 == ~T7_E~0); 28102#L1082-1 assume !(1 == ~T8_E~0); 28101#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28100#L1092-1 assume !(1 == ~E_M~0); 28099#L1097-1 assume !(1 == ~E_1~0); 28098#L1102-1 assume !(1 == ~E_2~0); 28097#L1107-1 assume !(1 == ~E_3~0); 27419#L1112-1 assume !(1 == ~E_4~0); 27420#L1117-1 assume !(1 == ~E_5~0); 27459#L1122-1 assume !(1 == ~E_6~0); 27332#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 27333#L1132-1 assume !(1 == ~E_8~0); 27886#L1137-1 assume !(1 == ~E_9~0); 26948#L1142-1 assume { :end_inline_reset_delta_events } true; 26800#L1428-2 [2023-11-19 07:59:17,062 INFO L750 eck$LassoCheckResult]: Loop: 26800#L1428-2 assume !false; 26801#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27475#L914-1 assume !false; 27476#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27614#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26649#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 26650#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 27658#L783 assume !(0 != eval_~tmp~0#1); 27659#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27371#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27372#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 27869#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28576#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28575#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28574#L954-3 assume !(0 == ~T4_E~0); 28573#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28572#L964-3 assume !(0 == ~T6_E~0); 28571#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28570#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28569#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28568#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28567#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28566#L994-3 assume !(0 == ~E_2~0); 28565#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28564#L1004-3 assume !(0 == ~E_4~0); 28563#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28562#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28561#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28560#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28559#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28558#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28557#L460-33 assume 1 == ~m_pc~0; 28555#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28554#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28553#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28552#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28551#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28550#L479-33 assume !(1 == ~t1_pc~0); 28548#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 28547#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28546#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28545#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28544#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28543#L498-33 assume !(1 == ~t2_pc~0); 28541#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 28540#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28539#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28538#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28537#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28536#L517-33 assume !(1 == ~t3_pc~0); 28534#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 28533#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28532#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28531#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28530#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28529#L536-33 assume !(1 == ~t4_pc~0); 28528#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 28526#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28525#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28524#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28523#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28522#L555-33 assume !(1 == ~t5_pc~0); 28520#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 28519#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28518#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28517#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28516#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28515#L574-33 assume 1 == ~t6_pc~0; 28513#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28512#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28511#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28510#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 28509#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28508#L593-33 assume 1 == ~t7_pc~0; 28506#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28505#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28504#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28503#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28502#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28501#L612-33 assume !(1 == ~t8_pc~0); 28499#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 28498#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28497#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28496#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28495#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28494#L631-33 assume 1 == ~t9_pc~0; 28492#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28491#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28490#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28489#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 26893#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26894#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27062#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27745#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27666#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27667#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26786#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26787#L1072-3 assume !(1 == ~T6_E~0); 27189#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27021#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 27022#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27088#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 27413#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27330#L1102-3 assume !(1 == ~E_2~0); 27331#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27711#L1112-3 assume !(1 == ~E_4~0); 27016#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27017#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27063#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27064#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27506#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27859#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 26898#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26775#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 27089#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 27090#L1447 assume !(0 == start_simulation_~tmp~3#1); 27210#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27688#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26926#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 26710#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 26711#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26794#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26795#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 27278#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 26800#L1428-2 [2023-11-19 07:59:17,063 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:17,063 INFO L85 PathProgramCache]: Analyzing trace with hash 1976588353, now seen corresponding path program 1 times [2023-11-19 07:59:17,063 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:17,063 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2088084220] [2023-11-19 07:59:17,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:17,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:17,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:17,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:17,166 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:17,167 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2088084220] [2023-11-19 07:59:17,167 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2088084220] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:17,167 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:17,167 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:59:17,167 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2117055726] [2023-11-19 07:59:17,167 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:17,168 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:17,168 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:17,168 INFO L85 PathProgramCache]: Analyzing trace with hash -237143792, now seen corresponding path program 1 times [2023-11-19 07:59:17,168 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:17,169 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1670069603] [2023-11-19 07:59:17,169 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:17,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:17,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:17,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:17,261 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:17,261 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1670069603] [2023-11-19 07:59:17,262 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1670069603] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:17,262 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:17,262 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:59:17,262 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [878847381] [2023-11-19 07:59:17,262 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:17,263 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:17,263 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:17,264 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:59:17,264 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:59:17,264 INFO L87 Difference]: Start difference. First operand 2161 states and 3153 transitions. cyclomatic complexity: 994 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:17,392 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:17,392 INFO L93 Difference]: Finished difference Result 4145 states and 5992 transitions. [2023-11-19 07:59:17,392 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4145 states and 5992 transitions. [2023-11-19 07:59:17,417 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3997 [2023-11-19 07:59:17,448 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4145 states to 4145 states and 5992 transitions. [2023-11-19 07:59:17,448 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4145 [2023-11-19 07:59:17,453 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4145 [2023-11-19 07:59:17,453 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4145 states and 5992 transitions. [2023-11-19 07:59:17,460 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:17,461 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4145 states and 5992 transitions. [2023-11-19 07:59:17,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4145 states and 5992 transitions. [2023-11-19 07:59:17,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4145 to 4007. [2023-11-19 07:59:17,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4007 states, 4007 states have (on average 1.4474669328674818) internal successors, (5800), 4006 states have internal predecessors, (5800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:17,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4007 states to 4007 states and 5800 transitions. [2023-11-19 07:59:17,611 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4007 states and 5800 transitions. [2023-11-19 07:59:17,611 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:59:17,612 INFO L428 stractBuchiCegarLoop]: Abstraction has 4007 states and 5800 transitions. [2023-11-19 07:59:17,612 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-19 07:59:17,612 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4007 states and 5800 transitions. [2023-11-19 07:59:17,630 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3859 [2023-11-19 07:59:17,631 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:17,631 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:17,633 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:17,633 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:17,633 INFO L748 eck$LassoCheckResult]: Stem: 33285#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 33286#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 34168#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34169#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34083#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 33682#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33683#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34055#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33459#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33460#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33967#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33968#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32956#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 32957#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33159#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33570#L939 assume !(0 == ~M_E~0); 33840#L939-2 assume !(0 == ~T1_E~0); 33841#L944-1 assume !(0 == ~T2_E~0); 33608#L949-1 assume !(0 == ~T3_E~0); 33606#L954-1 assume !(0 == ~T4_E~0); 33607#L959-1 assume !(0 == ~T5_E~0); 34100#L964-1 assume !(0 == ~T6_E~0); 33308#L969-1 assume !(0 == ~T7_E~0); 33309#L974-1 assume !(0 == ~T8_E~0); 34038#L979-1 assume !(0 == ~T9_E~0); 34039#L984-1 assume !(0 == ~E_M~0); 33473#L989-1 assume !(0 == ~E_1~0); 33474#L994-1 assume !(0 == ~E_2~0); 33359#L999-1 assume !(0 == ~E_3~0); 33360#L1004-1 assume !(0 == ~E_4~0); 33025#L1009-1 assume !(0 == ~E_5~0); 33026#L1014-1 assume !(0 == ~E_6~0); 33353#L1019-1 assume !(0 == ~E_7~0); 33972#L1024-1 assume !(0 == ~E_8~0); 33280#L1029-1 assume !(0 == ~E_9~0); 33281#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33365#L460 assume !(1 == ~m_pc~0); 34224#L460-2 is_master_triggered_~__retres1~0#1 := 0; 33926#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33927#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 34068#L1167 assume !(0 != activate_threads_~tmp~1#1); 33591#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33592#L479 assume 1 == ~t1_pc~0; 33571#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33572#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33027#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33028#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 33293#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33138#L498 assume !(1 == ~t2_pc~0); 33139#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33569#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33463#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33464#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33915#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33916#L517 assume 1 == ~t3_pc~0; 34185#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34186#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32963#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32964#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 33329#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33980#L536 assume !(1 == ~t4_pc~0); 33636#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33635#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33119#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33120#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 33629#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33881#L555 assume 1 == ~t5_pc~0; 33882#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33973#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34036#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33282#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 33162#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33063#L574 assume !(1 == ~t6_pc~0); 33064#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 33740#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33452#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33453#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 34000#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34234#L593 assume 1 == ~t7_pc~0; 34235#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33301#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34103#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34276#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 34189#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33468#L612 assume !(1 == ~t8_pc~0); 33469#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 33951#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34008#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34009#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 33742#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33743#L631 assume 1 == ~t9_pc~0; 33756#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33055#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33056#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33517#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 33574#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33984#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 32990#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32991#L1052-1 assume !(1 == ~T2_E~0); 32973#L1057-1 assume !(1 == ~T3_E~0); 32974#L1062-1 assume !(1 == ~T4_E~0); 33266#L1067-1 assume !(1 == ~T5_E~0); 33595#L1072-1 assume !(1 == ~T6_E~0); 33596#L1077-1 assume !(1 == ~T7_E~0); 33153#L1082-1 assume !(1 == ~T8_E~0); 33154#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32950#L1092-1 assume !(1 == ~E_M~0); 32951#L1097-1 assume !(1 == ~E_1~0); 32975#L1102-1 assume !(1 == ~E_2~0); 33804#L1107-1 assume !(1 == ~E_3~0); 33738#L1112-1 assume !(1 == ~E_4~0); 33739#L1117-1 assume !(1 == ~E_5~0); 33778#L1122-1 assume !(1 == ~E_6~0); 33652#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 33370#L1132-1 assume !(1 == ~E_8~0); 33371#L1137-1 assume !(1 == ~E_9~0); 34220#L1142-1 assume { :end_inline_reset_delta_events } true; 33112#L1428-2 [2023-11-19 07:59:17,634 INFO L750 eck$LassoCheckResult]: Loop: 33112#L1428-2 assume !false; 33113#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33496#L914-1 assume !false; 33734#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 33735#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 32961#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 32962#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 34005#L783 assume !(0 != eval_~tmp~0#1); 34006#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33690#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33691#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33177#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33178#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32948#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32949#L954-3 assume !(0 == ~T4_E~0); 33612#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33613#L964-3 assume !(0 == ~T6_E~0); 36787#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36786#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36785#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36784#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36783#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36782#L994-3 assume !(0 == ~E_2~0); 36781#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36780#L1004-3 assume !(0 == ~E_4~0); 36779#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36778#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36777#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36776#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 36775#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36774#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34207#L460-33 assume !(1 == ~m_pc~0); 34208#L460-35 is_master_triggered_~__retres1~0#1 := 0; 33865#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33866#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 32954#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32955#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33317#L479-33 assume !(1 == ~t1_pc~0); 33318#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 33283#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33284#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 34154#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34155#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36723#L498-33 assume !(1 == ~t2_pc~0); 36720#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 33550#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33551#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36715#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33179#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33180#L517-33 assume !(1 == ~t3_pc~0); 36710#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 34074#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33136#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33137#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34001#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34002#L536-33 assume 1 == ~t4_pc~0; 33932#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33933#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34212#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34213#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 34125#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33000#L555-33 assume 1 == ~t5_pc~0; 33001#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34084#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34251#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33800#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33801#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36656#L574-33 assume 1 == ~t6_pc~0; 36654#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34142#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34143#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33902#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 33903#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36636#L593-33 assume 1 == ~t7_pc~0; 36630#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34225#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34226#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33863#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33864#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36615#L612-33 assume !(1 == ~t8_pc~0); 36609#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 34144#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33781#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33782#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36598#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34298#L631-33 assume 1 == ~t9_pc~0; 34299#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33090#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33091#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36269#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33205#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33206#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33376#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34099#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34013#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34014#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33098#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33099#L1072-3 assume !(1 == ~T6_E~0); 33507#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33335#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33336#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33403#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33732#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33650#L1102-3 assume !(1 == ~E_2~0); 33651#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34062#L1112-3 assume !(1 == ~E_4~0); 33330#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33331#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33377#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33378#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33818#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33795#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 33207#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 33085#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 33404#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 33405#L1447 assume !(0 == start_simulation_~tmp~3#1); 33528#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 34037#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 35260#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 33023#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 33024#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35182#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35180#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 35171#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 33112#L1428-2 [2023-11-19 07:59:17,635 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:17,635 INFO L85 PathProgramCache]: Analyzing trace with hash -858385022, now seen corresponding path program 1 times [2023-11-19 07:59:17,636 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:17,638 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1670174511] [2023-11-19 07:59:17,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:17,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:17,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:17,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:17,720 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:17,720 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1670174511] [2023-11-19 07:59:17,720 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1670174511] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:17,720 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:17,720 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:17,722 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1114344067] [2023-11-19 07:59:17,722 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:17,723 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:17,723 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:17,723 INFO L85 PathProgramCache]: Analyzing trace with hash -834516337, now seen corresponding path program 1 times [2023-11-19 07:59:17,723 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:17,724 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [783229869] [2023-11-19 07:59:17,724 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:17,724 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:17,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:17,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:17,788 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:17,788 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [783229869] [2023-11-19 07:59:17,788 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [783229869] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:17,788 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:17,788 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:17,789 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2019780135] [2023-11-19 07:59:17,789 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:17,789 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:17,789 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:17,790 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:59:17,790 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:59:17,790 INFO L87 Difference]: Start difference. First operand 4007 states and 5800 transitions. cyclomatic complexity: 1797 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:18,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:18,081 INFO L93 Difference]: Finished difference Result 9605 states and 13763 transitions. [2023-11-19 07:59:18,081 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9605 states and 13763 transitions. [2023-11-19 07:59:18,137 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 9304 [2023-11-19 07:59:18,193 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9605 states to 9605 states and 13763 transitions. [2023-11-19 07:59:18,193 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9605 [2023-11-19 07:59:18,204 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9605 [2023-11-19 07:59:18,204 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9605 states and 13763 transitions. [2023-11-19 07:59:18,220 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:18,221 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9605 states and 13763 transitions. [2023-11-19 07:59:18,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9605 states and 13763 transitions. [2023-11-19 07:59:18,443 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9605 to 7529. [2023-11-19 07:59:18,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7529 states, 7529 states have (on average 1.4384380395802896) internal successors, (10830), 7528 states have internal predecessors, (10830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:18,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7529 states to 7529 states and 10830 transitions. [2023-11-19 07:59:18,485 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7529 states and 10830 transitions. [2023-11-19 07:59:18,486 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:59:18,486 INFO L428 stractBuchiCegarLoop]: Abstraction has 7529 states and 10830 transitions. [2023-11-19 07:59:18,487 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-19 07:59:18,487 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7529 states and 10830 transitions. [2023-11-19 07:59:18,525 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7380 [2023-11-19 07:59:18,526 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:18,526 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:18,529 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:18,529 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:18,530 INFO L748 eck$LassoCheckResult]: Stem: 46906#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 46907#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 47772#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47773#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47684#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 47291#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47292#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47655#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47080#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47081#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47570#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 47571#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46578#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46579#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 46781#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47183#L939 assume !(0 == ~M_E~0); 47462#L939-2 assume !(0 == ~T1_E~0); 47463#L944-1 assume !(0 == ~T2_E~0); 47218#L949-1 assume !(0 == ~T3_E~0); 47216#L954-1 assume !(0 == ~T4_E~0); 47217#L959-1 assume !(0 == ~T5_E~0); 47700#L964-1 assume !(0 == ~T6_E~0); 46930#L969-1 assume !(0 == ~T7_E~0); 46931#L974-1 assume !(0 == ~T8_E~0); 47638#L979-1 assume !(0 == ~T9_E~0); 47639#L984-1 assume !(0 == ~E_M~0); 47094#L989-1 assume !(0 == ~E_1~0); 47095#L994-1 assume !(0 == ~E_2~0); 46981#L999-1 assume !(0 == ~E_3~0); 46982#L1004-1 assume !(0 == ~E_4~0); 46645#L1009-1 assume !(0 == ~E_5~0); 46646#L1014-1 assume !(0 == ~E_6~0); 46976#L1019-1 assume !(0 == ~E_7~0); 47577#L1024-1 assume !(0 == ~E_8~0); 46901#L1029-1 assume !(0 == ~E_9~0); 46902#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46987#L460 assume !(1 == ~m_pc~0); 47823#L460-2 is_master_triggered_~__retres1~0#1 := 0; 47536#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47537#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 47668#L1167 assume !(0 != activate_threads_~tmp~1#1); 47201#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47202#L479 assume !(1 == ~t1_pc~0); 47372#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47373#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46649#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 46650#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 46914#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46760#L498 assume !(1 == ~t2_pc~0); 46761#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 47182#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47084#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47085#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47523#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47524#L517 assume 1 == ~t3_pc~0; 47784#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47785#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46585#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46586#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 46951#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47582#L536 assume !(1 == ~t4_pc~0); 47247#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 47246#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46741#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46742#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 47239#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47498#L555 assume 1 == ~t5_pc~0; 47499#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47578#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47635#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46903#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 46784#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46685#L574 assume !(1 == ~t6_pc~0); 46686#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 47353#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47074#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47075#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 47601#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47835#L593 assume 1 == ~t7_pc~0; 47836#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46922#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47704#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47869#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 47791#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47089#L612 assume !(1 == ~t8_pc~0); 47090#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 47557#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47607#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47608#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 47356#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47357#L631 assume 1 == ~t9_pc~0; 47370#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46677#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46678#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47134#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 47184#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47585#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 46613#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46614#L1052-1 assume !(1 == ~T2_E~0); 46595#L1057-1 assume !(1 == ~T3_E~0); 46596#L1062-1 assume !(1 == ~T4_E~0); 46886#L1067-1 assume !(1 == ~T5_E~0); 47701#L1072-1 assume !(1 == ~T6_E~0); 47558#L1077-1 assume !(1 == ~T7_E~0); 47559#L1082-1 assume !(1 == ~T8_E~0); 47322#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47323#L1092-1 assume !(1 == ~E_M~0); 46597#L1097-1 assume !(1 == ~E_1~0); 46598#L1102-1 assume !(1 == ~E_2~0); 47425#L1107-1 assume !(1 == ~E_3~0); 47426#L1112-1 assume !(1 == ~E_4~0); 47396#L1117-1 assume !(1 == ~E_5~0); 47397#L1122-1 assume !(1 == ~E_6~0); 47263#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 47264#L1132-1 assume !(1 == ~E_8~0); 47821#L1137-1 assume !(1 == ~E_9~0); 47822#L1142-1 assume { :end_inline_reset_delta_events } true; 50899#L1428-2 [2023-11-19 07:59:18,530 INFO L750 eck$LassoCheckResult]: Loop: 50899#L1428-2 assume !false; 50893#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 50891#L914-1 assume !false; 50889#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 50886#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 50876#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 50874#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 50870#L783 assume !(0 != eval_~tmp~0#1); 50871#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 51490#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 51488#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 51486#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 51484#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 51481#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 51479#L954-3 assume !(0 == ~T4_E~0); 51477#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51475#L964-3 assume !(0 == ~T6_E~0); 51473#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 51471#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51468#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 51466#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 51464#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 51462#L994-3 assume !(0 == ~E_2~0); 51460#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 51458#L1004-3 assume !(0 == ~E_4~0); 51455#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51453#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51452#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 51434#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 51427#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 51420#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51412#L460-33 assume !(1 == ~m_pc~0); 51401#L460-35 is_master_triggered_~__retres1~0#1 := 0; 51390#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51382#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 51378#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51265#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51262#L479-33 assume !(1 == ~t1_pc~0); 49614#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 51259#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51257#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 51255#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 51253#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51250#L498-33 assume !(1 == ~t2_pc~0); 51247#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 51245#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51243#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 51241#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 51239#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51238#L517-33 assume !(1 == ~t3_pc~0); 51234#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 51232#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51230#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 51228#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51226#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51224#L536-33 assume 1 == ~t4_pc~0; 51218#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51215#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51213#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51211#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51209#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51207#L555-33 assume !(1 == ~t5_pc~0); 51204#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 51203#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51200#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 51198#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 51196#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 51194#L574-33 assume 1 == ~t6_pc~0; 51191#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 51189#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 51186#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51184#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 51182#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51180#L593-33 assume 1 == ~t7_pc~0; 51176#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 51174#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 51172#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51170#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 51168#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 51166#L612-33 assume !(1 == ~t8_pc~0); 51162#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 51160#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51158#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51156#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 51154#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51152#L631-33 assume 1 == ~t9_pc~0; 51148#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 51146#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51144#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51142#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51140#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51138#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46998#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 51135#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 51133#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 51131#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47888#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 51128#L1072-3 assume !(1 == ~T6_E~0); 51126#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 51123#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 51121#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 51119#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 51117#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 51115#L1102-3 assume !(1 == ~E_2~0); 51113#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 51110#L1112-3 assume !(1 == ~E_4~0); 51108#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 51106#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 51104#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 51102#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 51100#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51097#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 51089#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 51082#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 51081#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 51078#L1447 assume !(0 == start_simulation_~tmp~3#1); 51075#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 50974#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 50967#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 50965#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 50935#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50923#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50914#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 50906#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 50899#L1428-2 [2023-11-19 07:59:18,531 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:18,532 INFO L85 PathProgramCache]: Analyzing trace with hash -717285501, now seen corresponding path program 1 times [2023-11-19 07:59:18,532 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:18,532 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1020421348] [2023-11-19 07:59:18,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:18,533 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:18,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:18,758 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:18,758 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:18,759 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1020421348] [2023-11-19 07:59:18,759 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1020421348] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:18,759 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:18,759 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:59:18,759 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [950210437] [2023-11-19 07:59:18,760 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:18,761 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:18,761 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:18,762 INFO L85 PathProgramCache]: Analyzing trace with hash -257587696, now seen corresponding path program 1 times [2023-11-19 07:59:18,762 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:18,762 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1248252478] [2023-11-19 07:59:18,762 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:18,763 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:18,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:18,831 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:18,831 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:18,832 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1248252478] [2023-11-19 07:59:18,832 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1248252478] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:18,832 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:18,832 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:18,832 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1221359190] [2023-11-19 07:59:18,832 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:18,833 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:18,833 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:18,834 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 07:59:18,834 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 07:59:18,835 INFO L87 Difference]: Start difference. First operand 7529 states and 10830 transitions. cyclomatic complexity: 3305 Second operand has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:19,120 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:19,120 INFO L93 Difference]: Finished difference Result 9209 states and 13117 transitions. [2023-11-19 07:59:19,121 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9209 states and 13117 transitions. [2023-11-19 07:59:19,180 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9058 [2023-11-19 07:59:19,279 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9209 states to 9209 states and 13117 transitions. [2023-11-19 07:59:19,279 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9209 [2023-11-19 07:59:19,293 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9209 [2023-11-19 07:59:19,293 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9209 states and 13117 transitions. [2023-11-19 07:59:19,312 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:19,312 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9209 states and 13117 transitions. [2023-11-19 07:59:19,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9209 states and 13117 transitions. [2023-11-19 07:59:19,478 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9209 to 7541. [2023-11-19 07:59:19,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7541 states, 7541 states have (on average 1.4269990717411485) internal successors, (10761), 7540 states have internal predecessors, (10761), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:19,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7541 states to 7541 states and 10761 transitions. [2023-11-19 07:59:19,541 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7541 states and 10761 transitions. [2023-11-19 07:59:19,542 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-19 07:59:19,543 INFO L428 stractBuchiCegarLoop]: Abstraction has 7541 states and 10761 transitions. [2023-11-19 07:59:19,544 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-19 07:59:19,544 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7541 states and 10761 transitions. [2023-11-19 07:59:19,588 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7392 [2023-11-19 07:59:19,588 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:19,588 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:19,591 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:19,592 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:19,592 INFO L748 eck$LassoCheckResult]: Stem: 63658#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 63659#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 64635#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64636#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64518#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 64065#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 64066#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64475#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 63840#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 63841#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64378#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 64379#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 63329#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 63330#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 63532#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63953#L939 assume !(0 == ~M_E~0); 64249#L939-2 assume !(0 == ~T1_E~0); 64250#L944-1 assume !(0 == ~T2_E~0); 63991#L949-1 assume !(0 == ~T3_E~0); 63989#L954-1 assume !(0 == ~T4_E~0); 63990#L959-1 assume !(0 == ~T5_E~0); 64535#L964-1 assume !(0 == ~T6_E~0); 63684#L969-1 assume !(0 == ~T7_E~0); 63685#L974-1 assume !(0 == ~T8_E~0); 64460#L979-1 assume !(0 == ~T9_E~0); 64461#L984-1 assume !(0 == ~E_M~0); 63855#L989-1 assume !(0 == ~E_1~0); 63856#L994-1 assume !(0 == ~E_2~0); 63736#L999-1 assume !(0 == ~E_3~0); 63737#L1004-1 assume !(0 == ~E_4~0); 63395#L1009-1 assume !(0 == ~E_5~0); 63396#L1014-1 assume !(0 == ~E_6~0); 63731#L1019-1 assume !(0 == ~E_7~0); 64387#L1024-1 assume !(0 == ~E_8~0); 63653#L1029-1 assume !(0 == ~E_9~0); 63654#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63742#L460 assume !(1 == ~m_pc~0); 64707#L460-2 is_master_triggered_~__retres1~0#1 := 0; 64343#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64344#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 64496#L1167 assume !(0 != activate_threads_~tmp~1#1); 63973#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63974#L479 assume !(1 == ~t1_pc~0); 64152#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 64153#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63399#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 63400#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 63666#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63511#L498 assume !(1 == ~t2_pc~0); 63512#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 63952#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63844#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 63845#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 64329#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64330#L517 assume 1 == ~t3_pc~0; 64664#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 64665#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63336#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 63337#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 63705#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64396#L536 assume !(1 == ~t4_pc~0); 64020#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 64019#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 63492#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63493#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 64013#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64293#L555 assume 1 == ~t5_pc~0; 64294#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64388#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64458#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 63655#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 63535#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63436#L574 assume !(1 == ~t6_pc~0); 63437#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 64131#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63834#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 63835#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 64417#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64718#L593 assume 1 == ~t7_pc~0; 64719#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 63674#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64538#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 64794#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 64671#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 63850#L612 assume !(1 == ~t8_pc~0); 63851#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 64367#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64423#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64424#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 64133#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 64134#L631 assume 1 == ~t9_pc~0; 64150#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 63428#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 63429#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 63899#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 63954#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64400#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 64401#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 67741#L1052-1 assume !(1 == ~T2_E~0); 67740#L1057-1 assume !(1 == ~T3_E~0); 67739#L1062-1 assume !(1 == ~T4_E~0); 63638#L1067-1 assume !(1 == ~T5_E~0); 67738#L1072-1 assume !(1 == ~T6_E~0); 67737#L1077-1 assume !(1 == ~T7_E~0); 67736#L1082-1 assume !(1 == ~T8_E~0); 67735#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 67734#L1092-1 assume !(1 == ~E_M~0); 67733#L1097-1 assume !(1 == ~E_1~0); 67732#L1102-1 assume !(1 == ~E_2~0); 67731#L1107-1 assume !(1 == ~E_3~0); 67730#L1112-1 assume !(1 == ~E_4~0); 67729#L1117-1 assume !(1 == ~E_5~0); 67728#L1122-1 assume !(1 == ~E_6~0); 67727#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 63747#L1132-1 assume !(1 == ~E_8~0); 63748#L1137-1 assume !(1 == ~E_9~0); 64703#L1142-1 assume { :end_inline_reset_delta_events } true; 67588#L1428-2 [2023-11-19 07:59:19,593 INFO L750 eck$LassoCheckResult]: Loop: 67588#L1428-2 assume !false; 67589#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 66928#L914-1 assume !false; 66929#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 65508#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 65500#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 65487#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 65488#L783 assume !(0 != eval_~tmp~0#1); 64436#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 64073#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 64074#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 63550#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 63551#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 63321#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 63322#L954-3 assume !(0 == ~T4_E~0); 63995#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 63401#L964-3 assume !(0 == ~T6_E~0); 63402#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 63604#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 63605#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 64088#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 64089#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 63662#L994-3 assume !(0 == ~E_2~0); 63663#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 64259#L1004-3 assume !(0 == ~E_4~0); 63477#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 63478#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 64067#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 64068#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 64047#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 63997#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63998#L460-33 assume !(1 == ~m_pc~0); 64311#L460-35 is_master_triggered_~__retres1~0#1 := 0; 64279#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64280#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 63327#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 63328#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63688#L479-33 assume !(1 == ~t1_pc~0); 63689#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 65391#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65392#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 68030#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 67922#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65366#L498-33 assume !(1 == ~t2_pc~0); 65365#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 65353#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65354#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 65340#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 65341#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65327#L517-33 assume !(1 == ~t3_pc~0); 65328#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 65313#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65314#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 65298#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 65299#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65285#L536-33 assume 1 == ~t4_pc~0; 65286#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 65271#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65272#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 65256#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 65257#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65243#L555-33 assume 1 == ~t5_pc~0; 65244#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 65230#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65231#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65217#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 65218#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 67920#L574-33 assume !(1 == ~t6_pc~0); 67919#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 67917#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63966#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 63967#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 64315#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 67915#L593-33 assume 1 == ~t7_pc~0; 67913#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 64708#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64709#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 67912#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 67911#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64812#L612-33 assume 1 == ~t8_pc~0; 64686#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 64688#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64179#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64180#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 64368#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 67907#L631-33 assume !(1 == ~t9_pc~0); 67904#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 67902#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 67900#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 67899#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 63578#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63579#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 63753#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 64534#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 64432#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 64433#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 63471#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 63472#L1072-3 assume !(1 == ~T6_E~0); 63889#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 63713#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 63714#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 63784#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 64120#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 64034#L1102-3 assume !(1 == ~E_2~0); 64035#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 64490#L1112-3 assume !(1 == ~E_4~0); 63706#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 63707#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 64502#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 64225#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 64226#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 64795#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 63583#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 63460#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 63785#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 63786#L1447 assume !(0 == start_simulation_~tmp~3#1); 63910#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 68183#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 68175#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 68172#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 68169#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 68164#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 67595#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 67596#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 67588#L1428-2 [2023-11-19 07:59:19,594 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:19,594 INFO L85 PathProgramCache]: Analyzing trace with hash 1891501957, now seen corresponding path program 1 times [2023-11-19 07:59:19,594 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:19,595 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1402465065] [2023-11-19 07:59:19,595 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:19,595 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:19,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:19,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:19,721 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:19,721 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1402465065] [2023-11-19 07:59:19,722 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1402465065] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:19,722 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:19,722 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:19,722 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1481539104] [2023-11-19 07:59:19,722 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:19,725 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:19,725 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:19,726 INFO L85 PathProgramCache]: Analyzing trace with hash -650634094, now seen corresponding path program 1 times [2023-11-19 07:59:19,726 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:19,726 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1317303093] [2023-11-19 07:59:19,726 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:19,727 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:19,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:19,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:19,815 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:19,815 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1317303093] [2023-11-19 07:59:19,815 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1317303093] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:19,816 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:19,816 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:19,817 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1467522503] [2023-11-19 07:59:19,817 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:19,818 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:19,818 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:19,819 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:59:19,819 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:59:19,820 INFO L87 Difference]: Start difference. First operand 7541 states and 10761 transitions. cyclomatic complexity: 3224 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:20,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:20,313 INFO L93 Difference]: Finished difference Result 18149 states and 25679 transitions. [2023-11-19 07:59:20,313 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18149 states and 25679 transitions. [2023-11-19 07:59:20,422 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 17695 [2023-11-19 07:59:20,497 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18149 states to 18149 states and 25679 transitions. [2023-11-19 07:59:20,498 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18149 [2023-11-19 07:59:20,520 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18149 [2023-11-19 07:59:20,520 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18149 states and 25679 transitions. [2023-11-19 07:59:20,544 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:20,544 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18149 states and 25679 transitions. [2023-11-19 07:59:20,569 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18149 states and 25679 transitions. [2023-11-19 07:59:20,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18149 to 14268. [2023-11-19 07:59:20,815 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14268 states, 14268 states have (on average 1.41982057751612) internal successors, (20258), 14267 states have internal predecessors, (20258), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:20,872 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14268 states to 14268 states and 20258 transitions. [2023-11-19 07:59:20,873 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14268 states and 20258 transitions. [2023-11-19 07:59:20,873 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:59:20,874 INFO L428 stractBuchiCegarLoop]: Abstraction has 14268 states and 20258 transitions. [2023-11-19 07:59:20,874 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-19 07:59:20,874 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14268 states and 20258 transitions. [2023-11-19 07:59:20,943 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 14116 [2023-11-19 07:59:20,943 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:20,943 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:20,947 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:20,947 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:20,948 INFO L748 eck$LassoCheckResult]: Stem: 89360#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 89361#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 90209#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 90210#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 90126#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 89741#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 89742#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 90096#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 89530#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 89531#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 90019#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 90020#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 89029#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 89030#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 89234#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 89632#L939 assume !(0 == ~M_E~0); 89907#L939-2 assume !(0 == ~T1_E~0); 89908#L944-1 assume !(0 == ~T2_E~0); 89669#L949-1 assume !(0 == ~T3_E~0); 89667#L954-1 assume !(0 == ~T4_E~0); 89668#L959-1 assume !(0 == ~T5_E~0); 90142#L964-1 assume !(0 == ~T6_E~0); 89385#L969-1 assume !(0 == ~T7_E~0); 89386#L974-1 assume !(0 == ~T8_E~0); 90083#L979-1 assume !(0 == ~T9_E~0); 90084#L984-1 assume !(0 == ~E_M~0); 89544#L989-1 assume !(0 == ~E_1~0); 89545#L994-1 assume !(0 == ~E_2~0); 89433#L999-1 assume !(0 == ~E_3~0); 89434#L1004-1 assume !(0 == ~E_4~0); 89096#L1009-1 assume !(0 == ~E_5~0); 89097#L1014-1 assume !(0 == ~E_6~0); 89428#L1019-1 assume !(0 == ~E_7~0); 90027#L1024-1 assume !(0 == ~E_8~0); 89355#L1029-1 assume !(0 == ~E_9~0); 89356#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89439#L460 assume !(1 == ~m_pc~0); 90263#L460-2 is_master_triggered_~__retres1~0#1 := 0; 89988#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 89989#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 90109#L1167 assume !(0 != activate_threads_~tmp~1#1); 89651#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 89652#L479 assume !(1 == ~t1_pc~0); 89820#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 89821#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 89100#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 89101#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 89368#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 89213#L498 assume !(1 == ~t2_pc~0); 89214#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 89631#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 89534#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 89535#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 89974#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 89975#L517 assume !(1 == ~t3_pc~0); 90308#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 90309#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89036#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 89037#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 89405#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 90033#L536 assume !(1 == ~t4_pc~0); 89697#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 89696#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 89194#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 89195#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 89689#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 89946#L555 assume 1 == ~t5_pc~0; 89947#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 90028#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 90081#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 89357#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 89239#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 89136#L574 assume !(1 == ~t6_pc~0); 89137#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 89802#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 89524#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 89525#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 90051#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 90272#L593 assume 1 == ~t7_pc~0; 90273#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 89376#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 90146#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 90311#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 90227#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 89539#L612 assume !(1 == ~t8_pc~0); 89540#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 90007#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 90056#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 90057#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 89804#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 89805#L631 assume 1 == ~t9_pc~0; 89818#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 89128#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 89129#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 89584#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 89633#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 90036#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 89064#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 89065#L1052-1 assume !(1 == ~T2_E~0); 89046#L1057-1 assume !(1 == ~T3_E~0); 89047#L1062-1 assume !(1 == ~T4_E~0); 89340#L1067-1 assume !(1 == ~T5_E~0); 90143#L1072-1 assume !(1 == ~T6_E~0); 90008#L1077-1 assume !(1 == ~T7_E~0); 90009#L1082-1 assume !(1 == ~T8_E~0); 89774#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 89775#L1092-1 assume !(1 == ~E_M~0); 89048#L1097-1 assume !(1 == ~E_1~0); 89049#L1102-1 assume !(1 == ~E_2~0); 89868#L1107-1 assume !(1 == ~E_3~0); 89869#L1112-1 assume !(1 == ~E_4~0); 89841#L1117-1 assume !(1 == ~E_5~0); 89842#L1122-1 assume !(1 == ~E_6~0); 89713#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 89714#L1132-1 assume !(1 == ~E_8~0); 90258#L1137-1 assume !(1 == ~E_9~0); 90259#L1142-1 assume { :end_inline_reset_delta_events } true; 101778#L1428-2 [2023-11-19 07:59:20,949 INFO L750 eck$LassoCheckResult]: Loop: 101778#L1428-2 assume !false; 101704#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 101693#L914-1 assume !false; 101683#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 101580#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 101570#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 101568#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 101565#L783 assume !(0 != eval_~tmp~0#1); 101566#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 103111#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 103110#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 103109#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 103108#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 103107#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 103106#L954-3 assume !(0 == ~T4_E~0); 103105#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 103104#L964-3 assume !(0 == ~T6_E~0); 103103#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 103102#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 103101#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 103100#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 103099#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 103098#L994-3 assume !(0 == ~E_2~0); 103097#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 103096#L1004-3 assume !(0 == ~E_4~0); 103095#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 103094#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 103093#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 103092#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 103091#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 103090#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 103089#L460-33 assume !(1 == ~m_pc~0); 103087#L460-35 is_master_triggered_~__retres1~0#1 := 0; 103084#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103082#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 103078#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 103075#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 102023#L479-33 assume !(1 == ~t1_pc~0); 102021#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 102018#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 102016#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 102014#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 102012#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 102010#L498-33 assume !(1 == ~t2_pc~0); 102007#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 102004#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102002#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 102000#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 101998#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 101996#L517-33 assume !(1 == ~t3_pc~0); 93424#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 101992#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 101990#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 101988#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 101985#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 101984#L536-33 assume !(1 == ~t4_pc~0); 101983#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 101980#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 101979#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 101977#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 101976#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 101975#L555-33 assume !(1 == ~t5_pc~0); 101973#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 101972#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 101971#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 101970#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 101969#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 101968#L574-33 assume !(1 == ~t6_pc~0); 101967#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 101965#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 101964#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 101963#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 101962#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 101961#L593-33 assume 1 == ~t7_pc~0; 101959#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 101958#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 101957#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 101956#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 101953#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 101951#L612-33 assume 1 == ~t8_pc~0; 101949#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 101946#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 101944#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 101942#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 101940#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 101939#L631-33 assume !(1 == ~t9_pc~0); 101937#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 101934#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 101932#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 101930#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 101928#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 101925#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 89450#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 101922#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 101920#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 101918#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 90334#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 101914#L1072-3 assume !(1 == ~T6_E~0); 101912#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 101910#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 101908#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 101906#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 101904#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 101901#L1102-3 assume !(1 == ~E_2~0); 101899#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 101897#L1112-3 assume !(1 == ~E_4~0); 101895#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 101893#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 101891#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 101888#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 101886#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 101884#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 101870#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 101863#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 101860#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 101813#L1447 assume !(0 == start_simulation_~tmp~3#1); 101811#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 101805#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 101798#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 101797#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 101793#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 101789#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 101785#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 101781#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 101778#L1428-2 [2023-11-19 07:59:20,950 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:20,950 INFO L85 PathProgramCache]: Analyzing trace with hash -1826536698, now seen corresponding path program 1 times [2023-11-19 07:59:20,950 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:20,951 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [979641273] [2023-11-19 07:59:20,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:20,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:20,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:21,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:21,166 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:21,167 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [979641273] [2023-11-19 07:59:21,167 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [979641273] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:21,167 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:21,167 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:59:21,168 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1918334413] [2023-11-19 07:59:21,168 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:21,168 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:21,169 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:21,169 INFO L85 PathProgramCache]: Analyzing trace with hash 1063923412, now seen corresponding path program 1 times [2023-11-19 07:59:21,169 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:21,169 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2071391777] [2023-11-19 07:59:21,169 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:21,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:21,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:21,273 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:21,273 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:21,273 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2071391777] [2023-11-19 07:59:21,274 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2071391777] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:21,274 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:21,274 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:59:21,274 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [936643559] [2023-11-19 07:59:21,274 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:21,275 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:21,275 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:21,276 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:59:21,276 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:59:21,276 INFO L87 Difference]: Start difference. First operand 14268 states and 20258 transitions. cyclomatic complexity: 5994 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:21,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:21,532 INFO L93 Difference]: Finished difference Result 27103 states and 38299 transitions. [2023-11-19 07:59:21,532 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27103 states and 38299 transitions. [2023-11-19 07:59:21,683 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26912 [2023-11-19 07:59:21,792 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27103 states to 27103 states and 38299 transitions. [2023-11-19 07:59:21,792 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27103 [2023-11-19 07:59:21,820 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27103 [2023-11-19 07:59:21,820 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27103 states and 38299 transitions. [2023-11-19 07:59:21,854 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:21,854 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27103 states and 38299 transitions. [2023-11-19 07:59:21,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27103 states and 38299 transitions. [2023-11-19 07:59:22,557 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27103 to 27071. [2023-11-19 07:59:22,600 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27071 states, 27071 states have (on average 1.4135791067932475) internal successors, (38267), 27070 states have internal predecessors, (38267), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:22,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27071 states to 27071 states and 38267 transitions. [2023-11-19 07:59:22,711 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27071 states and 38267 transitions. [2023-11-19 07:59:22,712 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:59:22,712 INFO L428 stractBuchiCegarLoop]: Abstraction has 27071 states and 38267 transitions. [2023-11-19 07:59:22,712 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-19 07:59:22,712 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27071 states and 38267 transitions. [2023-11-19 07:59:22,835 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26880 [2023-11-19 07:59:22,835 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:22,835 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:22,839 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:22,839 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:22,840 INFO L748 eck$LassoCheckResult]: Stem: 130736#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 130737#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 131601#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 131602#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 131508#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 131127#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 131128#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 131481#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 130914#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 130915#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 131393#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 131394#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 130409#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 130410#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 130612#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 131019#L939 assume !(0 == ~M_E~0); 131288#L939-2 assume !(0 == ~T1_E~0); 131289#L944-1 assume !(0 == ~T2_E~0); 131056#L949-1 assume !(0 == ~T3_E~0); 131054#L954-1 assume !(0 == ~T4_E~0); 131055#L959-1 assume !(0 == ~T5_E~0); 131526#L964-1 assume !(0 == ~T6_E~0); 130761#L969-1 assume !(0 == ~T7_E~0); 130762#L974-1 assume !(0 == ~T8_E~0); 131460#L979-1 assume !(0 == ~T9_E~0); 131461#L984-1 assume !(0 == ~E_M~0); 130928#L989-1 assume !(0 == ~E_1~0); 130929#L994-1 assume !(0 == ~E_2~0); 130813#L999-1 assume !(0 == ~E_3~0); 130814#L1004-1 assume !(0 == ~E_4~0); 130474#L1009-1 assume !(0 == ~E_5~0); 130475#L1014-1 assume !(0 == ~E_6~0); 130808#L1019-1 assume !(0 == ~E_7~0); 131401#L1024-1 assume !(0 == ~E_8~0); 130731#L1029-1 assume !(0 == ~E_9~0); 130732#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 130819#L460 assume !(1 == ~m_pc~0); 131646#L460-2 is_master_triggered_~__retres1~0#1 := 0; 131361#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 131362#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 131494#L1167 assume !(0 != activate_threads_~tmp~1#1); 131039#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 131040#L479 assume !(1 == ~t1_pc~0); 131201#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 131202#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 130478#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 130479#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 130744#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 130591#L498 assume !(1 == ~t2_pc~0); 130592#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 131018#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 130918#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 130919#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 131350#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 131351#L517 assume !(1 == ~t3_pc~0); 131690#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 131691#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 130416#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 130417#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 130781#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 131406#L536 assume !(1 == ~t4_pc~0); 131084#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 131083#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 130572#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 130573#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 131076#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 131323#L555 assume !(1 == ~t5_pc~0); 131324#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 131402#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 131458#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 130733#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 130617#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 130515#L574 assume !(1 == ~t6_pc~0); 130516#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 131183#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 130907#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 130908#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 131424#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 131652#L593 assume 1 == ~t7_pc~0; 131653#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 130752#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 131529#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 131694#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 131618#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 130923#L612 assume !(1 == ~t8_pc~0); 130924#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 131382#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 131429#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 131430#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 131185#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 131186#L631 assume 1 == ~t9_pc~0; 131199#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 130506#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 130507#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 130970#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 131020#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 131409#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 130443#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 130444#L1052-1 assume !(1 == ~T2_E~0); 130426#L1057-1 assume !(1 == ~T3_E~0); 130427#L1062-1 assume !(1 == ~T4_E~0); 130717#L1067-1 assume !(1 == ~T5_E~0); 131043#L1072-1 assume !(1 == ~T6_E~0); 131044#L1077-1 assume !(1 == ~T7_E~0); 130606#L1082-1 assume !(1 == ~T8_E~0); 130607#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 130403#L1092-1 assume !(1 == ~E_M~0); 130404#L1097-1 assume !(1 == ~E_1~0); 130428#L1102-1 assume !(1 == ~E_2~0); 131254#L1107-1 assume !(1 == ~E_3~0); 131181#L1112-1 assume !(1 == ~E_4~0); 131182#L1117-1 assume !(1 == ~E_5~0); 131227#L1122-1 assume !(1 == ~E_6~0); 131099#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 130824#L1132-1 assume !(1 == ~E_8~0); 130825#L1137-1 assume !(1 == ~E_9~0); 130714#L1142-1 assume { :end_inline_reset_delta_events } true; 130566#L1428-2 [2023-11-19 07:59:22,840 INFO L750 eck$LassoCheckResult]: Loop: 130566#L1428-2 assume !false; 130567#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 130949#L914-1 assume !false; 131178#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 131179#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 130414#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 130415#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 130947#L783 assume !(0 != eval_~tmp~0#1); 131427#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 156485#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 156483#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 156481#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 156479#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 156477#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 156475#L954-3 assume !(0 == ~T4_E~0); 156473#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 156470#L964-3 assume !(0 == ~T6_E~0); 156469#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 156466#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 156464#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 156462#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 156460#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 156458#L994-3 assume !(0 == ~E_2~0); 156455#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 156453#L1004-3 assume !(0 == ~E_4~0); 156451#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 156449#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 156447#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 156445#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 156442#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 156439#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 156437#L460-33 assume !(1 == ~m_pc~0); 156435#L460-35 is_master_triggered_~__retres1~0#1 := 0; 156433#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 156431#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 156429#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 156426#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 130765#L479-33 assume !(1 == ~t1_pc~0); 130766#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 155934#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 155933#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 155932#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 155931#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 155930#L498-33 assume !(1 == ~t2_pc~0); 155925#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 155923#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 155921#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 155920#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 155919#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 155917#L517-33 assume !(1 == ~t3_pc~0); 155116#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 155914#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 155912#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 155909#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 155907#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 155905#L536-33 assume 1 == ~t4_pc~0; 155902#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 155900#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 155898#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 155895#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 155893#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 155891#L555-33 assume !(1 == ~t5_pc~0); 155890#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 155887#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 155886#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 131250#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 131251#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 155844#L574-33 assume 1 == ~t6_pc~0; 155842#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 155841#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 155840#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 155839#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 155837#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 155835#L593-33 assume 1 == ~t7_pc~0; 155832#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 155831#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 155829#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 155827#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 155826#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 155825#L612-33 assume !(1 == ~t8_pc~0); 155822#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 155820#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 155814#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 155811#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 155809#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 155807#L631-33 assume 1 == ~t9_pc~0; 155804#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 155801#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 155799#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 155797#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 130661#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 130662#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 130830#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 131525#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 155379#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 155375#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 149234#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 131672#L1072-3 assume !(1 == ~T6_E~0); 130960#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 130789#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 130790#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 130858#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 131177#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 131097#L1102-3 assume !(1 == ~E_2~0); 131098#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 131489#L1112-3 assume !(1 == ~E_4~0); 130782#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 130783#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 130831#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 130832#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 131267#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 131245#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 130666#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 130539#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 130859#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 130860#L1447 assume !(0 == start_simulation_~tmp~3#1); 130980#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 131459#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 130693#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 130476#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 130477#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 130560#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 130561#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 131047#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 130566#L1428-2 [2023-11-19 07:59:22,841 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:22,842 INFO L85 PathProgramCache]: Analyzing trace with hash 367589383, now seen corresponding path program 1 times [2023-11-19 07:59:22,842 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:22,842 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [53869713] [2023-11-19 07:59:22,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:22,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:23,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:23,083 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:23,084 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:23,084 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [53869713] [2023-11-19 07:59:23,084 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [53869713] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:23,084 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:23,085 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:23,085 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [564493843] [2023-11-19 07:59:23,085 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:23,085 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:23,086 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:23,086 INFO L85 PathProgramCache]: Analyzing trace with hash -230522094, now seen corresponding path program 1 times [2023-11-19 07:59:23,086 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:23,086 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1808395178] [2023-11-19 07:59:23,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:23,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:23,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:23,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:23,146 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:23,146 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1808395178] [2023-11-19 07:59:23,146 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1808395178] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:23,146 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:23,146 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:23,147 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [766064100] [2023-11-19 07:59:23,147 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:23,147 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:23,147 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:23,148 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:59:23,148 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:59:23,148 INFO L87 Difference]: Start difference. First operand 27071 states and 38267 transitions. cyclomatic complexity: 11204 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:23,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:23,907 INFO L93 Difference]: Finished difference Result 64722 states and 90812 transitions. [2023-11-19 07:59:23,907 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64722 states and 90812 transitions. [2023-11-19 07:59:24,420 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 63276 [2023-11-19 07:59:24,678 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64722 states to 64722 states and 90812 transitions. [2023-11-19 07:59:24,679 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 64722 [2023-11-19 07:59:24,731 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 64722 [2023-11-19 07:59:24,731 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64722 states and 90812 transitions. [2023-11-19 07:59:24,779 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:24,779 INFO L218 hiAutomatonCegarLoop]: Abstraction has 64722 states and 90812 transitions. [2023-11-19 07:59:24,972 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64722 states and 90812 transitions. [2023-11-19 07:59:25,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64722 to 51390. [2023-11-19 07:59:25,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51390 states, 51390 states have (on average 1.4080560420315236) internal successors, (72360), 51389 states have internal predecessors, (72360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:26,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51390 states to 51390 states and 72360 transitions. [2023-11-19 07:59:26,068 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51390 states and 72360 transitions. [2023-11-19 07:59:26,069 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:59:26,070 INFO L428 stractBuchiCegarLoop]: Abstraction has 51390 states and 72360 transitions. [2023-11-19 07:59:26,070 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-19 07:59:26,070 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51390 states and 72360 transitions. [2023-11-19 07:59:26,260 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 51152 [2023-11-19 07:59:26,261 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:26,261 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:26,265 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:26,265 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:26,265 INFO L748 eck$LassoCheckResult]: Stem: 222539#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 222540#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 223453#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 223454#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 223351#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 222941#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 222942#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 223318#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 222719#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 222720#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 223229#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 223230#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 222211#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 222212#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 222414#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 222830#L939 assume !(0 == ~M_E~0); 223109#L939-2 assume !(0 == ~T1_E~0); 223110#L944-1 assume !(0 == ~T2_E~0); 222865#L949-1 assume !(0 == ~T3_E~0); 222863#L954-1 assume !(0 == ~T4_E~0); 222864#L959-1 assume !(0 == ~T5_E~0); 223372#L964-1 assume !(0 == ~T6_E~0); 222566#L969-1 assume !(0 == ~T7_E~0); 222567#L974-1 assume !(0 == ~T8_E~0); 223304#L979-1 assume !(0 == ~T9_E~0); 223305#L984-1 assume !(0 == ~E_M~0); 222733#L989-1 assume !(0 == ~E_1~0); 222734#L994-1 assume !(0 == ~E_2~0); 222617#L999-1 assume !(0 == ~E_3~0); 222618#L1004-1 assume !(0 == ~E_4~0); 222277#L1009-1 assume !(0 == ~E_5~0); 222278#L1014-1 assume !(0 == ~E_6~0); 222612#L1019-1 assume !(0 == ~E_7~0); 223237#L1024-1 assume !(0 == ~E_8~0); 222534#L1029-1 assume !(0 == ~E_9~0); 222535#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 222624#L460 assume !(1 == ~m_pc~0); 223513#L460-2 is_master_triggered_~__retres1~0#1 := 0; 223194#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 223195#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 223332#L1167 assume !(0 != activate_threads_~tmp~1#1); 222848#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 222849#L479 assume !(1 == ~t1_pc~0); 223022#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 223023#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 222281#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 222282#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 222547#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 222393#L498 assume !(1 == ~t2_pc~0); 222394#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 222829#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 222723#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 222724#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 223183#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 223184#L517 assume !(1 == ~t3_pc~0); 223565#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 223566#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 222218#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 222219#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 222587#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 223247#L536 assume !(1 == ~t4_pc~0); 222893#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 222892#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 222375#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 222376#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 222885#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 223150#L555 assume !(1 == ~t5_pc~0); 223151#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 223238#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 223302#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 222536#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 222417#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 222317#L574 assume !(1 == ~t6_pc~0); 222318#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 223004#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 222713#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 222714#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 223265#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 223522#L593 assume !(1 == ~t7_pc~0); 222555#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 222556#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 223376#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 223573#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 223475#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 222728#L612 assume !(1 == ~t8_pc~0); 222729#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 223215#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 223271#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 223272#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 223006#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 223007#L631 assume 1 == ~t9_pc~0; 223020#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 222308#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 222309#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 222775#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 222831#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 223250#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 222246#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 222247#L1052-1 assume !(1 == ~T2_E~0); 222228#L1057-1 assume !(1 == ~T3_E~0); 222229#L1062-1 assume !(1 == ~T4_E~0); 222519#L1067-1 assume !(1 == ~T5_E~0); 223373#L1072-1 assume !(1 == ~T6_E~0); 223216#L1077-1 assume !(1 == ~T7_E~0); 223217#L1082-1 assume !(1 == ~T8_E~0); 222973#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 222974#L1092-1 assume !(1 == ~E_M~0); 222230#L1097-1 assume !(1 == ~E_1~0); 222231#L1102-1 assume !(1 == ~E_2~0); 223073#L1107-1 assume !(1 == ~E_3~0); 223074#L1112-1 assume !(1 == ~E_4~0); 223044#L1117-1 assume !(1 == ~E_5~0); 223045#L1122-1 assume !(1 == ~E_6~0); 222909#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 222910#L1132-1 assume !(1 == ~E_8~0); 223508#L1137-1 assume !(1 == ~E_9~0); 223509#L1142-1 assume { :end_inline_reset_delta_events } true; 266845#L1428-2 [2023-11-19 07:59:26,266 INFO L750 eck$LassoCheckResult]: Loop: 266845#L1428-2 assume !false; 266552#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 266550#L914-1 assume !false; 266548#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 266535#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 266295#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 266292#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 266289#L783 assume !(0 != eval_~tmp~0#1); 266290#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 273242#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 273241#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 273240#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 272185#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 272184#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 272183#L954-3 assume !(0 == ~T4_E~0); 272181#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 272179#L964-3 assume !(0 == ~T6_E~0); 272177#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 272175#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 272173#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 272171#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 272169#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 272167#L994-3 assume !(0 == ~E_2~0); 272165#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 272163#L1004-3 assume !(0 == ~E_4~0); 272160#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 272157#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 272154#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 272151#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 272148#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 272143#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 272141#L460-33 assume !(1 == ~m_pc~0); 272139#L460-35 is_master_triggered_~__retres1~0#1 := 0; 272137#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 272134#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 272131#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 272128#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 267472#L479-33 assume !(1 == ~t1_pc~0); 267470#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 267468#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 267466#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 267464#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 267458#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 267451#L498-33 assume !(1 == ~t2_pc~0); 267443#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 267437#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 267429#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 267422#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 267417#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 267015#L517-33 assume !(1 == ~t3_pc~0); 267013#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 267011#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 267010#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 267009#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 267008#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 267007#L536-33 assume 1 == ~t4_pc~0; 267005#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 267004#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 267003#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 267002#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 267000#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 266998#L555-33 assume !(1 == ~t5_pc~0); 266996#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 266994#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 266992#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 266990#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 266988#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 266985#L574-33 assume 1 == ~t6_pc~0; 266982#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 266980#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 266978#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 266976#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 266974#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 266972#L593-33 assume !(1 == ~t7_pc~0); 241876#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 266969#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 266967#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 266965#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 266963#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 266960#L612-33 assume !(1 == ~t8_pc~0); 266957#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 266955#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 266953#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 266951#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 266949#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 266948#L631-33 assume 1 == ~t9_pc~0; 266945#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 266943#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 266941#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 266939#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 266937#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 266934#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 266930#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 266928#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 266926#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 266924#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 266920#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 266917#L1072-3 assume !(1 == ~T6_E~0); 266915#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 266913#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 266911#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 266909#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 266907#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 266905#L1102-3 assume !(1 == ~E_2~0); 266903#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 266901#L1112-3 assume !(1 == ~E_4~0); 266899#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 266897#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 266895#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 266893#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 266891#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 266889#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 266877#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 266870#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 266868#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 266864#L1447 assume !(0 == start_simulation_~tmp~3#1); 266863#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 266858#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 266852#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 266851#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 266850#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 266849#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 266848#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 266847#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 266845#L1428-2 [2023-11-19 07:59:26,267 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:26,267 INFO L85 PathProgramCache]: Analyzing trace with hash -589339000, now seen corresponding path program 1 times [2023-11-19 07:59:26,267 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:26,267 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2043718732] [2023-11-19 07:59:26,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:26,268 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:26,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:26,383 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:26,384 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:26,384 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2043718732] [2023-11-19 07:59:26,384 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2043718732] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:26,385 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:26,385 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:26,385 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [502727178] [2023-11-19 07:59:26,385 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:26,386 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:26,386 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:26,386 INFO L85 PathProgramCache]: Analyzing trace with hash 1963603987, now seen corresponding path program 1 times [2023-11-19 07:59:26,386 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:26,387 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1585192079] [2023-11-19 07:59:26,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:26,387 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:26,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:26,453 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:26,454 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:26,454 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1585192079] [2023-11-19 07:59:26,454 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1585192079] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:26,454 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:26,455 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:26,455 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1832706106] [2023-11-19 07:59:26,455 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:26,456 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:26,456 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:26,456 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:59:26,456 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:59:26,457 INFO L87 Difference]: Start difference. First operand 51390 states and 72360 transitions. cyclomatic complexity: 20978 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:27,409 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:27,409 INFO L93 Difference]: Finished difference Result 121981 states and 170533 transitions. [2023-11-19 07:59:27,410 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 121981 states and 170533 transitions. [2023-11-19 07:59:28,325 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 119248 [2023-11-19 07:59:28,776 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 121981 states to 121981 states and 170533 transitions. [2023-11-19 07:59:28,776 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 121981 [2023-11-19 07:59:28,852 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 121981 [2023-11-19 07:59:28,853 INFO L73 IsDeterministic]: Start isDeterministic. Operand 121981 states and 170533 transitions. [2023-11-19 07:59:29,214 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:29,215 INFO L218 hiAutomatonCegarLoop]: Abstraction has 121981 states and 170533 transitions. [2023-11-19 07:59:29,306 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121981 states and 170533 transitions. [2023-11-19 07:59:30,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121981 to 97485. [2023-11-19 07:59:30,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97485 states, 97485 states have (on average 1.4031799764066266) internal successors, (136789), 97484 states have internal predecessors, (136789), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:30,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97485 states to 97485 states and 136789 transitions. [2023-11-19 07:59:30,990 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97485 states and 136789 transitions. [2023-11-19 07:59:30,990 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:59:30,991 INFO L428 stractBuchiCegarLoop]: Abstraction has 97485 states and 136789 transitions. [2023-11-19 07:59:30,991 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-19 07:59:30,991 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97485 states and 136789 transitions. [2023-11-19 07:59:31,287 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 97152 [2023-11-19 07:59:31,287 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:31,287 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:31,292 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:31,293 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:31,293 INFO L748 eck$LassoCheckResult]: Stem: 395921#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 395922#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 396816#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 396817#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 396717#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 396313#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 396314#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 396682#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 396091#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 396092#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 396594#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 396595#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 395592#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 395593#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 395792#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 396199#L939 assume !(0 == ~M_E~0); 396479#L939-2 assume !(0 == ~T1_E~0); 396480#L944-1 assume !(0 == ~T2_E~0); 396236#L949-1 assume !(0 == ~T3_E~0); 396232#L954-1 assume !(0 == ~T4_E~0); 396233#L959-1 assume !(0 == ~T5_E~0); 396736#L964-1 assume !(0 == ~T6_E~0); 395946#L969-1 assume !(0 == ~T7_E~0); 395947#L974-1 assume !(0 == ~T8_E~0); 396668#L979-1 assume !(0 == ~T9_E~0); 396669#L984-1 assume !(0 == ~E_M~0); 396105#L989-1 assume !(0 == ~E_1~0); 396106#L994-1 assume !(0 == ~E_2~0); 395993#L999-1 assume !(0 == ~E_3~0); 395994#L1004-1 assume !(0 == ~E_4~0); 395658#L1009-1 assume !(0 == ~E_5~0); 395659#L1014-1 assume !(0 == ~E_6~0); 395988#L1019-1 assume !(0 == ~E_7~0); 396602#L1024-1 assume !(0 == ~E_8~0); 395916#L1029-1 assume !(0 == ~E_9~0); 395917#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 396000#L460 assume !(1 == ~m_pc~0); 396879#L460-2 is_master_triggered_~__retres1~0#1 := 0; 396561#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 396562#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 396698#L1167 assume !(0 != activate_threads_~tmp~1#1); 396217#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 396218#L479 assume !(1 == ~t1_pc~0); 396389#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 396390#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 395662#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 395663#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 395929#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 395771#L498 assume !(1 == ~t2_pc~0); 395772#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 396198#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 396095#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 396096#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 396551#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 396552#L517 assume !(1 == ~t3_pc~0); 396933#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 396934#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 395599#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 395600#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 395965#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 396609#L536 assume !(1 == ~t4_pc~0); 396266#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 396265#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 395753#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 395754#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 396258#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 396522#L555 assume !(1 == ~t5_pc~0); 396523#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 396603#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 396666#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 395918#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 395797#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 395697#L574 assume !(1 == ~t6_pc~0); 395698#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 396373#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 396085#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 396086#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 396629#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 396888#L593 assume !(1 == ~t7_pc~0); 395936#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 395937#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 396741#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 396939#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 396839#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 396100#L612 assume !(1 == ~t8_pc~0); 396101#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 396581#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 396634#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 396635#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 396375#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 396376#L631 assume !(1 == ~t9_pc~0); 396447#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 395689#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 395690#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 396145#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 396200#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 396612#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 396613#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 396368#L1052-1 assume !(1 == ~T2_E~0); 396369#L1057-1 assume !(1 == ~T3_E~0); 395901#L1062-1 assume !(1 == ~T4_E~0); 395902#L1067-1 assume !(1 == ~T5_E~0); 396221#L1072-1 assume !(1 == ~T6_E~0); 396222#L1077-1 assume !(1 == ~T7_E~0); 395786#L1082-1 assume !(1 == ~T8_E~0); 395787#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 395586#L1092-1 assume !(1 == ~E_M~0); 395587#L1097-1 assume !(1 == ~E_1~0); 396871#L1102-1 assume !(1 == ~E_2~0); 396872#L1107-1 assume !(1 == ~E_3~0); 396371#L1112-1 assume !(1 == ~E_4~0); 396372#L1117-1 assume !(1 == ~E_5~0); 396964#L1122-1 assume !(1 == ~E_6~0); 396965#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 396005#L1132-1 assume !(1 == ~E_8~0); 396006#L1137-1 assume !(1 == ~E_9~0); 395897#L1142-1 assume { :end_inline_reset_delta_events } true; 395898#L1428-2 [2023-11-19 07:59:31,294 INFO L750 eck$LassoCheckResult]: Loop: 395898#L1428-2 assume !false; 481934#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 481932#L914-1 assume !false; 481930#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 481925#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 481915#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 481913#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 481910#L783 assume !(0 != eval_~tmp~0#1); 481911#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 493066#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 493065#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 395812#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 395813#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 493064#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 396686#L954-3 assume !(0 == ~T4_E~0); 396687#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 493063#L964-3 assume !(0 == ~T6_E~0); 493062#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 493061#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 493060#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 493059#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 493058#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 493057#L994-3 assume !(0 == ~E_2~0); 493056#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 493055#L1004-3 assume !(0 == ~E_4~0); 395738#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 395739#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 492932#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 492930#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 492928#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 492926#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 492868#L460-33 assume !(1 == ~m_pc~0); 492867#L460-35 is_master_triggered_~__retres1~0#1 := 0; 492865#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 492863#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 492848#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 492847#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 492846#L479-33 assume !(1 == ~t1_pc~0); 485483#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 492845#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 492844#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 492843#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 492842#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 492841#L498-33 assume !(1 == ~t2_pc~0); 492839#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 492838#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 492837#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 492836#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 492834#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 482270#L517-33 assume !(1 == ~t3_pc~0); 482268#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 482266#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 482264#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 482262#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 482260#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 482257#L536-33 assume !(1 == ~t4_pc~0); 482255#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 482252#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 482250#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 482248#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 482246#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 482244#L555-33 assume !(1 == ~t5_pc~0); 482242#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 482240#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 482238#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 482236#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 482234#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 482231#L574-33 assume !(1 == ~t6_pc~0); 482229#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 482226#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 482224#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 482222#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 482220#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 482219#L593-33 assume !(1 == ~t7_pc~0); 481298#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 482216#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 482214#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 482212#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 482210#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 482207#L612-33 assume 1 == ~t8_pc~0; 482205#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 482202#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 482200#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 482198#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 482196#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 482195#L631-33 assume !(1 == ~t9_pc~0); 408974#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 482192#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 482190#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 482188#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 482187#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 482183#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 470647#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 482180#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 482177#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 482176#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 470637#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 482175#L1072-3 assume !(1 == ~T6_E~0); 482173#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 482172#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 482170#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 482169#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 482168#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 482167#L1102-3 assume !(1 == ~E_2~0); 482166#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 482165#L1112-3 assume !(1 == ~E_4~0); 482164#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 482163#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 482162#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 482161#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 482160#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 482159#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 482154#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 482148#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 482147#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 482020#L1447 assume !(0 == start_simulation_~tmp~3#1); 482018#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 482006#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 481998#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 481996#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 481994#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 481992#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 481990#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 481988#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 395898#L1428-2 [2023-11-19 07:59:31,294 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:31,295 INFO L85 PathProgramCache]: Analyzing trace with hash 2033110665, now seen corresponding path program 1 times [2023-11-19 07:59:31,295 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:31,295 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [176442193] [2023-11-19 07:59:31,295 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:31,296 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:31,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:31,395 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:31,395 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:31,395 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [176442193] [2023-11-19 07:59:31,395 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [176442193] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:31,396 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:31,396 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:59:31,396 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [914868587] [2023-11-19 07:59:31,396 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:31,397 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:31,397 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:31,397 INFO L85 PathProgramCache]: Analyzing trace with hash -1036917803, now seen corresponding path program 1 times [2023-11-19 07:59:31,398 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:31,398 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [942198270] [2023-11-19 07:59:31,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:31,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:31,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:31,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:31,489 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:31,489 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [942198270] [2023-11-19 07:59:31,489 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [942198270] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:31,489 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:31,489 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:59:31,490 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [56147259] [2023-11-19 07:59:31,490 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:31,490 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:31,490 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:31,491 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:59:31,491 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:59:31,491 INFO L87 Difference]: Start difference. First operand 97485 states and 136789 transitions. cyclomatic complexity: 39312 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:32,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:32,646 INFO L93 Difference]: Finished difference Result 144585 states and 203180 transitions. [2023-11-19 07:59:32,646 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 144585 states and 203180 transitions. [2023-11-19 07:59:33,784 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 144160 [2023-11-19 07:59:34,234 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 144585 states to 144585 states and 203180 transitions. [2023-11-19 07:59:34,234 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 144585 [2023-11-19 07:59:34,315 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 144585 [2023-11-19 07:59:34,315 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144585 states and 203180 transitions. [2023-11-19 07:59:34,473 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:34,473 INFO L218 hiAutomatonCegarLoop]: Abstraction has 144585 states and 203180 transitions. [2023-11-19 07:59:34,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144585 states and 203180 transitions. [2023-11-19 07:59:35,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144585 to 98745. [2023-11-19 07:59:35,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98745 states, 98745 states have (on average 1.4088612081624385) internal successors, (139118), 98744 states have internal predecessors, (139118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:36,188 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98745 states to 98745 states and 139118 transitions. [2023-11-19 07:59:36,188 INFO L240 hiAutomatonCegarLoop]: Abstraction has 98745 states and 139118 transitions. [2023-11-19 07:59:36,189 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:59:36,189 INFO L428 stractBuchiCegarLoop]: Abstraction has 98745 states and 139118 transitions. [2023-11-19 07:59:36,190 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-19 07:59:36,190 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98745 states and 139118 transitions. [2023-11-19 07:59:36,505 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 98432 [2023-11-19 07:59:36,505 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:36,505 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:36,511 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:36,511 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:36,512 INFO L748 eck$LassoCheckResult]: Stem: 638002#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 638003#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 638921#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 638922#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 638818#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 638413#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 638414#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 638789#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 638180#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 638181#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 638693#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 638694#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 637671#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 637672#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 637874#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 638292#L939 assume !(0 == ~M_E~0); 638576#L939-2 assume !(0 == ~T1_E~0); 638577#L944-1 assume !(0 == ~T2_E~0); 638333#L949-1 assume !(0 == ~T3_E~0); 638329#L954-1 assume !(0 == ~T4_E~0); 638330#L959-1 assume !(0 == ~T5_E~0); 638839#L964-1 assume !(0 == ~T6_E~0); 638025#L969-1 assume !(0 == ~T7_E~0); 638026#L974-1 assume !(0 == ~T8_E~0); 638769#L979-1 assume !(0 == ~T9_E~0); 638770#L984-1 assume !(0 == ~E_M~0); 638195#L989-1 assume !(0 == ~E_1~0); 638196#L994-1 assume !(0 == ~E_2~0); 638078#L999-1 assume !(0 == ~E_3~0); 638079#L1004-1 assume !(0 == ~E_4~0); 637738#L1009-1 assume !(0 == ~E_5~0); 637739#L1014-1 assume !(0 == ~E_6~0); 638075#L1019-1 assume !(0 == ~E_7~0); 638699#L1024-1 assume !(0 == ~E_8~0); 637995#L1029-1 assume !(0 == ~E_9~0); 637996#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 638088#L460 assume !(1 == ~m_pc~0); 638964#L460-2 is_master_triggered_~__retres1~0#1 := 0; 638657#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 638658#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 638801#L1167 assume !(0 != activate_threads_~tmp~1#1); 638314#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 638315#L479 assume !(1 == ~t1_pc~0); 638487#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 638488#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 637744#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 637745#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 638010#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 637853#L498 assume !(1 == ~t2_pc~0); 637854#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 638291#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 638182#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 638183#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 638644#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 638645#L517 assume !(1 == ~t3_pc~0); 639021#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 639022#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 637678#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 637679#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 638046#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 638710#L536 assume !(1 == ~t4_pc~0); 638363#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 638362#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 637839#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 637840#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 638357#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 638625#L555 assume !(1 == ~t5_pc~0); 638626#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 638700#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 638764#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 637999#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 637881#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 637777#L574 assume !(1 == ~t6_pc~0); 637778#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 638469#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 638171#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 638172#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 638727#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 638972#L593 assume !(1 == ~t7_pc~0); 638015#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 638016#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 638844#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 639028#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 638939#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 638188#L612 assume !(1 == ~t8_pc~0); 638189#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 638680#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 638732#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 638733#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 638471#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 638472#L631 assume !(1 == ~t9_pc~0); 638542#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 637768#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 637769#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 638237#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 638293#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 638711#L1047 assume !(1 == ~M_E~0); 637707#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 637708#L1052-1 assume !(1 == ~T2_E~0); 637688#L1057-1 assume !(1 == ~T3_E~0); 637689#L1062-1 assume !(1 == ~T4_E~0); 637980#L1067-1 assume !(1 == ~T5_E~0); 638318#L1072-1 assume !(1 == ~T6_E~0); 638319#L1077-1 assume !(1 == ~T7_E~0); 637868#L1082-1 assume !(1 == ~T8_E~0); 637869#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 637667#L1092-1 assume !(1 == ~E_M~0); 637668#L1097-1 assume !(1 == ~E_1~0); 637690#L1102-1 assume !(1 == ~E_2~0); 638538#L1107-1 assume !(1 == ~E_3~0); 638467#L1112-1 assume !(1 == ~E_4~0); 638468#L1117-1 assume !(1 == ~E_5~0); 638511#L1122-1 assume !(1 == ~E_6~0); 638379#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 638091#L1132-1 assume !(1 == ~E_8~0); 638092#L1137-1 assume !(1 == ~E_9~0); 637978#L1142-1 assume { :end_inline_reset_delta_events } true; 637979#L1428-2 [2023-11-19 07:59:36,512 INFO L750 eck$LassoCheckResult]: Loop: 637979#L1428-2 assume !false; 679670#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 679665#L914-1 assume !false; 679568#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 679565#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 679556#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 679554#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 679552#L783 assume !(0 != eval_~tmp~0#1); 679553#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 684988#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 684985#L939-3 assume !(0 == ~M_E~0); 684979#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 684974#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 684969#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 684963#L954-3 assume !(0 == ~T4_E~0); 684958#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 684954#L964-3 assume !(0 == ~T6_E~0); 684950#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 684946#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 684941#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 684935#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 684929#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 684923#L994-3 assume !(0 == ~E_2~0); 684916#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 684911#L1004-3 assume !(0 == ~E_4~0); 684906#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 684902#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 684898#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 684893#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 684888#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 684884#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 684880#L460-33 assume !(1 == ~m_pc~0); 684873#L460-35 is_master_triggered_~__retres1~0#1 := 0; 684868#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 684864#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 684861#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 684857#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 684853#L479-33 assume !(1 == ~t1_pc~0); 683756#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 684847#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 684844#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 684841#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 684838#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 684835#L498-33 assume !(1 == ~t2_pc~0); 684832#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 684829#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 684827#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 684823#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 684819#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 684813#L517-33 assume !(1 == ~t3_pc~0); 670071#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 684803#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 684799#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 684795#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 684789#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 684785#L536-33 assume 1 == ~t4_pc~0; 684780#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 684776#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 684773#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 684769#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 684765#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 684760#L555-33 assume !(1 == ~t5_pc~0); 684756#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 684752#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 684749#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 684745#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 684742#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 684738#L574-33 assume 1 == ~t6_pc~0; 684734#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 684731#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 684727#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 684724#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 684721#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 684718#L593-33 assume !(1 == ~t7_pc~0); 661381#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 684715#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 684711#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 684708#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 684705#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 684701#L612-33 assume 1 == ~t8_pc~0; 684698#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 684693#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 684691#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 684686#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 684684#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 684682#L631-33 assume !(1 == ~t9_pc~0); 660627#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 684681#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 684679#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 684674#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 684671#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 684668#L1047-3 assume !(1 == ~M_E~0); 667709#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 684663#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 684660#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 684653#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 684649#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 684646#L1072-3 assume !(1 == ~T6_E~0); 684643#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 684640#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 684636#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 684629#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 684624#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 684619#L1102-3 assume !(1 == ~E_2~0); 684614#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 684609#L1112-3 assume !(1 == ~E_4~0); 684604#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 684599#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 684595#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 684590#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 684586#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 684583#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 684525#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 684515#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 684509#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 638251#L1447 assume !(0 == start_simulation_~tmp~3#1); 638252#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 679855#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 679848#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 679846#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 679844#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 679842#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 679839#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 679837#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 637979#L1428-2 [2023-11-19 07:59:36,513 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:36,514 INFO L85 PathProgramCache]: Analyzing trace with hash -1839154805, now seen corresponding path program 1 times [2023-11-19 07:59:36,514 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:36,514 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1765856758] [2023-11-19 07:59:36,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:36,515 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:36,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:36,598 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:36,598 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:36,598 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1765856758] [2023-11-19 07:59:36,599 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1765856758] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:36,599 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:36,599 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:59:36,599 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1228023558] [2023-11-19 07:59:36,599 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:36,600 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:36,600 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:36,600 INFO L85 PathProgramCache]: Analyzing trace with hash -485314285, now seen corresponding path program 1 times [2023-11-19 07:59:36,601 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:36,601 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2128106046] [2023-11-19 07:59:36,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:36,601 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:36,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:36,653 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:36,653 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:36,653 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2128106046] [2023-11-19 07:59:36,654 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2128106046] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:36,654 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:36,654 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:36,654 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1770422232] [2023-11-19 07:59:36,654 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:36,655 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:36,655 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:36,655 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:59:36,655 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:59:36,656 INFO L87 Difference]: Start difference. First operand 98745 states and 139118 transitions. cyclomatic complexity: 40377 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:37,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:37,858 INFO L93 Difference]: Finished difference Result 98745 states and 138732 transitions. [2023-11-19 07:59:37,858 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 98745 states and 138732 transitions. [2023-11-19 07:59:38,434 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 98432 [2023-11-19 07:59:38,809 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 98745 states to 98745 states and 138732 transitions. [2023-11-19 07:59:38,811 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 98745 [2023-11-19 07:59:38,879 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 98745 [2023-11-19 07:59:38,879 INFO L73 IsDeterministic]: Start isDeterministic. Operand 98745 states and 138732 transitions. [2023-11-19 07:59:38,940 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:38,941 INFO L218 hiAutomatonCegarLoop]: Abstraction has 98745 states and 138732 transitions. [2023-11-19 07:59:39,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98745 states and 138732 transitions. [2023-11-19 07:59:40,595 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98745 to 98745. [2023-11-19 07:59:40,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98745 states, 98745 states have (on average 1.4049521494759227) internal successors, (138732), 98744 states have internal predecessors, (138732), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:40,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98745 states to 98745 states and 138732 transitions. [2023-11-19 07:59:40,865 INFO L240 hiAutomatonCegarLoop]: Abstraction has 98745 states and 138732 transitions. [2023-11-19 07:59:40,865 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:59:40,866 INFO L428 stractBuchiCegarLoop]: Abstraction has 98745 states and 138732 transitions. [2023-11-19 07:59:40,866 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-19 07:59:40,866 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98745 states and 138732 transitions. [2023-11-19 07:59:41,165 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 98432 [2023-11-19 07:59:41,165 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:41,166 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:41,172 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:41,173 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:41,174 INFO L748 eck$LassoCheckResult]: Stem: 835498#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 835499#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 836409#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 836410#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 836307#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 835905#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 835906#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 836279#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 835679#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 835680#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 836185#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 836186#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 835168#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 835169#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 835371#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 835784#L939 assume !(0 == ~M_E~0); 836071#L939-2 assume !(0 == ~T1_E~0); 836072#L944-1 assume !(0 == ~T2_E~0); 835824#L949-1 assume !(0 == ~T3_E~0); 835822#L954-1 assume !(0 == ~T4_E~0); 835823#L959-1 assume !(0 == ~T5_E~0); 836328#L964-1 assume !(0 == ~T6_E~0); 835522#L969-1 assume !(0 == ~T7_E~0); 835523#L974-1 assume !(0 == ~T8_E~0); 836264#L979-1 assume !(0 == ~T9_E~0); 836265#L984-1 assume !(0 == ~E_M~0); 835693#L989-1 assume !(0 == ~E_1~0); 835694#L994-1 assume !(0 == ~E_2~0); 835574#L999-1 assume !(0 == ~E_3~0); 835575#L1004-1 assume !(0 == ~E_4~0); 835237#L1009-1 assume !(0 == ~E_5~0); 835238#L1014-1 assume !(0 == ~E_6~0); 835571#L1019-1 assume !(0 == ~E_7~0); 836191#L1024-1 assume !(0 == ~E_8~0); 835491#L1029-1 assume !(0 == ~E_9~0); 835492#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 835584#L460 assume !(1 == ~m_pc~0); 836464#L460-2 is_master_triggered_~__retres1~0#1 := 0; 836150#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 836151#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 836292#L1167 assume !(0 != activate_threads_~tmp~1#1); 835807#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 835808#L479 assume !(1 == ~t1_pc~0); 835979#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 835980#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 835243#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 835244#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 835506#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 835350#L498 assume !(1 == ~t2_pc~0); 835351#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 835783#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 835681#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 835682#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 836140#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 836141#L517 assume !(1 == ~t3_pc~0); 836522#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 836523#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 835175#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 835176#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 835543#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 836201#L536 assume !(1 == ~t4_pc~0); 835854#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 835853#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 835336#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 835337#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 835848#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 836117#L555 assume !(1 == ~t5_pc~0); 836118#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 836192#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 836258#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 835495#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 835378#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 835275#L574 assume !(1 == ~t6_pc~0); 835276#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 835960#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 835670#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 835671#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 836222#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 836472#L593 assume !(1 == ~t7_pc~0); 835511#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 835512#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 836333#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 836529#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 836428#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 835686#L612 assume !(1 == ~t8_pc~0); 835687#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 836173#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 836227#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 836228#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 835962#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 835963#L631 assume !(1 == ~t9_pc~0); 836034#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 835266#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 835267#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 835732#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 835785#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 836202#L1047 assume !(1 == ~M_E~0); 835204#L1047-2 assume !(1 == ~T1_E~0); 835205#L1052-1 assume !(1 == ~T2_E~0); 835185#L1057-1 assume !(1 == ~T3_E~0); 835186#L1062-1 assume !(1 == ~T4_E~0); 835477#L1067-1 assume !(1 == ~T5_E~0); 835811#L1072-1 assume !(1 == ~T6_E~0); 835812#L1077-1 assume !(1 == ~T7_E~0); 835365#L1082-1 assume !(1 == ~T8_E~0); 835366#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 835164#L1092-1 assume !(1 == ~E_M~0); 835165#L1097-1 assume !(1 == ~E_1~0); 835187#L1102-1 assume !(1 == ~E_2~0); 836030#L1107-1 assume !(1 == ~E_3~0); 835958#L1112-1 assume !(1 == ~E_4~0); 835959#L1117-1 assume !(1 == ~E_5~0); 836001#L1122-1 assume !(1 == ~E_6~0); 835870#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 835587#L1132-1 assume !(1 == ~E_8~0); 835588#L1137-1 assume !(1 == ~E_9~0); 835475#L1142-1 assume { :end_inline_reset_delta_events } true; 835476#L1428-2 [2023-11-19 07:59:41,175 INFO L750 eck$LassoCheckResult]: Loop: 835476#L1428-2 assume !false; 871157#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 871153#L914-1 assume !false; 871148#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 870929#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 870914#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 870906#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 870899#L783 assume !(0 != eval_~tmp~0#1); 870900#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 931767#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 931765#L939-3 assume !(0 == ~M_E~0); 931766#L939-5 assume !(0 == ~T1_E~0); 931877#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 931876#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 931875#L954-3 assume !(0 == ~T4_E~0); 931874#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 931873#L964-3 assume !(0 == ~T6_E~0); 931872#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 931871#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 931870#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 931869#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 931868#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 931867#L994-3 assume !(0 == ~E_2~0); 931866#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 931865#L1004-3 assume !(0 == ~E_4~0); 931864#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 931863#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 931862#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 931861#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 931860#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 931859#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 931858#L460-33 assume !(1 == ~m_pc~0); 931857#L460-35 is_master_triggered_~__retres1~0#1 := 0; 931856#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 931855#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 931854#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 930903#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 835526#L479-33 assume !(1 == ~t1_pc~0); 835527#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 836266#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 836517#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 836390#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 836391#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 835538#L498-33 assume !(1 == ~t2_pc~0); 835278#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 835279#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 835766#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 836197#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 931699#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 836490#L517-33 assume !(1 == ~t3_pc~0); 836491#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 836297#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 835348#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 835349#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 836061#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 835622#L536-33 assume !(1 == ~t4_pc~0); 835624#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 835707#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 835708#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 836458#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 930414#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 930410#L555-33 assume !(1 == ~t5_pc~0); 930406#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 930401#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 930396#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 930392#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 930387#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 930384#L574-33 assume 1 == ~t6_pc~0; 930380#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 930365#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 930362#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 930363#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 931644#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 871573#L593-33 assume !(1 == ~t7_pc~0); 871557#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 871553#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 871547#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 871542#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 871537#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 871532#L612-33 assume 1 == ~t8_pc~0; 871527#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 871519#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 871513#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 871508#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 871503#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 871498#L631-33 assume !(1 == ~t9_pc~0); 856721#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 871489#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 871482#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 871476#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 871470#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 871464#L1047-3 assume !(1 == ~M_E~0); 871458#L1047-5 assume !(1 == ~T1_E~0); 871455#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 871451#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 871447#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 871442#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 871437#L1072-3 assume !(1 == ~T6_E~0); 871431#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 871425#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 871420#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 871413#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 871404#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 871397#L1102-3 assume !(1 == ~E_2~0); 871391#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 871387#L1112-3 assume !(1 == ~E_4~0); 871383#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 871379#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 871375#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 871370#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 871366#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 871364#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 871329#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 871319#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 871313#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 871307#L1447 assume !(0 == start_simulation_~tmp~3#1); 871304#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 871228#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 871208#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 871202#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 871193#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 871187#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 871182#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 871174#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 835476#L1428-2 [2023-11-19 07:59:41,175 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:41,176 INFO L85 PathProgramCache]: Analyzing trace with hash 1638164041, now seen corresponding path program 1 times [2023-11-19 07:59:41,176 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:41,176 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1624082043] [2023-11-19 07:59:41,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:41,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:41,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:41,288 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:41,288 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:41,289 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1624082043] [2023-11-19 07:59:41,289 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1624082043] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:41,289 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:41,289 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:41,289 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1000511392] [2023-11-19 07:59:41,290 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:41,290 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:41,290 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:41,291 INFO L85 PathProgramCache]: Analyzing trace with hash -1640748140, now seen corresponding path program 1 times [2023-11-19 07:59:41,291 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:41,291 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [572179986] [2023-11-19 07:59:41,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:41,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:41,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:41,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:41,377 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:41,377 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [572179986] [2023-11-19 07:59:41,378 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [572179986] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:41,378 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:41,378 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:59:41,378 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [569801291] [2023-11-19 07:59:41,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:41,379 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:41,379 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:41,380 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:59:41,380 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:59:41,380 INFO L87 Difference]: Start difference. First operand 98745 states and 138732 transitions. cyclomatic complexity: 39991 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:42,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:42,981 INFO L93 Difference]: Finished difference Result 155929 states and 218773 transitions. [2023-11-19 07:59:42,981 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 155929 states and 218773 transitions. [2023-11-19 07:59:43,593 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 155424 [2023-11-19 07:59:44,675 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 155929 states to 155929 states and 218773 transitions. [2023-11-19 07:59:44,675 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 155929 [2023-11-19 07:59:44,803 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 155929 [2023-11-19 07:59:44,803 INFO L73 IsDeterministic]: Start isDeterministic. Operand 155929 states and 218773 transitions. [2023-11-19 07:59:44,859 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:44,859 INFO L218 hiAutomatonCegarLoop]: Abstraction has 155929 states and 218773 transitions. [2023-11-19 07:59:44,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155929 states and 218773 transitions. [2023-11-19 07:59:45,732 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155929 to 110094. [2023-11-19 07:59:45,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 110094 states, 110094 states have (on average 1.4070975711664577) internal successors, (154913), 110093 states have internal predecessors, (154913), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:46,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110094 states to 110094 states and 154913 transitions. [2023-11-19 07:59:46,709 INFO L240 hiAutomatonCegarLoop]: Abstraction has 110094 states and 154913 transitions. [2023-11-19 07:59:46,710 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:59:46,710 INFO L428 stractBuchiCegarLoop]: Abstraction has 110094 states and 154913 transitions. [2023-11-19 07:59:46,710 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-19 07:59:46,711 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 110094 states and 154913 transitions. [2023-11-19 07:59:47,003 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 109696 [2023-11-19 07:59:47,003 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:47,003 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:47,016 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:47,017 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:59:47,018 INFO L748 eck$LassoCheckResult]: Stem: 1090185#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1090186#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1091129#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1091130#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1091026#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 1090600#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1090601#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1090988#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1090365#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1090366#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1090883#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1090884#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1089854#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1089855#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1090056#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1090476#L939 assume !(0 == ~M_E~0); 1090762#L939-2 assume !(0 == ~T1_E~0); 1090763#L944-1 assume !(0 == ~T2_E~0); 1090519#L949-1 assume !(0 == ~T3_E~0); 1090517#L954-1 assume !(0 == ~T4_E~0); 1090518#L959-1 assume !(0 == ~T5_E~0); 1091048#L964-1 assume !(0 == ~T6_E~0); 1090209#L969-1 assume !(0 == ~T7_E~0); 1090210#L974-1 assume !(0 == ~T8_E~0); 1090973#L979-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1090974#L984-1 assume !(0 == ~E_M~0); 1090379#L989-1 assume !(0 == ~E_1~0); 1090380#L994-1 assume !(0 == ~E_2~0); 1090262#L999-1 assume !(0 == ~E_3~0); 1090263#L1004-1 assume !(0 == ~E_4~0); 1089921#L1009-1 assume !(0 == ~E_5~0); 1089922#L1014-1 assume !(0 == ~E_6~0); 1090259#L1019-1 assume !(0 == ~E_7~0); 1091315#L1024-1 assume !(0 == ~E_8~0); 1090178#L1029-1 assume !(0 == ~E_9~0); 1090179#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1090272#L460 assume !(1 == ~m_pc~0); 1091180#L460-2 is_master_triggered_~__retres1~0#1 := 0; 1090845#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1090846#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1091215#L1167 assume !(0 != activate_threads_~tmp~1#1); 1091216#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1091312#L479 assume !(1 == ~t1_pc~0); 1091311#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1091229#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1091230#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1090193#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 1090194#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1090034#L498 assume !(1 == ~t2_pc~0); 1090035#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1090474#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1090475#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1090936#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 1090937#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1091277#L517 assume !(1 == ~t3_pc~0); 1091278#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1091250#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1091251#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1090229#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 1090230#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1091309#L536 assume !(1 == ~t4_pc~0); 1090551#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1090550#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1090019#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1090020#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 1091263#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1091264#L555 assume !(1 == ~t5_pc~0); 1090891#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1090892#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1091007#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1091008#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 1091308#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1091307#L574 assume !(1 == ~t6_pc~0); 1090655#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1090656#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1090356#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1090357#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 1091266#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1091191#L593 assume !(1 == ~t7_pc~0); 1091192#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1091305#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1091260#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1091261#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 1091304#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1090372#L612 assume !(1 == ~t8_pc~0); 1090373#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1091303#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1090938#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1090939#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 1090659#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1090660#L631 assume !(1 == ~t9_pc~0); 1090732#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1091299#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1090419#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1090420#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 1091239#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1091240#L1047 assume !(1 == ~M_E~0); 1089890#L1047-2 assume !(1 == ~T1_E~0); 1089891#L1052-1 assume !(1 == ~T2_E~0); 1089871#L1057-1 assume !(1 == ~T3_E~0); 1089872#L1062-1 assume !(1 == ~T4_E~0); 1091296#L1067-1 assume !(1 == ~T5_E~0); 1090504#L1072-1 assume !(1 == ~T6_E~0); 1090505#L1077-1 assume !(1 == ~T7_E~0); 1091295#L1082-1 assume !(1 == ~T8_E~0); 1091294#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1089850#L1092-1 assume !(1 == ~E_M~0); 1089851#L1097-1 assume !(1 == ~E_1~0); 1089873#L1102-1 assume !(1 == ~E_2~0); 1090727#L1107-1 assume !(1 == ~E_3~0); 1090652#L1112-1 assume !(1 == ~E_4~0); 1090653#L1117-1 assume !(1 == ~E_5~0); 1090701#L1122-1 assume !(1 == ~E_6~0); 1090568#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1090275#L1132-1 assume !(1 == ~E_8~0); 1090276#L1137-1 assume !(1 == ~E_9~0); 1090161#L1142-1 assume { :end_inline_reset_delta_events } true; 1090162#L1428-2 [2023-11-19 07:59:47,019 INFO L750 eck$LassoCheckResult]: Loop: 1090162#L1428-2 assume !false; 1135416#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1134415#L914-1 assume !false; 1135402#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1135258#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1135249#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1135245#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1135242#L783 assume !(0 != eval_~tmp~0#1); 1135243#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1140041#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1140034#L939-3 assume !(0 == ~M_E~0); 1140027#L939-5 assume !(0 == ~T1_E~0); 1140019#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1140018#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1140017#L954-3 assume !(0 == ~T4_E~0); 1140004#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1139997#L964-3 assume !(0 == ~T6_E~0); 1139990#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1139983#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1139967#L979-3 assume !(0 == ~T9_E~0); 1139968#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1143651#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1143650#L994-3 assume !(0 == ~E_2~0); 1143649#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1143648#L1004-3 assume !(0 == ~E_4~0); 1143647#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1143646#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1143645#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1143644#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1143643#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1143642#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1143641#L460-33 assume !(1 == ~m_pc~0); 1143640#L460-35 is_master_triggered_~__retres1~0#1 := 0; 1143639#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1143638#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1143637#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1143636#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1143635#L479-33 assume !(1 == ~t1_pc~0); 1142928#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1143634#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1143633#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1143631#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1143629#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1143627#L498-33 assume !(1 == ~t2_pc~0); 1143624#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1143622#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1143620#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1143618#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 1143616#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1140736#L517-33 assume !(1 == ~t3_pc~0); 1140735#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1140734#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1140733#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1140731#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1140729#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1140727#L536-33 assume !(1 == ~t4_pc~0); 1140725#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 1140722#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1140720#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1140718#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1140717#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1140715#L555-33 assume !(1 == ~t5_pc~0); 1140713#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1140711#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1140709#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1140706#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1140704#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1140702#L574-33 assume 1 == ~t6_pc~0; 1140699#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1140697#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1140695#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1140693#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 1140690#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1140688#L593-33 assume !(1 == ~t7_pc~0); 1139303#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1140685#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1140683#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1140681#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1140678#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1140676#L612-33 assume !(1 == ~t8_pc~0); 1140673#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 1140671#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1140669#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1140667#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1140665#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1140663#L631-33 assume !(1 == ~t9_pc~0); 1115589#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1140660#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1140658#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1140656#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1140655#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1140652#L1047-3 assume !(1 == ~M_E~0); 1113029#L1047-5 assume !(1 == ~T1_E~0); 1140649#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1140647#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1140645#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1127154#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1127152#L1072-3 assume !(1 == ~T6_E~0); 1127150#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1127148#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1123625#L1087-3 assume !(1 == ~T9_E~0); 1123622#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1123620#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1123618#L1102-3 assume !(1 == ~E_2~0); 1123616#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1123615#L1112-3 assume !(1 == ~E_4~0); 1123613#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1123611#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1123609#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1123607#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1123605#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1123602#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1123588#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1123581#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1123579#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1112871#L1447 assume !(0 == start_simulation_~tmp~3#1); 1112872#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1135478#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1135471#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1135469#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 1135467#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1135444#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1135437#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1135430#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 1090162#L1428-2 [2023-11-19 07:59:47,020 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:47,020 INFO L85 PathProgramCache]: Analyzing trace with hash -1773294265, now seen corresponding path program 1 times [2023-11-19 07:59:47,021 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:47,021 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1252979842] [2023-11-19 07:59:47,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:47,021 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:47,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:47,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:47,124 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:47,124 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1252979842] [2023-11-19 07:59:47,125 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1252979842] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:47,126 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:47,126 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:59:47,126 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [785584263] [2023-11-19 07:59:47,126 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:47,127 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:59:47,127 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:47,127 INFO L85 PathProgramCache]: Analyzing trace with hash 1765169429, now seen corresponding path program 1 times [2023-11-19 07:59:47,128 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:47,128 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1228093712] [2023-11-19 07:59:47,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:47,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:47,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:47,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:47,223 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:47,223 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1228093712] [2023-11-19 07:59:47,223 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1228093712] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:59:47,223 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:59:47,223 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:59:47,224 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [407121536] [2023-11-19 07:59:47,224 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:59:47,224 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:59:47,225 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:47,225 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:59:47,225 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:59:47,225 INFO L87 Difference]: Start difference. First operand 110094 states and 154913 transitions. cyclomatic complexity: 44823 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:47,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:47,843 INFO L93 Difference]: Finished difference Result 144569 states and 202122 transitions. [2023-11-19 07:59:47,843 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 144569 states and 202122 transitions. [2023-11-19 07:59:49,184 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 144160 [2023-11-19 07:59:49,441 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 144569 states to 144569 states and 202122 transitions. [2023-11-19 07:59:49,441 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 144569 [2023-11-19 07:59:49,489 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 144569 [2023-11-19 07:59:49,490 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144569 states and 202122 transitions. [2023-11-19 07:59:49,533 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:49,533 INFO L218 hiAutomatonCegarLoop]: Abstraction has 144569 states and 202122 transitions. [2023-11-19 07:59:49,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144569 states and 202122 transitions. [2023-11-19 07:59:51,029 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144569 to 98745. [2023-11-19 07:59:51,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98745 states, 98745 states have (on average 1.4010430907894071) internal successors, (138346), 98744 states have internal predecessors, (138346), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:51,394 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98745 states to 98745 states and 138346 transitions. [2023-11-19 07:59:51,394 INFO L240 hiAutomatonCegarLoop]: Abstraction has 98745 states and 138346 transitions. [2023-11-19 07:59:51,395 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:59:51,395 INFO L428 stractBuchiCegarLoop]: Abstraction has 98745 states and 138346 transitions. [2023-11-19 07:59:51,395 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-19 07:59:51,395 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98745 states and 138346 transitions.