./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.09.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 9bd2c7ff Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7a6ee040-3921-4f32-9908-fb759840cd23/bin/uautomizer-verify-uCwYo4JHxu/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7a6ee040-3921-4f32-9908-fb759840cd23/bin/uautomizer-verify-uCwYo4JHxu/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7a6ee040-3921-4f32-9908-fb759840cd23/bin/uautomizer-verify-uCwYo4JHxu/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7a6ee040-3921-4f32-9908-fb759840cd23/bin/uautomizer-verify-uCwYo4JHxu/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.09.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7a6ee040-3921-4f32-9908-fb759840cd23/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7a6ee040-3921-4f32-9908-fb759840cd23/bin/uautomizer-verify-uCwYo4JHxu --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ae06fa96255229a08f1e8c01eaa7f353b1ba462dacd64e058a3c6957598773d9 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-9bd2c7f [2023-11-19 08:02:33,457 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-19 08:02:33,527 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7a6ee040-3921-4f32-9908-fb759840cd23/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-19 08:02:33,533 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-19 08:02:33,533 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-19 08:02:33,560 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-19 08:02:33,561 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-19 08:02:33,561 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-19 08:02:33,562 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-19 08:02:33,563 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-19 08:02:33,564 INFO L153 SettingsManager]: * Use SBE=true [2023-11-19 08:02:33,564 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-19 08:02:33,565 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-19 08:02:33,565 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-19 08:02:33,566 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-19 08:02:33,566 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-19 08:02:33,567 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-19 08:02:33,568 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-19 08:02:33,568 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-19 08:02:33,569 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-19 08:02:33,569 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-19 08:02:33,570 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-19 08:02:33,570 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-19 08:02:33,571 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-19 08:02:33,571 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-19 08:02:33,572 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-19 08:02:33,572 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-19 08:02:33,572 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-19 08:02:33,573 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-19 08:02:33,573 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-19 08:02:33,574 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-19 08:02:33,574 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-19 08:02:33,574 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-19 08:02:33,575 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-19 08:02:33,575 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-19 08:02:33,579 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-19 08:02:33,580 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7a6ee040-3921-4f32-9908-fb759840cd23/bin/uautomizer-verify-uCwYo4JHxu/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7a6ee040-3921-4f32-9908-fb759840cd23/bin/uautomizer-verify-uCwYo4JHxu Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ae06fa96255229a08f1e8c01eaa7f353b1ba462dacd64e058a3c6957598773d9 [2023-11-19 08:02:33,825 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-19 08:02:33,848 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-19 08:02:33,851 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-19 08:02:33,852 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-19 08:02:33,853 INFO L274 PluginConnector]: CDTParser initialized [2023-11-19 08:02:33,854 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7a6ee040-3921-4f32-9908-fb759840cd23/bin/uautomizer-verify-uCwYo4JHxu/../../sv-benchmarks/c/systemc/token_ring.09.cil-2.c [2023-11-19 08:02:37,060 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-19 08:02:37,387 INFO L384 CDTParser]: Found 1 translation units. [2023-11-19 08:02:37,388 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7a6ee040-3921-4f32-9908-fb759840cd23/sv-benchmarks/c/systemc/token_ring.09.cil-2.c [2023-11-19 08:02:37,416 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7a6ee040-3921-4f32-9908-fb759840cd23/bin/uautomizer-verify-uCwYo4JHxu/data/1b7c05793/2715373d0e60491ca3946cc4f28b6d2c/FLAG45013d99a [2023-11-19 08:02:37,434 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7a6ee040-3921-4f32-9908-fb759840cd23/bin/uautomizer-verify-uCwYo4JHxu/data/1b7c05793/2715373d0e60491ca3946cc4f28b6d2c [2023-11-19 08:02:37,437 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-19 08:02:37,439 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-19 08:02:37,441 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-19 08:02:37,441 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-19 08:02:37,452 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-19 08:02:37,456 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 08:02:37" (1/1) ... [2023-11-19 08:02:37,457 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@14d65793 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:37, skipping insertion in model container [2023-11-19 08:02:37,457 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 08:02:37" (1/1) ... [2023-11-19 08:02:37,522 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-19 08:02:37,776 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 08:02:37,793 INFO L202 MainTranslator]: Completed pre-run [2023-11-19 08:02:37,864 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 08:02:37,885 INFO L206 MainTranslator]: Completed translation [2023-11-19 08:02:37,886 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:37 WrapperNode [2023-11-19 08:02:37,886 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-19 08:02:37,887 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-19 08:02:37,887 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-19 08:02:37,887 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-19 08:02:37,895 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:37" (1/1) ... [2023-11-19 08:02:37,909 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:37" (1/1) ... [2023-11-19 08:02:38,006 INFO L138 Inliner]: procedures = 46, calls = 60, calls flagged for inlining = 55, calls inlined = 185, statements flattened = 2792 [2023-11-19 08:02:38,006 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-19 08:02:38,007 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-19 08:02:38,008 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-19 08:02:38,008 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-19 08:02:38,018 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:37" (1/1) ... [2023-11-19 08:02:38,018 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:37" (1/1) ... [2023-11-19 08:02:38,044 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:37" (1/1) ... [2023-11-19 08:02:38,044 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:37" (1/1) ... [2023-11-19 08:02:38,107 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:37" (1/1) ... [2023-11-19 08:02:38,149 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:37" (1/1) ... [2023-11-19 08:02:38,158 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:37" (1/1) ... [2023-11-19 08:02:38,171 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:37" (1/1) ... [2023-11-19 08:02:38,239 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-19 08:02:38,241 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-19 08:02:38,241 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-19 08:02:38,241 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-19 08:02:38,242 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:37" (1/1) ... [2023-11-19 08:02:38,248 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 08:02:38,262 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7a6ee040-3921-4f32-9908-fb759840cd23/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 08:02:38,277 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7a6ee040-3921-4f32-9908-fb759840cd23/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 08:02:38,306 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7a6ee040-3921-4f32-9908-fb759840cd23/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-19 08:02:38,328 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-19 08:02:38,329 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-19 08:02:38,329 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-19 08:02:38,329 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-19 08:02:38,492 INFO L236 CfgBuilder]: Building ICFG [2023-11-19 08:02:38,496 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-19 08:02:40,402 INFO L277 CfgBuilder]: Performing block encoding [2023-11-19 08:02:40,430 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-19 08:02:40,430 INFO L302 CfgBuilder]: Removed 12 assume(true) statements. [2023-11-19 08:02:40,442 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 08:02:40 BoogieIcfgContainer [2023-11-19 08:02:40,443 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-19 08:02:40,444 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-19 08:02:40,444 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-19 08:02:40,448 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-19 08:02:40,449 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 08:02:40,449 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 08:02:37" (1/3) ... [2023-11-19 08:02:40,450 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@78b3a034 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 08:02:40, skipping insertion in model container [2023-11-19 08:02:40,450 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 08:02:40,450 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:37" (2/3) ... [2023-11-19 08:02:40,451 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@78b3a034 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 08:02:40, skipping insertion in model container [2023-11-19 08:02:40,451 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 08:02:40,451 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 08:02:40" (3/3) ... [2023-11-19 08:02:40,452 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.09.cil-2.c [2023-11-19 08:02:40,539 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-19 08:02:40,539 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-19 08:02:40,540 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-19 08:02:40,540 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-19 08:02:40,540 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-19 08:02:40,540 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-19 08:02:40,540 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-19 08:02:40,540 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-19 08:02:40,552 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1195 states, 1194 states have (on average 1.5058626465661642) internal successors, (1798), 1194 states have internal predecessors, (1798), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:40,647 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1064 [2023-11-19 08:02:40,647 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:40,648 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:40,670 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:40,671 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:40,671 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-19 08:02:40,675 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1195 states, 1194 states have (on average 1.5058626465661642) internal successors, (1798), 1194 states have internal predecessors, (1798), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:40,693 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1064 [2023-11-19 08:02:40,693 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:40,693 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:40,699 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:40,699 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:40,710 INFO L748 eck$LassoCheckResult]: Stem: 181#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1095#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 882#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1093#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 521#L670true assume !(1 == ~m_i~0);~m_st~0 := 2; 305#L670-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 841#L675-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 926#L680-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1032#L685-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 906#L690-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1182#L695-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 397#L700-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 386#L705-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 538#L710-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 255#L715-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 779#L951true assume !(0 == ~M_E~0); 112#L951-2true assume !(0 == ~T1_E~0); 194#L956-1true assume !(0 == ~T2_E~0); 1151#L961-1true assume !(0 == ~T3_E~0); 537#L966-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 657#L971-1true assume !(0 == ~T5_E~0); 1084#L976-1true assume !(0 == ~T6_E~0); 632#L981-1true assume !(0 == ~T7_E~0); 422#L986-1true assume !(0 == ~T8_E~0); 224#L991-1true assume !(0 == ~T9_E~0); 1125#L996-1true assume !(0 == ~E_M~0); 1004#L1001-1true assume !(0 == ~E_1~0); 585#L1006-1true assume 0 == ~E_2~0;~E_2~0 := 1; 927#L1011-1true assume !(0 == ~E_3~0); 962#L1016-1true assume !(0 == ~E_4~0); 1097#L1021-1true assume !(0 == ~E_5~0); 17#L1026-1true assume !(0 == ~E_6~0); 1161#L1031-1true assume !(0 == ~E_7~0); 545#L1036-1true assume !(0 == ~E_8~0); 542#L1041-1true assume !(0 == ~E_9~0); 853#L1046-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1086#L472true assume 1 == ~m_pc~0; 1041#L473true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 568#L483true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 754#is_master_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 578#L1179true assume !(0 != activate_threads_~tmp~1#1); 21#L1179-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 898#L491true assume 1 == ~t1_pc~0; 584#L492true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 644#L502true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9#L1187true assume !(0 != activate_threads_~tmp___0~0#1); 18#L1187-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 835#L510true assume !(1 == ~t2_pc~0); 4#L510-2true is_transmit2_triggered_~__retres1~2#1 := 0; 1001#L521true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 298#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1160#L1195true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 137#L1195-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 428#L529true assume 1 == ~t3_pc~0; 361#L530true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 769#L540true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1075#L1203true assume !(0 != activate_threads_~tmp___2~0#1); 100#L1203-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1126#L548true assume !(1 == ~t4_pc~0); 315#L548-2true is_transmit4_triggered_~__retres1~4#1 := 0; 201#L559true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 67#L1211true assume !(0 != activate_threads_~tmp___3~0#1); 642#L1211-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45#L567true assume 1 == ~t5_pc~0; 894#L568true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1100#L578true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 756#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1030#L1219true assume !(0 != activate_threads_~tmp___4~0#1); 831#L1219-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 105#L586true assume !(1 == ~t6_pc~0); 139#L586-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1027#L597true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 289#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1186#L1227true assume !(0 != activate_threads_~tmp___5~0#1); 824#L1227-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1123#L605true assume 1 == ~t7_pc~0; 761#L606true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 570#L616true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1116#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1107#L1235true assume !(0 != activate_threads_~tmp___6~0#1); 1096#L1235-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 514#L624true assume !(1 == ~t8_pc~0); 1060#L624-2true is_transmit8_triggered_~__retres1~8#1 := 0; 619#L635true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 684#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 790#L1243true assume !(0 != activate_threads_~tmp___7~0#1); 1169#L1243-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29#L643true assume 1 == ~t9_pc~0; 861#L644true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 716#L654true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 336#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 227#L1251true assume !(0 != activate_threads_~tmp___8~0#1); 1122#L1251-2true havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 127#L1059true assume !(1 == ~M_E~0); 1189#L1059-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 212#L1064-1true assume !(1 == ~T2_E~0); 725#L1069-1true assume !(1 == ~T3_E~0); 1083#L1074-1true assume !(1 == ~T4_E~0); 786#L1079-1true assume !(1 == ~T5_E~0); 760#L1084-1true assume !(1 == ~T6_E~0); 935#L1089-1true assume !(1 == ~T7_E~0); 815#L1094-1true assume !(1 == ~T8_E~0); 450#L1099-1true assume 1 == ~T9_E~0;~T9_E~0 := 2; 951#L1104-1true assume !(1 == ~E_M~0); 623#L1109-1true assume !(1 == ~E_1~0); 299#L1114-1true assume !(1 == ~E_2~0); 1130#L1119-1true assume !(1 == ~E_3~0); 344#L1124-1true assume !(1 == ~E_4~0); 27#L1129-1true assume !(1 == ~E_5~0); 524#L1134-1true assume !(1 == ~E_6~0); 192#L1139-1true assume 1 == ~E_7~0;~E_7~0 := 2; 311#L1144-1true assume !(1 == ~E_8~0); 1173#L1149-1true assume !(1 == ~E_9~0); 108#L1154-1true assume { :end_inline_reset_delta_events } true; 174#L1440-2true [2023-11-19 08:02:40,714 INFO L750 eck$LassoCheckResult]: Loop: 174#L1440-2true assume !false; 987#L1441true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 876#L926-1true assume false; 690#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 457#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 246#L951-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1162#L951-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 673#L956-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 516#L961-3true assume !(0 == ~T3_E~0); 332#L966-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 946#L971-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 562#L976-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 39#L981-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 237#L986-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 28#L991-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 651#L996-3true assume 0 == ~E_M~0;~E_M~0 := 1; 783#L1001-3true assume !(0 == ~E_1~0); 310#L1006-3true assume 0 == ~E_2~0;~E_2~0 := 1; 681#L1011-3true assume 0 == ~E_3~0;~E_3~0 := 1; 923#L1016-3true assume 0 == ~E_4~0;~E_4~0 := 1; 734#L1021-3true assume 0 == ~E_5~0;~E_5~0 := 1; 462#L1026-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1078#L1031-3true assume 0 == ~E_7~0;~E_7~0 := 1; 648#L1036-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1137#L1041-3true assume !(0 == ~E_9~0); 720#L1046-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 671#L472-33true assume !(1 == ~m_pc~0); 79#L472-35true is_master_triggered_~__retres1~0#1 := 0; 932#L483-11true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 705#is_master_triggered_returnLabel#12true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 678#L1179-33true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 339#L1179-35true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1063#L491-33true assume 1 == ~t1_pc~0; 579#L492-11true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 982#L502-11true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1079#is_transmit1_triggered_returnLabel#12true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1020#L1187-33true assume !(0 != activate_threads_~tmp___0~0#1); 1082#L1187-35true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 627#L510-33true assume 1 == ~t2_pc~0; 682#L511-11true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1006#L521-11true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 660#is_transmit2_triggered_returnLabel#12true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 740#L1195-33true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2#L1195-35true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 152#L529-33true assume !(1 == ~t3_pc~0); 208#L529-35true is_transmit3_triggered_~__retres1~3#1 := 0; 143#L540-11true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86#is_transmit3_triggered_returnLabel#12true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1028#L1203-33true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59#L1203-35true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 183#L548-33true assume !(1 == ~t4_pc~0); 1181#L548-35true is_transmit4_triggered_~__retres1~4#1 := 0; 592#L559-11true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 940#is_transmit4_triggered_returnLabel#12true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 281#L1211-33true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 148#L1211-35true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 937#L567-33true assume 1 == ~t5_pc~0; 435#L568-11true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 367#L578-11true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1026#is_transmit5_triggered_returnLabel#12true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1048#L1219-33true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1138#L1219-35true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 536#L586-33true assume 1 == ~t6_pc~0; 503#L587-11true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 572#L597-11true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 379#is_transmit6_triggered_returnLabel#12true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1157#L1227-33true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 158#L1227-35true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 261#L605-33true assume !(1 == ~t7_pc~0); 555#L605-35true is_transmit7_triggered_~__retres1~7#1 := 0; 123#L616-11true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 775#is_transmit7_triggered_returnLabel#12true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1127#L1235-33true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 64#L1235-35true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 142#L624-33true assume !(1 == ~t8_pc~0); 146#L624-35true is_transmit8_triggered_~__retres1~8#1 := 0; 1057#L635-11true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 515#is_transmit8_triggered_returnLabel#12true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 270#L1243-33true assume !(0 != activate_threads_~tmp___7~0#1); 1174#L1243-35true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 124#L643-33true assume !(1 == ~t9_pc~0); 165#L643-35true is_transmit9_triggered_~__retres1~9#1 := 0; 484#L654-11true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 664#is_transmit9_triggered_returnLabel#12true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 448#L1251-33true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 809#L1251-35true havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60#L1059-3true assume !(1 == ~M_E~0); 352#L1059-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1184#L1064-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 394#L1069-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 633#L1074-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 886#L1079-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 546#L1084-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 483#L1089-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 595#L1094-3true assume !(1 == ~T8_E~0); 415#L1099-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 653#L1104-3true assume 1 == ~E_M~0;~E_M~0 := 2; 958#L1109-3true assume 1 == ~E_1~0;~E_1~0 := 2; 641#L1114-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1049#L1119-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1183#L1124-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1080#L1129-3true assume 1 == ~E_5~0;~E_5~0 := 2; 216#L1134-3true assume !(1 == ~E_6~0); 500#L1139-3true assume 1 == ~E_7~0;~E_7~0 := 2; 328#L1144-3true assume 1 == ~E_8~0;~E_8~0 := 2; 451#L1149-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1177#L1154-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1114#L728-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 751#L780-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 268#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 12#L1459true assume !(0 == start_simulation_~tmp~3#1); 736#L1459-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 919#L728-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 552#L780-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 30#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 243#L1414true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 355#L1421true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 473#stop_simulation_returnLabel#1true start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 732#L1472true assume !(0 != start_simulation_~tmp___0~1#1); 174#L1440-2true [2023-11-19 08:02:40,722 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:40,723 INFO L85 PathProgramCache]: Analyzing trace with hash -986421749, now seen corresponding path program 1 times [2023-11-19 08:02:40,733 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:40,734 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [426381643] [2023-11-19 08:02:40,734 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:40,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:40,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:41,133 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:41,135 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:41,135 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [426381643] [2023-11-19 08:02:41,136 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [426381643] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:41,136 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:41,139 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:41,142 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1387335419] [2023-11-19 08:02:41,143 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:41,150 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:41,153 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:41,153 INFO L85 PathProgramCache]: Analyzing trace with hash 1748189105, now seen corresponding path program 1 times [2023-11-19 08:02:41,153 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:41,154 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1036200311] [2023-11-19 08:02:41,154 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:41,154 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:41,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:41,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:41,271 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:41,271 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1036200311] [2023-11-19 08:02:41,271 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1036200311] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:41,271 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:41,272 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 08:02:41,272 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [505127490] [2023-11-19 08:02:41,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:41,274 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:41,275 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:41,319 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:02:41,319 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:02:41,325 INFO L87 Difference]: Start difference. First operand has 1195 states, 1194 states have (on average 1.5058626465661642) internal successors, (1798), 1194 states have internal predecessors, (1798), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:41,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:41,452 INFO L93 Difference]: Finished difference Result 1191 states and 1767 transitions. [2023-11-19 08:02:41,454 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1191 states and 1767 transitions. [2023-11-19 08:02:41,473 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-19 08:02:41,494 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1191 states to 1185 states and 1761 transitions. [2023-11-19 08:02:41,495 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1185 [2023-11-19 08:02:41,499 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1185 [2023-11-19 08:02:41,500 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1185 states and 1761 transitions. [2023-11-19 08:02:41,515 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:41,516 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1761 transitions. [2023-11-19 08:02:41,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1185 states and 1761 transitions. [2023-11-19 08:02:41,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1185 to 1185. [2023-11-19 08:02:41,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.4860759493670885) internal successors, (1761), 1184 states have internal predecessors, (1761), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:41,614 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1761 transitions. [2023-11-19 08:02:41,615 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1761 transitions. [2023-11-19 08:02:41,616 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:02:41,620 INFO L428 stractBuchiCegarLoop]: Abstraction has 1185 states and 1761 transitions. [2023-11-19 08:02:41,620 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-19 08:02:41,621 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1761 transitions. [2023-11-19 08:02:41,631 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-19 08:02:41,631 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:41,631 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:41,635 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:41,635 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:41,636 INFO L748 eck$LassoCheckResult]: Stem: 2773#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 2774#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3517#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3518#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3241#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 2967#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2968#L675-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3496#L680-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3530#L685-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3523#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3524#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3095#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3082#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3083#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2892#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2893#L951 assume !(0 == ~M_E~0); 2637#L951-2 assume !(0 == ~T1_E~0); 2638#L956-1 assume !(0 == ~T2_E~0); 2792#L961-1 assume !(0 == ~T3_E~0); 3260#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3261#L971-1 assume !(0 == ~T5_E~0); 3384#L976-1 assume !(0 == ~T6_E~0); 3359#L981-1 assume !(0 == ~T7_E~0); 3131#L986-1 assume !(0 == ~T8_E~0); 2842#L991-1 assume !(0 == ~T9_E~0); 2843#L996-1 assume !(0 == ~E_M~0); 3553#L1001-1 assume !(0 == ~E_1~0); 3311#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 3312#L1011-1 assume !(0 == ~E_3~0); 3531#L1016-1 assume !(0 == ~E_4~0); 3540#L1021-1 assume !(0 == ~E_5~0); 2431#L1026-1 assume !(0 == ~E_6~0); 2432#L1031-1 assume !(0 == ~E_7~0); 3267#L1036-1 assume !(0 == ~E_8~0); 3263#L1041-1 assume !(0 == ~E_9~0); 3264#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3503#L472 assume 1 == ~m_pc~0; 3569#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3292#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3293#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3301#L1179 assume !(0 != activate_threads_~tmp~1#1); 2439#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2440#L491 assume 1 == ~t1_pc~0; 3310#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2937#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2464#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2411#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 2412#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2435#L510 assume !(1 == ~t2_pc~0); 2400#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2401#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2959#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2960#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2692#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2693#L529 assume 1 == ~t3_pc~0; 3044#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3045#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2409#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2410#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 2612#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2613#L548 assume !(1 == ~t4_pc~0); 2506#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2505#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2577#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2548#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 2549#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2493#L567 assume 1 == ~t5_pc~0; 2494#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2550#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3451#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3452#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 3491#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2623#L586 assume !(1 == ~t6_pc~0); 2624#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2696#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2942#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2943#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 3485#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3486#L605 assume 1 == ~t7_pc~0; 3459#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3118#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3294#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3578#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 3577#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3235#L624 assume !(1 == ~t8_pc~0); 2687#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2686#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3344#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3403#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 3469#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2456#L643 assume 1 == ~t9_pc~0; 2457#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3423#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3009#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2849#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 2850#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2669#L1059 assume !(1 == ~M_E~0); 2670#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2820#L1064-1 assume !(1 == ~T2_E~0); 2821#L1069-1 assume !(1 == ~T3_E~0); 3430#L1074-1 assume !(1 == ~T4_E~0); 3467#L1079-1 assume !(1 == ~T5_E~0); 3457#L1084-1 assume !(1 == ~T6_E~0); 3458#L1089-1 assume !(1 == ~T7_E~0); 3481#L1094-1 assume !(1 == ~T8_E~0); 3169#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3170#L1104-1 assume !(1 == ~E_M~0); 3346#L1109-1 assume !(1 == ~E_1~0); 2961#L1114-1 assume !(1 == ~E_2~0); 2962#L1119-1 assume !(1 == ~E_3~0); 3019#L1124-1 assume !(1 == ~E_4~0); 2452#L1129-1 assume !(1 == ~E_5~0); 2453#L1134-1 assume !(1 == ~E_6~0); 2788#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2789#L1144-1 assume !(1 == ~E_8~0); 2977#L1149-1 assume !(1 == ~E_9~0); 2629#L1154-1 assume { :end_inline_reset_delta_events } true; 2630#L1440-2 [2023-11-19 08:02:41,637 INFO L750 eck$LassoCheckResult]: Loop: 2630#L1440-2 assume !false; 2758#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3333#L926-1 assume !false; 3021#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3022#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2717#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2718#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2725#L795 assume !(0 != eval_~tmp~0#1); 2726#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3178#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2876#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2877#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3394#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3237#L961-3 assume !(0 == ~T3_E~0); 3004#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3005#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3286#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2479#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2480#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2454#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2455#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3381#L1001-3 assume !(0 == ~E_1~0); 2973#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2974#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3402#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3437#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3182#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3183#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3375#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3376#L1041-3 assume !(0 == ~E_9~0); 3428#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3392#L472-33 assume 1 == ~m_pc~0; 3393#L473-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2575#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3419#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3399#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3012#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3013#L491-33 assume !(1 == ~t1_pc~0); 2513#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2514#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3546#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3561#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 3562#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3353#L510-33 assume !(1 == ~t2_pc~0); 3347#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 3348#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3386#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3387#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2395#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2396#L529-33 assume 1 == ~t3_pc~0; 2420#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2422#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2587#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2588#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2527#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2528#L548-33 assume 1 == ~t4_pc~0; 2776#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2894#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3318#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2931#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2712#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2713#L567-33 assume !(1 == ~t5_pc~0); 2815#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 2816#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3055#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3566#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3571#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3259#L586-33 assume !(1 == ~t6_pc~0); 2832#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 2833#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3071#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3072#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2729#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2730#L605-33 assume 1 == ~t7_pc~0; 2898#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2654#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2655#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3462#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2539#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2540#L624-33 assume !(1 == ~t8_pc~0); 2701#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 2709#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3236#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2913#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 2914#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2656#L643-33 assume 1 == ~t9_pc~0; 2657#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2743#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3209#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3165#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3166#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2529#L1059-3 assume !(1 == ~M_E~0); 2530#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3033#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3091#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3092#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3360#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3268#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3207#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3208#L1094-3 assume !(1 == ~T8_E~0); 3124#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3125#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3382#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3366#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3367#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3572#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3576#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2827#L1134-3 assume !(1 == ~E_6~0); 2828#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2990#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2991#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3171#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3579#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2532#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2909#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 2417#L1459 assume !(0 == start_simulation_~tmp~3#1); 2418#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3438#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2715#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2459#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 2460#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2873#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3034#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3194#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 2630#L1440-2 [2023-11-19 08:02:41,638 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:41,638 INFO L85 PathProgramCache]: Analyzing trace with hash 1581400585, now seen corresponding path program 1 times [2023-11-19 08:02:41,638 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:41,639 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [804110890] [2023-11-19 08:02:41,639 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:41,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:41,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:41,758 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:41,759 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:41,759 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [804110890] [2023-11-19 08:02:41,759 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [804110890] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:41,759 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:41,760 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:41,760 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2038522513] [2023-11-19 08:02:41,760 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:41,761 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:41,761 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:41,762 INFO L85 PathProgramCache]: Analyzing trace with hash 1812965149, now seen corresponding path program 1 times [2023-11-19 08:02:41,762 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:41,762 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [295350026] [2023-11-19 08:02:41,762 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:41,763 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:41,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:41,875 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:41,875 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:41,876 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [295350026] [2023-11-19 08:02:41,876 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [295350026] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:41,876 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:41,876 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:41,877 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1728044093] [2023-11-19 08:02:41,877 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:41,877 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:41,877 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:41,878 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:02:41,878 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:02:41,879 INFO L87 Difference]: Start difference. First operand 1185 states and 1761 transitions. cyclomatic complexity: 577 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:41,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:41,921 INFO L93 Difference]: Finished difference Result 1185 states and 1760 transitions. [2023-11-19 08:02:41,922 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1185 states and 1760 transitions. [2023-11-19 08:02:41,935 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-19 08:02:41,945 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1185 states to 1185 states and 1760 transitions. [2023-11-19 08:02:41,946 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1185 [2023-11-19 08:02:41,947 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1185 [2023-11-19 08:02:41,948 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1185 states and 1760 transitions. [2023-11-19 08:02:41,951 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:41,951 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1760 transitions. [2023-11-19 08:02:41,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1185 states and 1760 transitions. [2023-11-19 08:02:41,973 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1185 to 1185. [2023-11-19 08:02:41,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.4852320675105486) internal successors, (1760), 1184 states have internal predecessors, (1760), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:41,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1760 transitions. [2023-11-19 08:02:41,982 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1760 transitions. [2023-11-19 08:02:41,984 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:02:41,987 INFO L428 stractBuchiCegarLoop]: Abstraction has 1185 states and 1760 transitions. [2023-11-19 08:02:41,988 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-19 08:02:41,988 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1760 transitions. [2023-11-19 08:02:41,997 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-19 08:02:41,998 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:41,998 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:42,003 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:42,010 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:42,013 INFO L748 eck$LassoCheckResult]: Stem: 5153#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 5154#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 5894#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5895#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5618#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 5344#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5345#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5873#L680-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5907#L685-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5900#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5901#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5472#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5459#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5460#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5270#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5271#L951 assume !(0 == ~M_E~0); 5014#L951-2 assume !(0 == ~T1_E~0); 5015#L956-1 assume !(0 == ~T2_E~0); 5169#L961-1 assume !(0 == ~T3_E~0); 5637#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5638#L971-1 assume !(0 == ~T5_E~0); 5761#L976-1 assume !(0 == ~T6_E~0); 5736#L981-1 assume !(0 == ~T7_E~0); 5511#L986-1 assume !(0 == ~T8_E~0); 5219#L991-1 assume !(0 == ~T9_E~0); 5220#L996-1 assume !(0 == ~E_M~0); 5930#L1001-1 assume !(0 == ~E_1~0); 5688#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5689#L1011-1 assume !(0 == ~E_3~0); 5908#L1016-1 assume !(0 == ~E_4~0); 5917#L1021-1 assume !(0 == ~E_5~0); 4808#L1026-1 assume !(0 == ~E_6~0); 4809#L1031-1 assume !(0 == ~E_7~0); 5644#L1036-1 assume !(0 == ~E_8~0); 5642#L1041-1 assume !(0 == ~E_9~0); 5643#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5880#L472 assume 1 == ~m_pc~0; 5946#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5669#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5670#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5678#L1179 assume !(0 != activate_threads_~tmp~1#1); 4816#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4817#L491 assume 1 == ~t1_pc~0; 5687#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5316#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4841#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4788#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 4789#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4812#L510 assume !(1 == ~t2_pc~0); 4777#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4778#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5336#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5337#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5069#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5070#L529 assume 1 == ~t3_pc~0; 5421#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5422#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4786#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4787#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 4989#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4990#L548 assume !(1 == ~t4_pc~0); 4883#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4882#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4954#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4925#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 4926#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4875#L567 assume 1 == ~t5_pc~0; 4876#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4927#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5828#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5829#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 5868#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5000#L586 assume !(1 == ~t6_pc~0); 5001#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5075#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5322#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5323#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 5862#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5863#L605 assume 1 == ~t7_pc~0; 5836#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5496#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5672#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5955#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 5954#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5612#L624 assume !(1 == ~t8_pc~0); 5064#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5063#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5721#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5780#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 5846#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4833#L643 assume 1 == ~t9_pc~0; 4834#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5800#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5386#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5226#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 5227#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5046#L1059 assume !(1 == ~M_E~0); 5047#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5197#L1064-1 assume !(1 == ~T2_E~0); 5198#L1069-1 assume !(1 == ~T3_E~0); 5807#L1074-1 assume !(1 == ~T4_E~0); 5845#L1079-1 assume !(1 == ~T5_E~0); 5834#L1084-1 assume !(1 == ~T6_E~0); 5835#L1089-1 assume !(1 == ~T7_E~0); 5858#L1094-1 assume !(1 == ~T8_E~0); 5546#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5547#L1104-1 assume !(1 == ~E_M~0); 5725#L1109-1 assume !(1 == ~E_1~0); 5338#L1114-1 assume !(1 == ~E_2~0); 5339#L1119-1 assume !(1 == ~E_3~0); 5396#L1124-1 assume !(1 == ~E_4~0); 4829#L1129-1 assume !(1 == ~E_5~0); 4830#L1134-1 assume !(1 == ~E_6~0); 5165#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 5166#L1144-1 assume !(1 == ~E_8~0); 5354#L1149-1 assume !(1 == ~E_9~0); 5006#L1154-1 assume { :end_inline_reset_delta_events } true; 5007#L1440-2 [2023-11-19 08:02:42,013 INFO L750 eck$LassoCheckResult]: Loop: 5007#L1440-2 assume !false; 5137#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5710#L926-1 assume !false; 5398#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5399#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5094#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5095#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5102#L795 assume !(0 != eval_~tmp~0#1); 5103#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5555#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5255#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5256#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5771#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5614#L961-3 assume !(0 == ~T3_E~0); 5382#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5383#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5663#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4856#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4857#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4831#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4832#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5758#L1001-3 assume !(0 == ~E_1~0); 5350#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5351#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5779#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5814#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5560#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5561#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5752#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5753#L1041-3 assume !(0 == ~E_9~0); 5805#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5769#L472-33 assume !(1 == ~m_pc~0); 4951#L472-35 is_master_triggered_~__retres1~0#1 := 0; 4952#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5796#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5776#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5389#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5390#L491-33 assume !(1 == ~t1_pc~0); 4887#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 4888#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5923#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5938#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 5939#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5726#L510-33 assume !(1 == ~t2_pc~0); 5723#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 5724#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5763#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5764#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4772#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4773#L529-33 assume 1 == ~t3_pc~0; 4797#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4799#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4962#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4963#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4904#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4905#L548-33 assume 1 == ~t4_pc~0; 5149#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5269#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5695#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5308#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5089#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5090#L567-33 assume 1 == ~t5_pc~0; 5527#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5193#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5431#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5943#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5948#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5636#L586-33 assume 1 == ~t6_pc~0; 5602#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5211#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5448#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5449#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5108#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5109#L605-33 assume 1 == ~t7_pc~0; 5278#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5031#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5032#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5839#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4916#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4917#L624-33 assume !(1 == ~t8_pc~0); 5078#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 5086#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5613#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5290#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 5291#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5033#L643-33 assume 1 == ~t9_pc~0; 5034#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5120#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5586#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5542#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5543#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4906#L1059-3 assume !(1 == ~M_E~0); 4907#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5410#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5468#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5469#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5737#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5645#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5584#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5585#L1094-3 assume !(1 == ~T8_E~0); 5501#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5502#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5759#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5743#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5744#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5949#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5953#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5204#L1134-3 assume !(1 == ~E_6~0); 5205#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5370#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5371#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5548#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5956#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4909#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5288#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 4794#L1459 assume !(0 == start_simulation_~tmp~3#1); 4795#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5815#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5092#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4836#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 4837#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 5250#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5412#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 5571#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 5007#L1440-2 [2023-11-19 08:02:42,014 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:42,014 INFO L85 PathProgramCache]: Analyzing trace with hash -1066203769, now seen corresponding path program 1 times [2023-11-19 08:02:42,014 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:42,015 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1946586476] [2023-11-19 08:02:42,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:42,015 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:42,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:42,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:42,086 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:42,087 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1946586476] [2023-11-19 08:02:42,087 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1946586476] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:42,087 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:42,087 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:42,087 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1260328280] [2023-11-19 08:02:42,088 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:42,088 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:42,089 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:42,089 INFO L85 PathProgramCache]: Analyzing trace with hash 2112954140, now seen corresponding path program 1 times [2023-11-19 08:02:42,089 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:42,089 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1528793594] [2023-11-19 08:02:42,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:42,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:42,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:42,217 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:42,217 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:42,217 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1528793594] [2023-11-19 08:02:42,218 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1528793594] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:42,218 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:42,218 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:42,218 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1089212514] [2023-11-19 08:02:42,218 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:42,219 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:42,219 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:42,220 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:02:42,220 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:02:42,226 INFO L87 Difference]: Start difference. First operand 1185 states and 1760 transitions. cyclomatic complexity: 576 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:42,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:42,263 INFO L93 Difference]: Finished difference Result 1185 states and 1759 transitions. [2023-11-19 08:02:42,264 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1185 states and 1759 transitions. [2023-11-19 08:02:42,274 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-19 08:02:42,284 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1185 states to 1185 states and 1759 transitions. [2023-11-19 08:02:42,284 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1185 [2023-11-19 08:02:42,286 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1185 [2023-11-19 08:02:42,286 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1185 states and 1759 transitions. [2023-11-19 08:02:42,288 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:42,288 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1759 transitions. [2023-11-19 08:02:42,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1185 states and 1759 transitions. [2023-11-19 08:02:42,308 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1185 to 1185. [2023-11-19 08:02:42,311 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.4843881856540084) internal successors, (1759), 1184 states have internal predecessors, (1759), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:42,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1759 transitions. [2023-11-19 08:02:42,317 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1759 transitions. [2023-11-19 08:02:42,318 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:02:42,320 INFO L428 stractBuchiCegarLoop]: Abstraction has 1185 states and 1759 transitions. [2023-11-19 08:02:42,321 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-19 08:02:42,321 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1759 transitions. [2023-11-19 08:02:42,329 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-19 08:02:42,329 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:42,329 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:42,336 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:42,337 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:42,337 INFO L748 eck$LassoCheckResult]: Stem: 7530#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 7531#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 8271#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8272#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7995#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 7723#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7724#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8250#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8284#L685-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8277#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8278#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7849#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7836#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7837#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7647#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7648#L951 assume !(0 == ~M_E~0); 7393#L951-2 assume !(0 == ~T1_E~0); 7394#L956-1 assume !(0 == ~T2_E~0); 7546#L961-1 assume !(0 == ~T3_E~0); 8014#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8015#L971-1 assume !(0 == ~T5_E~0); 8138#L976-1 assume !(0 == ~T6_E~0); 8113#L981-1 assume !(0 == ~T7_E~0); 7888#L986-1 assume !(0 == ~T8_E~0); 7596#L991-1 assume !(0 == ~T9_E~0); 7597#L996-1 assume !(0 == ~E_M~0); 8307#L1001-1 assume !(0 == ~E_1~0); 8065#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 8066#L1011-1 assume !(0 == ~E_3~0); 8286#L1016-1 assume !(0 == ~E_4~0); 8294#L1021-1 assume !(0 == ~E_5~0); 7185#L1026-1 assume !(0 == ~E_6~0); 7186#L1031-1 assume !(0 == ~E_7~0); 8021#L1036-1 assume !(0 == ~E_8~0); 8019#L1041-1 assume !(0 == ~E_9~0); 8020#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8257#L472 assume 1 == ~m_pc~0; 8323#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8046#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8047#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8055#L1179 assume !(0 != activate_threads_~tmp~1#1); 7193#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7194#L491 assume 1 == ~t1_pc~0; 8064#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7693#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7218#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7165#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 7166#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7189#L510 assume !(1 == ~t2_pc~0); 7154#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7155#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7713#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7714#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7446#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7447#L529 assume 1 == ~t3_pc~0; 7798#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7799#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7163#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7164#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 7366#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7367#L548 assume !(1 == ~t4_pc~0); 7261#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7260#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7331#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7302#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 7303#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7252#L567 assume 1 == ~t5_pc~0; 7253#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7304#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8205#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8206#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 8245#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7377#L586 assume !(1 == ~t6_pc~0); 7378#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7452#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7699#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7700#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 8239#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8240#L605 assume 1 == ~t7_pc~0; 8213#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7876#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8049#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8332#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 8331#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7989#L624 assume !(1 == ~t8_pc~0); 7441#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7440#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8098#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8158#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 8223#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7210#L643 assume 1 == ~t9_pc~0; 7211#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8177#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7763#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7603#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 7604#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7423#L1059 assume !(1 == ~M_E~0); 7424#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7574#L1064-1 assume !(1 == ~T2_E~0); 7575#L1069-1 assume !(1 == ~T3_E~0); 8184#L1074-1 assume !(1 == ~T4_E~0); 8222#L1079-1 assume !(1 == ~T5_E~0); 8211#L1084-1 assume !(1 == ~T6_E~0); 8212#L1089-1 assume !(1 == ~T7_E~0); 8235#L1094-1 assume !(1 == ~T8_E~0); 7923#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7924#L1104-1 assume !(1 == ~E_M~0); 8102#L1109-1 assume !(1 == ~E_1~0); 7715#L1114-1 assume !(1 == ~E_2~0); 7716#L1119-1 assume !(1 == ~E_3~0); 7774#L1124-1 assume !(1 == ~E_4~0); 7208#L1129-1 assume !(1 == ~E_5~0); 7209#L1134-1 assume !(1 == ~E_6~0); 7544#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7545#L1144-1 assume !(1 == ~E_8~0); 7731#L1149-1 assume !(1 == ~E_9~0); 7383#L1154-1 assume { :end_inline_reset_delta_events } true; 7384#L1440-2 [2023-11-19 08:02:42,339 INFO L750 eck$LassoCheckResult]: Loop: 7384#L1440-2 assume !false; 7514#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8087#L926-1 assume !false; 7775#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7776#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7471#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7472#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7479#L795 assume !(0 != eval_~tmp~0#1); 7480#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7932#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7632#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7633#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8149#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7992#L961-3 assume !(0 == ~T3_E~0); 7755#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7756#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8040#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7230#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7231#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7206#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7207#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8135#L1001-3 assume !(0 == ~E_1~0); 7727#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7728#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8156#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8191#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7936#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7937#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8129#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8130#L1041-3 assume !(0 == ~E_9~0); 8182#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8146#L472-33 assume !(1 == ~m_pc~0); 7328#L472-35 is_master_triggered_~__retres1~0#1 := 0; 7329#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8173#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8153#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7766#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7767#L491-33 assume !(1 == ~t1_pc~0); 7267#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 7268#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8300#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8315#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 8316#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8106#L510-33 assume !(1 == ~t2_pc~0); 8100#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 8101#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8140#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8141#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7149#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7150#L529-33 assume 1 == ~t3_pc~0; 7174#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7176#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7341#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7342#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7281#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7282#L548-33 assume 1 == ~t4_pc~0; 7526#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7646#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8072#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7685#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7466#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7467#L567-33 assume !(1 == ~t5_pc~0); 7569#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 7570#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7808#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8320#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8325#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8013#L586-33 assume !(1 == ~t6_pc~0); 7587#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 7588#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7826#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7827#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7485#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7486#L605-33 assume 1 == ~t7_pc~0; 7655#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7415#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7416#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8216#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7293#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7294#L624-33 assume 1 == ~t8_pc~0; 7456#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7463#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7990#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7667#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 7668#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7417#L643-33 assume 1 == ~t9_pc~0; 7418#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7497#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7963#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7919#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7920#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7283#L1059-3 assume !(1 == ~M_E~0); 7284#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7787#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7846#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7847#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8114#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8022#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7961#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7962#L1094-3 assume !(1 == ~T8_E~0); 7878#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7879#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8136#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8122#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8123#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8326#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8330#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7581#L1134-3 assume !(1 == ~E_6~0); 7582#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7749#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7750#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7925#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 8333#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7288#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7665#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 7171#L1459 assume !(0 == start_simulation_~tmp~3#1); 7172#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 8192#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7469#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7213#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 7214#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 7627#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7789#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 7948#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 7384#L1440-2 [2023-11-19 08:02:42,340 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:42,340 INFO L85 PathProgramCache]: Analyzing trace with hash 1065146953, now seen corresponding path program 1 times [2023-11-19 08:02:42,340 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:42,341 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [884043686] [2023-11-19 08:02:42,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:42,341 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:42,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:42,431 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:42,432 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:42,433 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [884043686] [2023-11-19 08:02:42,433 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [884043686] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:42,433 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:42,433 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:42,434 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [8103742] [2023-11-19 08:02:42,434 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:42,434 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:42,435 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:42,435 INFO L85 PathProgramCache]: Analyzing trace with hash -491339491, now seen corresponding path program 1 times [2023-11-19 08:02:42,436 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:42,440 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [719014764] [2023-11-19 08:02:42,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:42,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:42,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:42,536 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:42,536 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:42,536 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [719014764] [2023-11-19 08:02:42,536 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [719014764] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:42,536 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:42,537 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:42,537 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [120585174] [2023-11-19 08:02:42,537 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:42,537 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:42,537 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:42,538 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:02:42,538 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:02:42,538 INFO L87 Difference]: Start difference. First operand 1185 states and 1759 transitions. cyclomatic complexity: 575 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:42,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:42,573 INFO L93 Difference]: Finished difference Result 1185 states and 1758 transitions. [2023-11-19 08:02:42,574 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1185 states and 1758 transitions. [2023-11-19 08:02:42,584 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-19 08:02:42,595 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1185 states to 1185 states and 1758 transitions. [2023-11-19 08:02:42,595 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1185 [2023-11-19 08:02:42,596 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1185 [2023-11-19 08:02:42,597 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1185 states and 1758 transitions. [2023-11-19 08:02:42,599 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:42,599 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1758 transitions. [2023-11-19 08:02:42,601 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1185 states and 1758 transitions. [2023-11-19 08:02:42,619 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1185 to 1185. [2023-11-19 08:02:42,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.4835443037974683) internal successors, (1758), 1184 states have internal predecessors, (1758), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:42,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1758 transitions. [2023-11-19 08:02:42,628 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1758 transitions. [2023-11-19 08:02:42,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:02:42,630 INFO L428 stractBuchiCegarLoop]: Abstraction has 1185 states and 1758 transitions. [2023-11-19 08:02:42,630 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-19 08:02:42,633 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1758 transitions. [2023-11-19 08:02:42,641 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-19 08:02:42,642 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:42,642 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:42,644 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:42,644 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:42,651 INFO L748 eck$LassoCheckResult]: Stem: 9902#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 9903#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 10646#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10647#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10372#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 10098#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10099#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10627#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10661#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10654#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10655#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10226#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10213#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10214#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 10023#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10024#L951 assume !(0 == ~M_E~0); 9768#L951-2 assume !(0 == ~T1_E~0); 9769#L956-1 assume !(0 == ~T2_E~0); 9923#L961-1 assume !(0 == ~T3_E~0); 10391#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10392#L971-1 assume !(0 == ~T5_E~0); 10515#L976-1 assume !(0 == ~T6_E~0); 10490#L981-1 assume !(0 == ~T7_E~0); 10262#L986-1 assume !(0 == ~T8_E~0); 9973#L991-1 assume !(0 == ~T9_E~0); 9974#L996-1 assume !(0 == ~E_M~0); 10683#L1001-1 assume !(0 == ~E_1~0); 10442#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 10443#L1011-1 assume !(0 == ~E_3~0); 10662#L1016-1 assume !(0 == ~E_4~0); 10671#L1021-1 assume !(0 == ~E_5~0); 9562#L1026-1 assume !(0 == ~E_6~0); 9563#L1031-1 assume !(0 == ~E_7~0); 10398#L1036-1 assume !(0 == ~E_8~0); 10394#L1041-1 assume !(0 == ~E_9~0); 10395#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10634#L472 assume 1 == ~m_pc~0; 10700#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10423#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10424#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10432#L1179 assume !(0 != activate_threads_~tmp~1#1); 9570#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9571#L491 assume 1 == ~t1_pc~0; 10441#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10068#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9595#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9542#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 9543#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9564#L510 assume !(1 == ~t2_pc~0); 9531#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9532#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10090#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10091#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9823#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9824#L529 assume 1 == ~t3_pc~0; 10175#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10176#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9540#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9541#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 9743#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9744#L548 assume !(1 == ~t4_pc~0); 9637#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9636#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9708#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9677#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 9678#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9624#L567 assume 1 == ~t5_pc~0; 9625#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9679#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10582#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10583#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 10622#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9754#L586 assume !(1 == ~t6_pc~0); 9755#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9827#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10073#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10074#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 10616#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10617#L605 assume 1 == ~t7_pc~0; 10590#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10246#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10425#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10709#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 10708#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10366#L624 assume !(1 == ~t8_pc~0); 9818#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 9817#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10475#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10534#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 10600#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9587#L643 assume 1 == ~t9_pc~0; 9588#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10554#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10138#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9978#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 9979#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9800#L1059 assume !(1 == ~M_E~0); 9801#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9951#L1064-1 assume !(1 == ~T2_E~0); 9952#L1069-1 assume !(1 == ~T3_E~0); 10561#L1074-1 assume !(1 == ~T4_E~0); 10598#L1079-1 assume !(1 == ~T5_E~0); 10588#L1084-1 assume !(1 == ~T6_E~0); 10589#L1089-1 assume !(1 == ~T7_E~0); 10612#L1094-1 assume !(1 == ~T8_E~0); 10300#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10301#L1104-1 assume !(1 == ~E_M~0); 10477#L1109-1 assume !(1 == ~E_1~0); 10092#L1114-1 assume !(1 == ~E_2~0); 10093#L1119-1 assume !(1 == ~E_3~0); 10150#L1124-1 assume !(1 == ~E_4~0); 9583#L1129-1 assume !(1 == ~E_5~0); 9584#L1134-1 assume !(1 == ~E_6~0); 9919#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 9920#L1144-1 assume !(1 == ~E_8~0); 10106#L1149-1 assume !(1 == ~E_9~0); 9760#L1154-1 assume { :end_inline_reset_delta_events } true; 9761#L1440-2 [2023-11-19 08:02:42,652 INFO L750 eck$LassoCheckResult]: Loop: 9761#L1440-2 assume !false; 9889#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10464#L926-1 assume !false; 10152#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10153#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9845#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9846#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9855#L795 assume !(0 != eval_~tmp~0#1); 9856#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10309#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10007#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10008#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10525#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10368#L961-3 assume !(0 == ~T3_E~0); 10132#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10133#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10417#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9607#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9608#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9585#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9586#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10512#L1001-3 assume !(0 == ~E_1~0); 10104#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10105#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10533#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10568#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10313#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10314#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10506#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10507#L1041-3 assume !(0 == ~E_9~0); 10559#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10523#L472-33 assume !(1 == ~m_pc~0); 9705#L472-35 is_master_triggered_~__retres1~0#1 := 0; 9706#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10550#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10530#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10143#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10144#L491-33 assume 1 == ~t1_pc~0; 10433#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9645#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10677#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10692#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 10693#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10483#L510-33 assume 1 == ~t2_pc~0; 10484#L511-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10479#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10517#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10518#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9526#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9527#L529-33 assume !(1 == ~t3_pc~0); 9552#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 9553#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9718#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9719#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9658#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9659#L548-33 assume 1 == ~t4_pc~0; 9905#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10025#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10449#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10062#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9843#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9844#L567-33 assume !(1 == ~t5_pc~0); 9946#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 9947#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10185#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10697#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10702#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10390#L586-33 assume 1 == ~t6_pc~0; 10356#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9965#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10203#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10204#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9862#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9863#L605-33 assume 1 == ~t7_pc~0; 10032#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9792#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9793#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10593#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9670#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9671#L624-33 assume !(1 == ~t8_pc~0); 9832#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 9840#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10367#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10044#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 10045#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9794#L643-33 assume 1 == ~t9_pc~0; 9795#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9874#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10340#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10296#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10297#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9660#L1059-3 assume !(1 == ~M_E~0); 9661#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10164#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10223#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10224#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10491#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10399#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10338#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10339#L1094-3 assume !(1 == ~T8_E~0); 10255#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10256#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10513#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10499#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10500#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10703#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10707#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9958#L1134-3 assume !(1 == ~E_6~0); 9959#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10126#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10127#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10302#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10710#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9665#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 10042#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 9548#L1459 assume !(0 == start_simulation_~tmp~3#1); 9549#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10569#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9848#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9590#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 9591#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 10004#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10168#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 10328#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 9761#L1440-2 [2023-11-19 08:02:42,654 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:42,656 INFO L85 PathProgramCache]: Analyzing trace with hash 2103731527, now seen corresponding path program 1 times [2023-11-19 08:02:42,657 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:42,657 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2099288443] [2023-11-19 08:02:42,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:42,657 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:42,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:42,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:42,712 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:42,713 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2099288443] [2023-11-19 08:02:42,713 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2099288443] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:42,713 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:42,713 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:42,713 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1533954887] [2023-11-19 08:02:42,713 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:42,714 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:42,714 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:42,714 INFO L85 PathProgramCache]: Analyzing trace with hash -1438738724, now seen corresponding path program 1 times [2023-11-19 08:02:42,714 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:42,715 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1899366910] [2023-11-19 08:02:42,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:42,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:42,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:42,776 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:42,776 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:42,776 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1899366910] [2023-11-19 08:02:42,776 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1899366910] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:42,777 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:42,777 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:42,777 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1993228294] [2023-11-19 08:02:42,777 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:42,777 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:42,778 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:42,778 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:02:42,778 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:02:42,778 INFO L87 Difference]: Start difference. First operand 1185 states and 1758 transitions. cyclomatic complexity: 574 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:42,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:42,816 INFO L93 Difference]: Finished difference Result 1185 states and 1757 transitions. [2023-11-19 08:02:42,816 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1185 states and 1757 transitions. [2023-11-19 08:02:42,827 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-19 08:02:42,838 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1185 states to 1185 states and 1757 transitions. [2023-11-19 08:02:42,838 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1185 [2023-11-19 08:02:42,840 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1185 [2023-11-19 08:02:42,840 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1185 states and 1757 transitions. [2023-11-19 08:02:42,842 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:42,842 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1757 transitions. [2023-11-19 08:02:42,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1185 states and 1757 transitions. [2023-11-19 08:02:42,862 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1185 to 1185. [2023-11-19 08:02:42,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.4827004219409283) internal successors, (1757), 1184 states have internal predecessors, (1757), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:42,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1757 transitions. [2023-11-19 08:02:42,871 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1757 transitions. [2023-11-19 08:02:42,872 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:02:42,874 INFO L428 stractBuchiCegarLoop]: Abstraction has 1185 states and 1757 transitions. [2023-11-19 08:02:42,874 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-19 08:02:42,875 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1757 transitions. [2023-11-19 08:02:42,883 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-19 08:02:42,883 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:42,883 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:42,885 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:42,885 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:42,886 INFO L748 eck$LassoCheckResult]: Stem: 12279#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 12280#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 13023#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13024#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12749#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 12475#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12476#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13004#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13038#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13031#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13032#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12603#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12590#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12591#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12400#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12401#L951 assume !(0 == ~M_E~0); 12145#L951-2 assume !(0 == ~T1_E~0); 12146#L956-1 assume !(0 == ~T2_E~0); 12300#L961-1 assume !(0 == ~T3_E~0); 12768#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12769#L971-1 assume !(0 == ~T5_E~0); 12892#L976-1 assume !(0 == ~T6_E~0); 12867#L981-1 assume !(0 == ~T7_E~0); 12639#L986-1 assume !(0 == ~T8_E~0); 12350#L991-1 assume !(0 == ~T9_E~0); 12351#L996-1 assume !(0 == ~E_M~0); 13060#L1001-1 assume !(0 == ~E_1~0); 12819#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 12820#L1011-1 assume !(0 == ~E_3~0); 13039#L1016-1 assume !(0 == ~E_4~0); 13048#L1021-1 assume !(0 == ~E_5~0); 11939#L1026-1 assume !(0 == ~E_6~0); 11940#L1031-1 assume !(0 == ~E_7~0); 12775#L1036-1 assume !(0 == ~E_8~0); 12771#L1041-1 assume !(0 == ~E_9~0); 12772#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13011#L472 assume 1 == ~m_pc~0; 13077#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12800#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12801#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12809#L1179 assume !(0 != activate_threads_~tmp~1#1); 11947#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11948#L491 assume 1 == ~t1_pc~0; 12818#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12445#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11972#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11919#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 11920#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11941#L510 assume !(1 == ~t2_pc~0); 11908#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11909#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12467#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12468#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12200#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12201#L529 assume 1 == ~t3_pc~0; 12552#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12553#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11917#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11918#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 12120#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12121#L548 assume !(1 == ~t4_pc~0); 12014#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12013#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12085#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12054#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 12055#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12001#L567 assume 1 == ~t5_pc~0; 12002#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12056#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12959#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12960#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 12999#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12131#L586 assume !(1 == ~t6_pc~0); 12132#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12204#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12450#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12451#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 12993#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12994#L605 assume 1 == ~t7_pc~0; 12967#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12623#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12802#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13086#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 13085#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12743#L624 assume !(1 == ~t8_pc~0); 12195#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12194#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12852#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12911#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 12977#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11964#L643 assume 1 == ~t9_pc~0; 11965#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12931#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12515#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12355#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 12356#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12177#L1059 assume !(1 == ~M_E~0); 12178#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12328#L1064-1 assume !(1 == ~T2_E~0); 12329#L1069-1 assume !(1 == ~T3_E~0); 12938#L1074-1 assume !(1 == ~T4_E~0); 12975#L1079-1 assume !(1 == ~T5_E~0); 12965#L1084-1 assume !(1 == ~T6_E~0); 12966#L1089-1 assume !(1 == ~T7_E~0); 12989#L1094-1 assume !(1 == ~T8_E~0); 12677#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12678#L1104-1 assume !(1 == ~E_M~0); 12854#L1109-1 assume !(1 == ~E_1~0); 12469#L1114-1 assume !(1 == ~E_2~0); 12470#L1119-1 assume !(1 == ~E_3~0); 12527#L1124-1 assume !(1 == ~E_4~0); 11960#L1129-1 assume !(1 == ~E_5~0); 11961#L1134-1 assume !(1 == ~E_6~0); 12296#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 12297#L1144-1 assume !(1 == ~E_8~0); 12483#L1149-1 assume !(1 == ~E_9~0); 12137#L1154-1 assume { :end_inline_reset_delta_events } true; 12138#L1440-2 [2023-11-19 08:02:42,886 INFO L750 eck$LassoCheckResult]: Loop: 12138#L1440-2 assume !false; 12266#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12841#L926-1 assume !false; 12529#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12530#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12222#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12223#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12232#L795 assume !(0 != eval_~tmp~0#1); 12233#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12686#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12384#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12385#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12902#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12745#L961-3 assume !(0 == ~T3_E~0); 12509#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12510#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12794#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11984#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11985#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11962#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11963#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12889#L1001-3 assume !(0 == ~E_1~0); 12481#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12482#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12910#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12945#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12690#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12691#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12883#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12884#L1041-3 assume !(0 == ~E_9~0); 12936#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12900#L472-33 assume !(1 == ~m_pc~0); 12082#L472-35 is_master_triggered_~__retres1~0#1 := 0; 12083#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12927#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12907#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12520#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12521#L491-33 assume !(1 == ~t1_pc~0); 12021#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 12022#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13054#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13069#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 13070#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12860#L510-33 assume !(1 == ~t2_pc~0); 12855#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 12856#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12894#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12895#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11903#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11904#L529-33 assume 1 == ~t3_pc~0; 11928#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11930#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12095#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12096#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12035#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12036#L548-33 assume 1 == ~t4_pc~0; 12282#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12402#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12826#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12439#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12220#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12221#L567-33 assume !(1 == ~t5_pc~0); 12323#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 12324#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12562#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13074#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13079#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12767#L586-33 assume !(1 == ~t6_pc~0); 12341#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 12342#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12580#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12581#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12239#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12240#L605-33 assume 1 == ~t7_pc~0; 12409#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12169#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12170#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12970#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12047#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12048#L624-33 assume !(1 == ~t8_pc~0); 12209#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 12217#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12744#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12421#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 12422#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12171#L643-33 assume 1 == ~t9_pc~0; 12172#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12251#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12717#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12673#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12674#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12037#L1059-3 assume !(1 == ~M_E~0); 12038#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12541#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12600#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12601#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12868#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12776#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12715#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12716#L1094-3 assume !(1 == ~T8_E~0); 12632#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12633#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12890#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12876#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12877#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13080#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13084#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12335#L1134-3 assume !(1 == ~E_6~0); 12336#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12503#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12504#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12679#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 13087#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12042#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12419#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 11925#L1459 assume !(0 == start_simulation_~tmp~3#1); 11926#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12946#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12225#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11967#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 11968#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 12381#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12545#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 12705#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 12138#L1440-2 [2023-11-19 08:02:42,887 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:42,888 INFO L85 PathProgramCache]: Analyzing trace with hash -218070391, now seen corresponding path program 1 times [2023-11-19 08:02:42,888 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:42,888 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [662872211] [2023-11-19 08:02:42,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:42,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:42,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:42,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:42,959 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:42,959 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [662872211] [2023-11-19 08:02:42,959 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [662872211] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:42,959 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:42,960 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:42,960 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1010913757] [2023-11-19 08:02:42,960 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:42,960 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:42,961 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:42,961 INFO L85 PathProgramCache]: Analyzing trace with hash -1364817186, now seen corresponding path program 1 times [2023-11-19 08:02:42,962 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:42,965 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1113698854] [2023-11-19 08:02:42,965 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:42,965 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:42,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:43,024 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:43,024 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:43,024 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1113698854] [2023-11-19 08:02:43,024 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1113698854] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:43,025 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:43,025 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:43,025 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2106729265] [2023-11-19 08:02:43,025 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:43,026 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:43,026 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:43,027 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:02:43,027 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:02:43,027 INFO L87 Difference]: Start difference. First operand 1185 states and 1757 transitions. cyclomatic complexity: 573 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:43,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:43,061 INFO L93 Difference]: Finished difference Result 1185 states and 1756 transitions. [2023-11-19 08:02:43,061 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1185 states and 1756 transitions. [2023-11-19 08:02:43,072 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-19 08:02:43,083 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1185 states to 1185 states and 1756 transitions. [2023-11-19 08:02:43,083 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1185 [2023-11-19 08:02:43,084 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1185 [2023-11-19 08:02:43,085 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1185 states and 1756 transitions. [2023-11-19 08:02:43,087 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:43,087 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1756 transitions. [2023-11-19 08:02:43,089 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1185 states and 1756 transitions. [2023-11-19 08:02:43,106 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1185 to 1185. [2023-11-19 08:02:43,109 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.4818565400843882) internal successors, (1756), 1184 states have internal predecessors, (1756), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:43,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1756 transitions. [2023-11-19 08:02:43,115 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1756 transitions. [2023-11-19 08:02:43,116 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:02:43,118 INFO L428 stractBuchiCegarLoop]: Abstraction has 1185 states and 1756 transitions. [2023-11-19 08:02:43,118 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-19 08:02:43,118 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1756 transitions. [2023-11-19 08:02:43,126 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-19 08:02:43,126 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:43,130 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:43,132 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:43,132 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:43,133 INFO L748 eck$LassoCheckResult]: Stem: 14656#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 14657#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 15400#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15401#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15126#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 14852#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14853#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15381#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15415#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15408#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15409#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14980#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14967#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14968#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14777#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14778#L951 assume !(0 == ~M_E~0); 14522#L951-2 assume !(0 == ~T1_E~0); 14523#L956-1 assume !(0 == ~T2_E~0); 14677#L961-1 assume !(0 == ~T3_E~0); 15145#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15146#L971-1 assume !(0 == ~T5_E~0); 15269#L976-1 assume !(0 == ~T6_E~0); 15244#L981-1 assume !(0 == ~T7_E~0); 15016#L986-1 assume !(0 == ~T8_E~0); 14727#L991-1 assume !(0 == ~T9_E~0); 14728#L996-1 assume !(0 == ~E_M~0); 15437#L1001-1 assume !(0 == ~E_1~0); 15196#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 15197#L1011-1 assume !(0 == ~E_3~0); 15416#L1016-1 assume !(0 == ~E_4~0); 15425#L1021-1 assume !(0 == ~E_5~0); 14316#L1026-1 assume !(0 == ~E_6~0); 14317#L1031-1 assume !(0 == ~E_7~0); 15152#L1036-1 assume !(0 == ~E_8~0); 15148#L1041-1 assume !(0 == ~E_9~0); 15149#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15388#L472 assume 1 == ~m_pc~0; 15454#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15177#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15178#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15186#L1179 assume !(0 != activate_threads_~tmp~1#1); 14324#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14325#L491 assume 1 == ~t1_pc~0; 15195#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14822#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14349#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14296#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 14297#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14318#L510 assume !(1 == ~t2_pc~0); 14285#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14286#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14844#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14845#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14577#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14578#L529 assume 1 == ~t3_pc~0; 14929#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14930#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14294#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14295#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 14497#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14498#L548 assume !(1 == ~t4_pc~0); 14391#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14390#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14462#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14431#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 14432#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14378#L567 assume 1 == ~t5_pc~0; 14379#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14433#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15336#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15337#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 15376#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14508#L586 assume !(1 == ~t6_pc~0); 14509#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14581#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14827#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14828#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 15370#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15371#L605 assume 1 == ~t7_pc~0; 15344#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15000#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15179#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15463#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 15462#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15120#L624 assume !(1 == ~t8_pc~0); 14572#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14571#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15229#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15288#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 15354#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14341#L643 assume 1 == ~t9_pc~0; 14342#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15308#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14892#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14732#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 14733#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14554#L1059 assume !(1 == ~M_E~0); 14555#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14705#L1064-1 assume !(1 == ~T2_E~0); 14706#L1069-1 assume !(1 == ~T3_E~0); 15315#L1074-1 assume !(1 == ~T4_E~0); 15352#L1079-1 assume !(1 == ~T5_E~0); 15342#L1084-1 assume !(1 == ~T6_E~0); 15343#L1089-1 assume !(1 == ~T7_E~0); 15366#L1094-1 assume !(1 == ~T8_E~0); 15054#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15055#L1104-1 assume !(1 == ~E_M~0); 15231#L1109-1 assume !(1 == ~E_1~0); 14846#L1114-1 assume !(1 == ~E_2~0); 14847#L1119-1 assume !(1 == ~E_3~0); 14904#L1124-1 assume !(1 == ~E_4~0); 14337#L1129-1 assume !(1 == ~E_5~0); 14338#L1134-1 assume !(1 == ~E_6~0); 14673#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14674#L1144-1 assume !(1 == ~E_8~0); 14860#L1149-1 assume !(1 == ~E_9~0); 14514#L1154-1 assume { :end_inline_reset_delta_events } true; 14515#L1440-2 [2023-11-19 08:02:43,133 INFO L750 eck$LassoCheckResult]: Loop: 14515#L1440-2 assume !false; 14643#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15218#L926-1 assume !false; 14906#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14907#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14599#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14600#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14609#L795 assume !(0 != eval_~tmp~0#1); 14610#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15063#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14761#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14762#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15279#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15122#L961-3 assume !(0 == ~T3_E~0); 14886#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14887#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15171#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14361#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14362#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14339#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14340#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15266#L1001-3 assume !(0 == ~E_1~0); 14858#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14859#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15287#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15322#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15067#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15068#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15260#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15261#L1041-3 assume !(0 == ~E_9~0); 15313#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15277#L472-33 assume !(1 == ~m_pc~0); 14459#L472-35 is_master_triggered_~__retres1~0#1 := 0; 14460#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15304#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15284#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14897#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14898#L491-33 assume 1 == ~t1_pc~0; 15187#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14399#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15431#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15446#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 15447#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15237#L510-33 assume !(1 == ~t2_pc~0); 15232#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 15233#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15271#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15272#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14280#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14281#L529-33 assume 1 == ~t3_pc~0; 14305#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14307#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14472#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14473#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14412#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14413#L548-33 assume 1 == ~t4_pc~0; 14659#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14779#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15203#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14816#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14597#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14598#L567-33 assume !(1 == ~t5_pc~0); 14700#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 14701#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14939#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15451#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15456#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15144#L586-33 assume 1 == ~t6_pc~0; 15110#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14719#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14957#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14958#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14616#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14617#L605-33 assume 1 == ~t7_pc~0; 14786#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14546#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14547#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15347#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14424#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14425#L624-33 assume !(1 == ~t8_pc~0); 14586#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 14594#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15121#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14798#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 14799#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14548#L643-33 assume 1 == ~t9_pc~0; 14549#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14628#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15094#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15050#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15051#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14414#L1059-3 assume !(1 == ~M_E~0); 14415#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14918#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14977#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14978#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15245#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15153#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15092#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15093#L1094-3 assume !(1 == ~T8_E~0); 15009#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15010#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15267#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15253#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15254#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15457#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15461#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14712#L1134-3 assume !(1 == ~E_6~0); 14713#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14880#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14881#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15056#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 15464#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14419#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14796#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 14302#L1459 assume !(0 == start_simulation_~tmp~3#1); 14303#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 15323#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14602#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14344#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 14345#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 14758#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14922#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 15082#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 14515#L1440-2 [2023-11-19 08:02:43,134 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:43,134 INFO L85 PathProgramCache]: Analyzing trace with hash 1923790087, now seen corresponding path program 1 times [2023-11-19 08:02:43,134 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:43,135 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [422702750] [2023-11-19 08:02:43,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:43,135 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:43,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:43,179 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:43,179 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:43,179 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [422702750] [2023-11-19 08:02:43,180 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [422702750] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:43,180 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:43,180 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:43,180 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1611272902] [2023-11-19 08:02:43,181 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:43,181 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:43,182 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:43,182 INFO L85 PathProgramCache]: Analyzing trace with hash -119844324, now seen corresponding path program 1 times [2023-11-19 08:02:43,182 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:43,182 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1402596920] [2023-11-19 08:02:43,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:43,183 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:43,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:43,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:43,277 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:43,277 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1402596920] [2023-11-19 08:02:43,278 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1402596920] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:43,278 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:43,278 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:43,278 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [463377035] [2023-11-19 08:02:43,278 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:43,279 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:43,279 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:43,279 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:02:43,280 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:02:43,280 INFO L87 Difference]: Start difference. First operand 1185 states and 1756 transitions. cyclomatic complexity: 572 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:43,313 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:43,313 INFO L93 Difference]: Finished difference Result 1185 states and 1755 transitions. [2023-11-19 08:02:43,313 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1185 states and 1755 transitions. [2023-11-19 08:02:43,324 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-19 08:02:43,334 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1185 states to 1185 states and 1755 transitions. [2023-11-19 08:02:43,334 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1185 [2023-11-19 08:02:43,335 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1185 [2023-11-19 08:02:43,335 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1185 states and 1755 transitions. [2023-11-19 08:02:43,337 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:43,338 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1755 transitions. [2023-11-19 08:02:43,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1185 states and 1755 transitions. [2023-11-19 08:02:43,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1185 to 1185. [2023-11-19 08:02:43,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.481012658227848) internal successors, (1755), 1184 states have internal predecessors, (1755), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:43,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1755 transitions. [2023-11-19 08:02:43,367 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1755 transitions. [2023-11-19 08:02:43,367 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:02:43,369 INFO L428 stractBuchiCegarLoop]: Abstraction has 1185 states and 1755 transitions. [2023-11-19 08:02:43,369 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-19 08:02:43,369 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1755 transitions. [2023-11-19 08:02:43,378 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-19 08:02:43,378 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:43,378 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:43,380 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:43,380 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:43,381 INFO L748 eck$LassoCheckResult]: Stem: 17035#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 17036#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 17779#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17780#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17503#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 17229#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17230#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17758#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17792#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17785#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17786#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17357#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 17344#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17345#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17154#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17155#L951 assume !(0 == ~M_E~0); 16899#L951-2 assume !(0 == ~T1_E~0); 16900#L956-1 assume !(0 == ~T2_E~0); 17054#L961-1 assume !(0 == ~T3_E~0); 17522#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17523#L971-1 assume !(0 == ~T5_E~0); 17646#L976-1 assume !(0 == ~T6_E~0); 17621#L981-1 assume !(0 == ~T7_E~0); 17393#L986-1 assume !(0 == ~T8_E~0); 17104#L991-1 assume !(0 == ~T9_E~0); 17105#L996-1 assume !(0 == ~E_M~0); 17814#L1001-1 assume !(0 == ~E_1~0); 17573#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 17574#L1011-1 assume !(0 == ~E_3~0); 17793#L1016-1 assume !(0 == ~E_4~0); 17802#L1021-1 assume !(0 == ~E_5~0); 16693#L1026-1 assume !(0 == ~E_6~0); 16694#L1031-1 assume !(0 == ~E_7~0); 17529#L1036-1 assume !(0 == ~E_8~0); 17525#L1041-1 assume !(0 == ~E_9~0); 17526#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17765#L472 assume 1 == ~m_pc~0; 17831#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17554#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17555#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17563#L1179 assume !(0 != activate_threads_~tmp~1#1); 16701#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16702#L491 assume 1 == ~t1_pc~0; 17572#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17199#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16726#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16673#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 16674#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16697#L510 assume !(1 == ~t2_pc~0); 16662#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16663#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17221#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17222#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16954#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16955#L529 assume 1 == ~t3_pc~0; 17306#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17307#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16671#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16672#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 16874#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16875#L548 assume !(1 == ~t4_pc~0); 16768#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16767#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16839#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16810#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 16811#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16755#L567 assume 1 == ~t5_pc~0; 16756#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16812#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17713#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17714#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 17753#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16885#L586 assume !(1 == ~t6_pc~0); 16886#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16958#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17204#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17205#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 17747#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17748#L605 assume 1 == ~t7_pc~0; 17721#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17379#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17556#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17840#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 17839#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17497#L624 assume !(1 == ~t8_pc~0); 16949#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16948#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17606#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17665#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 17731#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16718#L643 assume 1 == ~t9_pc~0; 16719#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17685#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17271#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17111#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 17112#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16931#L1059 assume !(1 == ~M_E~0); 16932#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17082#L1064-1 assume !(1 == ~T2_E~0); 17083#L1069-1 assume !(1 == ~T3_E~0); 17692#L1074-1 assume !(1 == ~T4_E~0); 17729#L1079-1 assume !(1 == ~T5_E~0); 17719#L1084-1 assume !(1 == ~T6_E~0); 17720#L1089-1 assume !(1 == ~T7_E~0); 17743#L1094-1 assume !(1 == ~T8_E~0); 17431#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17432#L1104-1 assume !(1 == ~E_M~0); 17608#L1109-1 assume !(1 == ~E_1~0); 17223#L1114-1 assume !(1 == ~E_2~0); 17224#L1119-1 assume !(1 == ~E_3~0); 17281#L1124-1 assume !(1 == ~E_4~0); 16714#L1129-1 assume !(1 == ~E_5~0); 16715#L1134-1 assume !(1 == ~E_6~0); 17050#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 17051#L1144-1 assume !(1 == ~E_8~0); 17239#L1149-1 assume !(1 == ~E_9~0); 16891#L1154-1 assume { :end_inline_reset_delta_events } true; 16892#L1440-2 [2023-11-19 08:02:43,382 INFO L750 eck$LassoCheckResult]: Loop: 16892#L1440-2 assume !false; 17020#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17595#L926-1 assume !false; 17283#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17284#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16979#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16980#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16987#L795 assume !(0 != eval_~tmp~0#1); 16988#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17440#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17138#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17139#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17656#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17499#L961-3 assume !(0 == ~T3_E~0); 17264#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17265#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17548#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16741#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16742#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16716#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16717#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17643#L1001-3 assume !(0 == ~E_1~0); 17235#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17236#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17664#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17699#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17444#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17445#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17637#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17638#L1041-3 assume !(0 == ~E_9~0); 17690#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17654#L472-33 assume !(1 == ~m_pc~0); 16836#L472-35 is_master_triggered_~__retres1~0#1 := 0; 16837#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17681#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17661#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17274#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17275#L491-33 assume !(1 == ~t1_pc~0); 16775#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 16776#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17808#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17823#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 17824#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17614#L510-33 assume !(1 == ~t2_pc~0); 17609#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 17610#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17648#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17649#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16657#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16658#L529-33 assume 1 == ~t3_pc~0; 16682#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16684#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16849#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16850#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16789#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16790#L548-33 assume 1 == ~t4_pc~0; 17038#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17156#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17580#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17193#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16974#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16975#L567-33 assume !(1 == ~t5_pc~0); 17077#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 17078#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17317#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17828#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17834#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17521#L586-33 assume !(1 == ~t6_pc~0); 17095#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 17096#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17333#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17334#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16991#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16992#L605-33 assume 1 == ~t7_pc~0; 17160#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16916#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16917#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17724#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16801#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16802#L624-33 assume !(1 == ~t8_pc~0); 16961#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 16968#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17498#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17175#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 17176#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16918#L643-33 assume 1 == ~t9_pc~0; 16919#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17005#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17471#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17427#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17428#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16791#L1059-3 assume !(1 == ~M_E~0); 16792#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17295#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17353#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17354#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17622#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17530#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17469#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17470#L1094-3 assume !(1 == ~T8_E~0); 17386#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17387#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17644#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17628#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17629#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17833#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17838#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17089#L1134-3 assume !(1 == ~E_6~0); 17090#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17252#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17253#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17433#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17841#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16794#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17171#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 16679#L1459 assume !(0 == start_simulation_~tmp~3#1); 16680#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17700#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16977#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16721#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 16722#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 17135#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17296#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 17456#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 16892#L1440-2 [2023-11-19 08:02:43,383 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:43,383 INFO L85 PathProgramCache]: Analyzing trace with hash -1747895607, now seen corresponding path program 1 times [2023-11-19 08:02:43,383 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:43,383 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [466531003] [2023-11-19 08:02:43,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:43,384 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:43,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:43,431 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:43,432 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:43,433 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [466531003] [2023-11-19 08:02:43,433 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [466531003] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:43,433 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:43,434 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:43,436 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1184013675] [2023-11-19 08:02:43,436 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:43,436 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:43,437 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:43,437 INFO L85 PathProgramCache]: Analyzing trace with hash -1364817186, now seen corresponding path program 2 times [2023-11-19 08:02:43,437 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:43,439 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1605866273] [2023-11-19 08:02:43,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:43,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:43,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:43,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:43,532 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:43,532 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1605866273] [2023-11-19 08:02:43,532 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1605866273] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:43,532 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:43,532 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:43,533 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [272266685] [2023-11-19 08:02:43,533 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:43,533 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:43,533 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:43,534 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:02:43,534 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:02:43,534 INFO L87 Difference]: Start difference. First operand 1185 states and 1755 transitions. cyclomatic complexity: 571 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:43,577 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:43,577 INFO L93 Difference]: Finished difference Result 1185 states and 1754 transitions. [2023-11-19 08:02:43,577 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1185 states and 1754 transitions. [2023-11-19 08:02:43,587 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-19 08:02:43,598 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1185 states to 1185 states and 1754 transitions. [2023-11-19 08:02:43,599 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1185 [2023-11-19 08:02:43,600 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1185 [2023-11-19 08:02:43,601 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1185 states and 1754 transitions. [2023-11-19 08:02:43,603 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:43,603 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1754 transitions. [2023-11-19 08:02:43,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1185 states and 1754 transitions. [2023-11-19 08:02:43,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1185 to 1185. [2023-11-19 08:02:43,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.480168776371308) internal successors, (1754), 1184 states have internal predecessors, (1754), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:43,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1754 transitions. [2023-11-19 08:02:43,638 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1754 transitions. [2023-11-19 08:02:43,638 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:02:43,641 INFO L428 stractBuchiCegarLoop]: Abstraction has 1185 states and 1754 transitions. [2023-11-19 08:02:43,641 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-19 08:02:43,641 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1754 transitions. [2023-11-19 08:02:43,651 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-19 08:02:43,651 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:43,652 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:43,654 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:43,654 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:43,655 INFO L748 eck$LassoCheckResult]: Stem: 19414#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 19415#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 20156#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20157#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19880#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 19606#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19607#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20135#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20169#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20162#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20163#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19734#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19721#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 19722#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19532#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19533#L951 assume !(0 == ~M_E~0); 19276#L951-2 assume !(0 == ~T1_E~0); 19277#L956-1 assume !(0 == ~T2_E~0); 19431#L961-1 assume !(0 == ~T3_E~0); 19899#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19900#L971-1 assume !(0 == ~T5_E~0); 20023#L976-1 assume !(0 == ~T6_E~0); 19998#L981-1 assume !(0 == ~T7_E~0); 19773#L986-1 assume !(0 == ~T8_E~0); 19481#L991-1 assume !(0 == ~T9_E~0); 19482#L996-1 assume !(0 == ~E_M~0); 20192#L1001-1 assume !(0 == ~E_1~0); 19950#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 19951#L1011-1 assume !(0 == ~E_3~0); 20170#L1016-1 assume !(0 == ~E_4~0); 20179#L1021-1 assume !(0 == ~E_5~0); 19070#L1026-1 assume !(0 == ~E_6~0); 19071#L1031-1 assume !(0 == ~E_7~0); 19906#L1036-1 assume !(0 == ~E_8~0); 19904#L1041-1 assume !(0 == ~E_9~0); 19905#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20142#L472 assume 1 == ~m_pc~0; 20208#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19931#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19932#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19940#L1179 assume !(0 != activate_threads_~tmp~1#1); 19078#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19079#L491 assume 1 == ~t1_pc~0; 19949#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19576#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19103#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19050#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 19051#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19074#L510 assume !(1 == ~t2_pc~0); 19039#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19040#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19598#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19599#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19331#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19332#L529 assume 1 == ~t3_pc~0; 19683#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19684#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19048#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19049#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 19251#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19252#L548 assume !(1 == ~t4_pc~0); 19145#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19144#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19216#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19187#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 19188#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19132#L567 assume 1 == ~t5_pc~0; 19133#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19189#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20090#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20091#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 20130#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19262#L586 assume !(1 == ~t6_pc~0); 19263#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19337#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19584#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19585#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 20124#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20125#L605 assume 1 == ~t7_pc~0; 20098#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19757#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19934#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20217#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 20216#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19874#L624 assume !(1 == ~t8_pc~0); 19326#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19325#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19983#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20042#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 20108#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19095#L643 assume 1 == ~t9_pc~0; 19096#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20062#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19648#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19488#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 19489#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19308#L1059 assume !(1 == ~M_E~0); 19309#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19459#L1064-1 assume !(1 == ~T2_E~0); 19460#L1069-1 assume !(1 == ~T3_E~0); 20069#L1074-1 assume !(1 == ~T4_E~0); 20107#L1079-1 assume !(1 == ~T5_E~0); 20096#L1084-1 assume !(1 == ~T6_E~0); 20097#L1089-1 assume !(1 == ~T7_E~0); 20120#L1094-1 assume !(1 == ~T8_E~0); 19808#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19809#L1104-1 assume !(1 == ~E_M~0); 19987#L1109-1 assume !(1 == ~E_1~0); 19600#L1114-1 assume !(1 == ~E_2~0); 19601#L1119-1 assume !(1 == ~E_3~0); 19658#L1124-1 assume !(1 == ~E_4~0); 19091#L1129-1 assume !(1 == ~E_5~0); 19092#L1134-1 assume !(1 == ~E_6~0); 19427#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19428#L1144-1 assume !(1 == ~E_8~0); 19616#L1149-1 assume !(1 == ~E_9~0); 19268#L1154-1 assume { :end_inline_reset_delta_events } true; 19269#L1440-2 [2023-11-19 08:02:43,656 INFO L750 eck$LassoCheckResult]: Loop: 19269#L1440-2 assume !false; 19399#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19972#L926-1 assume !false; 19660#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19661#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19356#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19357#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19364#L795 assume !(0 != eval_~tmp~0#1); 19365#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19817#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19515#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19516#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20033#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19876#L961-3 assume !(0 == ~T3_E~0); 19644#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19645#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19925#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19118#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19119#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19093#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19094#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20020#L1001-3 assume !(0 == ~E_1~0); 19612#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19613#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20041#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20076#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19822#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19823#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20014#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20015#L1041-3 assume !(0 == ~E_9~0); 20067#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20031#L472-33 assume 1 == ~m_pc~0; 20032#L473-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19214#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20058#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20038#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19651#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19652#L491-33 assume !(1 == ~t1_pc~0); 19152#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 19153#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20185#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20200#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 20201#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19992#L510-33 assume !(1 == ~t2_pc~0); 19985#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 19986#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20025#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20026#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19034#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19035#L529-33 assume 1 == ~t3_pc~0; 19059#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19061#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19224#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19225#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19166#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19167#L548-33 assume 1 == ~t4_pc~0; 19410#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19531#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19957#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19568#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19351#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19352#L567-33 assume 1 == ~t5_pc~0; 19789#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19455#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19693#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20205#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20210#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19898#L586-33 assume !(1 == ~t6_pc~0); 19472#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 19473#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19710#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19711#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19370#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19371#L605-33 assume 1 == ~t7_pc~0; 19540#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19293#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19294#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20101#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19178#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19179#L624-33 assume !(1 == ~t8_pc~0); 19340#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 19348#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19875#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19552#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 19553#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19295#L643-33 assume 1 == ~t9_pc~0; 19296#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19382#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19848#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19804#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19805#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19168#L1059-3 assume !(1 == ~M_E~0); 19169#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19672#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19730#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19731#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19999#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19907#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19846#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19847#L1094-3 assume !(1 == ~T8_E~0); 19763#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19764#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20021#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20005#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20006#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20211#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20215#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19466#L1134-3 assume !(1 == ~E_6~0); 19467#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19632#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19633#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19810#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 20218#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19171#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19550#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 19056#L1459 assume !(0 == start_simulation_~tmp~3#1); 19057#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 20077#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19354#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19098#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 19099#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 19512#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19674#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 19833#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 19269#L1440-2 [2023-11-19 08:02:43,657 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:43,657 INFO L85 PathProgramCache]: Analyzing trace with hash -1866337081, now seen corresponding path program 1 times [2023-11-19 08:02:43,657 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:43,657 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [471952429] [2023-11-19 08:02:43,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:43,658 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:43,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:43,767 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:43,767 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:43,768 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [471952429] [2023-11-19 08:02:43,768 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [471952429] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:43,768 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:43,768 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:43,768 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [219120859] [2023-11-19 08:02:43,769 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:43,769 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:43,770 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:43,770 INFO L85 PathProgramCache]: Analyzing trace with hash 1236036508, now seen corresponding path program 1 times [2023-11-19 08:02:43,770 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:43,771 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [986275364] [2023-11-19 08:02:43,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:43,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:43,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:43,828 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:43,829 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:43,829 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [986275364] [2023-11-19 08:02:43,829 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [986275364] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:43,829 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:43,829 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:43,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [516542212] [2023-11-19 08:02:43,830 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:43,830 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:43,830 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:43,831 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 08:02:43,831 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 08:02:43,831 INFO L87 Difference]: Start difference. First operand 1185 states and 1754 transitions. cyclomatic complexity: 570 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:44,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:44,007 INFO L93 Difference]: Finished difference Result 2171 states and 3201 transitions. [2023-11-19 08:02:44,008 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2171 states and 3201 transitions. [2023-11-19 08:02:44,024 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2024 [2023-11-19 08:02:44,044 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2171 states to 2171 states and 3201 transitions. [2023-11-19 08:02:44,044 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2171 [2023-11-19 08:02:44,047 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2171 [2023-11-19 08:02:44,047 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2171 states and 3201 transitions. [2023-11-19 08:02:44,051 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:44,051 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2171 states and 3201 transitions. [2023-11-19 08:02:44,055 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2171 states and 3201 transitions. [2023-11-19 08:02:44,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2171 to 2171. [2023-11-19 08:02:44,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2171 states, 2171 states have (on average 1.4744357438968216) internal successors, (3201), 2170 states have internal predecessors, (3201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:44,116 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2171 states to 2171 states and 3201 transitions. [2023-11-19 08:02:44,116 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2171 states and 3201 transitions. [2023-11-19 08:02:44,117 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 08:02:44,118 INFO L428 stractBuchiCegarLoop]: Abstraction has 2171 states and 3201 transitions. [2023-11-19 08:02:44,118 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-19 08:02:44,119 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2171 states and 3201 transitions. [2023-11-19 08:02:44,130 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2024 [2023-11-19 08:02:44,130 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:44,130 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:44,132 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:44,133 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:44,133 INFO L748 eck$LassoCheckResult]: Stem: 22784#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 22785#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 23574#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23575#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23263#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 22979#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22980#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23552#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23587#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23580#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23581#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23107#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 23094#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 23095#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22902#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22903#L951 assume !(0 == ~M_E~0); 22645#L951-2 assume !(0 == ~T1_E~0); 22646#L956-1 assume !(0 == ~T2_E~0); 22800#L961-1 assume !(0 == ~T3_E~0); 23284#L966-1 assume !(0 == ~T4_E~0); 23285#L971-1 assume !(0 == ~T5_E~0); 23417#L976-1 assume !(0 == ~T6_E~0); 23391#L981-1 assume !(0 == ~T7_E~0); 23148#L986-1 assume !(0 == ~T8_E~0); 22851#L991-1 assume !(0 == ~T9_E~0); 22852#L996-1 assume !(0 == ~E_M~0); 23617#L1001-1 assume !(0 == ~E_1~0); 23338#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 23339#L1011-1 assume !(0 == ~E_3~0); 23589#L1016-1 assume !(0 == ~E_4~0); 23598#L1021-1 assume !(0 == ~E_5~0); 22436#L1026-1 assume !(0 == ~E_6~0); 22437#L1031-1 assume !(0 == ~E_7~0); 23291#L1036-1 assume !(0 == ~E_8~0); 23289#L1041-1 assume !(0 == ~E_9~0); 23290#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23559#L472 assume 1 == ~m_pc~0; 23634#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23319#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23320#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23328#L1179 assume !(0 != activate_threads_~tmp~1#1); 22444#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22445#L491 assume 1 == ~t1_pc~0; 23337#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22949#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22469#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22416#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 22417#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22440#L510 assume !(1 == ~t2_pc~0); 22405#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 22406#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22969#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22970#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22699#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22700#L529 assume 1 == ~t3_pc~0; 23056#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23057#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22414#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22415#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 22618#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22619#L548 assume !(1 == ~t4_pc~0); 22512#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22511#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22583#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22554#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 22555#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22503#L567 assume 1 == ~t5_pc~0; 22504#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22556#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23496#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23497#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 23546#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22629#L586 assume !(1 == ~t6_pc~0); 22630#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22705#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22955#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22956#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 23538#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23539#L605 assume 1 == ~t7_pc~0; 23504#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23135#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23322#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23648#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 23647#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23257#L624 assume !(1 == ~t8_pc~0); 22694#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22693#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23375#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23441#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 23516#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22461#L643 assume 1 == ~t9_pc~0; 22462#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23463#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23021#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22858#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 22859#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22675#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 22676#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23657#L1064-1 assume !(1 == ~T2_E~0); 23690#L1069-1 assume !(1 == ~T3_E~0); 23689#L1074-1 assume !(1 == ~T4_E~0); 23643#L1079-1 assume !(1 == ~T5_E~0); 23688#L1084-1 assume !(1 == ~T6_E~0); 23687#L1089-1 assume !(1 == ~T7_E~0); 23686#L1094-1 assume !(1 == ~T8_E~0); 23685#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 23684#L1104-1 assume !(1 == ~E_M~0); 23683#L1109-1 assume !(1 == ~E_1~0); 23682#L1114-1 assume !(1 == ~E_2~0); 23681#L1119-1 assume !(1 == ~E_3~0); 23680#L1124-1 assume !(1 == ~E_4~0); 23679#L1129-1 assume !(1 == ~E_5~0); 23678#L1134-1 assume !(1 == ~E_6~0); 23677#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 23676#L1144-1 assume !(1 == ~E_8~0); 23675#L1149-1 assume !(1 == ~E_9~0); 23674#L1154-1 assume { :end_inline_reset_delta_events } true; 23672#L1440-2 [2023-11-19 08:02:44,134 INFO L750 eck$LassoCheckResult]: Loop: 23672#L1440-2 assume !false; 23671#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23670#L926-1 assume !false; 23669#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23667#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 22724#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 22725#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22732#L795 assume !(0 != eval_~tmp~0#1); 22733#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23195#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23196#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23655#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23431#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23260#L961-3 assume !(0 == ~T3_E~0); 23013#L966-3 assume !(0 == ~T4_E~0); 23014#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23311#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22481#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22482#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22457#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22458#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23414#L1001-3 assume !(0 == ~E_1~0); 22983#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22984#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23438#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23478#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23201#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23202#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23408#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23409#L1041-3 assume !(0 == ~E_9~0); 23468#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23427#L472-33 assume 1 == ~m_pc~0; 23428#L473-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 24130#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24129#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24128#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24127#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24126#L491-33 assume 1 == ~t1_pc~0; 24124#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23606#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23607#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23625#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 23626#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23383#L510-33 assume 1 == ~t2_pc~0; 23384#L511-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24119#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24118#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24117#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24116#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24115#L529-33 assume !(1 == ~t3_pc~0); 24113#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 24112#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24111#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24110#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24109#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24108#L548-33 assume 1 == ~t4_pc~0; 24106#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24105#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24104#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24103#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24102#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24101#L567-33 assume !(1 == ~t5_pc~0); 24099#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 24098#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24097#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24096#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24095#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23281#L586-33 assume 1 == ~t6_pc~0; 23282#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24094#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24093#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24092#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24091#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24090#L605-33 assume !(1 == ~t7_pc~0); 24088#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 24087#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24086#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24085#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24084#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24083#L624-33 assume 1 == ~t8_pc~0; 24081#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24080#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24079#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24078#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 24077#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24076#L643-33 assume 1 == ~t9_pc~0; 24074#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24073#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24072#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24071#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24070#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24069#L1059-3 assume !(1 == ~M_E~0); 22536#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24068#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24067#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24066#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23392#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24065#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24064#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24063#L1094-3 assume !(1 == ~T8_E~0); 24062#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24061#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 24060#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24059#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 24058#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 24057#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24056#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24055#L1134-3 assume !(1 == ~E_6~0); 24054#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24053#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23185#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 23186#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23656#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 23710#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 23709#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 23708#L1459 assume !(0 == start_simulation_~tmp~3#1); 23563#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23704#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 23695#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 23694#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 23693#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 23692#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23691#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 23673#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 23672#L1440-2 [2023-11-19 08:02:44,135 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:44,135 INFO L85 PathProgramCache]: Analyzing trace with hash 99525123, now seen corresponding path program 1 times [2023-11-19 08:02:44,135 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:44,135 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [349127484] [2023-11-19 08:02:44,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:44,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:44,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:44,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:44,197 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:44,197 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [349127484] [2023-11-19 08:02:44,198 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [349127484] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:44,198 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:44,198 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 08:02:44,198 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2053569035] [2023-11-19 08:02:44,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:44,200 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:44,200 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:44,201 INFO L85 PathProgramCache]: Analyzing trace with hash -1619670631, now seen corresponding path program 1 times [2023-11-19 08:02:44,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:44,201 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1124265828] [2023-11-19 08:02:44,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:44,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:44,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:44,287 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:44,287 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:44,287 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1124265828] [2023-11-19 08:02:44,288 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1124265828] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:44,288 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:44,288 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:44,288 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [149866438] [2023-11-19 08:02:44,288 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:44,289 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:44,289 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:44,289 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:02:44,289 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:02:44,290 INFO L87 Difference]: Start difference. First operand 2171 states and 3201 transitions. cyclomatic complexity: 1032 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:44,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:44,378 INFO L93 Difference]: Finished difference Result 2171 states and 3171 transitions. [2023-11-19 08:02:44,379 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2171 states and 3171 transitions. [2023-11-19 08:02:44,395 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2024 [2023-11-19 08:02:44,415 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2171 states to 2171 states and 3171 transitions. [2023-11-19 08:02:44,415 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2171 [2023-11-19 08:02:44,418 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2171 [2023-11-19 08:02:44,418 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2171 states and 3171 transitions. [2023-11-19 08:02:44,422 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:44,423 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2171 states and 3171 transitions. [2023-11-19 08:02:44,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2171 states and 3171 transitions. [2023-11-19 08:02:44,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2171 to 2171. [2023-11-19 08:02:44,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2171 states, 2171 states have (on average 1.460617227084293) internal successors, (3171), 2170 states have internal predecessors, (3171), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:44,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2171 states to 2171 states and 3171 transitions. [2023-11-19 08:02:44,487 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2171 states and 3171 transitions. [2023-11-19 08:02:44,487 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:02:44,488 INFO L428 stractBuchiCegarLoop]: Abstraction has 2171 states and 3171 transitions. [2023-11-19 08:02:44,488 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-19 08:02:44,489 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2171 states and 3171 transitions. [2023-11-19 08:02:44,500 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2024 [2023-11-19 08:02:44,501 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:44,501 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:44,503 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:44,503 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:44,504 INFO L748 eck$LassoCheckResult]: Stem: 27127#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 27128#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 27921#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27922#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27615#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 27326#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27327#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27897#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27938#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27930#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27931#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27457#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 27444#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27445#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27250#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27251#L951 assume !(0 == ~M_E~0); 26990#L951-2 assume !(0 == ~T1_E~0); 26991#L956-1 assume !(0 == ~T2_E~0); 27148#L961-1 assume !(0 == ~T3_E~0); 27634#L966-1 assume !(0 == ~T4_E~0); 27635#L971-1 assume !(0 == ~T5_E~0); 27769#L976-1 assume !(0 == ~T6_E~0); 27744#L981-1 assume !(0 == ~T7_E~0); 27497#L986-1 assume !(0 == ~T8_E~0); 27200#L991-1 assume !(0 == ~T9_E~0); 27201#L996-1 assume !(0 == ~E_M~0); 27968#L1001-1 assume !(0 == ~E_1~0); 27687#L1006-1 assume !(0 == ~E_2~0); 27688#L1011-1 assume !(0 == ~E_3~0); 27939#L1016-1 assume !(0 == ~E_4~0); 27948#L1021-1 assume !(0 == ~E_5~0); 26784#L1026-1 assume !(0 == ~E_6~0); 26785#L1031-1 assume !(0 == ~E_7~0); 27643#L1036-1 assume !(0 == ~E_8~0); 27639#L1041-1 assume !(0 == ~E_9~0); 27640#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27904#L472 assume 1 == ~m_pc~0; 27987#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 27668#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27669#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27677#L1179 assume !(0 != activate_threads_~tmp~1#1); 26792#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26793#L491 assume 1 == ~t1_pc~0; 27686#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27296#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26818#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26765#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 26766#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26786#L510 assume !(1 == ~t2_pc~0); 26754#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26755#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27318#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27319#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27046#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27047#L529 assume 1 == ~t3_pc~0; 27406#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27407#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26763#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26764#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 26965#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26966#L548 assume !(1 == ~t4_pc~0); 26860#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 26859#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26931#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26900#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 26901#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26847#L567 assume 1 == ~t5_pc~0; 26848#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26902#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27848#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27849#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 27891#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26976#L586 assume !(1 == ~t6_pc~0); 26977#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27050#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27301#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27302#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 27885#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27886#L605 assume 1 == ~t7_pc~0; 27856#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27478#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27670#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27996#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 27995#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27609#L624 assume !(1 == ~t8_pc~0); 27041#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27040#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27728#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27791#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 27867#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26809#L643 assume 1 == ~t9_pc~0; 26810#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27814#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27369#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27205#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 27206#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27022#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 27023#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27176#L1064-1 assume !(1 == ~T2_E~0); 27177#L1069-1 assume !(1 == ~T3_E~0); 27823#L1074-1 assume !(1 == ~T4_E~0); 27865#L1079-1 assume !(1 == ~T5_E~0); 27854#L1084-1 assume !(1 == ~T6_E~0); 27855#L1089-1 assume !(1 == ~T7_E~0); 27880#L1094-1 assume !(1 == ~T8_E~0); 27534#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27535#L1104-1 assume !(1 == ~E_M~0); 27730#L1109-1 assume !(1 == ~E_1~0); 27320#L1114-1 assume !(1 == ~E_2~0); 27321#L1119-1 assume !(1 == ~E_3~0); 27381#L1124-1 assume !(1 == ~E_4~0); 26805#L1129-1 assume !(1 == ~E_5~0); 26806#L1134-1 assume !(1 == ~E_6~0); 27144#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 27145#L1144-1 assume !(1 == ~E_8~0); 27334#L1149-1 assume !(1 == ~E_9~0); 26982#L1154-1 assume { :end_inline_reset_delta_events } true; 26983#L1440-2 [2023-11-19 08:02:44,505 INFO L750 eck$LassoCheckResult]: Loop: 26983#L1440-2 assume !false; 27963#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27716#L926-1 assume !false; 27383#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27384#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 27068#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 27069#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 28008#L795 assume !(0 != eval_~tmp~0#1); 27795#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27796#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28006#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28007#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28889#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28888#L961-3 assume !(0 == ~T3_E~0); 28887#L966-3 assume !(0 == ~T4_E~0); 28886#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28885#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28884#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28883#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28882#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28881#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28880#L1001-3 assume !(0 == ~E_1~0); 28879#L1006-3 assume !(0 == ~E_2~0); 28878#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28877#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28876#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28875#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28874#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28873#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28872#L1041-3 assume !(0 == ~E_9~0); 28871#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28870#L472-33 assume !(1 == ~m_pc~0); 28868#L472-35 is_master_triggered_~__retres1~0#1 := 0; 28867#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28866#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28865#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28864#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28863#L491-33 assume 1 == ~t1_pc~0; 28861#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28860#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28859#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28858#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 28857#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28856#L510-33 assume !(1 == ~t2_pc~0); 28854#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 28853#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28852#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28851#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28850#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28849#L529-33 assume 1 == ~t3_pc~0; 28848#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28846#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28845#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28844#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28843#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28842#L548-33 assume 1 == ~t4_pc~0; 28840#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28839#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28838#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28837#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28836#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28835#L567-33 assume !(1 == ~t5_pc~0); 28833#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 28832#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28831#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28830#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28829#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28828#L586-33 assume 1 == ~t6_pc~0; 28826#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28825#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28824#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28652#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 28651#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28650#L605-33 assume !(1 == ~t7_pc~0); 28647#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 28644#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28642#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28640#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28638#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28636#L624-33 assume 1 == ~t8_pc~0; 28633#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28630#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28628#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28626#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 28624#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27015#L643-33 assume 1 == ~t9_pc~0; 27016#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27097#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27575#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27530#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27531#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26883#L1059-3 assume !(1 == ~M_E~0); 26884#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27395#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27454#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27455#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27745#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27644#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27573#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27574#L1094-3 assume !(1 == ~T8_E~0); 27488#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27489#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 27767#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27753#L1114-3 assume !(1 == ~E_2~0); 27754#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27990#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27994#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27184#L1134-3 assume !(1 == ~E_6~0); 27185#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27357#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27358#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27536#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27997#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26888#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 28161#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 28160#L1459 assume !(0 == start_simulation_~tmp~3#1); 27909#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 28045#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 28035#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 28034#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 28033#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 28032#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28031#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 27828#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 26983#L1440-2 [2023-11-19 08:02:44,506 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:44,506 INFO L85 PathProgramCache]: Analyzing trace with hash 1976588353, now seen corresponding path program 1 times [2023-11-19 08:02:44,506 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:44,506 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1301358397] [2023-11-19 08:02:44,507 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:44,507 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:44,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:44,576 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:44,577 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:44,577 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1301358397] [2023-11-19 08:02:44,577 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1301358397] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:44,577 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:44,577 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 08:02:44,578 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1329385293] [2023-11-19 08:02:44,578 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:44,578 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:44,579 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:44,579 INFO L85 PathProgramCache]: Analyzing trace with hash -627598118, now seen corresponding path program 1 times [2023-11-19 08:02:44,579 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:44,579 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1959684345] [2023-11-19 08:02:44,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:44,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:44,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:44,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:44,658 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:44,658 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1959684345] [2023-11-19 08:02:44,658 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1959684345] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:44,658 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:44,658 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:44,659 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1596341662] [2023-11-19 08:02:44,659 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:44,659 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:44,675 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:44,676 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:02:44,676 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:02:44,676 INFO L87 Difference]: Start difference. First operand 2171 states and 3171 transitions. cyclomatic complexity: 1002 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:44,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:44,812 INFO L93 Difference]: Finished difference Result 4155 states and 6010 transitions. [2023-11-19 08:02:44,812 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4155 states and 6010 transitions. [2023-11-19 08:02:44,841 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4007 [2023-11-19 08:02:44,875 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4155 states to 4155 states and 6010 transitions. [2023-11-19 08:02:44,876 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4155 [2023-11-19 08:02:44,881 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4155 [2023-11-19 08:02:44,881 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4155 states and 6010 transitions. [2023-11-19 08:02:44,889 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:44,889 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4155 states and 6010 transitions. [2023-11-19 08:02:44,896 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4155 states and 6010 transitions. [2023-11-19 08:02:44,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4155 to 4017. [2023-11-19 08:02:44,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4017 states, 4017 states have (on average 1.4483445357231766) internal successors, (5818), 4016 states have internal predecessors, (5818), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:45,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4017 states to 4017 states and 5818 transitions. [2023-11-19 08:02:45,072 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4017 states and 5818 transitions. [2023-11-19 08:02:45,072 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:02:45,073 INFO L428 stractBuchiCegarLoop]: Abstraction has 4017 states and 5818 transitions. [2023-11-19 08:02:45,073 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-19 08:02:45,073 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4017 states and 5818 transitions. [2023-11-19 08:02:45,093 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3869 [2023-11-19 08:02:45,093 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:45,094 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:45,096 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:45,096 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:45,097 INFO L748 eck$LassoCheckResult]: Stem: 33463#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 33464#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 34318#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34319#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33974#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 33675#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33676#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34281#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34348#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34335#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34336#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33814#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33799#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33800#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33591#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33592#L951 assume !(0 == ~M_E~0); 33323#L951-2 assume !(0 == ~T1_E~0); 33324#L956-1 assume !(0 == ~T2_E~0); 33487#L961-1 assume !(0 == ~T3_E~0); 33997#L966-1 assume !(0 == ~T4_E~0); 33998#L971-1 assume !(0 == ~T5_E~0); 34134#L976-1 assume !(0 == ~T6_E~0); 34106#L981-1 assume !(0 == ~T7_E~0); 33854#L986-1 assume !(0 == ~T8_E~0); 33540#L991-1 assume !(0 == ~T9_E~0); 33541#L996-1 assume !(0 == ~E_M~0); 34387#L1001-1 assume !(0 == ~E_1~0); 34052#L1006-1 assume !(0 == ~E_2~0); 34053#L1011-1 assume !(0 == ~E_3~0); 34349#L1016-1 assume !(0 == ~E_4~0); 34364#L1021-1 assume !(0 == ~E_5~0); 33117#L1026-1 assume !(0 == ~E_6~0); 33118#L1031-1 assume !(0 == ~E_7~0); 34004#L1036-1 assume !(0 == ~E_8~0); 34000#L1041-1 assume !(0 == ~E_9~0); 34001#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34291#L472 assume !(1 == ~m_pc~0); 34236#L472-2 is_master_triggered_~__retres1~0#1 := 0; 34031#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34032#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 34041#L1179 assume !(0 != activate_threads_~tmp~1#1); 33125#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33126#L491 assume 1 == ~t1_pc~0; 34051#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33640#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33151#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33098#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 33099#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33119#L510 assume !(1 == ~t2_pc~0); 33087#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33088#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33663#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33664#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33378#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33379#L529 assume 1 == ~t3_pc~0; 33758#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33759#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33096#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33097#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 33298#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33299#L548 assume !(1 == ~t4_pc~0); 33192#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33191#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33263#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33232#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 33233#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33179#L567 assume 1 == ~t5_pc~0; 33180#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33234#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34218#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34219#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 34275#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33309#L586 assume !(1 == ~t6_pc~0); 33310#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 33382#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33645#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33646#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 34267#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34268#L605 assume 1 == ~t7_pc~0; 34226#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33834#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34034#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34430#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 34427#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33967#L624 assume !(1 == ~t8_pc~0); 33373#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 33372#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34090#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34156#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 34240#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33142#L643 assume 1 == ~t9_pc~0; 33143#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34183#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33722#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33547#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 33548#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33355#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 33356#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36065#L1064-1 assume !(1 == ~T2_E~0); 36064#L1069-1 assume !(1 == ~T3_E~0); 36063#L1074-1 assume !(1 == ~T4_E~0); 34424#L1079-1 assume !(1 == ~T5_E~0); 36062#L1084-1 assume !(1 == ~T6_E~0); 36061#L1089-1 assume !(1 == ~T7_E~0); 36060#L1094-1 assume !(1 == ~T8_E~0); 36059#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36058#L1104-1 assume !(1 == ~E_M~0); 36057#L1109-1 assume !(1 == ~E_1~0); 36056#L1114-1 assume !(1 == ~E_2~0); 36055#L1119-1 assume !(1 == ~E_3~0); 36054#L1124-1 assume !(1 == ~E_4~0); 36053#L1129-1 assume !(1 == ~E_5~0); 36052#L1134-1 assume !(1 == ~E_6~0); 36051#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 36050#L1144-1 assume !(1 == ~E_8~0); 36049#L1149-1 assume !(1 == ~E_9~0); 36048#L1154-1 assume { :end_inline_reset_delta_events } true; 36046#L1440-2 [2023-11-19 08:02:45,098 INFO L750 eck$LassoCheckResult]: Loop: 36046#L1440-2 assume !false; 36045#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36041#L926-1 assume !false; 36040#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 36038#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 36029#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 36028#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 36026#L795 assume !(0 != eval_~tmp~0#1); 36025#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36024#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36023#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34450#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34145#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34146#L961-3 assume !(0 == ~T3_E~0); 35299#L966-3 assume !(0 == ~T4_E~0); 35298#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35297#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35296#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35295#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 35294#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35293#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35292#L1001-3 assume !(0 == ~E_1~0); 35291#L1006-3 assume !(0 == ~E_2~0); 35290#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35289#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35288#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35287#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 35286#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 35285#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34445#L1041-3 assume !(0 == ~E_9~0); 34188#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34143#L472-33 assume !(1 == ~m_pc~0); 33257#L472-35 is_master_triggered_~__retres1~0#1 := 0; 33258#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34175#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 34152#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33725#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33726#L491-33 assume 1 == ~t1_pc~0; 34042#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33200#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34376#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34400#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 34401#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34099#L510-33 assume !(1 == ~t2_pc~0); 34094#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 34095#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34136#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34137#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33082#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33083#L529-33 assume 1 == ~t3_pc~0; 33107#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33109#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33273#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33274#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33213#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33214#L548-33 assume 1 == ~t4_pc~0; 33466#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33593#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34059#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33633#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33634#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35178#L567-33 assume !(1 == ~t5_pc~0); 35176#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 35175#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35174#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35173#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 35172#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35171#L586-33 assume 1 == ~t6_pc~0; 35169#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 35168#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35167#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35166#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35165#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35164#L605-33 assume !(1 == ~t7_pc~0); 35162#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 33337#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33338#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34232#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33225#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33226#L624-33 assume !(1 == ~t8_pc~0); 33385#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 33392#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33968#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33615#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 33616#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33339#L643-33 assume 1 == ~t9_pc~0; 33340#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33429#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33937#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33890#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33891#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33215#L1059-3 assume !(1 == ~M_E~0); 33216#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33747#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33809#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33810#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 34107#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34005#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33935#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33936#L1094-3 assume !(1 == ~T8_E~0); 33844#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33845#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 34131#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34113#L1114-3 assume !(1 == ~E_2~0); 34114#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34413#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34423#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33524#L1134-3 assume !(1 == ~E_6~0); 33525#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33700#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33701#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33896#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 34436#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 33218#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 33610#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 33104#L1459 assume !(0 == start_simulation_~tmp~3#1); 33105#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 34991#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 36070#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 36069#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 36068#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 36067#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36066#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 36047#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 36046#L1440-2 [2023-11-19 08:02:45,098 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:45,099 INFO L85 PathProgramCache]: Analyzing trace with hash -858385022, now seen corresponding path program 1 times [2023-11-19 08:02:45,099 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:45,099 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1171116409] [2023-11-19 08:02:45,099 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:45,100 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:45,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:45,180 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:45,180 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:45,181 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1171116409] [2023-11-19 08:02:45,181 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1171116409] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:45,181 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:45,181 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:45,181 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1650628095] [2023-11-19 08:02:45,182 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:45,182 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:45,182 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:45,183 INFO L85 PathProgramCache]: Analyzing trace with hash -1501075813, now seen corresponding path program 1 times [2023-11-19 08:02:45,183 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:45,183 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1112139389] [2023-11-19 08:02:45,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:45,184 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:45,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:45,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:45,239 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:45,239 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1112139389] [2023-11-19 08:02:45,239 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1112139389] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:45,239 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:45,240 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:45,240 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [389195896] [2023-11-19 08:02:45,240 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:45,240 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:45,241 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:45,241 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 08:02:45,241 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 08:02:45,241 INFO L87 Difference]: Start difference. First operand 4017 states and 5818 transitions. cyclomatic complexity: 1805 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:45,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:45,563 INFO L93 Difference]: Finished difference Result 9625 states and 13799 transitions. [2023-11-19 08:02:45,563 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9625 states and 13799 transitions. [2023-11-19 08:02:45,634 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 9324 [2023-11-19 08:02:45,696 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9625 states to 9625 states and 13799 transitions. [2023-11-19 08:02:45,696 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9625 [2023-11-19 08:02:45,708 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9625 [2023-11-19 08:02:45,708 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9625 states and 13799 transitions. [2023-11-19 08:02:45,724 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:45,725 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9625 states and 13799 transitions. [2023-11-19 08:02:45,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9625 states and 13799 transitions. [2023-11-19 08:02:45,975 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9625 to 7549. [2023-11-19 08:02:45,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7549 states, 7549 states have (on average 1.439395946482978) internal successors, (10866), 7548 states have internal predecessors, (10866), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:46,021 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7549 states to 7549 states and 10866 transitions. [2023-11-19 08:02:46,021 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7549 states and 10866 transitions. [2023-11-19 08:02:46,022 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 08:02:46,022 INFO L428 stractBuchiCegarLoop]: Abstraction has 7549 states and 10866 transitions. [2023-11-19 08:02:46,022 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-19 08:02:46,023 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7549 states and 10866 transitions. [2023-11-19 08:02:46,061 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7400 [2023-11-19 08:02:46,062 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:46,062 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:46,064 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:46,065 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:46,065 INFO L748 eck$LassoCheckResult]: Stem: 47110#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 47111#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 47939#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47940#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47602#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 47317#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47318#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47913#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47964#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47951#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47952#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 47451#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 47437#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 47438#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47235#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47236#L951 assume !(0 == ~M_E~0); 46974#L951-2 assume !(0 == ~T1_E~0); 46975#L956-1 assume !(0 == ~T2_E~0); 47133#L961-1 assume !(0 == ~T3_E~0); 47624#L966-1 assume !(0 == ~T4_E~0); 47625#L971-1 assume !(0 == ~T5_E~0); 47755#L976-1 assume !(0 == ~T6_E~0); 47730#L981-1 assume !(0 == ~T7_E~0); 47489#L986-1 assume !(0 == ~T8_E~0); 47183#L991-1 assume !(0 == ~T9_E~0); 47184#L996-1 assume !(0 == ~E_M~0); 48005#L1001-1 assume !(0 == ~E_1~0); 47676#L1006-1 assume !(0 == ~E_2~0); 47677#L1011-1 assume !(0 == ~E_3~0); 47965#L1016-1 assume !(0 == ~E_4~0); 47986#L1021-1 assume !(0 == ~E_5~0); 46769#L1026-1 assume !(0 == ~E_6~0); 46770#L1031-1 assume !(0 == ~E_7~0); 47631#L1036-1 assume !(0 == ~E_8~0); 47627#L1041-1 assume !(0 == ~E_9~0); 47628#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47922#L472 assume !(1 == ~m_pc~0); 47867#L472-2 is_master_triggered_~__retres1~0#1 := 0; 47655#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47656#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47665#L1179 assume !(0 != activate_threads_~tmp~1#1); 46777#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46778#L491 assume !(1 == ~t1_pc~0); 47281#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47282#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46803#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 46750#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 46751#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46771#L510 assume !(1 == ~t2_pc~0); 46739#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 46740#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47304#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47305#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47029#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47030#L529 assume 1 == ~t3_pc~0; 47399#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47400#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46748#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46749#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 46949#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46950#L548 assume !(1 == ~t4_pc~0); 46844#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 46843#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46914#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46884#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 46885#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46831#L567 assume 1 == ~t5_pc~0; 46832#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46886#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47850#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47851#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 47907#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46960#L586 assume !(1 == ~t6_pc~0); 46961#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 47033#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47287#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47288#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 47897#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47898#L605 assume 1 == ~t7_pc~0; 47858#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47471#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47657#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48038#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 48036#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47596#L624 assume !(1 == ~t8_pc~0); 47024#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 47023#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47714#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47781#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 47872#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 46794#L643 assume 1 == ~t9_pc~0; 46795#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47810#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47360#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47188#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 47189#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47006#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 47007#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 48048#L1064-1 assume !(1 == ~T2_E~0); 47822#L1069-1 assume !(1 == ~T3_E~0); 47823#L1074-1 assume !(1 == ~T4_E~0); 47869#L1079-1 assume !(1 == ~T5_E~0); 47870#L1084-1 assume !(1 == ~T6_E~0); 47969#L1089-1 assume !(1 == ~T7_E~0); 47970#L1094-1 assume !(1 == ~T8_E~0); 47527#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47528#L1104-1 assume !(1 == ~E_M~0); 47716#L1109-1 assume !(1 == ~E_1~0); 47717#L1114-1 assume !(1 == ~E_2~0); 48041#L1119-1 assume !(1 == ~E_3~0); 48042#L1124-1 assume !(1 == ~E_4~0); 46790#L1129-1 assume !(1 == ~E_5~0); 46791#L1134-1 assume !(1 == ~E_6~0); 47129#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 47130#L1144-1 assume !(1 == ~E_8~0); 48046#L1149-1 assume !(1 == ~E_9~0); 48047#L1154-1 assume { :end_inline_reset_delta_events } true; 53413#L1440-2 [2023-11-19 08:02:46,066 INFO L750 eck$LassoCheckResult]: Loop: 53413#L1440-2 assume !false; 53405#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47937#L926-1 assume !false; 47938#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 47762#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 47051#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 47052#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 53393#L795 assume !(0 != eval_~tmp~0#1); 47785#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47786#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53392#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 48044#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 47772#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 47598#L961-3 assume !(0 == ~T3_E~0); 47354#L966-3 assume !(0 == ~T4_E~0); 47355#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47650#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46815#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 46816#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 46792#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46793#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 47752#L1001-3 assume !(0 == ~E_1~0); 47323#L1006-3 assume !(0 == ~E_2~0); 47324#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47780#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 47831#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47540#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47541#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 47747#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47748#L1041-3 assume !(0 == ~E_9~0); 47816#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47768#L472-33 assume !(1 == ~m_pc~0); 46908#L472-35 is_master_triggered_~__retres1~0#1 := 0; 46909#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47803#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47777#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47365#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47366#L491-33 assume !(1 == ~t1_pc~0); 46851#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 46852#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47994#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 48016#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 48017#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47720#L510-33 assume !(1 == ~t2_pc~0); 47718#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 47719#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47757#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47758#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46734#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46735#L529-33 assume 1 == ~t3_pc~0; 46759#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46761#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46923#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46924#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46865#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46866#L548-33 assume 1 == ~t4_pc~0; 47112#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 47237#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47683#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47275#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47049#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47050#L567-33 assume !(1 == ~t5_pc~0); 47156#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 47157#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47409#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48021#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 48026#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47623#L586-33 assume 1 == ~t6_pc~0; 47585#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47175#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47427#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47428#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47068#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47069#L605-33 assume 1 == ~t7_pc~0; 47242#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46994#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46995#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47864#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 46877#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46878#L624-33 assume !(1 == ~t8_pc~0); 47036#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 47046#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47597#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47257#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 47258#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 46996#L643-33 assume 1 == ~t9_pc~0; 46997#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47082#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47567#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47523#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47524#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46867#L1059-3 assume !(1 == ~M_E~0); 46868#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 47387#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47448#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47449#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47731#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47632#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 47565#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 47566#L1094-3 assume !(1 == ~T8_E~0); 47481#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47482#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 47753#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 47740#L1114-3 assume !(1 == ~E_2~0); 47741#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 48027#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48033#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47168#L1134-3 assume !(1 == ~E_6~0); 47169#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47347#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 47348#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47529#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 48039#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 46872#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 47255#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 46756#L1459 assume !(0 == start_simulation_~tmp~3#1); 46757#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 47959#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 47054#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 46797#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 46798#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 47214#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47391#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 47555#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 53413#L1440-2 [2023-11-19 08:02:46,067 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:46,067 INFO L85 PathProgramCache]: Analyzing trace with hash -717285501, now seen corresponding path program 1 times [2023-11-19 08:02:46,067 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:46,068 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [133435648] [2023-11-19 08:02:46,068 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:46,068 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:46,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:46,143 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:46,143 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:46,144 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [133435648] [2023-11-19 08:02:46,144 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [133435648] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:46,144 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:46,144 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 08:02:46,144 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1529159708] [2023-11-19 08:02:46,144 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:46,145 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:46,145 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:46,146 INFO L85 PathProgramCache]: Analyzing trace with hash -885474789, now seen corresponding path program 1 times [2023-11-19 08:02:46,146 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:46,146 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [560003761] [2023-11-19 08:02:46,146 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:46,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:46,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:46,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:46,198 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:46,198 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [560003761] [2023-11-19 08:02:46,198 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [560003761] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:46,198 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:46,198 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:46,199 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1002665258] [2023-11-19 08:02:46,199 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:46,199 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:46,199 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:46,200 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 08:02:46,200 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 08:02:46,200 INFO L87 Difference]: Start difference. First operand 7549 states and 10866 transitions. cyclomatic complexity: 3321 Second operand has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:46,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:46,593 INFO L93 Difference]: Finished difference Result 9239 states and 13171 transitions. [2023-11-19 08:02:46,594 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9239 states and 13171 transitions. [2023-11-19 08:02:46,661 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9088 [2023-11-19 08:02:46,706 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9239 states to 9239 states and 13171 transitions. [2023-11-19 08:02:46,706 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9239 [2023-11-19 08:02:46,717 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9239 [2023-11-19 08:02:46,717 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9239 states and 13171 transitions. [2023-11-19 08:02:46,733 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:46,733 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9239 states and 13171 transitions. [2023-11-19 08:02:46,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9239 states and 13171 transitions. [2023-11-19 08:02:46,899 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9239 to 7561. [2023-11-19 08:02:46,921 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7561 states, 7561 states have (on average 1.427985716175109) internal successors, (10797), 7560 states have internal predecessors, (10797), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:46,950 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7561 states to 7561 states and 10797 transitions. [2023-11-19 08:02:46,950 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7561 states and 10797 transitions. [2023-11-19 08:02:46,950 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-19 08:02:46,951 INFO L428 stractBuchiCegarLoop]: Abstraction has 7561 states and 10797 transitions. [2023-11-19 08:02:46,951 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-19 08:02:46,951 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7561 states and 10797 transitions. [2023-11-19 08:02:46,993 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7412 [2023-11-19 08:02:46,993 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:46,993 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:46,996 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:46,996 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:46,997 INFO L748 eck$LassoCheckResult]: Stem: 63917#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 63918#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 64810#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64811#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64441#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 64136#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 64137#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64781#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64845#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 64825#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64826#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 64276#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 64262#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 64263#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 64047#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 64048#L951 assume !(0 == ~M_E~0); 63777#L951-2 assume !(0 == ~T1_E~0); 63778#L956-1 assume !(0 == ~T2_E~0); 63939#L961-1 assume !(0 == ~T3_E~0); 64465#L966-1 assume !(0 == ~T4_E~0); 64466#L971-1 assume !(0 == ~T5_E~0); 64612#L976-1 assume !(0 == ~T6_E~0); 64585#L981-1 assume !(0 == ~T7_E~0); 64317#L986-1 assume !(0 == ~T8_E~0); 63993#L991-1 assume !(0 == ~T9_E~0); 63994#L996-1 assume !(0 == ~E_M~0); 64887#L1001-1 assume !(0 == ~E_1~0); 64525#L1006-1 assume !(0 == ~E_2~0); 64526#L1011-1 assume !(0 == ~E_3~0); 64846#L1016-1 assume !(0 == ~E_4~0); 64868#L1021-1 assume !(0 == ~E_5~0); 63570#L1026-1 assume !(0 == ~E_6~0); 63571#L1031-1 assume !(0 == ~E_7~0); 64476#L1036-1 assume !(0 == ~E_8~0); 64472#L1041-1 assume !(0 == ~E_9~0); 64473#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64791#L472 assume !(1 == ~m_pc~0); 64724#L472-2 is_master_triggered_~__retres1~0#1 := 0; 64505#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64506#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 64514#L1179 assume !(0 != activate_threads_~tmp~1#1); 63578#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63579#L491 assume !(1 == ~t1_pc~0); 64103#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 64104#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63604#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 63551#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 63552#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63572#L510 assume !(1 == ~t2_pc~0); 63540#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 63541#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64126#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 64127#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 63832#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63833#L529 assume 1 == ~t3_pc~0; 64219#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 64220#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63549#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63550#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 63752#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63753#L548 assume !(1 == ~t4_pc~0); 63645#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 63644#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 63717#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 63686#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 63687#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 63632#L567 assume 1 == ~t5_pc~0; 63633#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 63688#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64705#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64706#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 64773#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63763#L586 assume !(1 == ~t6_pc~0); 63764#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 63836#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64109#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 64110#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 64762#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64763#L605 assume 1 == ~t7_pc~0; 64713#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 64296#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64507#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64944#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 64942#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64434#L624 assume !(1 == ~t8_pc~0); 63827#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 63826#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64567#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 64635#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 64730#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63595#L643 assume 1 == ~t9_pc~0; 63596#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 64663#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64180#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 63999#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 64000#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63809#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 63810#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 63969#L1064-1 assume !(1 == ~T2_E~0); 63970#L1069-1 assume !(1 == ~T3_E~0); 64675#L1074-1 assume !(1 == ~T4_E~0); 64726#L1079-1 assume !(1 == ~T5_E~0); 64711#L1084-1 assume !(1 == ~T6_E~0); 64712#L1089-1 assume !(1 == ~T7_E~0); 64754#L1094-1 assume !(1 == ~T8_E~0); 64355#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 64356#L1104-1 assume !(1 == ~E_M~0); 64571#L1109-1 assume !(1 == ~E_1~0); 64128#L1114-1 assume !(1 == ~E_2~0); 64129#L1119-1 assume !(1 == ~E_3~0); 64193#L1124-1 assume !(1 == ~E_4~0); 63591#L1129-1 assume !(1 == ~E_5~0); 63592#L1134-1 assume !(1 == ~E_6~0); 64445#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 67088#L1144-1 assume !(1 == ~E_8~0); 64968#L1149-1 assume !(1 == ~E_9~0); 64969#L1154-1 assume { :end_inline_reset_delta_events } true; 67054#L1440-2 [2023-11-19 08:02:46,997 INFO L750 eck$LassoCheckResult]: Loop: 67054#L1440-2 assume !false; 67048#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 67044#L926-1 assume !false; 67043#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 67041#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 67032#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 67031#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 67029#L795 assume !(0 != eval_~tmp~0#1); 67030#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 67790#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 67789#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 67788#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 67787#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 67786#L961-3 assume !(0 == ~T3_E~0); 67785#L966-3 assume !(0 == ~T4_E~0); 67784#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 67783#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 67782#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 67781#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 67780#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 67779#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 67778#L1001-3 assume !(0 == ~E_1~0); 67777#L1006-3 assume !(0 == ~E_2~0); 67776#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 67775#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 67774#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 67773#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 67772#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 67771#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 67770#L1041-3 assume !(0 == ~E_9~0); 67769#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67768#L472-33 assume !(1 == ~m_pc~0); 67767#L472-35 is_master_triggered_~__retres1~0#1 := 0; 67766#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67765#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 67764#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 67763#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67762#L491-33 assume !(1 == ~t1_pc~0); 67759#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 67758#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67757#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 67756#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 67755#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 67754#L510-33 assume !(1 == ~t2_pc~0); 67752#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 64889#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64615#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 64616#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 64692#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67749#L529-33 assume 1 == ~t3_pc~0; 63560#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 63562#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63844#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64907#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 64908#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67747#L548-33 assume 1 == ~t4_pc~0; 64049#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 64050#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64534#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 67741#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 63854#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 63855#L567-33 assume !(1 == ~t5_pc~0); 67735#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 67733#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64905#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64906#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 67729#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64462#L586-33 assume !(1 == ~t6_pc~0); 64464#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 67724#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 67722#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 67720#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 63875#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 63876#L605-33 assume 1 == ~t7_pc~0; 64976#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 63797#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63798#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64720#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 64949#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 63839#L624-33 assume !(1 == ~t8_pc~0); 63840#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 63851#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 67701#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 64078#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 64079#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 67696#L643-33 assume 1 == ~t9_pc~0; 64467#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 63888#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 67692#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 64351#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 64352#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64750#L1059-3 assume !(1 == ~M_E~0); 63670#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 64207#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 64273#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 64274#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 64586#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 64814#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 67670#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 64538#L1094-3 assume !(1 == ~T8_E~0); 64308#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 64309#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 64610#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 67657#L1114-3 assume !(1 == ~E_2~0); 64920#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 64921#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 64974#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 67650#L1134-3 assume !(1 == ~E_6~0); 64419#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 64167#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 64168#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 64971#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 64972#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 67573#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 64075#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 64076#L1459 assume !(0 == start_simulation_~tmp~3#1); 67555#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 67465#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 67292#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 67090#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 67089#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 67087#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 67069#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 67061#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 67054#L1440-2 [2023-11-19 08:02:46,998 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:46,998 INFO L85 PathProgramCache]: Analyzing trace with hash 1891501957, now seen corresponding path program 1 times [2023-11-19 08:02:46,999 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:46,999 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1435204138] [2023-11-19 08:02:46,999 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:46,999 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:47,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:47,108 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:47,109 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:47,109 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1435204138] [2023-11-19 08:02:47,109 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1435204138] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:47,110 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:47,110 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:47,110 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [473061117] [2023-11-19 08:02:47,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:47,112 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:47,113 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:47,113 INFO L85 PathProgramCache]: Analyzing trace with hash -618141858, now seen corresponding path program 1 times [2023-11-19 08:02:47,113 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:47,114 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [994720083] [2023-11-19 08:02:47,114 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:47,114 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:47,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:47,272 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:47,272 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:47,272 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [994720083] [2023-11-19 08:02:47,273 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [994720083] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:47,273 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:47,273 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:47,273 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1016408836] [2023-11-19 08:02:47,274 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:47,274 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:47,274 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:47,275 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 08:02:47,275 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 08:02:47,276 INFO L87 Difference]: Start difference. First operand 7561 states and 10797 transitions. cyclomatic complexity: 3240 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:47,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:47,614 INFO L93 Difference]: Finished difference Result 18189 states and 25751 transitions. [2023-11-19 08:02:47,614 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18189 states and 25751 transitions. [2023-11-19 08:02:47,717 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 17735 [2023-11-19 08:02:47,785 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18189 states to 18189 states and 25751 transitions. [2023-11-19 08:02:47,785 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18189 [2023-11-19 08:02:47,806 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18189 [2023-11-19 08:02:47,806 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18189 states and 25751 transitions. [2023-11-19 08:02:47,828 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:47,828 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18189 states and 25751 transitions. [2023-11-19 08:02:47,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18189 states and 25751 transitions. [2023-11-19 08:02:48,146 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18189 to 14308. [2023-11-19 08:02:48,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14308 states, 14308 states have (on average 1.4208834218618955) internal successors, (20330), 14307 states have internal predecessors, (20330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:48,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14308 states to 14308 states and 20330 transitions. [2023-11-19 08:02:48,322 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14308 states and 20330 transitions. [2023-11-19 08:02:48,322 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 08:02:48,323 INFO L428 stractBuchiCegarLoop]: Abstraction has 14308 states and 20330 transitions. [2023-11-19 08:02:48,323 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-19 08:02:48,323 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14308 states and 20330 transitions. [2023-11-19 08:02:48,375 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 14156 [2023-11-19 08:02:48,375 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:48,375 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:48,378 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:48,378 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:48,378 INFO L748 eck$LassoCheckResult]: Stem: 89671#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 89672#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 90524#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 90525#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 90181#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 89884#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 89885#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 90497#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 90553#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 90539#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 90540#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 90023#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 90007#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 90008#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 89801#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 89802#L951 assume !(0 == ~M_E~0); 89534#L951-2 assume !(0 == ~T1_E~0); 89535#L956-1 assume !(0 == ~T2_E~0); 89694#L961-1 assume !(0 == ~T3_E~0); 90203#L966-1 assume !(0 == ~T4_E~0); 90204#L971-1 assume !(0 == ~T5_E~0); 90336#L976-1 assume !(0 == ~T6_E~0); 90310#L981-1 assume !(0 == ~T7_E~0); 90062#L986-1 assume !(0 == ~T8_E~0); 89747#L991-1 assume !(0 == ~T9_E~0); 89748#L996-1 assume !(0 == ~E_M~0); 90591#L1001-1 assume !(0 == ~E_1~0); 90257#L1006-1 assume !(0 == ~E_2~0); 90258#L1011-1 assume !(0 == ~E_3~0); 90554#L1016-1 assume !(0 == ~E_4~0); 90573#L1021-1 assume !(0 == ~E_5~0); 89330#L1026-1 assume !(0 == ~E_6~0); 89331#L1031-1 assume !(0 == ~E_7~0); 90210#L1036-1 assume !(0 == ~E_8~0); 90206#L1041-1 assume !(0 == ~E_9~0); 90207#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 90507#L472 assume !(1 == ~m_pc~0); 90447#L472-2 is_master_triggered_~__retres1~0#1 := 0; 90237#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 90238#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 90246#L1179 assume !(0 != activate_threads_~tmp~1#1); 89338#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 89339#L491 assume !(1 == ~t1_pc~0); 89848#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 89849#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 89364#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 89311#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 89312#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 89332#L510 assume !(1 == ~t2_pc~0); 89300#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 89301#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 89871#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 89872#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 89590#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 89591#L529 assume !(1 == ~t3_pc~0); 90071#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 90367#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89309#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 89310#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 89509#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 89510#L548 assume !(1 == ~t4_pc~0); 89405#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 89404#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 89474#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 89444#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 89445#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 89392#L567 assume 1 == ~t5_pc~0; 89393#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 89446#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 90430#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 90431#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 90492#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 89520#L586 assume !(1 == ~t6_pc~0); 89521#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 89594#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 89854#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 89855#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 90481#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 90482#L605 assume 1 == ~t7_pc~0; 90437#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 90043#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 90239#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 90633#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 90632#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 90174#L624 assume !(1 == ~t8_pc~0); 89585#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 89584#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 90294#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 90362#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 90456#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 89355#L643 assume 1 == ~t9_pc~0; 89356#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 90393#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 89930#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 89753#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 89754#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 89566#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 89567#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 89723#L1064-1 assume !(1 == ~T2_E~0); 89724#L1069-1 assume !(1 == ~T3_E~0); 90627#L1074-1 assume !(1 == ~T4_E~0); 90628#L1079-1 assume !(1 == ~T5_E~0); 90435#L1084-1 assume !(1 == ~T6_E~0); 90436#L1089-1 assume !(1 == ~T7_E~0); 90476#L1094-1 assume !(1 == ~T8_E~0); 90477#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 90567#L1104-1 assume !(1 == ~E_M~0); 90568#L1109-1 assume !(1 == ~E_1~0); 89873#L1114-1 assume !(1 == ~E_2~0); 89874#L1119-1 assume !(1 == ~E_3~0); 89943#L1124-1 assume !(1 == ~E_4~0); 89944#L1129-1 assume !(1 == ~E_5~0); 90185#L1134-1 assume !(1 == ~E_6~0); 90186#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 89896#L1144-1 assume !(1 == ~E_8~0); 89897#L1149-1 assume !(1 == ~E_9~0); 89526#L1154-1 assume { :end_inline_reset_delta_events } true; 89527#L1440-2 [2023-11-19 08:02:48,379 INFO L750 eck$LassoCheckResult]: Loop: 89527#L1440-2 assume !false; 89658#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 90283#L926-1 assume !false; 89947#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 89948#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 89613#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 89614#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 89624#L795 assume !(0 != eval_~tmp~0#1); 89625#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 102799#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 102798#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 102797#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 102796#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 102795#L961-3 assume !(0 == ~T3_E~0); 102794#L966-3 assume !(0 == ~T4_E~0); 102793#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 102791#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 102789#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 102787#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 102785#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 102783#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 102781#L1001-3 assume !(0 == ~E_1~0); 102780#L1006-3 assume !(0 == ~E_2~0); 102779#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 102778#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 102776#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 102775#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 102774#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 102773#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 102771#L1041-3 assume !(0 == ~E_9~0); 102769#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 102767#L472-33 assume !(1 == ~m_pc~0); 102765#L472-35 is_master_triggered_~__retres1~0#1 := 0; 102763#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 102761#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 90358#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 89935#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 89936#L491-33 assume !(1 == ~t1_pc~0); 89409#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 89410#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 90580#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 90602#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 90603#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 90300#L510-33 assume !(1 == ~t2_pc~0); 90298#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 90299#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 90338#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 90339#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 89295#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 89296#L529-33 assume !(1 == ~t3_pc~0); 89618#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 89601#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89483#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 89484#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 89426#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 89427#L548-33 assume 1 == ~t4_pc~0; 89673#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 89803#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 90264#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 89842#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 89611#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 89612#L567-33 assume !(1 == ~t5_pc~0); 89715#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 89716#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 89978#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 90607#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 90612#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 90202#L586-33 assume 1 == ~t6_pc~0; 90163#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 89737#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 89997#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 89998#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 89629#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 89630#L605-33 assume !(1 == ~t7_pc~0); 89808#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 89554#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 89555#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 90444#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 89438#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 89439#L624-33 assume !(1 == ~t8_pc~0); 89597#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 89605#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 90175#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 89824#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 89825#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 89556#L643-33 assume 1 == ~t9_pc~0; 89557#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 89641#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 90146#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 90097#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 90098#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 89428#L1059-3 assume !(1 == ~M_E~0); 89429#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 89959#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 90020#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 90021#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 90311#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 102722#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 102720#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 102718#L1094-3 assume !(1 == ~T8_E~0); 102716#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 102714#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 102712#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 102710#L1114-3 assume !(1 == ~E_2~0); 102708#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 102704#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 102702#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 102701#L1134-3 assume !(1 == ~E_6~0); 102700#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 102699#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 102698#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 102697#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 102695#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 99702#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 99595#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 89317#L1459 assume !(0 == start_simulation_~tmp~3#1); 89318#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 90412#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 89616#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 89358#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 89359#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 89781#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 89963#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 90131#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 89527#L1440-2 [2023-11-19 08:02:48,380 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:48,380 INFO L85 PathProgramCache]: Analyzing trace with hash -1826536698, now seen corresponding path program 1 times [2023-11-19 08:02:48,380 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:48,380 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1533939457] [2023-11-19 08:02:48,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:48,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:48,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:48,452 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:48,452 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:48,452 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1533939457] [2023-11-19 08:02:48,452 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1533939457] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:48,452 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:48,453 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 08:02:48,453 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [604145691] [2023-11-19 08:02:48,453 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:48,453 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:48,454 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:48,454 INFO L85 PathProgramCache]: Analyzing trace with hash 1476816415, now seen corresponding path program 1 times [2023-11-19 08:02:48,454 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:48,454 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [929206596] [2023-11-19 08:02:48,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:48,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:48,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:48,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:48,504 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:48,504 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [929206596] [2023-11-19 08:02:48,504 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [929206596] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:48,504 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:48,505 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:48,505 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2024659240] [2023-11-19 08:02:48,505 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:48,505 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:48,506 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:48,506 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:02:48,506 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:02:48,506 INFO L87 Difference]: Start difference. First operand 14308 states and 20330 transitions. cyclomatic complexity: 6026 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:48,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:48,831 INFO L93 Difference]: Finished difference Result 27183 states and 38443 transitions. [2023-11-19 08:02:48,832 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27183 states and 38443 transitions. [2023-11-19 08:02:48,991 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26992 [2023-11-19 08:02:49,115 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27183 states to 27183 states and 38443 transitions. [2023-11-19 08:02:49,116 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27183 [2023-11-19 08:02:49,152 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27183 [2023-11-19 08:02:49,153 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27183 states and 38443 transitions. [2023-11-19 08:02:49,191 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:49,191 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27183 states and 38443 transitions. [2023-11-19 08:02:49,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27183 states and 38443 transitions. [2023-11-19 08:02:49,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27183 to 27151. [2023-11-19 08:02:49,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27151 states, 27151 states have (on average 1.414717689956171) internal successors, (38411), 27150 states have internal predecessors, (38411), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:49,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27151 states to 27151 states and 38411 transitions. [2023-11-19 08:02:49,913 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27151 states and 38411 transitions. [2023-11-19 08:02:49,913 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:02:49,914 INFO L428 stractBuchiCegarLoop]: Abstraction has 27151 states and 38411 transitions. [2023-11-19 08:02:49,914 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-19 08:02:49,914 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27151 states and 38411 transitions. [2023-11-19 08:02:50,043 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26960 [2023-11-19 08:02:50,043 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:50,043 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:50,046 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:50,046 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:50,046 INFO L748 eck$LassoCheckResult]: Stem: 131169#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 131170#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 131998#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 131999#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 131670#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 131374#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 131375#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 131969#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 132025#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 132010#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 132011#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 131511#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 131497#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 131498#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 131295#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 131296#L951 assume !(0 == ~M_E~0); 131032#L951-2 assume !(0 == ~T1_E~0); 131033#L956-1 assume !(0 == ~T2_E~0); 131192#L961-1 assume !(0 == ~T3_E~0); 131689#L966-1 assume !(0 == ~T4_E~0); 131690#L971-1 assume !(0 == ~T5_E~0); 131818#L976-1 assume !(0 == ~T6_E~0); 131790#L981-1 assume !(0 == ~T7_E~0); 131548#L986-1 assume !(0 == ~T8_E~0); 131244#L991-1 assume !(0 == ~T9_E~0); 131245#L996-1 assume !(0 == ~E_M~0); 132059#L1001-1 assume !(0 == ~E_1~0); 131741#L1006-1 assume !(0 == ~E_2~0); 131742#L1011-1 assume !(0 == ~E_3~0); 132026#L1016-1 assume !(0 == ~E_4~0); 132043#L1021-1 assume !(0 == ~E_5~0); 130828#L1026-1 assume !(0 == ~E_6~0); 130829#L1031-1 assume !(0 == ~E_7~0); 131696#L1036-1 assume !(0 == ~E_8~0); 131692#L1041-1 assume !(0 == ~E_9~0); 131693#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 131981#L472 assume !(1 == ~m_pc~0); 131924#L472-2 is_master_triggered_~__retres1~0#1 := 0; 131721#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 131722#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 131730#L1179 assume !(0 != activate_threads_~tmp~1#1); 130836#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 130837#L491 assume !(1 == ~t1_pc~0); 131340#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 131341#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 130862#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 130809#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 130810#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 130830#L510 assume !(1 == ~t2_pc~0); 130798#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 130799#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 131363#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 131364#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 131087#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 131088#L529 assume !(1 == ~t3_pc~0); 131557#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 131844#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 130807#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 130808#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 131007#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 131008#L548 assume !(1 == ~t4_pc~0); 130902#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 130901#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 130972#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 130941#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 130942#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 130890#L567 assume !(1 == ~t5_pc~0); 130891#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 130943#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 131909#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 131910#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 131964#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 131018#L586 assume !(1 == ~t6_pc~0); 131019#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 131091#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 131346#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 131347#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 131955#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 131956#L605 assume 1 == ~t7_pc~0; 131916#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 131531#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 131723#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 132102#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 132101#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 131663#L624 assume !(1 == ~t8_pc~0); 131082#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 131081#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 131775#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 131840#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 131930#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 130853#L643 assume 1 == ~t9_pc~0; 130854#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 131872#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 131421#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 131249#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 131250#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 131064#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 131065#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 139310#L1064-1 assume !(1 == ~T2_E~0); 139309#L1069-1 assume !(1 == ~T3_E~0); 139308#L1074-1 assume !(1 == ~T4_E~0); 132097#L1079-1 assume !(1 == ~T5_E~0); 139307#L1084-1 assume !(1 == ~T6_E~0); 139306#L1089-1 assume !(1 == ~T7_E~0); 139305#L1094-1 assume !(1 == ~T8_E~0); 139304#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 139303#L1104-1 assume !(1 == ~E_M~0); 139302#L1109-1 assume !(1 == ~E_1~0); 139301#L1114-1 assume !(1 == ~E_2~0); 139300#L1119-1 assume !(1 == ~E_3~0); 139299#L1124-1 assume !(1 == ~E_4~0); 139298#L1129-1 assume !(1 == ~E_5~0); 139297#L1134-1 assume !(1 == ~E_6~0); 139296#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 139295#L1144-1 assume !(1 == ~E_8~0); 139294#L1149-1 assume !(1 == ~E_9~0); 139292#L1154-1 assume { :end_inline_reset_delta_events } true; 139290#L1440-2 [2023-11-19 08:02:50,047 INFO L750 eck$LassoCheckResult]: Loop: 139290#L1440-2 assume !false; 139198#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 139192#L926-1 assume !false; 139189#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 139150#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 139134#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 139126#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 139115#L795 assume !(0 != eval_~tmp~0#1); 139116#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 146536#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 146534#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 146531#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 146529#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 146527#L961-3 assume !(0 == ~T3_E~0); 146525#L966-3 assume !(0 == ~T4_E~0); 146523#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 146521#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 146519#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 146517#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 146515#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 146513#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 146510#L1001-3 assume !(0 == ~E_1~0); 146506#L1006-3 assume !(0 == ~E_2~0); 146501#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 146497#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 146493#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 146489#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 146485#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 146482#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 146478#L1041-3 assume !(0 == ~E_9~0); 146474#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 146469#L472-33 assume !(1 == ~m_pc~0); 146463#L472-35 is_master_triggered_~__retres1~0#1 := 0; 146456#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 146451#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 146445#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 146440#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 146435#L491-33 assume !(1 == ~t1_pc~0); 145836#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 146428#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 146422#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 146414#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 146408#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 146400#L510-33 assume !(1 == ~t2_pc~0); 146393#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 146389#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 146385#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 146379#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 146257#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 140286#L529-33 assume !(1 == ~t3_pc~0); 140284#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 140282#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 140280#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 140278#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 140276#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 140274#L548-33 assume !(1 == ~t4_pc~0); 140272#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 140256#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 140244#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 140234#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 140223#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 140216#L567-33 assume !(1 == ~t5_pc~0); 140212#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 140210#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 140206#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 139965#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 139964#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 139963#L586-33 assume !(1 == ~t6_pc~0); 139962#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 139960#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 139958#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 139957#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 139824#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 139815#L605-33 assume !(1 == ~t7_pc~0); 139811#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 139809#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 139807#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 139805#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 139803#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 139801#L624-33 assume !(1 == ~t8_pc~0); 139798#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 139795#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 139793#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 139791#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 139789#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 139788#L643-33 assume 1 == ~t9_pc~0; 139786#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 139785#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 139784#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 139782#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 139780#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 139773#L1059-3 assume !(1 == ~M_E~0); 139771#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 139769#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 139767#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 139765#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 139761#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 139759#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 139756#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 139754#L1094-3 assume !(1 == ~T8_E~0); 139752#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 139750#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 139748#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 139746#L1114-3 assume !(1 == ~E_2~0); 139739#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 139728#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 139721#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 139716#L1134-3 assume !(1 == ~E_6~0); 139711#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 139706#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 139701#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 139697#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 139496#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 139485#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 139484#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 139477#L1459 assume !(0 == start_simulation_~tmp~3#1); 139474#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 139471#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 139457#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 139450#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 139336#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 139323#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 139317#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 139291#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 139290#L1440-2 [2023-11-19 08:02:50,048 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:50,048 INFO L85 PathProgramCache]: Analyzing trace with hash 367589383, now seen corresponding path program 1 times [2023-11-19 08:02:50,048 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:50,048 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [415902536] [2023-11-19 08:02:50,048 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:50,049 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:50,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:50,137 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:50,137 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:50,137 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [415902536] [2023-11-19 08:02:50,137 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [415902536] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:50,138 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:50,138 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:50,138 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [581096591] [2023-11-19 08:02:50,138 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:50,138 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:50,139 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:50,139 INFO L85 PathProgramCache]: Analyzing trace with hash -1440254687, now seen corresponding path program 1 times [2023-11-19 08:02:50,139 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:50,139 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1697654017] [2023-11-19 08:02:50,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:50,140 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:50,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:50,201 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:50,201 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:50,202 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1697654017] [2023-11-19 08:02:50,202 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1697654017] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:50,202 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:50,202 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:50,202 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1129108981] [2023-11-19 08:02:50,202 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:50,203 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:50,203 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:50,203 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 08:02:50,203 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 08:02:50,204 INFO L87 Difference]: Start difference. First operand 27151 states and 38411 transitions. cyclomatic complexity: 11268 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:50,846 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:50,847 INFO L93 Difference]: Finished difference Result 64882 states and 91100 transitions. [2023-11-19 08:02:50,847 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64882 states and 91100 transitions. [2023-11-19 08:02:51,397 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 63436 [2023-11-19 08:02:51,753 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64882 states to 64882 states and 91100 transitions. [2023-11-19 08:02:51,753 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 64882 [2023-11-19 08:02:51,810 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 64882 [2023-11-19 08:02:51,810 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64882 states and 91100 transitions. [2023-11-19 08:02:51,868 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:51,869 INFO L218 hiAutomatonCegarLoop]: Abstraction has 64882 states and 91100 transitions. [2023-11-19 08:02:51,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64882 states and 91100 transitions. [2023-11-19 08:02:52,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64882 to 51550. [2023-11-19 08:02:52,716 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51550 states, 51550 states have (on average 1.4092725509214354) internal successors, (72648), 51549 states have internal predecessors, (72648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:52,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51550 states to 51550 states and 72648 transitions. [2023-11-19 08:02:52,860 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51550 states and 72648 transitions. [2023-11-19 08:02:52,860 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 08:02:52,861 INFO L428 stractBuchiCegarLoop]: Abstraction has 51550 states and 72648 transitions. [2023-11-19 08:02:52,862 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-19 08:02:52,862 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51550 states and 72648 transitions. [2023-11-19 08:02:53,297 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 51312 [2023-11-19 08:02:53,298 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:53,298 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:53,302 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:53,303 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:53,303 INFO L748 eck$LassoCheckResult]: Stem: 223212#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 223213#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 224092#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 224093#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 223726#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 223422#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 223423#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 224061#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 224125#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 224110#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 224111#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 223561#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 223546#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 223547#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 223341#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 223342#L951 assume !(0 == ~M_E~0); 223073#L951-2 assume !(0 == ~T1_E~0); 223074#L956-1 assume !(0 == ~T2_E~0); 223237#L961-1 assume !(0 == ~T3_E~0); 223750#L966-1 assume !(0 == ~T4_E~0); 223751#L971-1 assume !(0 == ~T5_E~0); 223891#L976-1 assume !(0 == ~T6_E~0); 223864#L981-1 assume !(0 == ~T7_E~0); 223599#L986-1 assume !(0 == ~T8_E~0); 223291#L991-1 assume !(0 == ~T9_E~0); 223292#L996-1 assume !(0 == ~E_M~0); 224167#L1001-1 assume !(0 == ~E_1~0); 223808#L1006-1 assume !(0 == ~E_2~0); 223809#L1011-1 assume !(0 == ~E_3~0); 224126#L1016-1 assume !(0 == ~E_4~0); 224147#L1021-1 assume !(0 == ~E_5~0); 222871#L1026-1 assume !(0 == ~E_6~0); 222872#L1031-1 assume !(0 == ~E_7~0); 223757#L1036-1 assume !(0 == ~E_8~0); 223753#L1041-1 assume !(0 == ~E_9~0); 223754#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 224074#L472 assume !(1 == ~m_pc~0); 224015#L472-2 is_master_triggered_~__retres1~0#1 := 0; 223786#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 223787#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 223797#L1179 assume !(0 != activate_threads_~tmp~1#1); 222879#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 222880#L491 assume !(1 == ~t1_pc~0); 223385#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 223386#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 222905#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 222852#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 222853#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 222873#L510 assume !(1 == ~t2_pc~0); 222841#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 222842#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 223409#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 223410#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 223128#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 223129#L529 assume !(1 == ~t3_pc~0); 223608#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 223924#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 222850#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 222851#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 223048#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 223049#L548 assume !(1 == ~t4_pc~0); 222945#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 222944#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 223013#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 222985#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 222986#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 222933#L567 assume !(1 == ~t5_pc~0); 222934#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 222984#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 223997#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 223998#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 224055#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 223059#L586 assume !(1 == ~t6_pc~0); 223060#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 223132#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 223391#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 223392#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 224046#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 224047#L605 assume !(1 == ~t7_pc~0); 223579#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 223580#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 223788#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 224212#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 224211#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 223717#L624 assume !(1 == ~t8_pc~0); 223123#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 223122#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 223848#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 223919#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 224020#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 222896#L643 assume 1 == ~t9_pc~0; 222897#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 223953#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 223469#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 223296#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 223297#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 223105#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 223106#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 223267#L1064-1 assume !(1 == ~T2_E~0); 223268#L1069-1 assume !(1 == ~T3_E~0); 224206#L1074-1 assume !(1 == ~T4_E~0); 224207#L1079-1 assume !(1 == ~T5_E~0); 224002#L1084-1 assume !(1 == ~T6_E~0); 224003#L1089-1 assume !(1 == ~T7_E~0); 224040#L1094-1 assume !(1 == ~T8_E~0); 224041#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 224141#L1104-1 assume !(1 == ~E_M~0); 224142#L1109-1 assume !(1 == ~E_1~0); 223411#L1114-1 assume !(1 == ~E_2~0); 223412#L1119-1 assume !(1 == ~E_3~0); 223481#L1124-1 assume !(1 == ~E_4~0); 223482#L1129-1 assume !(1 == ~E_5~0); 223731#L1134-1 assume !(1 == ~E_6~0); 223732#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 223433#L1144-1 assume !(1 == ~E_8~0); 223434#L1149-1 assume !(1 == ~E_9~0); 223065#L1154-1 assume { :end_inline_reset_delta_events } true; 223066#L1440-2 [2023-11-19 08:02:53,304 INFO L750 eck$LassoCheckResult]: Loop: 223066#L1440-2 assume !false; 268616#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 268566#L926-1 assume !false; 268562#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 268516#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 268506#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 268504#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 268450#L795 assume !(0 != eval_~tmp~0#1); 268451#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 273905#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 273904#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 273903#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 273901#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 273899#L961-3 assume !(0 == ~T3_E~0); 273897#L966-3 assume !(0 == ~T4_E~0); 273895#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 273893#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 273891#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 273889#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 273888#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 273886#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 273884#L1001-3 assume !(0 == ~E_1~0); 273860#L1006-3 assume !(0 == ~E_2~0); 273858#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 273856#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 273854#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 273852#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 273850#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 273847#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 273845#L1041-3 assume !(0 == ~E_9~0); 273843#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 273841#L472-33 assume !(1 == ~m_pc~0); 273839#L472-35 is_master_triggered_~__retres1~0#1 := 0; 273820#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 273814#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 273749#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 273748#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 269384#L491-33 assume !(1 == ~t1_pc~0); 269379#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 269374#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 269369#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 269364#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 269357#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 269352#L510-33 assume !(1 == ~t2_pc~0); 269346#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 269341#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 269336#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 269331#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 269324#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 269319#L529-33 assume !(1 == ~t3_pc~0); 268873#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 269310#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 269305#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 269298#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 269223#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 269220#L548-33 assume !(1 == ~t4_pc~0); 269216#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 269211#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 269206#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 269203#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 269200#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 269195#L567-33 assume !(1 == ~t5_pc~0); 269191#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 269187#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 269183#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 269180#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 269176#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 269172#L586-33 assume 1 == ~t6_pc~0; 269168#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 269164#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 269159#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 269155#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 269150#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 269143#L605-33 assume !(1 == ~t7_pc~0); 243377#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 269134#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 269128#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 269123#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 269116#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 269111#L624-33 assume 1 == ~t8_pc~0; 269105#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 269099#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 269093#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 269086#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 269080#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 269074#L643-33 assume 1 == ~t9_pc~0; 269066#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 269060#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 269054#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 269048#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 269042#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 269034#L1059-3 assume !(1 == ~M_E~0); 265382#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 269023#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 269018#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 269012#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 265373#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 269002#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 268995#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 268989#L1094-3 assume !(1 == ~T8_E~0); 268983#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 268978#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 268972#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 268966#L1114-3 assume !(1 == ~E_2~0); 268960#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 268955#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 268949#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 268942#L1134-3 assume !(1 == ~E_6~0); 268936#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 268929#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 268924#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 268921#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 268840#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 268825#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 268819#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 268811#L1459 assume !(0 == start_simulation_~tmp~3#1); 268806#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 268706#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 268696#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 268694#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 268692#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 268690#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 268653#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 268638#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 223066#L1440-2 [2023-11-19 08:02:53,305 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:53,305 INFO L85 PathProgramCache]: Analyzing trace with hash -589339000, now seen corresponding path program 1 times [2023-11-19 08:02:53,305 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:53,306 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1907584097] [2023-11-19 08:02:53,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:53,306 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:53,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:53,409 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:53,409 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:53,410 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1907584097] [2023-11-19 08:02:53,410 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1907584097] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:53,410 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:53,410 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:53,411 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1914204552] [2023-11-19 08:02:53,411 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:53,411 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:53,412 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:53,412 INFO L85 PathProgramCache]: Analyzing trace with hash -807044321, now seen corresponding path program 1 times [2023-11-19 08:02:53,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:53,413 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [230311377] [2023-11-19 08:02:53,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:53,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:53,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:53,480 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:53,481 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:53,481 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [230311377] [2023-11-19 08:02:53,481 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [230311377] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:53,481 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:53,482 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:53,482 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [312343584] [2023-11-19 08:02:53,482 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:53,483 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:53,483 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:53,483 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 08:02:53,484 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 08:02:53,484 INFO L87 Difference]: Start difference. First operand 51550 states and 72648 transitions. cyclomatic complexity: 21106 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:54,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:54,600 INFO L93 Difference]: Finished difference Result 122301 states and 171109 transitions. [2023-11-19 08:02:54,600 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122301 states and 171109 transitions. [2023-11-19 08:02:55,445 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 119568 [2023-11-19 08:02:56,030 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122301 states to 122301 states and 171109 transitions. [2023-11-19 08:02:56,030 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 122301 [2023-11-19 08:02:56,089 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 122301 [2023-11-19 08:02:56,089 INFO L73 IsDeterministic]: Start isDeterministic. Operand 122301 states and 171109 transitions. [2023-11-19 08:02:56,181 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:56,181 INFO L218 hiAutomatonCegarLoop]: Abstraction has 122301 states and 171109 transitions. [2023-11-19 08:02:56,288 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122301 states and 171109 transitions. [2023-11-19 08:02:57,427 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122301 to 97805. [2023-11-19 08:02:57,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97805 states, 97805 states have (on average 1.404478298655488) internal successors, (137365), 97804 states have internal predecessors, (137365), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:57,785 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97805 states to 97805 states and 137365 transitions. [2023-11-19 08:02:57,785 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97805 states and 137365 transitions. [2023-11-19 08:02:57,785 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 08:02:57,786 INFO L428 stractBuchiCegarLoop]: Abstraction has 97805 states and 137365 transitions. [2023-11-19 08:02:57,786 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-19 08:02:57,786 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97805 states and 137365 transitions. [2023-11-19 08:02:58,464 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 97472 [2023-11-19 08:02:58,465 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:58,465 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:58,470 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:58,470 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:58,471 INFO L748 eck$LassoCheckResult]: Stem: 397069#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 397070#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 397956#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 397957#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 397593#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 397278#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 397279#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 397923#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 397987#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 397972#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 397973#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 397422#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 397404#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 397405#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 397197#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 397198#L951 assume !(0 == ~M_E~0); 396932#L951-2 assume !(0 == ~T1_E~0); 396933#L956-1 assume !(0 == ~T2_E~0); 397094#L961-1 assume !(0 == ~T3_E~0); 397615#L966-1 assume !(0 == ~T4_E~0); 397616#L971-1 assume !(0 == ~T5_E~0); 397758#L976-1 assume !(0 == ~T6_E~0); 397732#L981-1 assume !(0 == ~T7_E~0); 397461#L986-1 assume !(0 == ~T8_E~0); 397146#L991-1 assume !(0 == ~T9_E~0); 397147#L996-1 assume !(0 == ~E_M~0); 398024#L1001-1 assume !(0 == ~E_1~0); 397674#L1006-1 assume !(0 == ~E_2~0); 397675#L1011-1 assume !(0 == ~E_3~0); 397988#L1016-1 assume !(0 == ~E_4~0); 398006#L1021-1 assume !(0 == ~E_5~0); 396732#L1026-1 assume !(0 == ~E_6~0); 396733#L1031-1 assume !(0 == ~E_7~0); 397625#L1036-1 assume !(0 == ~E_8~0); 397621#L1041-1 assume !(0 == ~E_9~0); 397622#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 397938#L472 assume !(1 == ~m_pc~0); 397876#L472-2 is_master_triggered_~__retres1~0#1 := 0; 397653#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 397654#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 397663#L1179 assume !(0 != activate_threads_~tmp~1#1); 396740#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 396741#L491 assume !(1 == ~t1_pc~0); 397242#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 397243#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 396764#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 396713#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 396714#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 396734#L510 assume !(1 == ~t2_pc~0); 396702#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 396703#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 397265#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 397266#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 396986#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 396987#L529 assume !(1 == ~t3_pc~0); 397470#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 397789#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 396711#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 396712#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 396907#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 396908#L548 assume !(1 == ~t4_pc~0); 396803#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 396802#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 396872#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 396841#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 396842#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 396791#L567 assume !(1 == ~t5_pc~0); 396792#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 396843#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 397859#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 397860#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 397918#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 396918#L586 assume !(1 == ~t6_pc~0); 396919#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 396990#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 397248#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 397249#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 397911#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 397912#L605 assume !(1 == ~t7_pc~0); 397440#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 397441#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 397655#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 398077#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 398073#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 397585#L624 assume !(1 == ~t8_pc~0); 396981#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 396980#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 397714#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 397785#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 397881#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 396756#L643 assume !(1 == ~t9_pc~0); 396757#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 397818#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 397326#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 397151#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 397152#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 396963#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 396964#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 397124#L1064-1 assume !(1 == ~T2_E~0); 397125#L1069-1 assume !(1 == ~T3_E~0); 398069#L1074-1 assume !(1 == ~T4_E~0); 398070#L1079-1 assume !(1 == ~T5_E~0); 397864#L1084-1 assume !(1 == ~T6_E~0); 397865#L1089-1 assume !(1 == ~T7_E~0); 397905#L1094-1 assume !(1 == ~T8_E~0); 397906#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 397999#L1104-1 assume !(1 == ~E_M~0); 398000#L1109-1 assume !(1 == ~E_1~0); 397267#L1114-1 assume !(1 == ~E_2~0); 397268#L1119-1 assume !(1 == ~E_3~0); 397339#L1124-1 assume !(1 == ~E_4~0); 397340#L1129-1 assume !(1 == ~E_5~0); 397598#L1134-1 assume !(1 == ~E_6~0); 397599#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 397289#L1144-1 assume !(1 == ~E_8~0); 397290#L1149-1 assume !(1 == ~E_9~0); 396924#L1154-1 assume { :end_inline_reset_delta_events } true; 396925#L1440-2 [2023-11-19 08:02:58,471 INFO L750 eck$LassoCheckResult]: Loop: 396925#L1440-2 assume !false; 397057#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 397703#L926-1 assume !false; 397343#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 397344#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 490621#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 490617#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 490609#L795 assume !(0 != eval_~tmp~0#1); 397790#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 397512#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 397181#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 397182#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 397775#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 397587#L961-3 assume !(0 == ~T3_E~0); 397318#L966-3 assume !(0 == ~T4_E~0); 397319#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 397645#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 396776#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 396777#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 396754#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 396755#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 397754#L1001-3 assume !(0 == ~E_1~0); 397287#L1006-3 assume !(0 == ~E_2~0); 397288#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 397784#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 397840#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 397518#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 397519#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 397750#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 397751#L1041-3 assume !(0 == ~E_9~0); 494130#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 397770#L472-33 assume !(1 == ~m_pc~0); 396864#L472-35 is_master_triggered_~__retres1~0#1 := 0; 396865#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 397807#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 397780#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 397781#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 493474#L491-33 assume !(1 == ~t1_pc~0); 488563#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 493473#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 493472#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 493471#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 493470#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 493469#L510-33 assume !(1 == ~t2_pc~0); 493467#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 493466#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 493465#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 493464#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 493463#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 397013#L529-33 assume !(1 == ~t3_pc~0); 397014#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 491999#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 491997#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 491996#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 491993#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 491991#L548-33 assume !(1 == ~t4_pc~0); 491989#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 491986#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 491984#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 491982#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 491979#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 491977#L567-33 assume !(1 == ~t5_pc~0); 491975#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 491973#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 491971#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 491969#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 491967#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 491965#L586-33 assume !(1 == ~t6_pc~0); 491963#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 491960#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 491953#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 491870#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 491868#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 397203#L605-33 assume !(1 == ~t7_pc~0); 397204#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 396952#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 396953#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 397873#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 396835#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 396836#L624-33 assume 1 == ~t8_pc~0; 396994#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 397000#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 397586#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 397218#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 397219#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 396954#L643-33 assume !(1 == ~t9_pc~0); 396955#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 397039#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 397553#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 397497#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 397498#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 396825#L1059-3 assume !(1 == ~M_E~0); 396826#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 397355#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 397417#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 397418#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 397733#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 397626#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 397551#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 397552#L1094-3 assume !(1 == ~T8_E~0); 397451#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 397452#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 397756#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 397743#L1114-3 assume !(1 == ~E_2~0); 397744#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 398053#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 398068#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 397131#L1134-3 assume !(1 == ~E_6~0); 397132#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 397311#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 397312#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 397503#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 398080#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 396830#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 397216#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 396719#L1459 assume !(0 == start_simulation_~tmp~3#1); 396720#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 397841#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 397011#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 396758#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 396759#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 397176#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 397359#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 397536#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 396925#L1440-2 [2023-11-19 08:02:58,472 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:58,472 INFO L85 PathProgramCache]: Analyzing trace with hash 2033110665, now seen corresponding path program 1 times [2023-11-19 08:02:58,472 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:58,473 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [699794618] [2023-11-19 08:02:58,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:58,473 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:58,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:58,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:58,546 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:58,546 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [699794618] [2023-11-19 08:02:58,546 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [699794618] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:58,546 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:58,546 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 08:02:58,547 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1892733617] [2023-11-19 08:02:58,547 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:58,547 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:58,547 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:58,548 INFO L85 PathProgramCache]: Analyzing trace with hash -1523705375, now seen corresponding path program 1 times [2023-11-19 08:02:58,548 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:58,548 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2012310292] [2023-11-19 08:02:58,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:58,548 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:58,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:58,598 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:58,599 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:58,599 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2012310292] [2023-11-19 08:02:58,599 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2012310292] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:58,599 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:58,599 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:58,599 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [873050319] [2023-11-19 08:02:58,600 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:58,600 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:58,600 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:58,601 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:02:58,601 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:02:58,601 INFO L87 Difference]: Start difference. First operand 97805 states and 137365 transitions. cyclomatic complexity: 39568 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:59,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:59,179 INFO L93 Difference]: Finished difference Result 145065 states and 204044 transitions. [2023-11-19 08:02:59,179 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 145065 states and 204044 transitions. [2023-11-19 08:03:00,367 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 144640 [2023-11-19 08:03:00,921 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 145065 states to 145065 states and 204044 transitions. [2023-11-19 08:03:00,921 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 145065 [2023-11-19 08:03:01,009 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 145065 [2023-11-19 08:03:01,010 INFO L73 IsDeterministic]: Start isDeterministic. Operand 145065 states and 204044 transitions. [2023-11-19 08:03:01,158 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:03:01,159 INFO L218 hiAutomatonCegarLoop]: Abstraction has 145065 states and 204044 transitions. [2023-11-19 08:03:01,251 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145065 states and 204044 transitions. [2023-11-19 08:03:02,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145065 to 99065. [2023-11-19 08:03:02,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99065 states, 99065 states have (on average 1.4101246656235804) internal successors, (139694), 99064 states have internal predecessors, (139694), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:03:03,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99065 states to 99065 states and 139694 transitions. [2023-11-19 08:03:03,458 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99065 states and 139694 transitions. [2023-11-19 08:03:03,459 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:03:03,460 INFO L428 stractBuchiCegarLoop]: Abstraction has 99065 states and 139694 transitions. [2023-11-19 08:03:03,460 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-19 08:03:03,460 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99065 states and 139694 transitions. [2023-11-19 08:03:03,776 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 98752 [2023-11-19 08:03:03,776 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:03:03,776 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:03:03,786 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:03:03,786 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:03:03,787 INFO L748 eck$LassoCheckResult]: Stem: 639955#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 639956#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 640827#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 640828#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 640458#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 640160#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 640161#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 640794#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 640861#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 640849#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 640850#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 640299#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 640284#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 640285#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 640077#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 640078#L951 assume !(0 == ~M_E~0); 639814#L951-2 assume !(0 == ~T1_E~0); 639815#L956-1 assume !(0 == ~T2_E~0); 639973#L961-1 assume !(0 == ~T3_E~0); 640479#L966-1 assume !(0 == ~T4_E~0); 640480#L971-1 assume !(0 == ~T5_E~0); 640627#L976-1 assume !(0 == ~T6_E~0); 640601#L981-1 assume !(0 == ~T7_E~0); 640340#L986-1 assume !(0 == ~T8_E~0); 640026#L991-1 assume !(0 == ~T9_E~0); 640027#L996-1 assume !(0 == ~E_M~0); 640910#L1001-1 assume !(0 == ~E_1~0); 640542#L1006-1 assume !(0 == ~E_2~0); 640543#L1011-1 assume !(0 == ~E_3~0); 640863#L1016-1 assume !(0 == ~E_4~0); 640885#L1021-1 assume !(0 == ~E_5~0); 639609#L1026-1 assume !(0 == ~E_6~0); 639610#L1031-1 assume !(0 == ~E_7~0); 640488#L1036-1 assume !(0 == ~E_8~0); 640486#L1041-1 assume !(0 == ~E_9~0); 640487#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 640806#L472 assume !(1 == ~m_pc~0); 640749#L472-2 is_master_triggered_~__retres1~0#1 := 0; 640520#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 640521#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 640531#L1179 assume !(0 != activate_threads_~tmp~1#1); 639617#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 639618#L491 assume !(1 == ~t1_pc~0); 640126#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 640127#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 639642#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 639590#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 639591#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 639613#L510 assume !(1 == ~t2_pc~0); 639579#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 639580#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 640147#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 640148#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 639865#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 639866#L529 assume !(1 == ~t3_pc~0); 640348#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 640654#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 639588#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 639589#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 639787#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 639788#L548 assume !(1 == ~t4_pc~0); 639682#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 639681#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 639751#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 639721#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 639722#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 639674#L567 assume !(1 == ~t5_pc~0); 639675#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 639723#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 640728#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 640729#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 640788#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 639798#L586 assume !(1 == ~t6_pc~0); 639799#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 639871#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 640133#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 640134#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 640780#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 640781#L605 assume !(1 == ~t7_pc~0); 640324#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 640325#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 640523#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 640960#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 640955#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 640452#L624 assume !(1 == ~t8_pc~0); 639860#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 639859#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 640584#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 640651#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 640756#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 639634#L643 assume !(1 == ~t9_pc~0); 639635#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 640687#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 640205#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 640033#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 640034#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 639845#L1059 assume !(1 == ~M_E~0); 639846#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 640004#L1064-1 assume !(1 == ~T2_E~0); 640005#L1069-1 assume !(1 == ~T3_E~0); 640696#L1074-1 assume !(1 == ~T4_E~0); 640754#L1079-1 assume !(1 == ~T5_E~0); 640733#L1084-1 assume !(1 == ~T6_E~0); 640734#L1089-1 assume !(1 == ~T7_E~0); 640773#L1094-1 assume !(1 == ~T8_E~0); 640378#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 640379#L1104-1 assume !(1 == ~E_M~0); 640589#L1109-1 assume !(1 == ~E_1~0); 640150#L1114-1 assume !(1 == ~E_2~0); 640151#L1119-1 assume !(1 == ~E_3~0); 640217#L1124-1 assume !(1 == ~E_4~0); 639632#L1129-1 assume !(1 == ~E_5~0); 639633#L1134-1 assume !(1 == ~E_6~0); 639971#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 639972#L1144-1 assume !(1 == ~E_8~0); 640171#L1149-1 assume !(1 == ~E_9~0); 639804#L1154-1 assume { :end_inline_reset_delta_events } true; 639805#L1440-2 [2023-11-19 08:03:03,788 INFO L750 eck$LassoCheckResult]: Loop: 639805#L1440-2 assume !false; 710567#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 710555#L926-1 assume !false; 710548#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 710520#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 710507#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 710500#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 710493#L795 assume !(0 != eval_~tmp~0#1); 710494#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 738559#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 738558#L951-3 assume !(0 == ~M_E~0); 738557#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 738555#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 738552#L961-3 assume !(0 == ~T3_E~0); 738550#L966-3 assume !(0 == ~T4_E~0); 738548#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 738546#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 639660#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 639661#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 738321#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 738172#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 737491#L1001-3 assume !(0 == ~E_1~0); 737490#L1006-3 assume !(0 == ~E_2~0); 737489#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 737487#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 737485#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 737483#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 737481#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 737479#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 737477#L1041-3 assume !(0 == ~E_9~0); 737475#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 737474#L472-33 assume !(1 == ~m_pc~0); 737472#L472-35 is_master_triggered_~__retres1~0#1 := 0; 737470#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 737469#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 737465#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 737464#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 737461#L491-33 assume !(1 == ~t1_pc~0); 733913#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 737458#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 737456#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 737453#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 737449#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 737446#L510-33 assume !(1 == ~t2_pc~0); 737443#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 737441#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 737438#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 737435#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 737432#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 737430#L529-33 assume !(1 == ~t3_pc~0); 639990#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 639876#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 639877#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 734418#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 734419#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 734412#L548-33 assume !(1 == ~t4_pc~0); 734410#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 734409#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 734402#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 734400#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 734398#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 734396#L567-33 assume !(1 == ~t5_pc~0); 734393#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 734394#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 734386#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 734387#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 734380#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 734381#L586-33 assume !(1 == ~t6_pc~0); 734374#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 734373#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 734365#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 734366#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 734359#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 734360#L605-33 assume !(1 == ~t7_pc~0); 640500#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 639828#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 639829#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 640740#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 734297#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 734294#L624-33 assume !(1 == ~t8_pc~0); 639884#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 639885#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 640453#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 640100#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 640101#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 640983#L643-33 assume !(1 == ~t9_pc~0); 713996#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 713994#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 713992#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 713990#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 713988#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 713986#L1059-3 assume !(1 == ~M_E~0); 680842#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 713983#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 713981#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 713979#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 713977#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 713974#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 713972#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 713970#L1094-3 assume !(1 == ~T8_E~0); 713968#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 713966#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 713964#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 713963#L1114-3 assume !(1 == ~E_2~0); 713961#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 713959#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 713957#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 713955#L1134-3 assume !(1 == ~E_6~0); 713953#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 713950#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 713948#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 713946#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 713938#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 713050#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 713049#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 639596#L1459 assume !(0 == start_simulation_~tmp~3#1); 639597#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 710681#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 710665#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 710657#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 710614#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 710610#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 710597#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 710587#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 639805#L1440-2 [2023-11-19 08:03:03,789 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:03:03,789 INFO L85 PathProgramCache]: Analyzing trace with hash -1839154805, now seen corresponding path program 1 times [2023-11-19 08:03:03,789 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:03:03,790 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1810886493] [2023-11-19 08:03:03,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:03:03,790 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:03:03,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:03:03,872 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:03:03,872 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:03:03,872 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1810886493] [2023-11-19 08:03:03,873 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1810886493] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:03:03,873 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:03:03,873 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 08:03:03,873 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [947663230] [2023-11-19 08:03:03,874 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:03:03,874 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:03:03,874 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:03:03,875 INFO L85 PathProgramCache]: Analyzing trace with hash -395296800, now seen corresponding path program 1 times [2023-11-19 08:03:03,875 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:03:03,875 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [786912065] [2023-11-19 08:03:03,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:03:03,876 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:03:03,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:03:03,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:03:03,937 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:03:03,937 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [786912065] [2023-11-19 08:03:03,937 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [786912065] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:03:03,938 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:03:03,938 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:03:03,938 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1369578378] [2023-11-19 08:03:03,938 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:03:03,939 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:03:03,939 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:03:03,939 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:03:03,939 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:03:03,940 INFO L87 Difference]: Start difference. First operand 99065 states and 139694 transitions. cyclomatic complexity: 40633 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:03:04,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:03:04,344 INFO L93 Difference]: Finished difference Result 99065 states and 139308 transitions. [2023-11-19 08:03:04,344 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99065 states and 139308 transitions. [2023-11-19 08:03:04,848 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 98752 [2023-11-19 08:03:05,772 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99065 states to 99065 states and 139308 transitions. [2023-11-19 08:03:05,772 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99065 [2023-11-19 08:03:05,812 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99065 [2023-11-19 08:03:05,812 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99065 states and 139308 transitions. [2023-11-19 08:03:05,851 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:03:05,851 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99065 states and 139308 transitions. [2023-11-19 08:03:05,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99065 states and 139308 transitions. [2023-11-19 08:03:06,481 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99065 to 99065. [2023-11-19 08:03:06,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99065 states, 99065 states have (on average 1.4062282339877858) internal successors, (139308), 99064 states have internal predecessors, (139308), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:03:07,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99065 states to 99065 states and 139308 transitions. [2023-11-19 08:03:07,486 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99065 states and 139308 transitions. [2023-11-19 08:03:07,487 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:03:07,487 INFO L428 stractBuchiCegarLoop]: Abstraction has 99065 states and 139308 transitions. [2023-11-19 08:03:07,487 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-19 08:03:07,488 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99065 states and 139308 transitions. [2023-11-19 08:03:07,728 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 98752 [2023-11-19 08:03:07,728 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:03:07,729 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:03:07,735 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:03:07,736 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:03:07,736 INFO L748 eck$LassoCheckResult]: Stem: 838086#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 838087#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 838969#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 838970#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 838601#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 838293#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 838294#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 838935#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 838998#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 838987#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 838988#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 838430#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 838415#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 838416#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 838210#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 838211#L951 assume !(0 == ~M_E~0); 837949#L951-2 assume !(0 == ~T1_E~0); 837950#L956-1 assume !(0 == ~T2_E~0); 838106#L961-1 assume !(0 == ~T3_E~0); 838621#L966-1 assume !(0 == ~T4_E~0); 838622#L971-1 assume !(0 == ~T5_E~0); 838760#L976-1 assume !(0 == ~T6_E~0); 838734#L981-1 assume !(0 == ~T7_E~0); 838472#L986-1 assume !(0 == ~T8_E~0); 838158#L991-1 assume !(0 == ~T9_E~0); 838159#L996-1 assume !(0 == ~E_M~0); 839046#L1001-1 assume !(0 == ~E_1~0); 838676#L1006-1 assume !(0 == ~E_2~0); 838677#L1011-1 assume !(0 == ~E_3~0); 839000#L1016-1 assume !(0 == ~E_4~0); 839018#L1021-1 assume !(0 == ~E_5~0); 837746#L1026-1 assume !(0 == ~E_6~0); 837747#L1031-1 assume !(0 == ~E_7~0); 838629#L1036-1 assume !(0 == ~E_8~0); 838627#L1041-1 assume !(0 == ~E_9~0); 838628#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 838949#L472 assume !(1 == ~m_pc~0); 838882#L472-2 is_master_triggered_~__retres1~0#1 := 0; 838657#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 838658#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 838667#L1179 assume !(0 != activate_threads_~tmp~1#1); 837754#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 837755#L491 assume !(1 == ~t1_pc~0); 838259#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 838260#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 837779#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 837727#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 837728#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 837750#L510 assume !(1 == ~t2_pc~0); 837716#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 837717#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 838280#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 838281#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 838000#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 838001#L529 assume !(1 == ~t3_pc~0); 838479#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 838792#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 837725#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 837726#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 837922#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 837923#L548 assume !(1 == ~t4_pc~0); 837820#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 837819#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 837886#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 837860#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 837861#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 837812#L567 assume !(1 == ~t5_pc~0); 837813#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 837859#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 838863#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 838864#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 838927#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 837933#L586 assume !(1 == ~t6_pc~0); 837934#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 838006#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 838266#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 838267#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 838918#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 838919#L605 assume !(1 == ~t7_pc~0); 838455#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 838456#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 838660#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 839098#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 839093#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 838592#L624 assume !(1 == ~t8_pc~0); 837995#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 837994#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 838718#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 838789#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 838889#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 837771#L643 assume !(1 == ~t9_pc~0); 837772#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 838821#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 838337#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 838165#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 838166#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 837980#L1059 assume !(1 == ~M_E~0); 837981#L1059-2 assume !(1 == ~T1_E~0); 838135#L1064-1 assume !(1 == ~T2_E~0); 838136#L1069-1 assume !(1 == ~T3_E~0); 838831#L1074-1 assume !(1 == ~T4_E~0); 838888#L1079-1 assume !(1 == ~T5_E~0); 838868#L1084-1 assume !(1 == ~T6_E~0); 838869#L1089-1 assume !(1 == ~T7_E~0); 838910#L1094-1 assume !(1 == ~T8_E~0); 838509#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 838510#L1104-1 assume !(1 == ~E_M~0); 838723#L1109-1 assume !(1 == ~E_1~0); 838285#L1114-1 assume !(1 == ~E_2~0); 838286#L1119-1 assume !(1 == ~E_3~0); 838349#L1124-1 assume !(1 == ~E_4~0); 837769#L1129-1 assume !(1 == ~E_5~0); 837770#L1134-1 assume !(1 == ~E_6~0); 838104#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 838105#L1144-1 assume !(1 == ~E_8~0); 838303#L1149-1 assume !(1 == ~E_9~0); 837939#L1154-1 assume { :end_inline_reset_delta_events } true; 837940#L1440-2 [2023-11-19 08:03:07,737 INFO L750 eck$LassoCheckResult]: Loop: 837940#L1440-2 assume !false; 899334#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 899330#L926-1 assume !false; 899329#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 899327#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 899318#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 899316#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 899313#L795 assume !(0 != eval_~tmp~0#1); 899314#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 920866#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 920864#L951-3 assume !(0 == ~M_E~0); 920862#L951-5 assume !(0 == ~T1_E~0); 920860#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 920857#L961-3 assume !(0 == ~T3_E~0); 920855#L966-3 assume !(0 == ~T4_E~0); 920853#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 920851#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 920849#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 920847#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 920846#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 920843#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 920841#L1001-3 assume !(0 == ~E_1~0); 920839#L1006-3 assume !(0 == ~E_2~0); 920837#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 920835#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 920833#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 920832#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 920831#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 920829#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 920827#L1041-3 assume !(0 == ~E_9~0); 920825#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 920822#L472-33 assume !(1 == ~m_pc~0); 920820#L472-35 is_master_triggered_~__retres1~0#1 := 0; 920818#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 920816#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 920814#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 920813#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 903299#L491-33 assume !(1 == ~t1_pc~0); 903297#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 903295#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 903293#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 903291#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 903289#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 903287#L510-33 assume !(1 == ~t2_pc~0); 903284#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 903282#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 903280#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 903278#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 903276#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 903274#L529-33 assume !(1 == ~t3_pc~0); 903272#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 903270#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 903268#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 903266#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 903264#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 903262#L548-33 assume !(1 == ~t4_pc~0); 903260#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 903258#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 903256#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 903254#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 903252#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 903250#L567-33 assume !(1 == ~t5_pc~0); 903247#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 903245#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 903243#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 903241#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 903239#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 903237#L586-33 assume !(1 == ~t6_pc~0); 903235#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 903232#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 903230#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 903228#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 903226#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 900624#L605-33 assume !(1 == ~t7_pc~0); 900622#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 900620#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 900618#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 900616#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 900614#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 900612#L624-33 assume !(1 == ~t8_pc~0); 900609#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 900606#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 900604#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 900602#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 900600#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 899420#L643-33 assume !(1 == ~t9_pc~0); 899418#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 899416#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 899415#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 899414#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 899413#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 899412#L1059-3 assume !(1 == ~M_E~0); 891332#L1059-5 assume !(1 == ~T1_E~0); 899411#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 899410#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 899409#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 899408#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 899407#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 899406#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 899405#L1094-3 assume !(1 == ~T8_E~0); 899403#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 899401#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 899399#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 899397#L1114-3 assume !(1 == ~E_2~0); 899395#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 899393#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 899391#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 899389#L1134-3 assume !(1 == ~E_6~0); 899387#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 899385#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 899383#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 899381#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 899375#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 899365#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 899363#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 899362#L1459 assume !(0 == start_simulation_~tmp~3#1); 899360#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 899358#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 899349#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 899345#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 899343#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 899341#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 899340#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 899337#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 837940#L1440-2 [2023-11-19 08:03:07,737 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:03:07,738 INFO L85 PathProgramCache]: Analyzing trace with hash 1638164041, now seen corresponding path program 1 times [2023-11-19 08:03:07,738 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:03:07,738 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1618865842] [2023-11-19 08:03:07,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:03:07,738 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:03:07,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:03:07,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:03:07,817 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:03:07,818 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1618865842] [2023-11-19 08:03:07,818 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1618865842] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:03:07,818 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:03:07,818 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:03:07,818 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1358730902] [2023-11-19 08:03:07,818 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:03:07,819 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:03:07,819 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:03:07,820 INFO L85 PathProgramCache]: Analyzing trace with hash 1606607776, now seen corresponding path program 1 times [2023-11-19 08:03:07,820 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:03:07,820 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [212361852] [2023-11-19 08:03:07,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:03:07,820 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:03:07,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:03:07,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:03:07,868 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:03:07,868 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [212361852] [2023-11-19 08:03:07,868 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [212361852] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:03:07,868 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:03:07,868 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:03:07,869 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1870550284] [2023-11-19 08:03:07,869 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:03:07,869 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:03:07,869 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:03:07,870 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 08:03:07,870 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 08:03:07,870 INFO L87 Difference]: Start difference. First operand 99065 states and 139308 transitions. cyclomatic complexity: 40247 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:03:08,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:03:08,405 INFO L93 Difference]: Finished difference Result 156409 states and 219637 transitions. [2023-11-19 08:03:08,406 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 156409 states and 219637 transitions. [2023-11-19 08:03:09,659 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 155904 [2023-11-19 08:03:09,952 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 156409 states to 156409 states and 219637 transitions. [2023-11-19 08:03:09,952 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 156409 [2023-11-19 08:03:10,004 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 156409 [2023-11-19 08:03:10,005 INFO L73 IsDeterministic]: Start isDeterministic. Operand 156409 states and 219637 transitions. [2023-11-19 08:03:10,052 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:03:10,052 INFO L218 hiAutomatonCegarLoop]: Abstraction has 156409 states and 219637 transitions. [2023-11-19 08:03:10,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156409 states and 219637 transitions. [2023-11-19 08:03:11,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156409 to 110414. [2023-11-19 08:03:11,613 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 110414 states, 110414 states have (on average 1.4082362743854946) internal successors, (155489), 110413 states have internal predecessors, (155489), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:03:11,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110414 states to 110414 states and 155489 transitions. [2023-11-19 08:03:11,885 INFO L240 hiAutomatonCegarLoop]: Abstraction has 110414 states and 155489 transitions. [2023-11-19 08:03:11,886 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 08:03:11,886 INFO L428 stractBuchiCegarLoop]: Abstraction has 110414 states and 155489 transitions. [2023-11-19 08:03:11,887 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-19 08:03:11,887 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 110414 states and 155489 transitions. [2023-11-19 08:03:12,284 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 110016 [2023-11-19 08:03:12,284 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:03:12,284 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:03:12,295 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:03:12,295 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:03:12,296 INFO L748 eck$LassoCheckResult]: Stem: 1093575#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1093576#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1094480#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1094481#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1094097#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 1093785#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1093786#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1094451#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1094514#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1094499#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1094500#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1093921#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1093908#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1093909#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1093702#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1093703#L951 assume !(0 == ~M_E~0); 1093437#L951-2 assume !(0 == ~T1_E~0); 1093438#L956-1 assume !(0 == ~T2_E~0); 1093595#L961-1 assume !(0 == ~T3_E~0); 1094116#L966-1 assume !(0 == ~T4_E~0); 1094117#L971-1 assume !(0 == ~T5_E~0); 1094272#L976-1 assume !(0 == ~T6_E~0); 1094239#L981-1 assume !(0 == ~T7_E~0); 1093963#L986-1 assume !(0 == ~T8_E~0); 1093647#L991-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1093648#L996-1 assume !(0 == ~E_M~0); 1094674#L1001-1 assume !(0 == ~E_1~0); 1094178#L1006-1 assume !(0 == ~E_2~0); 1094179#L1011-1 assume !(0 == ~E_3~0); 1094535#L1016-1 assume !(0 == ~E_4~0); 1094536#L1021-1 assume !(0 == ~E_5~0); 1093230#L1026-1 assume !(0 == ~E_6~0); 1093231#L1031-1 assume !(0 == ~E_7~0); 1094125#L1036-1 assume !(0 == ~E_8~0); 1094126#L1041-1 assume !(0 == ~E_9~0); 1094461#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1094462#L472 assume !(1 == ~m_pc~0); 1094397#L472-2 is_master_triggered_~__retres1~0#1 := 0; 1094398#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1094375#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1094376#L1179 assume !(0 != activate_threads_~tmp~1#1); 1093239#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1093240#L491 assume !(1 == ~t1_pc~0); 1093751#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1093752#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1093264#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1093265#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 1093234#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1093235#L510 assume !(1 == ~t2_pc~0); 1093200#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1093201#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1094552#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1094649#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 1094650#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1093971#L529 assume !(1 == ~t3_pc~0); 1093972#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1094389#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1094390#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1094605#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 1094606#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1094636#L548 assume !(1 == ~t4_pc~0); 1094637#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1093606#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1093607#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1093344#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 1093345#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1093297#L567 assume !(1 == ~t5_pc~0); 1093298#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1094620#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1094621#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1094671#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 1094443#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1094444#L586 assume !(1 == ~t6_pc~0); 1093495#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1093496#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1094577#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1094660#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 1094661#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1094634#L605 assume !(1 == ~t7_pc~0); 1094635#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1094159#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1094160#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1094622#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 1094623#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1094669#L624 assume !(1 == ~t8_pc~0); 1093484#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1093483#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1094300#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1094301#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 1094657#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1093256#L643 assume !(1 == ~t9_pc~0); 1093257#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1094572#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1093832#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1093833#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 1094633#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1093468#L1059 assume !(1 == ~M_E~0); 1093469#L1059-2 assume !(1 == ~T1_E~0); 1093625#L1064-1 assume !(1 == ~T2_E~0); 1093626#L1069-1 assume !(1 == ~T3_E~0); 1094609#L1074-1 assume !(1 == ~T4_E~0); 1094610#L1079-1 assume !(1 == ~T5_E~0); 1094384#L1084-1 assume !(1 == ~T6_E~0); 1094385#L1089-1 assume !(1 == ~T7_E~0); 1094427#L1094-1 assume !(1 == ~T8_E~0); 1094428#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1094003#L1104-1 assume !(1 == ~E_M~0); 1094228#L1109-1 assume !(1 == ~E_1~0); 1093774#L1114-1 assume !(1 == ~E_2~0); 1093775#L1119-1 assume !(1 == ~E_3~0); 1093846#L1124-1 assume !(1 == ~E_4~0); 1093254#L1129-1 assume !(1 == ~E_5~0); 1093255#L1134-1 assume !(1 == ~E_6~0); 1093593#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1093594#L1144-1 assume !(1 == ~E_8~0); 1093796#L1149-1 assume !(1 == ~E_9~0); 1093427#L1154-1 assume { :end_inline_reset_delta_events } true; 1093428#L1440-2 [2023-11-19 08:03:12,296 INFO L750 eck$LassoCheckResult]: Loop: 1093428#L1440-2 assume !false; 1164404#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1164399#L926-1 assume !false; 1164398#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1164391#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1164381#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1164379#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1164376#L795 assume !(0 != eval_~tmp~0#1); 1164377#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1197817#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1197815#L951-3 assume !(0 == ~M_E~0); 1197813#L951-5 assume !(0 == ~T1_E~0); 1197811#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1197809#L961-3 assume !(0 == ~T3_E~0); 1197807#L966-3 assume !(0 == ~T4_E~0); 1197801#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1197793#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1197786#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1197780#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1197774#L991-3 assume !(0 == ~T9_E~0); 1197775#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1203497#L1001-3 assume !(0 == ~E_1~0); 1203495#L1006-3 assume !(0 == ~E_2~0); 1203487#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1203482#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1203477#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1203472#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1203466#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1203463#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1203462#L1041-3 assume !(0 == ~E_9~0); 1203289#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1203288#L472-33 assume !(1 == ~m_pc~0); 1203287#L472-35 is_master_triggered_~__retres1~0#1 := 0; 1203285#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1203284#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1202687#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1202671#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1194841#L491-33 assume !(1 == ~t1_pc~0); 1194839#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1194836#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1194834#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1194832#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 1194830#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1194828#L510-33 assume !(1 == ~t2_pc~0); 1194825#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1194822#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1194820#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1194818#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 1194816#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1185104#L529-33 assume !(1 == ~t3_pc~0); 1185102#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1185099#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1185097#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1185095#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1185093#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1185091#L548-33 assume 1 == ~t4_pc~0; 1185088#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1185085#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1185083#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1185081#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1185079#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1185077#L567-33 assume !(1 == ~t5_pc~0); 1185075#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1185072#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1185070#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1185068#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1185066#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1185064#L586-33 assume !(1 == ~t6_pc~0); 1185062#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 1185060#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1185059#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1185058#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1185057#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1185056#L605-33 assume !(1 == ~t7_pc~0); 1184106#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1185055#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1185054#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1185053#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1185052#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1185050#L624-33 assume !(1 == ~t8_pc~0); 1185046#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 1185041#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1185038#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1185035#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 1185032#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1144245#L643-33 assume !(1 == ~t9_pc~0); 1144243#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1144242#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1144240#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1144237#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1144235#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1144233#L1059-3 assume !(1 == ~M_E~0); 1143976#L1059-5 assume !(1 == ~T1_E~0); 1144228#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1144227#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1144223#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1144220#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1144217#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1144215#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1144213#L1094-3 assume !(1 == ~T8_E~0); 1144211#L1099-3 assume !(1 == ~T9_E~0); 1144208#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1144206#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1144204#L1114-3 assume !(1 == ~E_2~0); 1144202#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1144199#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1144197#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1144195#L1134-3 assume !(1 == ~E_6~0); 1144193#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1144191#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1144189#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1144188#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1144182#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1144172#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1144171#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1144168#L1459 assume !(0 == start_simulation_~tmp~3#1); 1144169#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1164426#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1164416#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1164414#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 1164412#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1164410#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1164409#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1164407#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 1093428#L1440-2 [2023-11-19 08:03:12,297 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:03:12,298 INFO L85 PathProgramCache]: Analyzing trace with hash -1773294265, now seen corresponding path program 1 times [2023-11-19 08:03:12,298 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:03:12,298 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [168924674] [2023-11-19 08:03:12,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:03:12,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:03:12,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:03:12,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:03:12,377 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:03:12,378 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [168924674] [2023-11-19 08:03:12,378 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [168924674] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:03:12,378 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:03:12,378 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:03:12,378 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1455567687] [2023-11-19 08:03:12,379 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:03:12,379 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:03:12,379 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:03:12,380 INFO L85 PathProgramCache]: Analyzing trace with hash 453406879, now seen corresponding path program 1 times [2023-11-19 08:03:12,380 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:03:12,380 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [549090557] [2023-11-19 08:03:12,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:03:12,381 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:03:12,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:03:12,445 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:03:12,445 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:03:12,446 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [549090557] [2023-11-19 08:03:12,446 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [549090557] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:03:12,446 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:03:12,446 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:03:12,447 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [846596068] [2023-11-19 08:03:12,447 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:03:12,447 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:03:12,448 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:03:12,448 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 08:03:12,448 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 08:03:12,448 INFO L87 Difference]: Start difference. First operand 110414 states and 155489 transitions. cyclomatic complexity: 45079 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:03:13,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:03:13,774 INFO L93 Difference]: Finished difference Result 145049 states and 202986 transitions. [2023-11-19 08:03:13,774 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 145049 states and 202986 transitions. [2023-11-19 08:03:14,315 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 144640 [2023-11-19 08:03:14,617 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 145049 states to 145049 states and 202986 transitions. [2023-11-19 08:03:14,618 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 145049 [2023-11-19 08:03:14,681 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 145049 [2023-11-19 08:03:14,681 INFO L73 IsDeterministic]: Start isDeterministic. Operand 145049 states and 202986 transitions. [2023-11-19 08:03:14,735 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:03:14,736 INFO L218 hiAutomatonCegarLoop]: Abstraction has 145049 states and 202986 transitions. [2023-11-19 08:03:14,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145049 states and 202986 transitions. [2023-11-19 08:03:16,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145049 to 99065. [2023-11-19 08:03:16,380 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99065 states, 99065 states have (on average 1.402331802351991) internal successors, (138922), 99064 states have internal predecessors, (138922), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:03:16,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99065 states to 99065 states and 138922 transitions. [2023-11-19 08:03:16,572 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99065 states and 138922 transitions. [2023-11-19 08:03:16,573 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 08:03:16,573 INFO L428 stractBuchiCegarLoop]: Abstraction has 99065 states and 138922 transitions. [2023-11-19 08:03:16,574 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-19 08:03:16,574 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99065 states and 138922 transitions. [2023-11-19 08:03:16,866 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 98752 [2023-11-19 08:03:16,868 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:03:16,868 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:03:16,877 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:03:16,877 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:03:16,877 INFO L748 eck$LassoCheckResult]: Stem: 1349042#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1349043#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1349939#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1349940#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1349560#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 1349245#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1349246#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1349904#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1349976#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1349960#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1349961#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1349383#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1349367#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1349368#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1349167#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1349168#L951 assume !(0 == ~M_E~0); 1348908#L951-2 assume !(0 == ~T1_E~0); 1348909#L956-1 assume !(0 == ~T2_E~0); 1349064#L961-1 assume !(0 == ~T3_E~0); 1349579#L966-1 assume !(0 == ~T4_E~0); 1349580#L971-1 assume !(0 == ~T5_E~0); 1349733#L976-1 assume !(0 == ~T6_E~0); 1349706#L981-1 assume !(0 == ~T7_E~0); 1349429#L986-1 assume !(0 == ~T8_E~0); 1349116#L991-1 assume !(0 == ~T9_E~0); 1349117#L996-1 assume !(0 == ~E_M~0); 1350015#L1001-1 assume !(0 == ~E_1~0); 1349645#L1006-1 assume !(0 == ~E_2~0); 1349646#L1011-1 assume !(0 == ~E_3~0); 1349978#L1016-1 assume !(0 == ~E_4~0); 1349992#L1021-1 assume !(0 == ~E_5~0); 1348703#L1026-1 assume !(0 == ~E_6~0); 1348704#L1031-1 assume !(0 == ~E_7~0); 1349591#L1036-1 assume !(0 == ~E_8~0); 1349589#L1041-1 assume !(0 == ~E_9~0); 1349590#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1349917#L472 assume !(1 == ~m_pc~0); 1349856#L472-2 is_master_triggered_~__retres1~0#1 := 0; 1349623#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1349624#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1349634#L1179 assume !(0 != activate_threads_~tmp~1#1); 1348711#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1348712#L491 assume !(1 == ~t1_pc~0); 1349215#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1349216#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1348736#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1348684#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 1348685#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1348707#L510 assume !(1 == ~t2_pc~0); 1348673#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1348674#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1349236#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1349237#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 1348959#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1348960#L529 assume !(1 == ~t3_pc~0); 1349435#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1349765#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1348682#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1348683#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 1348881#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1348882#L548 assume !(1 == ~t4_pc~0); 1348777#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1348776#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1348846#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1348816#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 1348817#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1348765#L567 assume !(1 == ~t5_pc~0); 1348766#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1348818#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1349839#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1349840#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 1349897#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1348892#L586 assume !(1 == ~t6_pc~0); 1348893#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1348965#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1349219#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1349220#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 1349888#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1349889#L605 assume !(1 == ~t7_pc~0); 1349407#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1349408#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1349626#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1350072#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 1350070#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1349553#L624 assume !(1 == ~t8_pc~0); 1348954#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1348953#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1349689#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1349762#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 1349863#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1348728#L643 assume !(1 == ~t9_pc~0); 1348729#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1349798#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1349290#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1349121#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 1349122#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1348939#L1059 assume !(1 == ~M_E~0); 1348940#L1059-2 assume !(1 == ~T1_E~0); 1349093#L1064-1 assume !(1 == ~T2_E~0); 1349094#L1069-1 assume !(1 == ~T3_E~0); 1349809#L1074-1 assume !(1 == ~T4_E~0); 1349860#L1079-1 assume !(1 == ~T5_E~0); 1349844#L1084-1 assume !(1 == ~T6_E~0); 1349845#L1089-1 assume !(1 == ~T7_E~0); 1349881#L1094-1 assume !(1 == ~T8_E~0); 1349470#L1099-1 assume !(1 == ~T9_E~0); 1349471#L1104-1 assume !(1 == ~E_M~0); 1349695#L1109-1 assume !(1 == ~E_1~0); 1349238#L1114-1 assume !(1 == ~E_2~0); 1349239#L1119-1 assume !(1 == ~E_3~0); 1349303#L1124-1 assume !(1 == ~E_4~0); 1348726#L1129-1 assume !(1 == ~E_5~0); 1348727#L1134-1 assume !(1 == ~E_6~0); 1349062#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1349063#L1144-1 assume !(1 == ~E_8~0); 1349255#L1149-1 assume !(1 == ~E_9~0); 1348898#L1154-1 assume { :end_inline_reset_delta_events } true; 1348899#L1440-2 [2023-11-19 08:03:16,878 INFO L750 eck$LassoCheckResult]: Loop: 1348899#L1440-2 assume !false; 1440693#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1440685#L926-1 assume !false; 1440680#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1440611#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1440601#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1440536#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1440526#L795 assume !(0 != eval_~tmp~0#1); 1440527#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1446612#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1446613#L951-3 assume !(0 == ~M_E~0); 1446608#L951-5 assume !(0 == ~T1_E~0); 1446609#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1446604#L961-3 assume !(0 == ~T3_E~0); 1446605#L966-3 assume !(0 == ~T4_E~0); 1446600#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1446601#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1446596#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1446597#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1446592#L991-3 assume !(0 == ~T9_E~0); 1446593#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1446587#L1001-3 assume !(0 == ~E_1~0); 1446588#L1006-3 assume !(0 == ~E_2~0); 1446580#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1446581#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1446574#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1446575#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1446568#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1446569#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1446563#L1041-3 assume !(0 == ~E_9~0); 1446564#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1446557#L472-33 assume !(1 == ~m_pc~0); 1446558#L472-35 is_master_triggered_~__retres1~0#1 := 0; 1446550#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1446551#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1446544#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1446545#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1443095#L491-33 assume !(1 == ~t1_pc~0); 1443096#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1443089#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1443090#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1443083#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 1443084#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1443072#L510-33 assume !(1 == ~t2_pc~0); 1443071#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1443046#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1443047#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1443030#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 1443031#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1437351#L529-33 assume !(1 == ~t3_pc~0); 1437349#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1437347#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1437345#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1437343#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1437340#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1437338#L548-33 assume 1 == ~t4_pc~0; 1437335#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1437333#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1437331#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1437315#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1437310#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1437305#L567-33 assume !(1 == ~t5_pc~0); 1437298#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1437290#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1437283#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1437277#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1437271#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1437264#L586-33 assume 1 == ~t6_pc~0; 1437255#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1437248#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1437243#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1437237#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1437231#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1396588#L605-33 assume !(1 == ~t7_pc~0); 1396586#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1396584#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1396581#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1396580#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1396577#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1396575#L624-33 assume !(1 == ~t8_pc~0); 1396573#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 1396570#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1396568#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1396566#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 1396565#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1396563#L643-33 assume !(1 == ~t9_pc~0); 1394969#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1396560#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1396558#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1396556#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1396554#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1396552#L1059-3 assume !(1 == ~M_E~0); 1391333#L1059-5 assume !(1 == ~T1_E~0); 1396549#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1396547#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1396545#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1396543#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1396541#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1396539#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1396537#L1094-3 assume !(1 == ~T8_E~0); 1396535#L1099-3 assume !(1 == ~T9_E~0); 1396533#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1396531#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1396529#L1114-3 assume !(1 == ~E_2~0); 1396528#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1396527#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1396526#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1396515#L1134-3 assume !(1 == ~E_6~0); 1396513#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1396511#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1396510#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1395823#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1395820#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1395801#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1395799#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1395795#L1459 assume !(0 == start_simulation_~tmp~3#1); 1395796#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1440774#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1440764#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1440761#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 1440760#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1440758#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1440721#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1440711#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 1348899#L1440-2 [2023-11-19 08:03:16,879 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:03:16,879 INFO L85 PathProgramCache]: Analyzing trace with hash 1896329479, now seen corresponding path program 1 times [2023-11-19 08:03:16,879 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:03:16,879 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1369520804] [2023-11-19 08:03:16,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:03:16,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:03:16,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:03:16,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:03:16,960 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:03:16,960 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1369520804] [2023-11-19 08:03:16,961 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1369520804] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:03:16,961 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:03:16,961 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:03:16,961 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [170281618] [2023-11-19 08:03:16,961 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:03:16,962 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:03:16,962 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:03:16,962 INFO L85 PathProgramCache]: Analyzing trace with hash 213139550, now seen corresponding path program 1 times [2023-11-19 08:03:16,963 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:03:16,963 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1826367445] [2023-11-19 08:03:16,963 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:03:16,963 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:03:16,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:03:17,012 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:03:17,013 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:03:17,013 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1826367445] [2023-11-19 08:03:17,013 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1826367445] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:03:17,013 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:03:17,013 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:03:17,013 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [712786867] [2023-11-19 08:03:17,014 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:03:17,014 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:03:17,014 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:03:17,015 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 08:03:17,015 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 08:03:17,015 INFO L87 Difference]: Start difference. First operand 99065 states and 138922 transitions. cyclomatic complexity: 39861 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:03:18,386 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:03:18,386 INFO L93 Difference]: Finished difference Result 153169 states and 213971 transitions. [2023-11-19 08:03:18,386 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 153169 states and 213971 transitions. [2023-11-19 08:03:19,002 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 152608 [2023-11-19 08:03:19,352 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 153169 states to 153169 states and 213971 transitions. [2023-11-19 08:03:19,353 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 153169 [2023-11-19 08:03:19,436 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 153169 [2023-11-19 08:03:19,436 INFO L73 IsDeterministic]: Start isDeterministic. Operand 153169 states and 213971 transitions. [2023-11-19 08:03:19,490 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:03:19,490 INFO L218 hiAutomatonCegarLoop]: Abstraction has 153169 states and 213971 transitions. [2023-11-19 08:03:19,560 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153169 states and 213971 transitions. [2023-11-19 08:03:21,352 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153169 to 110350. [2023-11-19 08:03:21,440 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 110350 states, 110350 states have (on average 1.3991662890801995) internal successors, (154398), 110349 states have internal predecessors, (154398), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:03:21,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110350 states to 110350 states and 154398 transitions. [2023-11-19 08:03:21,702 INFO L240 hiAutomatonCegarLoop]: Abstraction has 110350 states and 154398 transitions. [2023-11-19 08:03:21,703 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 08:03:21,703 INFO L428 stractBuchiCegarLoop]: Abstraction has 110350 states and 154398 transitions. [2023-11-19 08:03:21,703 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-19 08:03:21,703 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 110350 states and 154398 transitions.