./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.10.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 9bd2c7ff Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f01e1a23-3ddb-4c38-aece-121757e9a9ab/bin/uautomizer-verify-uCwYo4JHxu/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f01e1a23-3ddb-4c38-aece-121757e9a9ab/bin/uautomizer-verify-uCwYo4JHxu/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f01e1a23-3ddb-4c38-aece-121757e9a9ab/bin/uautomizer-verify-uCwYo4JHxu/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f01e1a23-3ddb-4c38-aece-121757e9a9ab/bin/uautomizer-verify-uCwYo4JHxu/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.10.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f01e1a23-3ddb-4c38-aece-121757e9a9ab/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f01e1a23-3ddb-4c38-aece-121757e9a9ab/bin/uautomizer-verify-uCwYo4JHxu --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 6ba9401cadb8fecd59a1a331c94e3215cc972a92f03516bfd6c95164e3ec98a9 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-9bd2c7f [2023-11-19 08:02:18,813 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-19 08:02:18,893 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f01e1a23-3ddb-4c38-aece-121757e9a9ab/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-19 08:02:18,899 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-19 08:02:18,900 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-19 08:02:18,931 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-19 08:02:18,931 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-19 08:02:18,932 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-19 08:02:18,934 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-19 08:02:18,939 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-19 08:02:18,941 INFO L153 SettingsManager]: * Use SBE=true [2023-11-19 08:02:18,941 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-19 08:02:18,942 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-19 08:02:18,944 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-19 08:02:18,944 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-19 08:02:18,944 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-19 08:02:18,945 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-19 08:02:18,946 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-19 08:02:18,946 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-19 08:02:18,947 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-19 08:02:18,947 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-19 08:02:18,948 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-19 08:02:18,948 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-19 08:02:18,949 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-19 08:02:18,949 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-19 08:02:18,949 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-19 08:02:18,950 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-19 08:02:18,950 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-19 08:02:18,951 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-19 08:02:18,951 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-19 08:02:18,952 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-19 08:02:18,953 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-19 08:02:18,953 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-19 08:02:18,953 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-19 08:02:18,954 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-19 08:02:18,955 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-19 08:02:18,955 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f01e1a23-3ddb-4c38-aece-121757e9a9ab/bin/uautomizer-verify-uCwYo4JHxu/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f01e1a23-3ddb-4c38-aece-121757e9a9ab/bin/uautomizer-verify-uCwYo4JHxu Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 6ba9401cadb8fecd59a1a331c94e3215cc972a92f03516bfd6c95164e3ec98a9 [2023-11-19 08:02:19,250 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-19 08:02:19,285 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-19 08:02:19,288 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-19 08:02:19,289 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-19 08:02:19,290 INFO L274 PluginConnector]: CDTParser initialized [2023-11-19 08:02:19,292 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f01e1a23-3ddb-4c38-aece-121757e9a9ab/bin/uautomizer-verify-uCwYo4JHxu/../../sv-benchmarks/c/systemc/token_ring.10.cil-2.c [2023-11-19 08:02:22,529 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-19 08:02:22,841 INFO L384 CDTParser]: Found 1 translation units. [2023-11-19 08:02:22,841 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f01e1a23-3ddb-4c38-aece-121757e9a9ab/sv-benchmarks/c/systemc/token_ring.10.cil-2.c [2023-11-19 08:02:22,871 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f01e1a23-3ddb-4c38-aece-121757e9a9ab/bin/uautomizer-verify-uCwYo4JHxu/data/dd94ba9ae/886fdfd1169340ed9e58e78fe9d56714/FLAGcb9c3c23b [2023-11-19 08:02:22,889 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f01e1a23-3ddb-4c38-aece-121757e9a9ab/bin/uautomizer-verify-uCwYo4JHxu/data/dd94ba9ae/886fdfd1169340ed9e58e78fe9d56714 [2023-11-19 08:02:22,893 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-19 08:02:22,895 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-19 08:02:22,897 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-19 08:02:22,897 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-19 08:02:22,905 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-19 08:02:22,905 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 08:02:22" (1/1) ... [2023-11-19 08:02:22,907 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@20b24b94 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:22, skipping insertion in model container [2023-11-19 08:02:22,907 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 08:02:22" (1/1) ... [2023-11-19 08:02:22,962 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-19 08:02:23,243 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 08:02:23,259 INFO L202 MainTranslator]: Completed pre-run [2023-11-19 08:02:23,367 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 08:02:23,399 INFO L206 MainTranslator]: Completed translation [2023-11-19 08:02:23,399 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:23 WrapperNode [2023-11-19 08:02:23,400 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-19 08:02:23,401 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-19 08:02:23,401 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-19 08:02:23,401 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-19 08:02:23,408 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:23" (1/1) ... [2023-11-19 08:02:23,423 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:23" (1/1) ... [2023-11-19 08:02:23,525 INFO L138 Inliner]: procedures = 48, calls = 62, calls flagged for inlining = 57, calls inlined = 210, statements flattened = 3209 [2023-11-19 08:02:23,525 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-19 08:02:23,526 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-19 08:02:23,526 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-19 08:02:23,526 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-19 08:02:23,543 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:23" (1/1) ... [2023-11-19 08:02:23,544 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:23" (1/1) ... [2023-11-19 08:02:23,579 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:23" (1/1) ... [2023-11-19 08:02:23,580 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:23" (1/1) ... [2023-11-19 08:02:23,654 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:23" (1/1) ... [2023-11-19 08:02:23,686 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:23" (1/1) ... [2023-11-19 08:02:23,691 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:23" (1/1) ... [2023-11-19 08:02:23,703 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:23" (1/1) ... [2023-11-19 08:02:23,718 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-19 08:02:23,719 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-19 08:02:23,719 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-19 08:02:23,719 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-19 08:02:23,720 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:23" (1/1) ... [2023-11-19 08:02:23,736 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 08:02:23,751 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f01e1a23-3ddb-4c38-aece-121757e9a9ab/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 08:02:23,764 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f01e1a23-3ddb-4c38-aece-121757e9a9ab/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 08:02:23,789 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f01e1a23-3ddb-4c38-aece-121757e9a9ab/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-19 08:02:23,810 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-19 08:02:23,811 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-19 08:02:23,811 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-19 08:02:23,811 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-19 08:02:23,933 INFO L236 CfgBuilder]: Building ICFG [2023-11-19 08:02:23,935 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-19 08:02:26,136 INFO L277 CfgBuilder]: Performing block encoding [2023-11-19 08:02:26,162 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-19 08:02:26,162 INFO L302 CfgBuilder]: Removed 13 assume(true) statements. [2023-11-19 08:02:26,179 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 08:02:26 BoogieIcfgContainer [2023-11-19 08:02:26,179 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-19 08:02:26,181 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-19 08:02:26,181 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-19 08:02:26,186 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-19 08:02:26,187 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 08:02:26,187 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 08:02:22" (1/3) ... [2023-11-19 08:02:26,188 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@530ed3db and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 08:02:26, skipping insertion in model container [2023-11-19 08:02:26,188 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 08:02:26,188 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:02:23" (2/3) ... [2023-11-19 08:02:26,189 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@530ed3db and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 08:02:26, skipping insertion in model container [2023-11-19 08:02:26,189 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 08:02:26,189 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 08:02:26" (3/3) ... [2023-11-19 08:02:26,191 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.10.cil-2.c [2023-11-19 08:02:26,315 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-19 08:02:26,316 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-19 08:02:26,316 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-19 08:02:26,316 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-19 08:02:26,316 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-19 08:02:26,316 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-19 08:02:26,316 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-19 08:02:26,317 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-19 08:02:26,329 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1379 states, 1378 states have (on average 1.5014513788098693) internal successors, (2069), 1378 states have internal predecessors, (2069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:26,428 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1236 [2023-11-19 08:02:26,429 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:26,429 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:26,451 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:26,452 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:26,452 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-19 08:02:26,457 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1379 states, 1378 states have (on average 1.5014513788098693) internal successors, (2069), 1378 states have internal predecessors, (2069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:26,481 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1236 [2023-11-19 08:02:26,481 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:26,481 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:26,488 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:26,489 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:26,501 INFO L748 eck$LassoCheckResult]: Stem: 188#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1260#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 998#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1256#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 589#L719true assume !(1 == ~m_i~0);~m_st~0 := 2; 358#L719-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 563#L724-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 730#L729-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1246#L734-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 477#L739-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 848#L744-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 392#L749-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 683#L754-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 869#L759-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 639#L764-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 571#L769-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 857#L1024true assume !(0 == ~M_E~0); 960#L1024-2true assume !(0 == ~T1_E~0); 186#L1029-1true assume !(0 == ~T2_E~0); 245#L1034-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1328#L1039-1true assume !(0 == ~T4_E~0); 1035#L1044-1true assume !(0 == ~T5_E~0); 407#L1049-1true assume !(0 == ~T6_E~0); 1342#L1054-1true assume !(0 == ~T7_E~0); 588#L1059-1true assume !(0 == ~T8_E~0); 214#L1064-1true assume !(0 == ~T9_E~0); 822#L1069-1true assume !(0 == ~T10_E~0); 1239#L1074-1true assume 0 == ~E_M~0;~E_M~0 := 1; 899#L1079-1true assume !(0 == ~E_1~0); 860#L1084-1true assume !(0 == ~E_2~0); 1059#L1089-1true assume !(0 == ~E_3~0); 933#L1094-1true assume !(0 == ~E_4~0); 469#L1099-1true assume !(0 == ~E_5~0); 1074#L1104-1true assume !(0 == ~E_6~0); 702#L1109-1true assume !(0 == ~E_7~0); 320#L1114-1true assume 0 == ~E_8~0;~E_8~0 := 1; 1291#L1119-1true assume !(0 == ~E_9~0); 365#L1124-1true assume !(0 == ~E_10~0); 39#L1129-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 721#L502true assume 1 == ~m_pc~0; 586#L503true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 100#L513true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 851#is_master_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 636#L1273true assume !(0 != activate_threads_~tmp~1#1); 1378#L1273-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1143#L521true assume !(1 == ~t1_pc~0); 1070#L521-2true is_transmit1_triggered_~__retres1~1#1 := 0; 63#L532true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 652#L1281true assume !(0 != activate_threads_~tmp___0~0#1); 56#L1281-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 875#L540true assume 1 == ~t2_pc~0; 1125#L541true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 879#L551true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 318#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1240#L1289true assume !(0 != activate_threads_~tmp___1~0#1); 968#L1289-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 203#L559true assume 1 == ~t3_pc~0; 1044#L560true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 377#L570true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 665#L1297true assume !(0 != activate_threads_~tmp___2~0#1); 108#L1297-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1267#L578true assume !(1 == ~t4_pc~0); 828#L578-2true is_transmit4_triggered_~__retres1~4#1 := 0; 854#L589true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1111#L1305true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 619#L1305-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1179#L597true assume 1 == ~t5_pc~0; 1347#L598true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 73#L608true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 855#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1366#L1313true assume !(0 != activate_threads_~tmp___4~0#1); 572#L1313-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 633#L616true assume !(1 == ~t6_pc~0); 1191#L616-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1087#L627true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 304#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 509#L1321true assume !(0 != activate_threads_~tmp___5~0#1); 462#L1321-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 697#L635true assume 1 == ~t7_pc~0; 622#L636true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 255#L646true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1276#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 928#L1329true assume !(0 != activate_threads_~tmp___6~0#1); 567#L1329-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 816#L654true assume !(1 == ~t8_pc~0); 426#L654-2true is_transmit8_triggered_~__retres1~8#1 := 0; 969#L665true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 764#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 819#L1337true assume !(0 != activate_threads_~tmp___7~0#1); 1021#L1337-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 185#L673true assume 1 == ~t9_pc~0; 1038#L674true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1215#L684true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 355#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 768#L1345true assume !(0 != activate_threads_~tmp___8~0#1); 715#L1345-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 888#L692true assume !(1 == ~t10_pc~0); 701#L692-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1028#L703true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 464#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 472#L1353true assume !(0 != activate_threads_~tmp___9~0#1); 792#L1353-2true havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1325#L1142true assume !(1 == ~M_E~0); 138#L1142-2true assume !(1 == ~T1_E~0); 769#L1147-1true assume !(1 == ~T2_E~0); 1324#L1152-1true assume !(1 == ~T3_E~0); 382#L1157-1true assume !(1 == ~T4_E~0); 868#L1162-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 491#L1167-1true assume !(1 == ~T6_E~0); 952#L1172-1true assume !(1 == ~T7_E~0); 982#L1177-1true assume !(1 == ~T8_E~0); 604#L1182-1true assume !(1 == ~T9_E~0); 708#L1187-1true assume !(1 == ~T10_E~0); 758#L1192-1true assume !(1 == ~E_M~0); 288#L1197-1true assume !(1 == ~E_1~0); 773#L1202-1true assume 1 == ~E_2~0;~E_2~0 := 2; 555#L1207-1true assume !(1 == ~E_3~0); 539#L1212-1true assume !(1 == ~E_4~0); 66#L1217-1true assume !(1 == ~E_5~0); 1380#L1222-1true assume !(1 == ~E_6~0); 536#L1227-1true assume !(1 == ~E_7~0); 601#L1232-1true assume !(1 == ~E_8~0); 7#L1237-1true assume !(1 == ~E_9~0); 1079#L1242-1true assume 1 == ~E_10~0;~E_10~0 := 2; 587#L1247-1true assume { :end_inline_reset_delta_events } true; 88#L1553-2true [2023-11-19 08:02:26,505 INFO L750 eck$LassoCheckResult]: Loop: 88#L1553-2true assume !false; 755#L1554true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 235#L999-1true assume false; 779#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 481#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1305#L1024-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1025#L1024-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 459#L1029-3true assume !(0 == ~T2_E~0); 435#L1034-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 735#L1039-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 788#L1044-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 183#L1049-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 664#L1054-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 64#L1059-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1350#L1064-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 415#L1069-3true assume !(0 == ~T10_E~0); 710#L1074-3true assume 0 == ~E_M~0;~E_M~0 := 1; 1001#L1079-3true assume 0 == ~E_1~0;~E_1~0 := 1; 595#L1084-3true assume 0 == ~E_2~0;~E_2~0 := 1; 504#L1089-3true assume 0 == ~E_3~0;~E_3~0 := 1; 662#L1094-3true assume 0 == ~E_4~0;~E_4~0 := 1; 448#L1099-3true assume 0 == ~E_5~0;~E_5~0 := 1; 733#L1104-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1085#L1109-3true assume !(0 == ~E_7~0); 719#L1114-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1204#L1119-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1344#L1124-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1237#L1129-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1118#L502-36true assume 1 == ~m_pc~0; 736#L503-12true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2#L513-12true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1003#is_master_triggered_returnLabel#13true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 215#L1273-36true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 703#L1273-38true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 394#L521-36true assume !(1 == ~t1_pc~0); 1098#L521-38true is_transmit1_triggered_~__retres1~1#1 := 0; 528#L532-12true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 999#is_transmit1_triggered_returnLabel#13true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1209#L1281-36true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 826#L1281-38true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1128#L540-36true assume !(1 == ~t2_pc~0); 42#L540-38true is_transmit2_triggered_~__retres1~2#1 := 0; 258#L551-12true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 827#is_transmit2_triggered_returnLabel#13true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1351#L1289-36true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 488#L1289-38true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6#L559-36true assume 1 == ~t3_pc~0; 726#L560-12true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 756#L570-12true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 353#is_transmit3_triggered_returnLabel#13true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 606#L1297-36true assume !(0 != activate_threads_~tmp___2~0#1); 894#L1297-38true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1250#L578-36true assume 1 == ~t4_pc~0; 579#L579-12true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1259#L589-12true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 496#is_transmit4_triggered_returnLabel#13true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1323#L1305-36true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 419#L1305-38true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 594#L597-36true assume !(1 == ~t5_pc~0); 1141#L597-38true is_transmit5_triggered_~__retres1~5#1 := 0; 1078#L608-12true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 967#is_transmit5_triggered_returnLabel#13true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 556#L1313-36true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 289#L1313-38true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1130#L616-36true assume 1 == ~t6_pc~0; 1349#L617-12true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37#L627-12true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 338#is_transmit6_triggered_returnLabel#13true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 456#L1321-36true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 754#L1321-38true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1362#L635-36true assume 1 == ~t7_pc~0; 1030#L636-12true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 838#L646-12true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 932#is_transmit7_triggered_returnLabel#13true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1284#L1329-36true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 446#L1329-38true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1297#L654-36true assume 1 == ~t8_pc~0; 1218#L655-12true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1346#L665-12true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 576#is_transmit8_triggered_returnLabel#13true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1190#L1337-36true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1145#L1337-38true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 231#L673-36true assume !(1 == ~t9_pc~0); 740#L673-38true is_transmit9_triggered_~__retres1~9#1 := 0; 478#L684-12true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 380#is_transmit9_triggered_returnLabel#13true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1050#L1345-36true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10#L1345-38true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1201#L692-36true assume !(1 == ~t10_pc~0); 112#L692-38true is_transmit10_triggered_~__retres1~10#1 := 0; 455#L703-12true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 278#is_transmit10_triggered_returnLabel#13true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 212#L1353-36true assume !(0 != activate_threads_~tmp___9~0#1); 454#L1353-38true havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 573#L1142-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1185#L1142-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1034#L1147-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1090#L1152-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 513#L1157-3true assume !(1 == ~T4_E~0); 834#L1162-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1088#L1167-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1011#L1172-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 444#L1177-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 374#L1182-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 867#L1187-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 384#L1192-3true assume 1 == ~E_M~0;~E_M~0 := 2; 266#L1197-3true assume !(1 == ~E_1~0); 433#L1202-3true assume 1 == ~E_2~0;~E_2~0 := 2; 522#L1207-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1126#L1212-3true assume 1 == ~E_4~0;~E_4~0 := 2; 731#L1217-3true assume 1 == ~E_5~0;~E_5~0 := 2; 207#L1222-3true assume 1 == ~E_6~0;~E_6~0 := 2; 48#L1227-3true assume 1 == ~E_7~0;~E_7~0 := 2; 900#L1232-3true assume 1 == ~E_8~0;~E_8~0 := 2; 870#L1237-3true assume !(1 == ~E_9~0); 1310#L1242-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1264#L1247-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 945#L782-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 120#L839-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 271#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 580#L1572true assume !(0 == start_simulation_~tmp~3#1); 395#L1572-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1231#L782-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1103#L839-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 43#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 1301#L1527true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4#L1534true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 499#stop_simulation_returnLabel#1true start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1371#L1585true assume !(0 != start_simulation_~tmp___0~1#1); 88#L1553-2true [2023-11-19 08:02:26,514 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:26,514 INFO L85 PathProgramCache]: Analyzing trace with hash 121410427, now seen corresponding path program 1 times [2023-11-19 08:02:26,526 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:26,526 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1031774638] [2023-11-19 08:02:26,527 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:26,528 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:26,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:26,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:26,913 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:26,913 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1031774638] [2023-11-19 08:02:26,914 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1031774638] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:26,915 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:26,915 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:26,917 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1552278690] [2023-11-19 08:02:26,918 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:26,925 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:26,926 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:26,927 INFO L85 PathProgramCache]: Analyzing trace with hash 1194100893, now seen corresponding path program 1 times [2023-11-19 08:02:26,927 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:26,928 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2113837645] [2023-11-19 08:02:26,928 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:26,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:26,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:27,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:27,061 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:27,061 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2113837645] [2023-11-19 08:02:27,062 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2113837645] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:27,062 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:27,062 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 08:02:27,062 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [52122083] [2023-11-19 08:02:27,062 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:27,064 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:27,065 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:27,107 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:02:27,108 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:02:27,114 INFO L87 Difference]: Start difference. First operand has 1379 states, 1378 states have (on average 1.5014513788098693) internal successors, (2069), 1378 states have internal predecessors, (2069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:27,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:27,215 INFO L93 Difference]: Finished difference Result 1377 states and 2039 transitions. [2023-11-19 08:02:27,216 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2039 transitions. [2023-11-19 08:02:27,234 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-19 08:02:27,257 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1372 states and 2034 transitions. [2023-11-19 08:02:27,258 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2023-11-19 08:02:27,261 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2023-11-19 08:02:27,262 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2034 transitions. [2023-11-19 08:02:27,276 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:27,276 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2034 transitions. [2023-11-19 08:02:27,308 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2034 transitions. [2023-11-19 08:02:27,384 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2023-11-19 08:02:27,389 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.4825072886297377) internal successors, (2034), 1371 states have internal predecessors, (2034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:27,397 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2034 transitions. [2023-11-19 08:02:27,398 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2034 transitions. [2023-11-19 08:02:27,400 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:02:27,405 INFO L428 stractBuchiCegarLoop]: Abstraction has 1372 states and 2034 transitions. [2023-11-19 08:02:27,405 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-19 08:02:27,405 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2034 transitions. [2023-11-19 08:02:27,418 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-19 08:02:27,418 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:27,418 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:27,423 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:27,423 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:27,424 INFO L748 eck$LassoCheckResult]: Stem: 3147#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3148#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4049#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4050#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3729#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 3418#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3419#L724-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3699#L729-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3869#L734-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3587#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3588#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3469#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3470#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3823#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3783#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 3707#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3708#L1024 assume !(0 == ~M_E~0); 3963#L1024-2 assume !(0 == ~T1_E~0); 3143#L1029-1 assume !(0 == ~T2_E~0); 3144#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3246#L1039-1 assume !(0 == ~T4_E~0); 4073#L1044-1 assume !(0 == ~T5_E~0); 3491#L1049-1 assume !(0 == ~T6_E~0); 3492#L1054-1 assume !(0 == ~T7_E~0); 3728#L1059-1 assume !(0 == ~T8_E~0); 3193#L1064-1 assume !(0 == ~T9_E~0); 3194#L1069-1 assume !(0 == ~T10_E~0); 3932#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3992#L1079-1 assume !(0 == ~E_1~0); 3965#L1084-1 assume !(0 == ~E_2~0); 3966#L1089-1 assume !(0 == ~E_3~0); 4010#L1094-1 assume !(0 == ~E_4~0); 3577#L1099-1 assume !(0 == ~E_5~0); 3578#L1104-1 assume !(0 == ~E_6~0); 3841#L1109-1 assume !(0 == ~E_7~0); 3360#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 3361#L1119-1 assume !(0 == ~E_9~0); 3431#L1124-1 assume !(0 == ~E_10~0); 2847#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2848#L502 assume 1 == ~m_pc~0; 3726#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2973#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2974#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3779#L1273 assume !(0 != activate_threads_~tmp~1#1); 3780#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4103#L521 assume !(1 == ~t1_pc~0); 4038#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2898#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2863#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2864#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 2884#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2885#L540 assume 1 == ~t2_pc~0; 3976#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3688#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3356#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3357#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 4034#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3171#L559 assume 1 == ~t3_pc~0; 3172#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3449#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2800#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2801#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 2991#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2992#L578 assume !(1 == ~t4_pc~0); 3115#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3114#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2931#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2932#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3760#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3761#L597 assume 1 == ~t5_pc~0; 4119#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2918#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2919#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3961#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 3709#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3710#L616 assume !(1 == ~t6_pc~0); 3725#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3724#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3332#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3333#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 3567#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3568#L635 assume 1 == ~t7_pc~0; 3764#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2887#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3264#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4006#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 3701#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3702#L654 assume !(1 == ~t8_pc~0); 3518#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3519#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3894#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3895#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 3930#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3141#L673 assume 1 == ~t9_pc~0; 3142#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2838#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3413#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3414#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 3853#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3854#L692 assume !(1 == ~t10_pc~0); 3798#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3797#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3569#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3570#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 3581#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3909#L1142 assume !(1 == ~M_E~0); 3052#L1142-2 assume !(1 == ~T1_E~0); 3053#L1147-1 assume !(1 == ~T2_E~0); 3898#L1152-1 assume !(1 == ~T3_E~0); 3455#L1157-1 assume !(1 == ~T4_E~0); 3456#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3605#L1167-1 assume !(1 == ~T6_E~0); 3606#L1172-1 assume !(1 == ~T7_E~0); 4028#L1177-1 assume !(1 == ~T8_E~0); 3746#L1182-1 assume !(1 == ~T9_E~0); 3747#L1187-1 assume !(1 == ~T10_E~0); 3846#L1192-1 assume !(1 == ~E_M~0); 3312#L1197-1 assume !(1 == ~E_1~0); 3313#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3691#L1207-1 assume !(1 == ~E_3~0); 3666#L1212-1 assume !(1 == ~E_4~0); 2903#L1217-1 assume !(1 == ~E_5~0); 2904#L1222-1 assume !(1 == ~E_6~0); 3663#L1227-1 assume !(1 == ~E_7~0); 3664#L1232-1 assume !(1 == ~E_8~0); 2777#L1237-1 assume !(1 == ~E_9~0); 2778#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 3727#L1247-1 assume { :end_inline_reset_delta_events } true; 2948#L1553-2 [2023-11-19 08:02:27,425 INFO L750 eck$LassoCheckResult]: Loop: 2948#L1553-2 assume !false; 2949#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3088#L999-1 assume !false; 3229#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3036#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2921#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3393#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3394#L854 assume !(0 != eval_~tmp~0#1); 3803#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3590#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3591#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4063#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3563#L1029-3 assume !(0 == ~T2_E~0); 3531#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3532#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3874#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3137#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3138#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2899#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2900#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3501#L1069-3 assume !(0 == ~T10_E~0); 3502#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3848#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3739#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3624#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3625#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3550#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3551#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3872#L1109-3 assume !(0 == ~E_7~0); 3860#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3861#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4124#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4131#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4097#L502-36 assume !(1 == ~m_pc~0); 3280#L502-38 is_master_triggered_~__retres1~0#1 := 0; 2765#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2766#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3195#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3196#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3474#L521-36 assume 1 == ~t1_pc~0; 3475#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3485#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3655#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4051#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3934#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3935#L540-36 assume !(1 == ~t2_pc~0); 2849#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 2850#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3267#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3936#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3600#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2771#L559-36 assume !(1 == ~t3_pc~0); 2772#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3230#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3408#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3409#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 3748#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3988#L578-36 assume 1 == ~t4_pc~0; 3717#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3673#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3611#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3612#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3507#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3508#L597-36 assume !(1 == ~t5_pc~0); 3736#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 4089#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4033#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3690#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3310#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3311#L616-36 assume 1 == ~t6_pc~0; 4100#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2843#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2844#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3388#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3560#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3889#L635-36 assume 1 == ~t7_pc~0; 4064#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3946#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3947#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4009#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3546#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3547#L654-36 assume !(1 == ~t8_pc~0); 4069#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 4070#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3713#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3714#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4104#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3221#L673-36 assume 1 == ~t9_pc~0; 3222#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3586#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3451#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3452#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2784#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2785#L692-36 assume !(1 == ~t10_pc~0); 2999#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3000#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3294#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3188#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 3189#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3557#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3706#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4071#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4072#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3637#L1157-3 assume !(1 == ~T4_E~0); 3638#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3942#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4055#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3545#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3443#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3444#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3458#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3277#L1197-3 assume !(1 == ~E_1~0); 3278#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3528#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3646#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3870#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3181#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2868#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2869#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3971#L1237-3 assume !(1 == ~E_9~0); 3972#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4134#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4020#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3019#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3020#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3284#L1572 assume !(0 == start_simulation_~tmp~3#1); 3315#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3477#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2798#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2856#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 2857#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2769#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2770#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3617#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 2948#L1553-2 [2023-11-19 08:02:27,426 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:27,427 INFO L85 PathProgramCache]: Analyzing trace with hash -825627459, now seen corresponding path program 1 times [2023-11-19 08:02:27,427 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:27,427 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2027948483] [2023-11-19 08:02:27,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:27,428 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:27,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:27,574 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:27,574 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:27,575 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2027948483] [2023-11-19 08:02:27,575 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2027948483] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:27,575 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:27,575 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:27,575 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1074015476] [2023-11-19 08:02:27,576 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:27,576 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:27,577 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:27,577 INFO L85 PathProgramCache]: Analyzing trace with hash 1542473243, now seen corresponding path program 1 times [2023-11-19 08:02:27,577 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:27,578 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1825301461] [2023-11-19 08:02:27,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:27,578 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:27,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:27,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:27,770 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:27,770 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1825301461] [2023-11-19 08:02:27,770 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1825301461] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:27,770 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:27,771 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:27,771 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1845320077] [2023-11-19 08:02:27,771 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:27,772 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:27,772 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:27,773 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:02:27,773 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:02:27,773 INFO L87 Difference]: Start difference. First operand 1372 states and 2034 transitions. cyclomatic complexity: 663 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:27,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:27,818 INFO L93 Difference]: Finished difference Result 1372 states and 2033 transitions. [2023-11-19 08:02:27,818 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2033 transitions. [2023-11-19 08:02:27,832 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-19 08:02:27,845 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2033 transitions. [2023-11-19 08:02:27,846 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2023-11-19 08:02:27,847 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2023-11-19 08:02:27,848 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2033 transitions. [2023-11-19 08:02:27,851 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:27,851 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2033 transitions. [2023-11-19 08:02:27,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2033 transitions. [2023-11-19 08:02:27,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2023-11-19 08:02:27,882 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.4817784256559767) internal successors, (2033), 1371 states have internal predecessors, (2033), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:27,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2033 transitions. [2023-11-19 08:02:27,893 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2033 transitions. [2023-11-19 08:02:27,894 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:02:27,895 INFO L428 stractBuchiCegarLoop]: Abstraction has 1372 states and 2033 transitions. [2023-11-19 08:02:27,895 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-19 08:02:27,896 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2033 transitions. [2023-11-19 08:02:27,907 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-19 08:02:27,908 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:27,908 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:27,914 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:27,920 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:27,923 INFO L748 eck$LassoCheckResult]: Stem: 5898#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 5899#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 6800#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6801#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6480#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 6168#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6169#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6450#L729-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6620#L734-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6337#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6338#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6220#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6221#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6574#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6534#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 6457#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6458#L1024 assume !(0 == ~M_E~0); 6714#L1024-2 assume !(0 == ~T1_E~0); 5894#L1029-1 assume !(0 == ~T2_E~0); 5895#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5997#L1039-1 assume !(0 == ~T4_E~0); 6824#L1044-1 assume !(0 == ~T5_E~0); 6240#L1049-1 assume !(0 == ~T6_E~0); 6241#L1054-1 assume !(0 == ~T7_E~0); 6479#L1059-1 assume !(0 == ~T8_E~0); 5944#L1064-1 assume !(0 == ~T9_E~0); 5945#L1069-1 assume !(0 == ~T10_E~0); 6683#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 6743#L1079-1 assume !(0 == ~E_1~0); 6716#L1084-1 assume !(0 == ~E_2~0); 6717#L1089-1 assume !(0 == ~E_3~0); 6761#L1094-1 assume !(0 == ~E_4~0); 6328#L1099-1 assume !(0 == ~E_5~0); 6329#L1104-1 assume !(0 == ~E_6~0); 6592#L1109-1 assume !(0 == ~E_7~0); 6111#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 6112#L1119-1 assume !(0 == ~E_9~0); 6178#L1124-1 assume !(0 == ~E_10~0); 5598#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5599#L502 assume 1 == ~m_pc~0; 6477#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5724#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5725#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6528#L1273 assume !(0 != activate_threads_~tmp~1#1); 6529#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6854#L521 assume !(1 == ~t1_pc~0); 6789#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5649#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5614#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5615#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 5635#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5636#L540 assume 1 == ~t2_pc~0; 6727#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6439#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6107#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6108#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 6785#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5922#L559 assume 1 == ~t3_pc~0; 5923#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6199#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5551#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5552#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 5742#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5743#L578 assume !(1 == ~t4_pc~0); 5861#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5860#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5681#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5682#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6509#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6510#L597 assume 1 == ~t5_pc~0; 6869#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5669#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5670#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6712#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 6459#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6460#L616 assume !(1 == ~t6_pc~0); 6474#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6473#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6083#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6084#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 6317#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6318#L635 assume 1 == ~t7_pc~0; 6514#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5638#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6013#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6757#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 6452#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6453#L654 assume !(1 == ~t8_pc~0); 6269#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6270#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6642#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6643#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 6681#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5892#L673 assume 1 == ~t9_pc~0; 5893#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5589#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6162#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6163#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 6604#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6605#L692 assume !(1 == ~t10_pc~0); 6549#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6548#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6320#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6321#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 6332#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6660#L1142 assume !(1 == ~M_E~0); 5803#L1142-2 assume !(1 == ~T1_E~0); 5804#L1147-1 assume !(1 == ~T2_E~0); 6649#L1152-1 assume !(1 == ~T3_E~0); 6206#L1157-1 assume !(1 == ~T4_E~0); 6207#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6356#L1167-1 assume !(1 == ~T6_E~0); 6357#L1172-1 assume !(1 == ~T7_E~0); 6778#L1177-1 assume !(1 == ~T8_E~0); 6497#L1182-1 assume !(1 == ~T9_E~0); 6498#L1187-1 assume !(1 == ~T10_E~0); 6597#L1192-1 assume !(1 == ~E_M~0); 6061#L1197-1 assume !(1 == ~E_1~0); 6062#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6441#L1207-1 assume !(1 == ~E_3~0); 6417#L1212-1 assume !(1 == ~E_4~0); 5654#L1217-1 assume !(1 == ~E_5~0); 5655#L1222-1 assume !(1 == ~E_6~0); 6414#L1227-1 assume !(1 == ~E_7~0); 6415#L1232-1 assume !(1 == ~E_8~0); 5528#L1237-1 assume !(1 == ~E_9~0); 5529#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 6478#L1247-1 assume { :end_inline_reset_delta_events } true; 5699#L1553-2 [2023-11-19 08:02:27,923 INFO L750 eck$LassoCheckResult]: Loop: 5699#L1553-2 assume !false; 5700#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5839#L999-1 assume !false; 5980#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5787#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5672#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6144#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6145#L854 assume !(0 != eval_~tmp~0#1); 6554#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6341#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6342#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6814#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6314#L1029-3 assume !(0 == ~T2_E~0); 6282#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6283#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6625#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5888#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5889#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5650#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5651#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6252#L1069-3 assume !(0 == ~T10_E~0); 6253#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6599#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6489#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6375#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6376#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6301#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6302#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6623#L1109-3 assume !(0 == ~E_7~0); 6611#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6612#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6875#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6882#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6848#L502-36 assume 1 == ~m_pc~0; 6626#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5516#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5517#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5946#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5947#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6225#L521-36 assume 1 == ~t1_pc~0; 6226#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6236#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6406#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6802#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6685#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6686#L540-36 assume 1 == ~t2_pc~0; 6850#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5606#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6018#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6687#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6351#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5525#L559-36 assume !(1 == ~t3_pc~0); 5526#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 5984#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6159#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6160#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 6499#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6739#L578-36 assume 1 == ~t4_pc~0; 6468#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6427#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6363#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6364#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6260#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6261#L597-36 assume !(1 == ~t5_pc~0); 6487#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 6840#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6784#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6442#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6063#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6064#L616-36 assume 1 == ~t6_pc~0; 6851#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5594#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5595#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6139#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6311#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6640#L635-36 assume !(1 == ~t7_pc~0); 6816#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 6697#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6698#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6760#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6297#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6298#L654-36 assume !(1 == ~t8_pc~0); 6820#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 6821#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6464#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6465#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6855#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5972#L673-36 assume 1 == ~t9_pc~0; 5973#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6339#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6202#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6203#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5535#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5536#L692-36 assume !(1 == ~t10_pc~0); 5750#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 5751#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6045#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5939#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 5940#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6310#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6461#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6822#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6823#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6388#L1157-3 assume !(1 == ~T4_E~0); 6389#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6693#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6806#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6296#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6194#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6195#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6209#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6028#L1197-3 assume !(1 == ~E_1~0); 6029#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6279#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6397#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6621#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5932#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5619#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5620#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6722#L1237-3 assume !(1 == ~E_9~0); 6723#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6885#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6771#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5770#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5771#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 6035#L1572 assume !(0 == start_simulation_~tmp~3#1); 6066#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6228#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5549#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5607#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 5608#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5520#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5521#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 6368#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 5699#L1553-2 [2023-11-19 08:02:27,924 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:27,924 INFO L85 PathProgramCache]: Analyzing trace with hash 1224781439, now seen corresponding path program 1 times [2023-11-19 08:02:27,925 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:27,925 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1269121863] [2023-11-19 08:02:27,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:27,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:27,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:28,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:28,046 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:28,047 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1269121863] [2023-11-19 08:02:28,047 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1269121863] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:28,047 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:28,047 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:28,048 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1287513725] [2023-11-19 08:02:28,048 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:28,048 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:28,049 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:28,049 INFO L85 PathProgramCache]: Analyzing trace with hash -1367151846, now seen corresponding path program 1 times [2023-11-19 08:02:28,049 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:28,050 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [546178038] [2023-11-19 08:02:28,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:28,050 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:28,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:28,184 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:28,184 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:28,185 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [546178038] [2023-11-19 08:02:28,185 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [546178038] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:28,185 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:28,185 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:28,186 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [546933111] [2023-11-19 08:02:28,186 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:28,186 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:28,186 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:28,187 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:02:28,187 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:02:28,187 INFO L87 Difference]: Start difference. First operand 1372 states and 2033 transitions. cyclomatic complexity: 662 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:28,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:28,223 INFO L93 Difference]: Finished difference Result 1372 states and 2032 transitions. [2023-11-19 08:02:28,223 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2032 transitions. [2023-11-19 08:02:28,236 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-19 08:02:28,248 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2032 transitions. [2023-11-19 08:02:28,249 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2023-11-19 08:02:28,251 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2023-11-19 08:02:28,251 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2032 transitions. [2023-11-19 08:02:28,253 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:28,254 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2032 transitions. [2023-11-19 08:02:28,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2032 transitions. [2023-11-19 08:02:28,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2023-11-19 08:02:28,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.4810495626822158) internal successors, (2032), 1371 states have internal predecessors, (2032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:28,290 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2032 transitions. [2023-11-19 08:02:28,291 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2032 transitions. [2023-11-19 08:02:28,291 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:02:28,294 INFO L428 stractBuchiCegarLoop]: Abstraction has 1372 states and 2032 transitions. [2023-11-19 08:02:28,295 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-19 08:02:28,295 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2032 transitions. [2023-11-19 08:02:28,305 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-19 08:02:28,305 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:28,305 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:28,310 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:28,311 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:28,312 INFO L748 eck$LassoCheckResult]: Stem: 8649#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 8650#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 9551#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9552#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9231#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 8919#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8920#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9201#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9371#L734-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9088#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9089#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8971#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8972#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9325#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9285#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9208#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9209#L1024 assume !(0 == ~M_E~0); 9465#L1024-2 assume !(0 == ~T1_E~0); 8645#L1029-1 assume !(0 == ~T2_E~0); 8646#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8748#L1039-1 assume !(0 == ~T4_E~0); 9575#L1044-1 assume !(0 == ~T5_E~0); 8991#L1049-1 assume !(0 == ~T6_E~0); 8992#L1054-1 assume !(0 == ~T7_E~0); 9230#L1059-1 assume !(0 == ~T8_E~0); 8695#L1064-1 assume !(0 == ~T9_E~0); 8696#L1069-1 assume !(0 == ~T10_E~0); 9434#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 9494#L1079-1 assume !(0 == ~E_1~0); 9467#L1084-1 assume !(0 == ~E_2~0); 9468#L1089-1 assume !(0 == ~E_3~0); 9512#L1094-1 assume !(0 == ~E_4~0); 9079#L1099-1 assume !(0 == ~E_5~0); 9080#L1104-1 assume !(0 == ~E_6~0); 9343#L1109-1 assume !(0 == ~E_7~0); 8862#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 8863#L1119-1 assume !(0 == ~E_9~0); 8929#L1124-1 assume !(0 == ~E_10~0); 8349#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8350#L502 assume 1 == ~m_pc~0; 9228#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8475#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8476#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9279#L1273 assume !(0 != activate_threads_~tmp~1#1); 9280#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9605#L521 assume !(1 == ~t1_pc~0); 9540#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8400#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8365#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8366#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 8386#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8387#L540 assume 1 == ~t2_pc~0; 9478#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9190#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8858#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8859#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 9536#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8673#L559 assume 1 == ~t3_pc~0; 8674#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8950#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8302#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8303#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 8493#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8494#L578 assume !(1 == ~t4_pc~0); 8614#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8613#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8433#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8434#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9262#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9263#L597 assume 1 == ~t5_pc~0; 9620#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8420#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8421#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9463#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 9210#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9211#L616 assume !(1 == ~t6_pc~0); 9225#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9224#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8834#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8835#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 9068#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9069#L635 assume 1 == ~t7_pc~0; 9265#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8389#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8764#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9508#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 9203#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9204#L654 assume !(1 == ~t8_pc~0); 9020#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 9021#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9395#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9396#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 9432#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8643#L673 assume 1 == ~t9_pc~0; 8644#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8340#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8915#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8916#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 9355#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9356#L692 assume !(1 == ~t10_pc~0); 9300#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 9299#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9071#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9072#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 9083#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9411#L1142 assume !(1 == ~M_E~0); 8554#L1142-2 assume !(1 == ~T1_E~0); 8555#L1147-1 assume !(1 == ~T2_E~0); 9400#L1152-1 assume !(1 == ~T3_E~0); 8957#L1157-1 assume !(1 == ~T4_E~0); 8958#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9107#L1167-1 assume !(1 == ~T6_E~0); 9108#L1172-1 assume !(1 == ~T7_E~0); 9529#L1177-1 assume !(1 == ~T8_E~0); 9248#L1182-1 assume !(1 == ~T9_E~0); 9249#L1187-1 assume !(1 == ~T10_E~0); 9348#L1192-1 assume !(1 == ~E_M~0); 8812#L1197-1 assume !(1 == ~E_1~0); 8813#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9192#L1207-1 assume !(1 == ~E_3~0); 9168#L1212-1 assume !(1 == ~E_4~0); 8405#L1217-1 assume !(1 == ~E_5~0); 8406#L1222-1 assume !(1 == ~E_6~0); 9165#L1227-1 assume !(1 == ~E_7~0); 9166#L1232-1 assume !(1 == ~E_8~0); 8279#L1237-1 assume !(1 == ~E_9~0); 8280#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 9229#L1247-1 assume { :end_inline_reset_delta_events } true; 8450#L1553-2 [2023-11-19 08:02:28,312 INFO L750 eck$LassoCheckResult]: Loop: 8450#L1553-2 assume !false; 8451#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8590#L999-1 assume !false; 8731#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8538#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8423#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8895#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8896#L854 assume !(0 != eval_~tmp~0#1); 9305#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9092#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9093#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9565#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9065#L1029-3 assume !(0 == ~T2_E~0); 9033#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9034#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9376#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8639#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8640#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8401#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8402#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9003#L1069-3 assume !(0 == ~T10_E~0); 9004#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9350#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9240#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9126#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9127#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9052#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9053#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9374#L1109-3 assume !(0 == ~E_7~0); 9362#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9363#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9626#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9633#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9599#L502-36 assume 1 == ~m_pc~0; 9377#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8267#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8268#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8697#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8698#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8976#L521-36 assume 1 == ~t1_pc~0; 8977#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8987#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9157#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9553#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9436#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9437#L540-36 assume 1 == ~t2_pc~0; 9601#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8357#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8769#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9438#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9102#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8276#L559-36 assume !(1 == ~t3_pc~0); 8277#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 8735#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8910#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8911#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 9250#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9490#L578-36 assume 1 == ~t4_pc~0; 9219#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9178#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9114#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9115#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9011#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9012#L597-36 assume !(1 == ~t5_pc~0); 9238#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 9591#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9535#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9193#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8814#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8815#L616-36 assume 1 == ~t6_pc~0; 9602#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8345#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8346#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8890#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9062#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9391#L635-36 assume 1 == ~t7_pc~0; 9566#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9448#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9449#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9511#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9048#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9049#L654-36 assume !(1 == ~t8_pc~0); 9571#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 9572#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9215#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9216#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9606#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8723#L673-36 assume 1 == ~t9_pc~0; 8724#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9090#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8953#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8954#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8286#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8287#L692-36 assume !(1 == ~t10_pc~0); 8501#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 8502#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8796#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8690#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 8691#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9061#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9212#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9573#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9574#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9139#L1157-3 assume !(1 == ~T4_E~0); 9140#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9444#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9557#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9047#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8947#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8948#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8960#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8779#L1197-3 assume !(1 == ~E_1~0); 8780#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9030#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9148#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9372#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8683#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8370#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8371#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9473#L1237-3 assume !(1 == ~E_9~0); 9474#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9636#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9522#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8521#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8522#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 8786#L1572 assume !(0 == start_simulation_~tmp~3#1); 8817#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8979#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8300#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8358#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 8359#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8271#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8272#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 9119#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 8450#L1553-2 [2023-11-19 08:02:28,316 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:28,317 INFO L85 PathProgramCache]: Analyzing trace with hash 736734333, now seen corresponding path program 1 times [2023-11-19 08:02:28,317 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:28,317 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [905670852] [2023-11-19 08:02:28,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:28,318 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:28,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:28,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:28,428 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:28,430 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [905670852] [2023-11-19 08:02:28,430 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [905670852] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:28,431 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:28,431 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:28,431 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [773471068] [2023-11-19 08:02:28,432 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:28,432 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:28,433 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:28,433 INFO L85 PathProgramCache]: Analyzing trace with hash -335821031, now seen corresponding path program 1 times [2023-11-19 08:02:28,433 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:28,439 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1435799339] [2023-11-19 08:02:28,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:28,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:28,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:28,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:28,545 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:28,546 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1435799339] [2023-11-19 08:02:28,546 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1435799339] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:28,546 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:28,547 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:28,547 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1229441245] [2023-11-19 08:02:28,547 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:28,548 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:28,548 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:28,549 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:02:28,549 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:02:28,549 INFO L87 Difference]: Start difference. First operand 1372 states and 2032 transitions. cyclomatic complexity: 661 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:28,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:28,588 INFO L93 Difference]: Finished difference Result 1372 states and 2031 transitions. [2023-11-19 08:02:28,588 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2031 transitions. [2023-11-19 08:02:28,600 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-19 08:02:28,611 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2031 transitions. [2023-11-19 08:02:28,612 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2023-11-19 08:02:28,613 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2023-11-19 08:02:28,614 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2031 transitions. [2023-11-19 08:02:28,616 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:28,616 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2031 transitions. [2023-11-19 08:02:28,619 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2031 transitions. [2023-11-19 08:02:28,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2023-11-19 08:02:28,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.4803206997084548) internal successors, (2031), 1371 states have internal predecessors, (2031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:28,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2031 transitions. [2023-11-19 08:02:28,650 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2031 transitions. [2023-11-19 08:02:28,650 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:02:28,653 INFO L428 stractBuchiCegarLoop]: Abstraction has 1372 states and 2031 transitions. [2023-11-19 08:02:28,657 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-19 08:02:28,657 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2031 transitions. [2023-11-19 08:02:28,666 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-19 08:02:28,666 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:28,666 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:28,669 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:28,669 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:28,670 INFO L748 eck$LassoCheckResult]: Stem: 11400#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 11401#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 12303#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12304#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11982#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 11671#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11672#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11952#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12122#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11840#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11841#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11722#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11723#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12076#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12036#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11960#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11961#L1024 assume !(0 == ~M_E~0); 12216#L1024-2 assume !(0 == ~T1_E~0); 11396#L1029-1 assume !(0 == ~T2_E~0); 11397#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11499#L1039-1 assume !(0 == ~T4_E~0); 12326#L1044-1 assume !(0 == ~T5_E~0); 11744#L1049-1 assume !(0 == ~T6_E~0); 11745#L1054-1 assume !(0 == ~T7_E~0); 11981#L1059-1 assume !(0 == ~T8_E~0); 11446#L1064-1 assume !(0 == ~T9_E~0); 11447#L1069-1 assume !(0 == ~T10_E~0); 12185#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 12245#L1079-1 assume !(0 == ~E_1~0); 12218#L1084-1 assume !(0 == ~E_2~0); 12219#L1089-1 assume !(0 == ~E_3~0); 12263#L1094-1 assume !(0 == ~E_4~0); 11830#L1099-1 assume !(0 == ~E_5~0); 11831#L1104-1 assume !(0 == ~E_6~0); 12094#L1109-1 assume !(0 == ~E_7~0); 11613#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 11614#L1119-1 assume !(0 == ~E_9~0); 11684#L1124-1 assume !(0 == ~E_10~0); 11100#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11101#L502 assume 1 == ~m_pc~0; 11979#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11226#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11227#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12032#L1273 assume !(0 != activate_threads_~tmp~1#1); 12033#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12356#L521 assume !(1 == ~t1_pc~0); 12291#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11151#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11116#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11117#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 11137#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11138#L540 assume 1 == ~t2_pc~0; 12229#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11941#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11609#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11610#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 12287#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11424#L559 assume 1 == ~t3_pc~0; 11425#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11702#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11053#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11054#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 11244#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11245#L578 assume !(1 == ~t4_pc~0); 11368#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11367#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11184#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11185#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12013#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12014#L597 assume 1 == ~t5_pc~0; 12372#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11171#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11172#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12214#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 11962#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11963#L616 assume !(1 == ~t6_pc~0); 11978#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11977#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11585#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11586#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 11820#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11821#L635 assume 1 == ~t7_pc~0; 12017#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11140#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11517#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12259#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 11954#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11955#L654 assume !(1 == ~t8_pc~0); 11771#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 11772#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12147#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12148#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 12183#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11394#L673 assume 1 == ~t9_pc~0; 11395#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11091#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11666#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11667#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 12106#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12107#L692 assume !(1 == ~t10_pc~0); 12051#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12050#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11822#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11823#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 11834#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12162#L1142 assume !(1 == ~M_E~0); 11305#L1142-2 assume !(1 == ~T1_E~0); 11306#L1147-1 assume !(1 == ~T2_E~0); 12151#L1152-1 assume !(1 == ~T3_E~0); 11708#L1157-1 assume !(1 == ~T4_E~0); 11709#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11858#L1167-1 assume !(1 == ~T6_E~0); 11859#L1172-1 assume !(1 == ~T7_E~0); 12281#L1177-1 assume !(1 == ~T8_E~0); 11999#L1182-1 assume !(1 == ~T9_E~0); 12000#L1187-1 assume !(1 == ~T10_E~0); 12099#L1192-1 assume !(1 == ~E_M~0); 11565#L1197-1 assume !(1 == ~E_1~0); 11566#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 11944#L1207-1 assume !(1 == ~E_3~0); 11919#L1212-1 assume !(1 == ~E_4~0); 11156#L1217-1 assume !(1 == ~E_5~0); 11157#L1222-1 assume !(1 == ~E_6~0); 11916#L1227-1 assume !(1 == ~E_7~0); 11917#L1232-1 assume !(1 == ~E_8~0); 11030#L1237-1 assume !(1 == ~E_9~0); 11031#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 11980#L1247-1 assume { :end_inline_reset_delta_events } true; 11201#L1553-2 [2023-11-19 08:02:28,671 INFO L750 eck$LassoCheckResult]: Loop: 11201#L1553-2 assume !false; 11202#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11341#L999-1 assume !false; 11482#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11289#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11174#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11646#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 11647#L854 assume !(0 != eval_~tmp~0#1); 12056#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11843#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11844#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12316#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11816#L1029-3 assume !(0 == ~T2_E~0); 11784#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11785#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12127#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11390#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11391#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11152#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11153#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11754#L1069-3 assume !(0 == ~T10_E~0); 11755#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12101#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11992#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11877#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11878#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11803#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11804#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12125#L1109-3 assume !(0 == ~E_7~0); 12113#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12114#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12377#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12384#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12350#L502-36 assume 1 == ~m_pc~0; 12128#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11018#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11019#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11448#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11449#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11727#L521-36 assume 1 == ~t1_pc~0; 11728#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11738#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11908#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12302#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12187#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12188#L540-36 assume 1 == ~t2_pc~0; 12352#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11103#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11520#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12189#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11853#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11024#L559-36 assume !(1 == ~t3_pc~0); 11025#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 11483#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11661#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11662#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 12001#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12241#L578-36 assume 1 == ~t4_pc~0; 11970#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11927#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11865#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11866#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11762#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11763#L597-36 assume !(1 == ~t5_pc~0); 11989#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 12342#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12286#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11943#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11563#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11564#L616-36 assume 1 == ~t6_pc~0; 12353#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11096#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11097#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11641#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11813#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12142#L635-36 assume 1 == ~t7_pc~0; 12317#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12199#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12200#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12262#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11799#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11800#L654-36 assume !(1 == ~t8_pc~0); 12322#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 12323#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11966#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11967#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12357#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11474#L673-36 assume 1 == ~t9_pc~0; 11475#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11839#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11704#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11705#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11037#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11038#L692-36 assume !(1 == ~t10_pc~0); 11252#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 11253#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11547#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11441#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 11442#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11810#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11959#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12324#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12325#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11890#L1157-3 assume !(1 == ~T4_E~0); 11891#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12195#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12308#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11798#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11696#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11697#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11711#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11530#L1197-3 assume !(1 == ~E_1~0); 11531#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11781#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11899#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12123#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11434#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11121#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11122#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12224#L1237-3 assume !(1 == ~E_9~0); 12225#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12387#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 12273#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11272#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11273#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 11537#L1572 assume !(0 == start_simulation_~tmp~3#1); 11568#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11730#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11051#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11109#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 11110#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11022#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11023#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 11870#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 11201#L1553-2 [2023-11-19 08:02:28,674 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:28,674 INFO L85 PathProgramCache]: Analyzing trace with hash 1829369535, now seen corresponding path program 1 times [2023-11-19 08:02:28,674 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:28,674 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1466037607] [2023-11-19 08:02:28,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:28,675 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:28,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:28,737 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:28,738 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:28,738 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1466037607] [2023-11-19 08:02:28,738 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1466037607] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:28,738 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:28,738 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:28,739 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [928245725] [2023-11-19 08:02:28,739 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:28,739 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:28,740 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:28,740 INFO L85 PathProgramCache]: Analyzing trace with hash -335821031, now seen corresponding path program 2 times [2023-11-19 08:02:28,740 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:28,741 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [995187863] [2023-11-19 08:02:28,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:28,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:28,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:28,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:28,819 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:28,819 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [995187863] [2023-11-19 08:02:28,819 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [995187863] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:28,819 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:28,819 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:28,820 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2013959066] [2023-11-19 08:02:28,820 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:28,820 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:28,820 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:28,821 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:02:28,821 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:02:28,821 INFO L87 Difference]: Start difference. First operand 1372 states and 2031 transitions. cyclomatic complexity: 660 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:28,864 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:28,864 INFO L93 Difference]: Finished difference Result 1372 states and 2030 transitions. [2023-11-19 08:02:28,865 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2030 transitions. [2023-11-19 08:02:28,876 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-19 08:02:28,887 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2030 transitions. [2023-11-19 08:02:28,887 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2023-11-19 08:02:28,889 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2023-11-19 08:02:28,889 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2030 transitions. [2023-11-19 08:02:28,892 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:28,893 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2030 transitions. [2023-11-19 08:02:28,896 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2030 transitions. [2023-11-19 08:02:28,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2023-11-19 08:02:28,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.4795918367346939) internal successors, (2030), 1371 states have internal predecessors, (2030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:28,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2030 transitions. [2023-11-19 08:02:28,926 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2030 transitions. [2023-11-19 08:02:28,926 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:02:28,929 INFO L428 stractBuchiCegarLoop]: Abstraction has 1372 states and 2030 transitions. [2023-11-19 08:02:28,929 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-19 08:02:28,930 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2030 transitions. [2023-11-19 08:02:28,938 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-19 08:02:28,938 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:28,939 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:28,941 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:28,941 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:28,942 INFO L748 eck$LassoCheckResult]: Stem: 14151#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 14152#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 15053#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15054#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14733#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 14421#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14422#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14703#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14873#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14590#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14591#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14473#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14474#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14827#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14787#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14710#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14711#L1024 assume !(0 == ~M_E~0); 14967#L1024-2 assume !(0 == ~T1_E~0); 14147#L1029-1 assume !(0 == ~T2_E~0); 14148#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14250#L1039-1 assume !(0 == ~T4_E~0); 15077#L1044-1 assume !(0 == ~T5_E~0); 14493#L1049-1 assume !(0 == ~T6_E~0); 14494#L1054-1 assume !(0 == ~T7_E~0); 14732#L1059-1 assume !(0 == ~T8_E~0); 14197#L1064-1 assume !(0 == ~T9_E~0); 14198#L1069-1 assume !(0 == ~T10_E~0); 14936#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 14996#L1079-1 assume !(0 == ~E_1~0); 14969#L1084-1 assume !(0 == ~E_2~0); 14970#L1089-1 assume !(0 == ~E_3~0); 15014#L1094-1 assume !(0 == ~E_4~0); 14581#L1099-1 assume !(0 == ~E_5~0); 14582#L1104-1 assume !(0 == ~E_6~0); 14845#L1109-1 assume !(0 == ~E_7~0); 14364#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 14365#L1119-1 assume !(0 == ~E_9~0); 14431#L1124-1 assume !(0 == ~E_10~0); 13851#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13852#L502 assume 1 == ~m_pc~0; 14730#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13977#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13978#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14781#L1273 assume !(0 != activate_threads_~tmp~1#1); 14782#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15107#L521 assume !(1 == ~t1_pc~0); 15042#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13902#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13867#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13868#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 13888#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13889#L540 assume 1 == ~t2_pc~0; 14980#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14692#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14360#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14361#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 15038#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14175#L559 assume 1 == ~t3_pc~0; 14176#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14452#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13804#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13805#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 13995#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13996#L578 assume !(1 == ~t4_pc~0); 14114#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14113#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13934#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13935#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14762#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14763#L597 assume 1 == ~t5_pc~0; 15122#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13922#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13923#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14965#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 14712#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14713#L616 assume !(1 == ~t6_pc~0); 14727#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14726#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14336#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14337#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 14570#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14571#L635 assume 1 == ~t7_pc~0; 14767#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13891#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14266#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15010#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 14705#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14706#L654 assume !(1 == ~t8_pc~0); 14522#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14523#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14895#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14896#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 14934#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14145#L673 assume 1 == ~t9_pc~0; 14146#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13842#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14415#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14416#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 14857#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14858#L692 assume !(1 == ~t10_pc~0); 14802#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14801#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14573#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14574#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 14585#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14913#L1142 assume !(1 == ~M_E~0); 14056#L1142-2 assume !(1 == ~T1_E~0); 14057#L1147-1 assume !(1 == ~T2_E~0); 14902#L1152-1 assume !(1 == ~T3_E~0); 14459#L1157-1 assume !(1 == ~T4_E~0); 14460#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14609#L1167-1 assume !(1 == ~T6_E~0); 14610#L1172-1 assume !(1 == ~T7_E~0); 15031#L1177-1 assume !(1 == ~T8_E~0); 14750#L1182-1 assume !(1 == ~T9_E~0); 14751#L1187-1 assume !(1 == ~T10_E~0); 14850#L1192-1 assume !(1 == ~E_M~0); 14314#L1197-1 assume !(1 == ~E_1~0); 14315#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 14694#L1207-1 assume !(1 == ~E_3~0); 14670#L1212-1 assume !(1 == ~E_4~0); 13907#L1217-1 assume !(1 == ~E_5~0); 13908#L1222-1 assume !(1 == ~E_6~0); 14667#L1227-1 assume !(1 == ~E_7~0); 14668#L1232-1 assume !(1 == ~E_8~0); 13781#L1237-1 assume !(1 == ~E_9~0); 13782#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 14731#L1247-1 assume { :end_inline_reset_delta_events } true; 13952#L1553-2 [2023-11-19 08:02:28,942 INFO L750 eck$LassoCheckResult]: Loop: 13952#L1553-2 assume !false; 13953#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14092#L999-1 assume !false; 14233#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14040#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13925#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14397#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14398#L854 assume !(0 != eval_~tmp~0#1); 14807#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14594#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14595#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15067#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14567#L1029-3 assume !(0 == ~T2_E~0); 14535#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14536#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14878#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14141#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14142#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13903#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13904#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14505#L1069-3 assume !(0 == ~T10_E~0); 14506#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14852#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14742#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14628#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14629#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14554#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14555#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14876#L1109-3 assume !(0 == ~E_7~0); 14864#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14865#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15128#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15135#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15101#L502-36 assume !(1 == ~m_pc~0); 14284#L502-38 is_master_triggered_~__retres1~0#1 := 0; 13769#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13770#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14199#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14200#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14478#L521-36 assume !(1 == ~t1_pc~0); 14480#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 14489#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14659#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15055#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14938#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14939#L540-36 assume !(1 == ~t2_pc~0); 13858#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 13859#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14271#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14940#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14604#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13778#L559-36 assume !(1 == ~t3_pc~0); 13779#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 14237#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14412#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14413#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 14752#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14992#L578-36 assume 1 == ~t4_pc~0; 14721#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14680#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14616#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14617#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14513#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14514#L597-36 assume !(1 == ~t5_pc~0); 14740#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 15093#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15037#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14695#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14316#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14317#L616-36 assume 1 == ~t6_pc~0; 15104#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13847#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13848#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14392#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14564#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14893#L635-36 assume 1 == ~t7_pc~0; 15068#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14950#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14951#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15013#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14550#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14551#L654-36 assume !(1 == ~t8_pc~0); 15073#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 15074#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14717#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14718#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15108#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14225#L673-36 assume 1 == ~t9_pc~0; 14226#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14592#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14455#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14456#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13788#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13789#L692-36 assume !(1 == ~t10_pc~0); 14003#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 14004#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14298#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14192#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 14193#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14563#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14714#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15075#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15076#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14641#L1157-3 assume !(1 == ~T4_E~0); 14642#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14946#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15059#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14549#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14447#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14448#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14462#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14281#L1197-3 assume !(1 == ~E_1~0); 14282#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14532#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14650#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14874#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14185#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13872#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13873#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14975#L1237-3 assume !(1 == ~E_9~0); 14976#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15138#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 15024#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 14023#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14024#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 14288#L1572 assume !(0 == start_simulation_~tmp~3#1); 14319#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14481#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13802#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13860#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 13861#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13773#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13774#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 14621#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 13952#L1553-2 [2023-11-19 08:02:28,944 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:28,944 INFO L85 PathProgramCache]: Analyzing trace with hash -1183425475, now seen corresponding path program 1 times [2023-11-19 08:02:28,944 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:28,944 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1633882577] [2023-11-19 08:02:28,944 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:28,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:28,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:29,043 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:29,043 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:29,043 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1633882577] [2023-11-19 08:02:29,044 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1633882577] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:29,044 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:29,044 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:29,044 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1419216345] [2023-11-19 08:02:29,045 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:29,045 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:29,046 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:29,046 INFO L85 PathProgramCache]: Analyzing trace with hash 1415396764, now seen corresponding path program 1 times [2023-11-19 08:02:29,052 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:29,052 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [812318416] [2023-11-19 08:02:29,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:29,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:29,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:29,151 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:29,151 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:29,152 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [812318416] [2023-11-19 08:02:29,152 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [812318416] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:29,152 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:29,153 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:29,153 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1816037919] [2023-11-19 08:02:29,153 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:29,154 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:29,154 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:29,155 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:02:29,155 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:02:29,155 INFO L87 Difference]: Start difference. First operand 1372 states and 2030 transitions. cyclomatic complexity: 659 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:29,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:29,207 INFO L93 Difference]: Finished difference Result 1372 states and 2029 transitions. [2023-11-19 08:02:29,207 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2029 transitions. [2023-11-19 08:02:29,222 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-19 08:02:29,236 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2029 transitions. [2023-11-19 08:02:29,236 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2023-11-19 08:02:29,238 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2023-11-19 08:02:29,238 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2029 transitions. [2023-11-19 08:02:29,241 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:29,241 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2029 transitions. [2023-11-19 08:02:29,245 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2029 transitions. [2023-11-19 08:02:29,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2023-11-19 08:02:29,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.478862973760933) internal successors, (2029), 1371 states have internal predecessors, (2029), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:29,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2029 transitions. [2023-11-19 08:02:29,284 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2029 transitions. [2023-11-19 08:02:29,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:02:29,285 INFO L428 stractBuchiCegarLoop]: Abstraction has 1372 states and 2029 transitions. [2023-11-19 08:02:29,285 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-19 08:02:29,285 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2029 transitions. [2023-11-19 08:02:29,295 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-19 08:02:29,295 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:29,295 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:29,298 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:29,299 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:29,299 INFO L748 eck$LassoCheckResult]: Stem: 16902#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 16903#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 17804#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17805#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17484#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 17172#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17173#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17454#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17624#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17341#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17342#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17224#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17225#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17578#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17538#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17461#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17462#L1024 assume !(0 == ~M_E~0); 17718#L1024-2 assume !(0 == ~T1_E~0); 16898#L1029-1 assume !(0 == ~T2_E~0); 16899#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17001#L1039-1 assume !(0 == ~T4_E~0); 17828#L1044-1 assume !(0 == ~T5_E~0); 17244#L1049-1 assume !(0 == ~T6_E~0); 17245#L1054-1 assume !(0 == ~T7_E~0); 17483#L1059-1 assume !(0 == ~T8_E~0); 16948#L1064-1 assume !(0 == ~T9_E~0); 16949#L1069-1 assume !(0 == ~T10_E~0); 17687#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 17747#L1079-1 assume !(0 == ~E_1~0); 17720#L1084-1 assume !(0 == ~E_2~0); 17721#L1089-1 assume !(0 == ~E_3~0); 17765#L1094-1 assume !(0 == ~E_4~0); 17332#L1099-1 assume !(0 == ~E_5~0); 17333#L1104-1 assume !(0 == ~E_6~0); 17596#L1109-1 assume !(0 == ~E_7~0); 17115#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 17116#L1119-1 assume !(0 == ~E_9~0); 17182#L1124-1 assume !(0 == ~E_10~0); 16602#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16603#L502 assume 1 == ~m_pc~0; 17481#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16728#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16729#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17532#L1273 assume !(0 != activate_threads_~tmp~1#1); 17533#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17858#L521 assume !(1 == ~t1_pc~0); 17793#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16653#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16618#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16619#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 16639#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16640#L540 assume 1 == ~t2_pc~0; 17731#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17443#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17111#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17112#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 17789#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16926#L559 assume 1 == ~t3_pc~0; 16927#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17203#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16555#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16556#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 16746#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16747#L578 assume !(1 == ~t4_pc~0); 16868#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16867#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16686#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16687#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17515#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17516#L597 assume 1 == ~t5_pc~0; 17873#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16673#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16674#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17716#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 17463#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17464#L616 assume !(1 == ~t6_pc~0); 17478#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17477#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17087#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17088#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 17321#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17322#L635 assume 1 == ~t7_pc~0; 17518#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16642#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17017#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17761#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 17456#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17457#L654 assume !(1 == ~t8_pc~0); 17273#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17274#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17648#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17649#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 17685#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16896#L673 assume 1 == ~t9_pc~0; 16897#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16593#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17168#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17169#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 17608#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17609#L692 assume !(1 == ~t10_pc~0); 17553#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 17552#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17324#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17325#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 17336#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17664#L1142 assume !(1 == ~M_E~0); 16807#L1142-2 assume !(1 == ~T1_E~0); 16808#L1147-1 assume !(1 == ~T2_E~0); 17653#L1152-1 assume !(1 == ~T3_E~0); 17210#L1157-1 assume !(1 == ~T4_E~0); 17211#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17360#L1167-1 assume !(1 == ~T6_E~0); 17361#L1172-1 assume !(1 == ~T7_E~0); 17782#L1177-1 assume !(1 == ~T8_E~0); 17501#L1182-1 assume !(1 == ~T9_E~0); 17502#L1187-1 assume !(1 == ~T10_E~0); 17601#L1192-1 assume !(1 == ~E_M~0); 17065#L1197-1 assume !(1 == ~E_1~0); 17066#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 17445#L1207-1 assume !(1 == ~E_3~0); 17421#L1212-1 assume !(1 == ~E_4~0); 16658#L1217-1 assume !(1 == ~E_5~0); 16659#L1222-1 assume !(1 == ~E_6~0); 17418#L1227-1 assume !(1 == ~E_7~0); 17419#L1232-1 assume !(1 == ~E_8~0); 16532#L1237-1 assume !(1 == ~E_9~0); 16533#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 17482#L1247-1 assume { :end_inline_reset_delta_events } true; 16703#L1553-2 [2023-11-19 08:02:29,300 INFO L750 eck$LassoCheckResult]: Loop: 16703#L1553-2 assume !false; 16704#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16843#L999-1 assume !false; 16984#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16791#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16676#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 17148#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17149#L854 assume !(0 != eval_~tmp~0#1); 17558#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17345#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17346#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17818#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17318#L1029-3 assume !(0 == ~T2_E~0); 17286#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17287#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17629#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16892#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16893#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16654#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16655#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17256#L1069-3 assume !(0 == ~T10_E~0); 17257#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17603#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17493#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17379#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17380#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17305#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17306#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17627#L1109-3 assume !(0 == ~E_7~0); 17615#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17616#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17879#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17886#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17852#L502-36 assume !(1 == ~m_pc~0); 17035#L502-38 is_master_triggered_~__retres1~0#1 := 0; 16520#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16521#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16950#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16951#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17229#L521-36 assume 1 == ~t1_pc~0; 17230#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17240#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17410#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17806#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17689#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17690#L540-36 assume !(1 == ~t2_pc~0); 16609#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 16610#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17022#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17691#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17355#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16529#L559-36 assume !(1 == ~t3_pc~0); 16530#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 16988#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17163#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17164#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 17503#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17743#L578-36 assume 1 == ~t4_pc~0; 17473#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17431#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17367#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17368#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17264#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17265#L597-36 assume !(1 == ~t5_pc~0); 17491#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 17844#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17788#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17446#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17067#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17068#L616-36 assume !(1 == ~t6_pc~0); 17814#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 16598#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16599#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17143#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17315#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17644#L635-36 assume 1 == ~t7_pc~0; 17819#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17701#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17702#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17764#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17301#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17302#L654-36 assume !(1 == ~t8_pc~0); 17824#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 17825#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17468#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17469#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17859#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16976#L673-36 assume 1 == ~t9_pc~0; 16977#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17343#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17206#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17207#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16539#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16540#L692-36 assume !(1 == ~t10_pc~0); 16754#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 16755#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17049#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16943#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 16944#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17314#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17465#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17826#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17827#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17392#L1157-3 assume !(1 == ~T4_E~0); 17393#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17697#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17811#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17300#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17200#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17201#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17213#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17032#L1197-3 assume !(1 == ~E_1~0); 17033#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17283#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17401#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17626#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16936#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16623#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16624#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17726#L1237-3 assume !(1 == ~E_9~0); 17727#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17889#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17775#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16774#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16775#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 17039#L1572 assume !(0 == start_simulation_~tmp~3#1); 17070#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17232#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16553#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16611#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 16612#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16524#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16525#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 17372#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 16703#L1553-2 [2023-11-19 08:02:29,301 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:29,301 INFO L85 PathProgramCache]: Analyzing trace with hash 659050239, now seen corresponding path program 1 times [2023-11-19 08:02:29,302 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:29,302 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [598245038] [2023-11-19 08:02:29,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:29,302 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:29,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:29,366 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:29,366 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:29,367 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [598245038] [2023-11-19 08:02:29,367 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [598245038] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:29,367 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:29,367 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:29,368 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1015139506] [2023-11-19 08:02:29,368 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:29,368 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:29,369 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:29,369 INFO L85 PathProgramCache]: Analyzing trace with hash 1920116060, now seen corresponding path program 1 times [2023-11-19 08:02:29,369 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:29,370 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [859783761] [2023-11-19 08:02:29,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:29,370 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:29,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:29,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:29,443 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:29,443 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [859783761] [2023-11-19 08:02:29,443 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [859783761] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:29,443 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:29,444 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:29,444 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [673160982] [2023-11-19 08:02:29,444 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:29,444 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:29,445 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:29,445 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:02:29,445 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:02:29,445 INFO L87 Difference]: Start difference. First operand 1372 states and 2029 transitions. cyclomatic complexity: 658 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:29,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:29,477 INFO L93 Difference]: Finished difference Result 1372 states and 2028 transitions. [2023-11-19 08:02:29,478 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2028 transitions. [2023-11-19 08:02:29,486 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-19 08:02:29,496 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2028 transitions. [2023-11-19 08:02:29,496 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2023-11-19 08:02:29,498 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2023-11-19 08:02:29,498 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2028 transitions. [2023-11-19 08:02:29,500 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:29,500 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2028 transitions. [2023-11-19 08:02:29,503 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2028 transitions. [2023-11-19 08:02:29,523 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2023-11-19 08:02:29,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.478134110787172) internal successors, (2028), 1371 states have internal predecessors, (2028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:29,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2028 transitions. [2023-11-19 08:02:29,532 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2028 transitions. [2023-11-19 08:02:29,533 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:02:29,534 INFO L428 stractBuchiCegarLoop]: Abstraction has 1372 states and 2028 transitions. [2023-11-19 08:02:29,534 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-19 08:02:29,534 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2028 transitions. [2023-11-19 08:02:29,540 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-19 08:02:29,541 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:29,541 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:29,543 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:29,543 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:29,544 INFO L748 eck$LassoCheckResult]: Stem: 19653#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 19654#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 20556#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20557#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20235#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 19924#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19925#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20206#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20375#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20093#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20094#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19978#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19979#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20329#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20289#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20213#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20214#L1024 assume !(0 == ~M_E~0); 20469#L1024-2 assume !(0 == ~T1_E~0); 19649#L1029-1 assume !(0 == ~T2_E~0); 19650#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19752#L1039-1 assume !(0 == ~T4_E~0); 20579#L1044-1 assume !(0 == ~T5_E~0); 19997#L1049-1 assume !(0 == ~T6_E~0); 19998#L1054-1 assume !(0 == ~T7_E~0); 20234#L1059-1 assume !(0 == ~T8_E~0); 19699#L1064-1 assume !(0 == ~T9_E~0); 19700#L1069-1 assume !(0 == ~T10_E~0); 20438#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 20498#L1079-1 assume !(0 == ~E_1~0); 20471#L1084-1 assume !(0 == ~E_2~0); 20472#L1089-1 assume !(0 == ~E_3~0); 20516#L1094-1 assume !(0 == ~E_4~0); 20083#L1099-1 assume !(0 == ~E_5~0); 20084#L1104-1 assume !(0 == ~E_6~0); 20347#L1109-1 assume !(0 == ~E_7~0); 19866#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 19867#L1119-1 assume !(0 == ~E_9~0); 19937#L1124-1 assume !(0 == ~E_10~0); 19353#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19354#L502 assume 1 == ~m_pc~0; 20232#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19479#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19480#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20285#L1273 assume !(0 != activate_threads_~tmp~1#1); 20286#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20609#L521 assume !(1 == ~t1_pc~0); 20544#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19404#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19369#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19370#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 19390#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19391#L540 assume 1 == ~t2_pc~0; 20482#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20194#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19864#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19865#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 20540#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19677#L559 assume 1 == ~t3_pc~0; 19678#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19955#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19306#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19307#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 19497#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19498#L578 assume !(1 == ~t4_pc~0); 19621#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19620#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19437#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19438#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20266#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20267#L597 assume 1 == ~t5_pc~0; 20625#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19424#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19425#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20467#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 20215#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20216#L616 assume !(1 == ~t6_pc~0); 20231#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 20230#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19838#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19839#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 20073#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20074#L635 assume 1 == ~t7_pc~0; 20270#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19393#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19770#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20512#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 20207#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20208#L654 assume !(1 == ~t8_pc~0); 20024#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 20025#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20400#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20401#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 20436#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19647#L673 assume 1 == ~t9_pc~0; 19648#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19344#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19919#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19920#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 20359#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20360#L692 assume !(1 == ~t10_pc~0); 20304#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20303#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20075#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20076#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 20087#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20415#L1142 assume !(1 == ~M_E~0); 19558#L1142-2 assume !(1 == ~T1_E~0); 19559#L1147-1 assume !(1 == ~T2_E~0); 20404#L1152-1 assume !(1 == ~T3_E~0); 19961#L1157-1 assume !(1 == ~T4_E~0); 19962#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20111#L1167-1 assume !(1 == ~T6_E~0); 20112#L1172-1 assume !(1 == ~T7_E~0); 20534#L1177-1 assume !(1 == ~T8_E~0); 20252#L1182-1 assume !(1 == ~T9_E~0); 20253#L1187-1 assume !(1 == ~T10_E~0); 20352#L1192-1 assume !(1 == ~E_M~0); 19818#L1197-1 assume !(1 == ~E_1~0); 19819#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 20197#L1207-1 assume !(1 == ~E_3~0); 20172#L1212-1 assume !(1 == ~E_4~0); 19409#L1217-1 assume !(1 == ~E_5~0); 19410#L1222-1 assume !(1 == ~E_6~0); 20169#L1227-1 assume !(1 == ~E_7~0); 20170#L1232-1 assume !(1 == ~E_8~0); 19283#L1237-1 assume !(1 == ~E_9~0); 19284#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 20233#L1247-1 assume { :end_inline_reset_delta_events } true; 19454#L1553-2 [2023-11-19 08:02:29,545 INFO L750 eck$LassoCheckResult]: Loop: 19454#L1553-2 assume !false; 19455#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19594#L999-1 assume !false; 19735#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19542#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19427#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19899#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19900#L854 assume !(0 != eval_~tmp~0#1); 20309#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20096#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20097#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20569#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20069#L1029-3 assume !(0 == ~T2_E~0); 20037#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20038#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20380#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19643#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19644#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19405#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19406#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 20007#L1069-3 assume !(0 == ~T10_E~0); 20008#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20354#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20245#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20130#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20131#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20056#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20057#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20378#L1109-3 assume !(0 == ~E_7~0); 20366#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20367#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 20630#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20637#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20603#L502-36 assume !(1 == ~m_pc~0); 19786#L502-38 is_master_triggered_~__retres1~0#1 := 0; 19271#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19272#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19701#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19702#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19975#L521-36 assume 1 == ~t1_pc~0; 19976#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19991#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20161#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20555#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20440#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20441#L540-36 assume 1 == ~t2_pc~0; 20605#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19358#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19773#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20442#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20106#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19277#L559-36 assume !(1 == ~t3_pc~0); 19278#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 19739#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19914#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19915#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 20254#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20494#L578-36 assume !(1 == ~t4_pc~0); 20179#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 20180#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20118#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20119#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20015#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20016#L597-36 assume !(1 == ~t5_pc~0); 20242#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 20595#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20539#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20196#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19816#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19817#L616-36 assume !(1 == ~t6_pc~0); 20565#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 19349#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19350#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19894#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20066#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20395#L635-36 assume 1 == ~t7_pc~0; 20570#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20452#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20453#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20515#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20052#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20053#L654-36 assume 1 == ~t8_pc~0; 20633#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20576#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20219#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20220#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20610#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19727#L673-36 assume 1 == ~t9_pc~0; 19728#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20092#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19957#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19958#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19290#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19291#L692-36 assume !(1 == ~t10_pc~0); 19505#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 19506#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19800#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19694#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 19695#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20063#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20212#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20577#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20578#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20143#L1157-3 assume !(1 == ~T4_E~0); 20144#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20448#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20561#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20051#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19949#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19950#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19964#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19783#L1197-3 assume !(1 == ~E_1~0); 19784#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20034#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20152#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20376#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19687#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19374#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19375#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20477#L1237-3 assume !(1 == ~E_9~0); 20478#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20640#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 20526#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19525#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19526#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 19790#L1572 assume !(0 == start_simulation_~tmp~3#1); 19821#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19983#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19304#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19362#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 19363#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19275#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19276#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 20123#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 19454#L1553-2 [2023-11-19 08:02:29,546 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:29,546 INFO L85 PathProgramCache]: Analyzing trace with hash -1913914371, now seen corresponding path program 1 times [2023-11-19 08:02:29,546 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:29,546 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1933217924] [2023-11-19 08:02:29,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:29,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:29,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:29,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:29,615 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:29,616 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1933217924] [2023-11-19 08:02:29,617 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1933217924] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:29,617 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:29,617 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:29,617 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [644387119] [2023-11-19 08:02:29,617 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:29,618 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:29,622 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:29,622 INFO L85 PathProgramCache]: Analyzing trace with hash 1738262043, now seen corresponding path program 1 times [2023-11-19 08:02:29,623 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:29,625 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514812050] [2023-11-19 08:02:29,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:29,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:29,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:29,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:29,734 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:29,734 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1514812050] [2023-11-19 08:02:29,735 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1514812050] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:29,735 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:29,735 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:29,735 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [630328120] [2023-11-19 08:02:29,735 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:29,736 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:29,736 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:29,736 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:02:29,736 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:02:29,737 INFO L87 Difference]: Start difference. First operand 1372 states and 2028 transitions. cyclomatic complexity: 657 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:29,776 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:29,777 INFO L93 Difference]: Finished difference Result 1372 states and 2027 transitions. [2023-11-19 08:02:29,777 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2027 transitions. [2023-11-19 08:02:29,786 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-19 08:02:29,798 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2027 transitions. [2023-11-19 08:02:29,799 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2023-11-19 08:02:29,801 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2023-11-19 08:02:29,801 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2027 transitions. [2023-11-19 08:02:29,804 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:29,804 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2027 transitions. [2023-11-19 08:02:29,807 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2027 transitions. [2023-11-19 08:02:29,833 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2023-11-19 08:02:29,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.477405247813411) internal successors, (2027), 1371 states have internal predecessors, (2027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:29,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2027 transitions. [2023-11-19 08:02:29,844 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2027 transitions. [2023-11-19 08:02:29,845 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:02:29,847 INFO L428 stractBuchiCegarLoop]: Abstraction has 1372 states and 2027 transitions. [2023-11-19 08:02:29,847 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-19 08:02:29,847 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2027 transitions. [2023-11-19 08:02:29,855 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-19 08:02:29,855 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:29,855 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:29,858 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:29,858 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:29,859 INFO L748 eck$LassoCheckResult]: Stem: 22404#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 22405#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 23306#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23307#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22986#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 22674#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22675#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22956#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23126#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22843#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22844#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22726#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22727#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 23080#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 23040#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22963#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22964#L1024 assume !(0 == ~M_E~0); 23220#L1024-2 assume !(0 == ~T1_E~0); 22400#L1029-1 assume !(0 == ~T2_E~0); 22401#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22503#L1039-1 assume !(0 == ~T4_E~0); 23330#L1044-1 assume !(0 == ~T5_E~0); 22746#L1049-1 assume !(0 == ~T6_E~0); 22747#L1054-1 assume !(0 == ~T7_E~0); 22985#L1059-1 assume !(0 == ~T8_E~0); 22450#L1064-1 assume !(0 == ~T9_E~0); 22451#L1069-1 assume !(0 == ~T10_E~0); 23189#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 23249#L1079-1 assume !(0 == ~E_1~0); 23222#L1084-1 assume !(0 == ~E_2~0); 23223#L1089-1 assume !(0 == ~E_3~0); 23267#L1094-1 assume !(0 == ~E_4~0); 22834#L1099-1 assume !(0 == ~E_5~0); 22835#L1104-1 assume !(0 == ~E_6~0); 23098#L1109-1 assume !(0 == ~E_7~0); 22617#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 22618#L1119-1 assume !(0 == ~E_9~0); 22684#L1124-1 assume !(0 == ~E_10~0); 22104#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22105#L502 assume 1 == ~m_pc~0; 22983#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22230#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22231#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23034#L1273 assume !(0 != activate_threads_~tmp~1#1); 23035#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23360#L521 assume !(1 == ~t1_pc~0); 23295#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22155#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22120#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22121#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 22141#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22142#L540 assume 1 == ~t2_pc~0; 23233#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22945#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22613#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22614#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 23291#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22428#L559 assume 1 == ~t3_pc~0; 22429#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22705#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22057#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22058#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 22248#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22249#L578 assume !(1 == ~t4_pc~0); 22367#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22366#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22187#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22188#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23015#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23016#L597 assume 1 == ~t5_pc~0; 23375#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22175#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22176#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23218#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 22965#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22966#L616 assume !(1 == ~t6_pc~0); 22980#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22979#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22589#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22590#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 22823#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22824#L635 assume 1 == ~t7_pc~0; 23020#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22144#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22519#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23263#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 22958#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22959#L654 assume !(1 == ~t8_pc~0); 22775#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22776#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23148#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23149#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 23187#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22398#L673 assume 1 == ~t9_pc~0; 22399#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22095#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22668#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22669#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 23110#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23111#L692 assume !(1 == ~t10_pc~0); 23055#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 23054#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22826#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22827#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 22838#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23166#L1142 assume !(1 == ~M_E~0); 22309#L1142-2 assume !(1 == ~T1_E~0); 22310#L1147-1 assume !(1 == ~T2_E~0); 23155#L1152-1 assume !(1 == ~T3_E~0); 22712#L1157-1 assume !(1 == ~T4_E~0); 22713#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22862#L1167-1 assume !(1 == ~T6_E~0); 22863#L1172-1 assume !(1 == ~T7_E~0); 23284#L1177-1 assume !(1 == ~T8_E~0); 23003#L1182-1 assume !(1 == ~T9_E~0); 23004#L1187-1 assume !(1 == ~T10_E~0); 23103#L1192-1 assume !(1 == ~E_M~0); 22567#L1197-1 assume !(1 == ~E_1~0); 22568#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22947#L1207-1 assume !(1 == ~E_3~0); 22923#L1212-1 assume !(1 == ~E_4~0); 22160#L1217-1 assume !(1 == ~E_5~0); 22161#L1222-1 assume !(1 == ~E_6~0); 22920#L1227-1 assume !(1 == ~E_7~0); 22921#L1232-1 assume !(1 == ~E_8~0); 22034#L1237-1 assume !(1 == ~E_9~0); 22035#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 22984#L1247-1 assume { :end_inline_reset_delta_events } true; 22205#L1553-2 [2023-11-19 08:02:29,860 INFO L750 eck$LassoCheckResult]: Loop: 22205#L1553-2 assume !false; 22206#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22345#L999-1 assume !false; 22486#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22293#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22178#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22650#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22651#L854 assume !(0 != eval_~tmp~0#1); 23060#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22847#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22848#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23320#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22820#L1029-3 assume !(0 == ~T2_E~0); 22788#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22789#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23131#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22394#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22395#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22156#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22157#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22758#L1069-3 assume !(0 == ~T10_E~0); 22759#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23105#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22995#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22881#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22882#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22807#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22808#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23129#L1109-3 assume !(0 == ~E_7~0); 23117#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23118#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23381#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23388#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23354#L502-36 assume !(1 == ~m_pc~0); 22537#L502-38 is_master_triggered_~__retres1~0#1 := 0; 22022#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22023#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22452#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22453#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22731#L521-36 assume 1 == ~t1_pc~0; 22732#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22742#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22912#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23308#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23191#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23192#L540-36 assume 1 == ~t2_pc~0; 23356#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22112#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22524#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23193#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22857#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22031#L559-36 assume !(1 == ~t3_pc~0); 22032#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 22490#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22665#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22666#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 23005#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23245#L578-36 assume !(1 == ~t4_pc~0); 22932#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 22933#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22869#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22870#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22766#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22767#L597-36 assume !(1 == ~t5_pc~0); 22993#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 23346#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23290#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22948#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22569#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22570#L616-36 assume !(1 == ~t6_pc~0); 23316#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 22100#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22101#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22645#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22817#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23146#L635-36 assume 1 == ~t7_pc~0; 23321#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23203#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23204#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23266#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22803#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22804#L654-36 assume 1 == ~t8_pc~0; 23384#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 23327#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22970#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22971#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 23361#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22478#L673-36 assume !(1 == ~t9_pc~0); 22480#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 22845#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22708#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22709#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22041#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22042#L692-36 assume !(1 == ~t10_pc~0); 22256#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 22257#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22551#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22445#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 22446#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22816#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22967#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23328#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23329#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22894#L1157-3 assume !(1 == ~T4_E~0); 22895#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23199#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23312#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22802#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22700#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22701#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22715#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22534#L1197-3 assume !(1 == ~E_1~0); 22535#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22785#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22903#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23127#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22438#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22125#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22126#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23228#L1237-3 assume !(1 == ~E_9~0); 23229#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 23391#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 23277#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22276#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22277#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 22541#L1572 assume !(0 == start_simulation_~tmp~3#1); 22572#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22734#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22055#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22113#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 22114#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22026#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22027#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 22874#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 22205#L1553-2 [2023-11-19 08:02:29,860 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:29,861 INFO L85 PathProgramCache]: Analyzing trace with hash -1581271233, now seen corresponding path program 1 times [2023-11-19 08:02:29,861 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:29,861 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [700565310] [2023-11-19 08:02:29,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:29,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:29,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:29,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:29,927 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:29,928 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [700565310] [2023-11-19 08:02:29,928 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [700565310] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:29,928 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:29,928 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:29,929 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1202069663] [2023-11-19 08:02:29,929 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:29,929 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:29,930 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:29,930 INFO L85 PathProgramCache]: Analyzing trace with hash -155180132, now seen corresponding path program 1 times [2023-11-19 08:02:29,930 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:29,931 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1137602538] [2023-11-19 08:02:29,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:29,931 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:29,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:30,004 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:30,004 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:30,005 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1137602538] [2023-11-19 08:02:30,005 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1137602538] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:30,005 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:30,005 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:30,006 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [411508777] [2023-11-19 08:02:30,006 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:30,006 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:30,007 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:30,007 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:02:30,007 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:02:30,007 INFO L87 Difference]: Start difference. First operand 1372 states and 2027 transitions. cyclomatic complexity: 656 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:30,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:30,046 INFO L93 Difference]: Finished difference Result 1372 states and 2026 transitions. [2023-11-19 08:02:30,047 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2026 transitions. [2023-11-19 08:02:30,055 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-19 08:02:30,067 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2026 transitions. [2023-11-19 08:02:30,067 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2023-11-19 08:02:30,072 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2023-11-19 08:02:30,072 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2026 transitions. [2023-11-19 08:02:30,074 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:30,075 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2026 transitions. [2023-11-19 08:02:30,078 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2026 transitions. [2023-11-19 08:02:30,101 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2023-11-19 08:02:30,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.4766763848396502) internal successors, (2026), 1371 states have internal predecessors, (2026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:30,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2026 transitions. [2023-11-19 08:02:30,111 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2026 transitions. [2023-11-19 08:02:30,111 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:02:30,113 INFO L428 stractBuchiCegarLoop]: Abstraction has 1372 states and 2026 transitions. [2023-11-19 08:02:30,113 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-19 08:02:30,113 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2026 transitions. [2023-11-19 08:02:30,120 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-19 08:02:30,120 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:30,120 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:30,123 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:30,123 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:30,124 INFO L748 eck$LassoCheckResult]: Stem: 25155#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 25156#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 26057#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26058#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25737#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 25425#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25426#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25707#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25877#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25595#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25596#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25477#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 25478#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 25831#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25791#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 25715#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25716#L1024 assume !(0 == ~M_E~0); 25971#L1024-2 assume !(0 == ~T1_E~0); 25151#L1029-1 assume !(0 == ~T2_E~0); 25152#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25254#L1039-1 assume !(0 == ~T4_E~0); 26081#L1044-1 assume !(0 == ~T5_E~0); 25497#L1049-1 assume !(0 == ~T6_E~0); 25498#L1054-1 assume !(0 == ~T7_E~0); 25736#L1059-1 assume !(0 == ~T8_E~0); 25201#L1064-1 assume !(0 == ~T9_E~0); 25202#L1069-1 assume !(0 == ~T10_E~0); 25940#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 26000#L1079-1 assume !(0 == ~E_1~0); 25973#L1084-1 assume !(0 == ~E_2~0); 25974#L1089-1 assume !(0 == ~E_3~0); 26018#L1094-1 assume !(0 == ~E_4~0); 25585#L1099-1 assume !(0 == ~E_5~0); 25586#L1104-1 assume !(0 == ~E_6~0); 25849#L1109-1 assume !(0 == ~E_7~0); 25368#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 25369#L1119-1 assume !(0 == ~E_9~0); 25435#L1124-1 assume !(0 == ~E_10~0); 24855#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24856#L502 assume 1 == ~m_pc~0; 25734#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 24981#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24982#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25785#L1273 assume !(0 != activate_threads_~tmp~1#1); 25786#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26111#L521 assume !(1 == ~t1_pc~0); 26046#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 24906#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24871#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24872#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 24892#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24893#L540 assume 1 == ~t2_pc~0; 25984#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25696#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25364#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25365#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 26042#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25179#L559 assume 1 == ~t3_pc~0; 25180#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25456#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24808#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24809#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 24999#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25000#L578 assume !(1 == ~t4_pc~0); 25121#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 25120#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24939#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24940#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25768#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25769#L597 assume 1 == ~t5_pc~0; 26126#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24926#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24927#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25969#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 25717#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25718#L616 assume !(1 == ~t6_pc~0); 25731#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25730#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25340#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25341#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 25574#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25575#L635 assume 1 == ~t7_pc~0; 25771#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24895#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25270#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26014#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 25709#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25710#L654 assume !(1 == ~t8_pc~0); 25526#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25527#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25901#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25902#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 25938#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25149#L673 assume 1 == ~t9_pc~0; 25150#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24846#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25421#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25422#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 25861#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25862#L692 assume !(1 == ~t10_pc~0); 25806#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25805#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25577#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25578#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 25589#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25917#L1142 assume !(1 == ~M_E~0); 25060#L1142-2 assume !(1 == ~T1_E~0); 25061#L1147-1 assume !(1 == ~T2_E~0); 25906#L1152-1 assume !(1 == ~T3_E~0); 25463#L1157-1 assume !(1 == ~T4_E~0); 25464#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25613#L1167-1 assume !(1 == ~T6_E~0); 25614#L1172-1 assume !(1 == ~T7_E~0); 26035#L1177-1 assume !(1 == ~T8_E~0); 25754#L1182-1 assume !(1 == ~T9_E~0); 25755#L1187-1 assume !(1 == ~T10_E~0); 25854#L1192-1 assume !(1 == ~E_M~0); 25318#L1197-1 assume !(1 == ~E_1~0); 25319#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25698#L1207-1 assume !(1 == ~E_3~0); 25674#L1212-1 assume !(1 == ~E_4~0); 24911#L1217-1 assume !(1 == ~E_5~0); 24912#L1222-1 assume !(1 == ~E_6~0); 25671#L1227-1 assume !(1 == ~E_7~0); 25672#L1232-1 assume !(1 == ~E_8~0); 24785#L1237-1 assume !(1 == ~E_9~0); 24786#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 25735#L1247-1 assume { :end_inline_reset_delta_events } true; 24956#L1553-2 [2023-11-19 08:02:30,124 INFO L750 eck$LassoCheckResult]: Loop: 24956#L1553-2 assume !false; 24957#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25096#L999-1 assume !false; 25237#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25044#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24929#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25401#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 25402#L854 assume !(0 != eval_~tmp~0#1); 25811#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25598#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25599#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26071#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25571#L1029-3 assume !(0 == ~T2_E~0); 25539#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25540#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25882#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25145#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25146#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24907#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24908#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25509#L1069-3 assume !(0 == ~T10_E~0); 25510#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25856#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25747#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25632#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25633#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25558#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25559#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25880#L1109-3 assume !(0 == ~E_7~0); 25868#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25869#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26132#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 26139#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26105#L502-36 assume !(1 == ~m_pc~0); 25288#L502-38 is_master_triggered_~__retres1~0#1 := 0; 24773#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24774#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25203#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25204#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25482#L521-36 assume 1 == ~t1_pc~0; 25483#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25493#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25663#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26059#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25942#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25943#L540-36 assume 1 == ~t2_pc~0; 26107#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24863#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25275#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25944#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25608#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24782#L559-36 assume 1 == ~t3_pc~0; 24784#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25241#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25416#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25417#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 25756#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25996#L578-36 assume !(1 == ~t4_pc~0); 25683#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 25684#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25620#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25621#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25517#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25518#L597-36 assume !(1 == ~t5_pc~0); 25744#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 26097#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26041#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25699#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25320#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25321#L616-36 assume !(1 == ~t6_pc~0); 26067#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 24851#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24852#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25396#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25568#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25897#L635-36 assume 1 == ~t7_pc~0; 26072#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25954#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25955#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26017#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25554#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25555#L654-36 assume 1 == ~t8_pc~0; 26135#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26080#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25721#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25722#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26112#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25226#L673-36 assume 1 == ~t9_pc~0; 25227#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25594#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25459#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25460#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24792#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24793#L692-36 assume 1 == ~t10_pc~0; 25746#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25005#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25302#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25194#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 25195#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25565#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25714#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26075#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26076#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25645#L1157-3 assume !(1 == ~T4_E~0); 25646#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25950#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26062#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25551#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25451#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25452#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25466#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25284#L1197-3 assume !(1 == ~E_1~0); 25285#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25532#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25653#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25878#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25189#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24876#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24877#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25979#L1237-3 assume !(1 == ~E_9~0); 25980#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 26142#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 26028#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 25027#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25028#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 25292#L1572 assume !(0 == start_simulation_~tmp~3#1); 25323#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25485#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24806#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 24864#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 24865#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24777#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24778#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 25625#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 24956#L1553-2 [2023-11-19 08:02:30,125 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:30,126 INFO L85 PathProgramCache]: Analyzing trace with hash 711809793, now seen corresponding path program 1 times [2023-11-19 08:02:30,126 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:30,126 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [604911235] [2023-11-19 08:02:30,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:30,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:30,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:30,241 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:30,241 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:30,241 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [604911235] [2023-11-19 08:02:30,242 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [604911235] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:30,242 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:30,242 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:30,242 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [543206401] [2023-11-19 08:02:30,242 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:30,244 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:30,244 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:30,245 INFO L85 PathProgramCache]: Analyzing trace with hash -671382823, now seen corresponding path program 1 times [2023-11-19 08:02:30,245 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:30,245 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1723356069] [2023-11-19 08:02:30,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:30,246 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:30,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:30,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:30,311 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:30,311 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1723356069] [2023-11-19 08:02:30,312 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1723356069] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:30,312 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:30,312 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:30,312 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [657850080] [2023-11-19 08:02:30,312 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:30,313 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:30,313 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:30,314 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 08:02:30,314 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 08:02:30,314 INFO L87 Difference]: Start difference. First operand 1372 states and 2026 transitions. cyclomatic complexity: 655 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:30,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:30,562 INFO L93 Difference]: Finished difference Result 2526 states and 3716 transitions. [2023-11-19 08:02:30,562 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2526 states and 3716 transitions. [2023-11-19 08:02:30,578 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2365 [2023-11-19 08:02:30,598 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2526 states to 2526 states and 3716 transitions. [2023-11-19 08:02:30,598 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2526 [2023-11-19 08:02:30,601 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2526 [2023-11-19 08:02:30,602 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2526 states and 3716 transitions. [2023-11-19 08:02:30,606 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:30,606 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2526 states and 3716 transitions. [2023-11-19 08:02:30,611 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2526 states and 3716 transitions. [2023-11-19 08:02:30,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2526 to 2526. [2023-11-19 08:02:30,666 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2526 states, 2526 states have (on average 1.471100554235946) internal successors, (3716), 2525 states have internal predecessors, (3716), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:30,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2526 states to 2526 states and 3716 transitions. [2023-11-19 08:02:30,683 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2526 states and 3716 transitions. [2023-11-19 08:02:30,684 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 08:02:30,685 INFO L428 stractBuchiCegarLoop]: Abstraction has 2526 states and 3716 transitions. [2023-11-19 08:02:30,685 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-19 08:02:30,685 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2526 states and 3716 transitions. [2023-11-19 08:02:30,697 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2365 [2023-11-19 08:02:30,698 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:30,698 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:30,700 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:30,701 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:30,701 INFO L748 eck$LassoCheckResult]: Stem: 29063#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 29064#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 29983#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29984#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29654#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 29335#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29336#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29622#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29797#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29508#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29509#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29387#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29388#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 29751#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29709#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 29629#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29630#L1024 assume !(0 == ~M_E~0); 29894#L1024-2 assume !(0 == ~T1_E~0); 29059#L1029-1 assume !(0 == ~T2_E~0); 29060#L1034-1 assume !(0 == ~T3_E~0); 29163#L1039-1 assume !(0 == ~T4_E~0); 30008#L1044-1 assume !(0 == ~T5_E~0); 29408#L1049-1 assume !(0 == ~T6_E~0); 29409#L1054-1 assume !(0 == ~T7_E~0); 29653#L1059-1 assume !(0 == ~T8_E~0); 29109#L1064-1 assume !(0 == ~T9_E~0); 29110#L1069-1 assume !(0 == ~T10_E~0); 29863#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 29924#L1079-1 assume !(0 == ~E_1~0); 29896#L1084-1 assume !(0 == ~E_2~0); 29897#L1089-1 assume !(0 == ~E_3~0); 29943#L1094-1 assume !(0 == ~E_4~0); 29499#L1099-1 assume !(0 == ~E_5~0); 29500#L1104-1 assume !(0 == ~E_6~0); 29769#L1109-1 assume !(0 == ~E_7~0); 29277#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 29278#L1119-1 assume !(0 == ~E_9~0); 29345#L1124-1 assume !(0 == ~E_10~0); 28763#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28764#L502 assume 1 == ~m_pc~0; 29651#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28889#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28890#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29703#L1273 assume !(0 != activate_threads_~tmp~1#1); 29704#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30054#L521 assume !(1 == ~t1_pc~0); 29972#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28814#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28779#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28780#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 28800#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28801#L540 assume 1 == ~t2_pc~0; 29908#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29611#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29273#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29274#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 29968#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29087#L559 assume 1 == ~t3_pc~0; 29088#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29366#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28716#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28717#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 28907#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28908#L578 assume !(1 == ~t4_pc~0); 29028#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 29027#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28846#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28847#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29685#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29686#L597 assume 1 == ~t5_pc~0; 30071#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28834#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28835#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29892#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 29631#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29632#L616 assume !(1 == ~t6_pc~0); 29648#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 29647#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29249#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29250#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 29488#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29489#L635 assume 1 == ~t7_pc~0; 29688#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28803#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29179#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29939#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 29624#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29625#L654 assume !(1 == ~t8_pc~0); 29439#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29440#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29820#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29821#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 29861#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29057#L673 assume 1 == ~t9_pc~0; 29058#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28754#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29329#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29330#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 29781#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29782#L692 assume !(1 == ~t10_pc~0); 29724#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29723#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29491#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29492#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 29503#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29839#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 30094#L1142-2 assume !(1 == ~T1_E~0); 30494#L1147-1 assume !(1 == ~T2_E~0); 30488#L1152-1 assume !(1 == ~T3_E~0); 30093#L1157-1 assume !(1 == ~T4_E~0); 30424#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30421#L1167-1 assume !(1 == ~T6_E~0); 30419#L1172-1 assume !(1 == ~T7_E~0); 30417#L1177-1 assume !(1 == ~T8_E~0); 30397#L1182-1 assume !(1 == ~T9_E~0); 30240#L1187-1 assume !(1 == ~T10_E~0); 30239#L1192-1 assume !(1 == ~E_M~0); 29227#L1197-1 assume !(1 == ~E_1~0); 29228#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 29613#L1207-1 assume !(1 == ~E_3~0); 29589#L1212-1 assume !(1 == ~E_4~0); 28819#L1217-1 assume !(1 == ~E_5~0); 28820#L1222-1 assume !(1 == ~E_6~0); 29586#L1227-1 assume !(1 == ~E_7~0); 29587#L1232-1 assume !(1 == ~E_8~0); 28693#L1237-1 assume !(1 == ~E_9~0); 28694#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 30138#L1247-1 assume { :end_inline_reset_delta_events } true; 30131#L1553-2 [2023-11-19 08:02:30,702 INFO L750 eck$LassoCheckResult]: Loop: 30131#L1553-2 assume !false; 30125#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30121#L999-1 assume !false; 30120#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30119#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30108#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30107#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 30105#L854 assume !(0 != eval_~tmp~0#1); 30104#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30103#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30101#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30102#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30962#L1029-3 assume !(0 == ~T2_E~0); 30961#L1034-3 assume !(0 == ~T3_E~0); 30960#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30959#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30958#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30957#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 30956#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30955#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30954#L1069-3 assume !(0 == ~T10_E~0); 30953#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 30952#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30951#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30950#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30949#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30948#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30947#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30031#L1109-3 assume !(0 == ~E_7~0); 29788#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29789#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 30078#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 30087#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30044#L502-36 assume 1 == ~m_pc~0; 29803#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28681#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28682#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29111#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29112#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29392#L521-36 assume 1 == ~t1_pc~0; 29393#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29404#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29578#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29985#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29865#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29866#L540-36 assume 1 == ~t2_pc~0; 30048#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28771#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29184#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29867#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29522#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28690#L559-36 assume !(1 == ~t3_pc~0); 28691#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 29150#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29326#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29327#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 29673#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29920#L578-36 assume 1 == ~t4_pc~0; 29641#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29599#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29534#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29535#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29428#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29429#L597-36 assume !(1 == ~t5_pc~0); 29661#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 30027#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29967#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29614#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29229#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29230#L616-36 assume 1 == ~t6_pc~0; 30049#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28759#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28760#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29305#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29482#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29817#L635-36 assume !(1 == ~t7_pc~0); 30097#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 30550#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30548#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30546#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 30544#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30338#L654-36 assume 1 == ~t8_pc~0; 30334#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30332#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30330#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30328#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 30326#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30324#L673-36 assume !(1 == ~t9_pc~0); 30320#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 30318#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30316#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30314#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30312#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30310#L692-36 assume 1 == ~t10_pc~0; 30306#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30304#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30302#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30300#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 30298#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30296#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29633#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30292#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30290#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30032#L1157-3 assume !(1 == ~T4_E~0); 30287#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30285#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30284#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30283#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30282#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30281#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30280#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30279#L1197-3 assume !(1 == ~E_1~0); 30278#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30277#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30276#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30275#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30274#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30273#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30272#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30271#L1237-3 assume !(1 == ~E_9~0); 30270#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30269#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30268#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30257#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30256#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 30255#L1572 assume !(0 == start_simulation_~tmp~3#1); 29232#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30249#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30241#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30170#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 30157#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30150#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30143#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 30139#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 30131#L1553-2 [2023-11-19 08:02:30,703 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:30,703 INFO L85 PathProgramCache]: Analyzing trace with hash 1478663553, now seen corresponding path program 1 times [2023-11-19 08:02:30,703 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:30,704 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1944966716] [2023-11-19 08:02:30,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:30,704 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:30,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:30,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:30,819 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:30,819 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1944966716] [2023-11-19 08:02:30,820 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1944966716] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:30,820 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:30,820 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:30,820 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [53752199] [2023-11-19 08:02:30,821 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:30,821 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:30,821 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:30,822 INFO L85 PathProgramCache]: Analyzing trace with hash -2013593701, now seen corresponding path program 1 times [2023-11-19 08:02:30,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:30,822 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1797933159] [2023-11-19 08:02:30,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:30,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:30,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:30,908 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:30,908 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:30,908 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1797933159] [2023-11-19 08:02:30,909 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1797933159] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:30,909 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:30,909 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:30,909 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1901724888] [2023-11-19 08:02:30,909 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:30,910 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:30,910 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:30,911 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 08:02:30,911 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 08:02:30,911 INFO L87 Difference]: Start difference. First operand 2526 states and 3716 transitions. cyclomatic complexity: 1192 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:31,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:31,141 INFO L93 Difference]: Finished difference Result 4664 states and 6847 transitions. [2023-11-19 08:02:31,141 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4664 states and 6847 transitions. [2023-11-19 08:02:31,169 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4471 [2023-11-19 08:02:31,207 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4664 states to 4664 states and 6847 transitions. [2023-11-19 08:02:31,208 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4664 [2023-11-19 08:02:31,214 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4664 [2023-11-19 08:02:31,214 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4664 states and 6847 transitions. [2023-11-19 08:02:31,222 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:31,222 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4664 states and 6847 transitions. [2023-11-19 08:02:31,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4664 states and 6847 transitions. [2023-11-19 08:02:31,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4664 to 4662. [2023-11-19 08:02:31,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4662 states, 4662 states have (on average 1.4682539682539681) internal successors, (6845), 4661 states have internal predecessors, (6845), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:31,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4662 states to 4662 states and 6845 transitions. [2023-11-19 08:02:31,329 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4662 states and 6845 transitions. [2023-11-19 08:02:31,329 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 08:02:31,330 INFO L428 stractBuchiCegarLoop]: Abstraction has 4662 states and 6845 transitions. [2023-11-19 08:02:31,330 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-19 08:02:31,330 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4662 states and 6845 transitions. [2023-11-19 08:02:31,351 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4471 [2023-11-19 08:02:31,351 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:31,351 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:31,353 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:31,354 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:31,354 INFO L748 eck$LassoCheckResult]: Stem: 36263#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 36264#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 37182#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37183#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36850#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 36535#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36536#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36819#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36992#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36705#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36706#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36589#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36590#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36945#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36905#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36827#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36828#L1024 assume !(0 == ~M_E~0); 37088#L1024-2 assume !(0 == ~T1_E~0); 36259#L1029-1 assume !(0 == ~T2_E~0); 36260#L1034-1 assume !(0 == ~T3_E~0); 36362#L1039-1 assume !(0 == ~T4_E~0); 37206#L1044-1 assume !(0 == ~T5_E~0); 36609#L1049-1 assume !(0 == ~T6_E~0); 36610#L1054-1 assume !(0 == ~T7_E~0); 36849#L1059-1 assume !(0 == ~T8_E~0); 36309#L1064-1 assume !(0 == ~T9_E~0); 36310#L1069-1 assume !(0 == ~T10_E~0); 37057#L1074-1 assume !(0 == ~E_M~0); 37118#L1079-1 assume !(0 == ~E_1~0); 37090#L1084-1 assume !(0 == ~E_2~0); 37091#L1089-1 assume !(0 == ~E_3~0); 37136#L1094-1 assume !(0 == ~E_4~0); 36695#L1099-1 assume !(0 == ~E_5~0); 36696#L1104-1 assume !(0 == ~E_6~0); 36963#L1109-1 assume !(0 == ~E_7~0); 36476#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 36477#L1119-1 assume !(0 == ~E_9~0); 36550#L1124-1 assume !(0 == ~E_10~0); 35963#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35964#L502 assume 1 == ~m_pc~0; 36847#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36089#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36090#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36901#L1273 assume !(0 != activate_threads_~tmp~1#1); 36902#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37238#L521 assume !(1 == ~t1_pc~0); 37167#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36014#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35979#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35980#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 36000#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36001#L540 assume 1 == ~t2_pc~0; 37102#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36807#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36474#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36475#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 37163#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36287#L559 assume 1 == ~t3_pc~0; 36288#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36566#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35916#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35917#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 36107#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36108#L578 assume !(1 == ~t4_pc~0); 36231#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 36230#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36047#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36048#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36881#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36882#L597 assume 1 == ~t5_pc~0; 37255#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36034#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36035#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37086#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 36829#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36830#L616 assume !(1 == ~t6_pc~0); 36846#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36845#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36448#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36449#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 36685#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36686#L635 assume 1 == ~t7_pc~0; 36885#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36003#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36380#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37132#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 36820#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36821#L654 assume !(1 == ~t8_pc~0); 36636#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 36637#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37019#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37020#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 37055#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36257#L673 assume 1 == ~t9_pc~0; 36258#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35956#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36530#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36531#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 36976#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36977#L692 assume !(1 == ~t10_pc~0); 36922#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36921#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36687#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36688#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 36699#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37034#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 37275#L1142-2 assume !(1 == ~T1_E~0); 37560#L1147-1 assume !(1 == ~T2_E~0); 37273#L1152-1 assume !(1 == ~T3_E~0); 37274#L1157-1 assume !(1 == ~T4_E~0); 37490#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36723#L1167-1 assume !(1 == ~T6_E~0); 36724#L1172-1 assume !(1 == ~T7_E~0); 37169#L1177-1 assume !(1 == ~T8_E~0); 37170#L1182-1 assume !(1 == ~T9_E~0); 36968#L1187-1 assume !(1 == ~T10_E~0); 36969#L1192-1 assume !(1 == ~E_M~0); 37369#L1197-1 assume !(1 == ~E_1~0); 37367#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 37365#L1207-1 assume !(1 == ~E_3~0); 37364#L1212-1 assume !(1 == ~E_4~0); 37352#L1217-1 assume !(1 == ~E_5~0); 37350#L1222-1 assume !(1 == ~E_6~0); 37348#L1227-1 assume !(1 == ~E_7~0); 37336#L1232-1 assume !(1 == ~E_8~0); 37327#L1237-1 assume !(1 == ~E_9~0); 37319#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 37312#L1247-1 assume { :end_inline_reset_delta_events } true; 37308#L1553-2 [2023-11-19 08:02:31,355 INFO L750 eck$LassoCheckResult]: Loop: 37308#L1553-2 assume !false; 37302#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37298#L999-1 assume !false; 37297#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37296#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37285#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37284#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 37282#L854 assume !(0 != eval_~tmp~0#1); 37281#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37280#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37278#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37279#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38470#L1029-3 assume !(0 == ~T2_E~0); 38467#L1034-3 assume !(0 == ~T3_E~0); 38464#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38461#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 38458#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38455#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 38452#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 38449#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38446#L1069-3 assume !(0 == ~T10_E~0); 38443#L1074-3 assume !(0 == ~E_M~0); 38439#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 38434#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38429#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38423#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 38418#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38413#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38408#L1109-3 assume !(0 == ~E_7~0); 38401#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 38396#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 38390#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 38385#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38381#L502-36 assume !(1 == ~m_pc~0); 38353#L502-38 is_master_triggered_~__retres1~0#1 := 0; 38351#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38348#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38346#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38344#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38342#L521-36 assume 1 == ~t1_pc~0; 38340#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 38337#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38335#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38333#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38331#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38329#L540-36 assume !(1 == ~t2_pc~0); 38326#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 38316#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38309#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38300#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38292#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38285#L559-36 assume 1 == ~t3_pc~0; 38278#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38269#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38261#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38252#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 38244#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38237#L578-36 assume 1 == ~t4_pc~0; 38229#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38220#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38212#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38203#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38195#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38189#L597-36 assume !(1 == ~t5_pc~0); 38182#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 38174#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38167#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38160#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38152#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38145#L616-36 assume 1 == ~t6_pc~0; 38138#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38131#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38124#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38117#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38110#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38105#L635-36 assume !(1 == ~t7_pc~0); 38065#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 38057#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38049#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38041#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 38033#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38025#L654-36 assume 1 == ~t8_pc~0; 38016#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38008#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38000#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37992#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37984#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37976#L673-36 assume 1 == ~t9_pc~0; 37968#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37959#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37951#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37941#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 37935#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37930#L692-36 assume 1 == ~t10_pc~0; 37820#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37817#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37815#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37813#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 37811#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37809#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36825#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37806#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37786#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37226#L1157-3 assume !(1 == ~T4_E~0); 37769#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37761#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37754#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37747#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37738#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 37730#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37722#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37713#L1197-3 assume !(1 == ~E_1~0); 37707#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37701#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37693#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37686#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37679#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37672#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37666#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37661#L1237-3 assume !(1 == ~E_9~0); 37654#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37648#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37444#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37433#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37432#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 37431#L1572 assume !(0 == start_simulation_~tmp~3#1); 36431#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37359#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37351#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37349#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 37337#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37328#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37320#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 37313#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 37308#L1553-2 [2023-11-19 08:02:31,355 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:31,355 INFO L85 PathProgramCache]: Analyzing trace with hash 171521155, now seen corresponding path program 1 times [2023-11-19 08:02:31,356 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:31,356 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1931567201] [2023-11-19 08:02:31,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:31,356 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:31,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:31,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:31,498 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:31,499 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1931567201] [2023-11-19 08:02:31,499 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1931567201] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:31,499 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:31,499 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:31,499 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1411104819] [2023-11-19 08:02:31,499 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:31,500 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:31,500 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:31,501 INFO L85 PathProgramCache]: Analyzing trace with hash 590468125, now seen corresponding path program 1 times [2023-11-19 08:02:31,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:31,501 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2041413507] [2023-11-19 08:02:31,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:31,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:31,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:31,562 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:31,563 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:31,563 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2041413507] [2023-11-19 08:02:31,563 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2041413507] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:31,563 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:31,563 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:31,563 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1623422370] [2023-11-19 08:02:31,564 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:31,564 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:31,564 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:31,565 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 08:02:31,565 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 08:02:31,565 INFO L87 Difference]: Start difference. First operand 4662 states and 6845 transitions. cyclomatic complexity: 2187 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:31,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:31,792 INFO L93 Difference]: Finished difference Result 8740 states and 12800 transitions. [2023-11-19 08:02:31,793 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8740 states and 12800 transitions. [2023-11-19 08:02:31,845 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8525 [2023-11-19 08:02:31,896 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8740 states to 8740 states and 12800 transitions. [2023-11-19 08:02:31,896 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8740 [2023-11-19 08:02:31,908 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8740 [2023-11-19 08:02:31,908 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8740 states and 12800 transitions. [2023-11-19 08:02:31,921 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:31,921 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8740 states and 12800 transitions. [2023-11-19 08:02:31,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8740 states and 12800 transitions. [2023-11-19 08:02:32,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8740 to 8736. [2023-11-19 08:02:32,132 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8736 states, 8736 states have (on average 1.4647435897435896) internal successors, (12796), 8735 states have internal predecessors, (12796), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:32,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8736 states to 8736 states and 12796 transitions. [2023-11-19 08:02:32,160 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8736 states and 12796 transitions. [2023-11-19 08:02:32,160 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 08:02:32,161 INFO L428 stractBuchiCegarLoop]: Abstraction has 8736 states and 12796 transitions. [2023-11-19 08:02:32,161 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-19 08:02:32,161 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8736 states and 12796 transitions. [2023-11-19 08:02:32,203 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8525 [2023-11-19 08:02:32,204 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:32,204 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:32,206 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:32,207 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:32,207 INFO L748 eck$LassoCheckResult]: Stem: 49675#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 49676#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 50613#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50614#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50269#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 49948#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49949#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50238#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50418#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50123#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50124#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50000#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50001#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50370#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50327#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 50245#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50246#L1024 assume !(0 == ~M_E~0); 50519#L1024-2 assume !(0 == ~T1_E~0); 49671#L1029-1 assume !(0 == ~T2_E~0); 49672#L1034-1 assume !(0 == ~T3_E~0); 49774#L1039-1 assume !(0 == ~T4_E~0); 50637#L1044-1 assume !(0 == ~T5_E~0); 50021#L1049-1 assume !(0 == ~T6_E~0); 50022#L1054-1 assume !(0 == ~T7_E~0); 50268#L1059-1 assume !(0 == ~T8_E~0); 49721#L1064-1 assume !(0 == ~T9_E~0); 49722#L1069-1 assume !(0 == ~T10_E~0); 50488#L1074-1 assume !(0 == ~E_M~0); 50550#L1079-1 assume !(0 == ~E_1~0); 50521#L1084-1 assume !(0 == ~E_2~0); 50522#L1089-1 assume !(0 == ~E_3~0); 50570#L1094-1 assume !(0 == ~E_4~0); 50114#L1099-1 assume !(0 == ~E_5~0); 50115#L1104-1 assume !(0 == ~E_6~0); 50388#L1109-1 assume !(0 == ~E_7~0); 49889#L1114-1 assume !(0 == ~E_8~0); 49890#L1119-1 assume !(0 == ~E_9~0); 49958#L1124-1 assume !(0 == ~E_10~0); 49375#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49376#L502 assume 1 == ~m_pc~0; 50266#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49501#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49502#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 50321#L1273 assume !(0 != activate_threads_~tmp~1#1); 50322#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50676#L521 assume !(1 == ~t1_pc~0); 50599#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 49426#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49391#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49392#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 49412#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49413#L540 assume 1 == ~t2_pc~0; 50534#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50226#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49885#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49886#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 50595#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49699#L559 assume 1 == ~t3_pc~0; 49700#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49979#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49328#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49329#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 49519#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49520#L578 assume !(1 == ~t4_pc~0); 49641#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49640#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49459#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49460#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50303#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50304#L597 assume 1 == ~t5_pc~0; 50694#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49446#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49447#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50517#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 50247#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50248#L616 assume !(1 == ~t6_pc~0); 50263#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50262#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49861#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49862#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 50102#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50103#L635 assume 1 == ~t7_pc~0; 50306#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49415#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49790#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50566#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 50240#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50241#L654 assume !(1 == ~t8_pc~0); 50051#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 50052#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50447#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50448#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 50486#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49669#L673 assume 1 == ~t9_pc~0; 49670#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49366#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49944#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49945#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 50402#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50403#L692 assume !(1 == ~t10_pc~0); 50342#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 50341#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50105#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50106#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 50118#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50465#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 50720#L1142-2 assume !(1 == ~T1_E~0); 50452#L1147-1 assume !(1 == ~T2_E~0); 50453#L1152-1 assume !(1 == ~T3_E~0); 51084#L1157-1 assume !(1 == ~T4_E~0); 51081#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 51077#L1167-1 assume !(1 == ~T6_E~0); 51074#L1172-1 assume !(1 == ~T7_E~0); 51071#L1177-1 assume !(1 == ~T8_E~0); 51068#L1182-1 assume !(1 == ~T9_E~0); 51064#L1187-1 assume !(1 == ~T10_E~0); 51061#L1192-1 assume !(1 == ~E_M~0); 51057#L1197-1 assume !(1 == ~E_1~0); 50866#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 50864#L1207-1 assume !(1 == ~E_3~0); 50839#L1212-1 assume !(1 == ~E_4~0); 50827#L1217-1 assume !(1 == ~E_5~0); 50825#L1222-1 assume !(1 == ~E_6~0); 50804#L1227-1 assume !(1 == ~E_7~0); 50802#L1232-1 assume !(1 == ~E_8~0); 50786#L1237-1 assume !(1 == ~E_9~0); 50770#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 50761#L1247-1 assume { :end_inline_reset_delta_events } true; 50754#L1553-2 [2023-11-19 08:02:32,208 INFO L750 eck$LassoCheckResult]: Loop: 50754#L1553-2 assume !false; 50748#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 50744#L999-1 assume !false; 50743#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50742#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50731#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50730#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 50728#L854 assume !(0 != eval_~tmp~0#1); 50727#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50726#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50724#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50725#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 52358#L1029-3 assume !(0 == ~T2_E~0); 52356#L1034-3 assume !(0 == ~T3_E~0); 52354#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 52352#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 52350#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52348#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 52346#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52344#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 52342#L1069-3 assume !(0 == ~T10_E~0); 52340#L1074-3 assume !(0 == ~E_M~0); 52338#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 52336#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52334#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52332#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 52329#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 52327#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 52325#L1109-3 assume !(0 == ~E_7~0); 52323#L1114-3 assume !(0 == ~E_8~0); 52321#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 52319#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 52316#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52314#L502-36 assume !(1 == ~m_pc~0); 52284#L502-38 is_master_triggered_~__retres1~0#1 := 0; 52282#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52279#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 52277#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52275#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52273#L521-36 assume 1 == ~t1_pc~0; 52270#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 52268#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52265#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 52263#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52261#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52259#L540-36 assume !(1 == ~t2_pc~0); 52256#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 52254#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52251#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 52249#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 52247#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52245#L559-36 assume 1 == ~t3_pc~0; 52242#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 52240#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52237#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 52235#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 52233#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 52231#L578-36 assume 1 == ~t4_pc~0; 52228#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 52226#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52223#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 51841#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51839#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50276#L597-36 assume !(1 == ~t5_pc~0); 50277#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 51694#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51691#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51689#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 51687#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 51685#L616-36 assume 1 == ~t6_pc~0; 51659#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 51644#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 51642#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51640#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 51637#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51635#L635-36 assume !(1 == ~t7_pc~0); 51632#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 51625#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 51598#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51596#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 51593#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 51592#L654-36 assume 1 == ~t8_pc~0; 51578#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 51566#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51564#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51561#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 51559#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51557#L673-36 assume !(1 == ~t9_pc~0); 51554#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 50125#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49982#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49983#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51504#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51502#L692-36 assume 1 == ~t10_pc~0; 51479#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 51477#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51468#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51460#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 51452#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51444#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50249#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 51429#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 51420#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50662#L1157-3 assume !(1 == ~T4_E~0); 51405#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 51400#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 51395#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 51390#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 51384#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 51379#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 51374#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 51367#L1197-3 assume !(1 == ~E_1~0); 51364#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 51361#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 51357#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51354#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 51351#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 51348#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 51345#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 51341#L1237-3 assume !(1 == ~E_9~0); 51338#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 51336#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 51334#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 51322#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 51177#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 50863#L1572 assume !(0 == start_simulation_~tmp~3#1); 49843#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50834#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50826#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50805#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 50788#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50774#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50771#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 50762#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 50754#L1553-2 [2023-11-19 08:02:32,208 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:32,209 INFO L85 PathProgramCache]: Analyzing trace with hash -711987835, now seen corresponding path program 1 times [2023-11-19 08:02:32,209 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:32,209 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [441157618] [2023-11-19 08:02:32,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:32,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:32,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:32,339 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:32,339 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:32,339 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [441157618] [2023-11-19 08:02:32,339 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [441157618] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:32,340 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:32,340 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 08:02:32,340 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [395552273] [2023-11-19 08:02:32,340 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:32,341 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:32,341 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:32,342 INFO L85 PathProgramCache]: Analyzing trace with hash -1184532576, now seen corresponding path program 1 times [2023-11-19 08:02:32,342 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:32,342 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1721398876] [2023-11-19 08:02:32,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:32,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:32,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:32,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:32,416 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:32,416 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1721398876] [2023-11-19 08:02:32,417 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1721398876] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:32,417 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:32,417 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:32,417 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1116092896] [2023-11-19 08:02:32,417 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:32,418 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:32,418 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:32,418 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:02:32,419 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:02:32,419 INFO L87 Difference]: Start difference. First operand 8736 states and 12796 transitions. cyclomatic complexity: 4068 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:32,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:32,625 INFO L93 Difference]: Finished difference Result 17147 states and 24931 transitions. [2023-11-19 08:02:32,625 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17147 states and 24931 transitions. [2023-11-19 08:02:32,744 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16929 [2023-11-19 08:02:32,823 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17147 states to 17147 states and 24931 transitions. [2023-11-19 08:02:32,823 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17147 [2023-11-19 08:02:32,844 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17147 [2023-11-19 08:02:32,845 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17147 states and 24931 transitions. [2023-11-19 08:02:32,863 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:32,864 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17147 states and 24931 transitions. [2023-11-19 08:02:32,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17147 states and 24931 transitions. [2023-11-19 08:02:33,149 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17147 to 16539. [2023-11-19 08:02:33,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16539 states, 16539 states have (on average 1.455650281153637) internal successors, (24075), 16538 states have internal predecessors, (24075), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:33,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16539 states to 16539 states and 24075 transitions. [2023-11-19 08:02:33,390 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16539 states and 24075 transitions. [2023-11-19 08:02:33,391 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:02:33,391 INFO L428 stractBuchiCegarLoop]: Abstraction has 16539 states and 24075 transitions. [2023-11-19 08:02:33,392 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-19 08:02:33,392 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16539 states and 24075 transitions. [2023-11-19 08:02:33,472 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16321 [2023-11-19 08:02:33,472 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:33,472 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:33,475 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:33,475 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:33,476 INFO L748 eck$LassoCheckResult]: Stem: 75577#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 75578#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 76631#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76632#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76206#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 75861#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 75862#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76172#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76372#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76050#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76051#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 75921#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 75922#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 76316#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 76269#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 76182#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76183#L1024 assume !(0 == ~M_E~0); 76510#L1024-2 assume !(0 == ~T1_E~0); 75572#L1029-1 assume !(0 == ~T2_E~0); 75573#L1034-1 assume !(0 == ~T3_E~0); 75686#L1039-1 assume !(0 == ~T4_E~0); 76665#L1044-1 assume !(0 == ~T5_E~0); 75940#L1049-1 assume !(0 == ~T6_E~0); 75941#L1054-1 assume !(0 == ~T7_E~0); 76204#L1059-1 assume !(0 == ~T8_E~0); 75629#L1064-1 assume !(0 == ~T9_E~0); 75630#L1069-1 assume !(0 == ~T10_E~0); 76469#L1074-1 assume !(0 == ~E_M~0); 76548#L1079-1 assume !(0 == ~E_1~0); 76513#L1084-1 assume !(0 == ~E_2~0); 76514#L1089-1 assume !(0 == ~E_3~0); 76576#L1094-1 assume !(0 == ~E_4~0); 76036#L1099-1 assume !(0 == ~E_5~0); 76037#L1104-1 assume !(0 == ~E_6~0); 76338#L1109-1 assume !(0 == ~E_7~0); 75802#L1114-1 assume !(0 == ~E_8~0); 75803#L1119-1 assume !(0 == ~E_9~0); 75876#L1124-1 assume !(0 == ~E_10~0); 75265#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75266#L502 assume !(1 == ~m_pc~0); 75467#L502-2 is_master_triggered_~__retres1~0#1 := 0; 75397#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75398#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 76265#L1273 assume !(0 != activate_threads_~tmp~1#1); 76266#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76749#L521 assume !(1 == ~t1_pc~0); 76616#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 75319#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75281#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 75282#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 75303#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75304#L540 assume 1 == ~t2_pc~0; 76526#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 76156#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75800#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 75801#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 76610#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75606#L559 assume 1 == ~t3_pc~0; 75607#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 75892#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75218#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 75219#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 75413#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75414#L578 assume !(1 == ~t4_pc~0); 75542#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 75541#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75351#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 75352#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 76243#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76244#L597 assume 1 == ~t5_pc~0; 76783#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 75337#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 75338#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76508#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 76184#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76185#L616 assume !(1 == ~t6_pc~0); 76202#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 76201#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75774#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 75775#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 76026#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76027#L635 assume 1 == ~t7_pc~0; 76246#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 75306#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75704#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76571#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 76174#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 76175#L654 assume !(1 == ~t8_pc~0); 75970#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 75971#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76413#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76414#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 76466#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 75570#L673 assume 1 == ~t9_pc~0; 75571#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 75258#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 75856#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75857#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 76353#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76354#L692 assume !(1 == ~t10_pc~0); 76287#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 76286#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76028#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76029#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 76040#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76437#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 76841#L1142-2 assume !(1 == ~T1_E~0); 76417#L1147-1 assume !(1 == ~T2_E~0); 76418#L1152-1 assume !(1 == ~T3_E~0); 76840#L1157-1 assume !(1 == ~T4_E~0); 86884#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 86883#L1167-1 assume !(1 == ~T6_E~0); 86882#L1172-1 assume !(1 == ~T7_E~0); 86881#L1177-1 assume !(1 == ~T8_E~0); 86880#L1182-1 assume !(1 == ~T9_E~0); 86879#L1187-1 assume !(1 == ~T10_E~0); 76404#L1192-1 assume !(1 == ~E_M~0); 75754#L1197-1 assume !(1 == ~E_1~0); 75755#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 76161#L1207-1 assume !(1 == ~E_3~0); 76133#L1212-1 assume !(1 == ~E_4~0); 75322#L1217-1 assume !(1 == ~E_5~0); 75323#L1222-1 assume !(1 == ~E_6~0); 76129#L1227-1 assume !(1 == ~E_7~0); 76130#L1232-1 assume !(1 == ~E_8~0); 76222#L1237-1 assume !(1 == ~E_9~0); 90859#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 76203#L1247-1 assume { :end_inline_reset_delta_events } true; 75372#L1553-2 [2023-11-19 08:02:33,476 INFO L750 eck$LassoCheckResult]: Loop: 75372#L1553-2 assume !false; 75373#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 75514#L999-1 assume !false; 75668#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 76474#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 90690#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 90689#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 76291#L854 assume !(0 != eval_~tmp~0#1); 76293#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 76053#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 76054#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 76653#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 76022#L1029-3 assume !(0 == ~T2_E~0); 75985#L1034-3 assume !(0 == ~T3_E~0); 75986#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 76377#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 77615#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 77614#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 75317#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 75318#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 77497#L1069-3 assume !(0 == ~T10_E~0); 76347#L1074-3 assume !(0 == ~E_M~0); 76348#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 76216#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 76087#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 76088#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 76008#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 76009#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 76375#L1109-3 assume !(0 == ~E_7~0); 76361#L1114-3 assume !(0 == ~E_8~0); 76362#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 76792#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 76806#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76731#L502-36 assume !(1 == ~m_pc~0); 75722#L502-38 is_master_triggered_~__retres1~0#1 := 0; 75183#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75184#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 75631#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 75632#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75918#L521-36 assume !(1 == ~t1_pc~0); 75920#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 75933#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76119#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 76630#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 76471#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76472#L540-36 assume 1 == ~t2_pc~0; 76741#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 75273#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75707#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 76473#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 76063#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75192#L559-36 assume !(1 == ~t3_pc~0); 75193#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 91470#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 91469#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 91468#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 91467#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 91466#L578-36 assume !(1 == ~t4_pc~0); 91465#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 91463#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 91462#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 91461#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 91460#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 91459#L597-36 assume !(1 == ~t5_pc~0); 91457#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 91456#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 91455#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 91454#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 91453#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 91452#L616-36 assume !(1 == ~t6_pc~0); 91451#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 91449#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 91448#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 91447#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 91446#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 91445#L635-36 assume !(1 == ~t7_pc~0); 91443#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 91442#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 91441#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 91440#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 91439#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 91438#L654-36 assume !(1 == ~t8_pc~0); 91437#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 91435#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 91434#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 91433#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 91432#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 91431#L673-36 assume !(1 == ~t9_pc~0); 91429#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 91428#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 91427#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 91426#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 91425#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 91424#L692-36 assume !(1 == ~t10_pc~0); 91423#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 91421#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 91420#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 91419#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 91418#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91417#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 76180#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 91416#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 91415#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 76708#L1157-3 assume !(1 == ~T4_E~0); 91414#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 91413#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 91412#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 91411#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 91410#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 91409#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 91408#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 90441#L1197-3 assume !(1 == ~E_1~0); 75979#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 75980#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 76109#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 76373#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 75616#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 75286#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 75287#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 76521#L1237-3 assume !(1 == ~E_9~0); 76522#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 76831#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 76589#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 75441#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 75442#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 75726#L1572 assume !(0 == start_simulation_~tmp~3#1); 75757#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 90890#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 90883#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 90882#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 90881#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 90880#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 90879#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 76856#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 75372#L1553-2 [2023-11-19 08:02:33,477 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:33,477 INFO L85 PathProgramCache]: Analyzing trace with hash -2098669114, now seen corresponding path program 1 times [2023-11-19 08:02:33,477 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:33,478 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1936050871] [2023-11-19 08:02:33,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:33,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:33,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:33,557 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:33,558 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:33,558 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1936050871] [2023-11-19 08:02:33,558 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1936050871] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:33,558 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:33,558 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:33,559 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1595064415] [2023-11-19 08:02:33,559 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:33,559 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:33,560 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:33,560 INFO L85 PathProgramCache]: Analyzing trace with hash 746267621, now seen corresponding path program 1 times [2023-11-19 08:02:33,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:33,560 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1713036419] [2023-11-19 08:02:33,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:33,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:33,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:33,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:33,616 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:33,617 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1713036419] [2023-11-19 08:02:33,617 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1713036419] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:33,617 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:33,617 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:33,617 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [132294392] [2023-11-19 08:02:33,618 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:33,618 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:33,618 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:33,619 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 08:02:33,619 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 08:02:33,620 INFO L87 Difference]: Start difference. First operand 16539 states and 24075 transitions. cyclomatic complexity: 7552 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:34,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:34,270 INFO L93 Difference]: Finished difference Result 40132 states and 57936 transitions. [2023-11-19 08:02:34,270 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40132 states and 57936 transitions. [2023-11-19 08:02:34,634 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 39243 [2023-11-19 08:02:34,810 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40132 states to 40132 states and 57936 transitions. [2023-11-19 08:02:34,810 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40132 [2023-11-19 08:02:34,862 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40132 [2023-11-19 08:02:34,862 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40132 states and 57936 transitions. [2023-11-19 08:02:34,903 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:34,903 INFO L218 hiAutomatonCegarLoop]: Abstraction has 40132 states and 57936 transitions. [2023-11-19 08:02:34,948 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40132 states and 57936 transitions. [2023-11-19 08:02:35,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40132 to 31409. [2023-11-19 08:02:35,515 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31409 states, 31409 states have (on average 1.4487885637874494) internal successors, (45505), 31408 states have internal predecessors, (45505), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:35,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31409 states to 31409 states and 45505 transitions. [2023-11-19 08:02:35,780 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31409 states and 45505 transitions. [2023-11-19 08:02:35,781 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 08:02:35,781 INFO L428 stractBuchiCegarLoop]: Abstraction has 31409 states and 45505 transitions. [2023-11-19 08:02:35,782 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-19 08:02:35,782 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31409 states and 45505 transitions. [2023-11-19 08:02:36,008 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 31184 [2023-11-19 08:02:36,008 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:36,009 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:36,011 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:36,012 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:36,012 INFO L748 eck$LassoCheckResult]: Stem: 132249#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 132250#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 133226#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 133227#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 132865#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 132533#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 132534#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 132827#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 133016#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 132706#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 132707#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 132586#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 132587#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 132970#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 132923#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 132838#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 132839#L1024 assume !(0 == ~M_E~0); 133126#L1024-2 assume !(0 == ~T1_E~0); 132245#L1029-1 assume !(0 == ~T2_E~0); 132246#L1034-1 assume !(0 == ~T3_E~0); 132353#L1039-1 assume !(0 == ~T4_E~0); 133257#L1044-1 assume !(0 == ~T5_E~0); 132607#L1049-1 assume !(0 == ~T6_E~0); 132608#L1054-1 assume !(0 == ~T7_E~0); 132864#L1059-1 assume !(0 == ~T8_E~0); 132300#L1064-1 assume !(0 == ~T9_E~0); 132301#L1069-1 assume !(0 == ~T10_E~0); 133093#L1074-1 assume !(0 == ~E_M~0); 133156#L1079-1 assume !(0 == ~E_1~0); 133128#L1084-1 assume !(0 == ~E_2~0); 133129#L1089-1 assume !(0 == ~E_3~0); 133178#L1094-1 assume !(0 == ~E_4~0); 132697#L1099-1 assume !(0 == ~E_5~0); 132698#L1104-1 assume !(0 == ~E_6~0); 132988#L1109-1 assume !(0 == ~E_7~0); 132473#L1114-1 assume !(0 == ~E_8~0); 132474#L1119-1 assume !(0 == ~E_9~0); 132544#L1124-1 assume !(0 == ~E_10~0); 131946#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 131947#L502 assume !(1 == ~m_pc~0); 132142#L502-2 is_master_triggered_~__retres1~0#1 := 0; 132073#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 132074#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 132917#L1273 assume !(0 != activate_threads_~tmp~1#1); 132918#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 133309#L521 assume !(1 == ~t1_pc~0); 133210#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 131997#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 131962#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 131963#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 131983#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 131984#L540 assume !(1 == ~t2_pc~0); 132812#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 132813#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 132469#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 132470#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 133203#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 132278#L559 assume 1 == ~t3_pc~0; 132279#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 132564#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 131899#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 131900#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 132091#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 132092#L578 assume !(1 == ~t4_pc~0); 132215#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 132214#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 132031#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 132032#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 132900#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 132901#L597 assume 1 == ~t5_pc~0; 133330#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 132018#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 132019#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 133124#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 132840#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 132841#L616 assume !(1 == ~t6_pc~0); 132859#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 132858#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 132445#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 132446#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 132686#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 132687#L635 assume 1 == ~t7_pc~0; 132903#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 131986#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 132369#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 133174#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 132833#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 132834#L654 assume !(1 == ~t8_pc~0); 132636#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 132637#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 133043#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 133044#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 133091#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 132243#L673 assume 1 == ~t9_pc~0; 132244#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 131937#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 132529#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 132530#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 133000#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 133001#L692 assume !(1 == ~t10_pc~0); 132940#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 132939#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 132689#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 132690#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 132701#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 133067#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 132152#L1142-2 assume !(1 == ~T1_E~0); 132153#L1147-1 assume !(1 == ~T2_E~0); 133375#L1152-1 assume !(1 == ~T3_E~0); 133376#L1157-1 assume !(1 == ~T4_E~0); 146280#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 146279#L1167-1 assume !(1 == ~T6_E~0); 146278#L1172-1 assume !(1 == ~T7_E~0); 146276#L1177-1 assume !(1 == ~T8_E~0); 146274#L1182-1 assume !(1 == ~T9_E~0); 146272#L1187-1 assume !(1 == ~T10_E~0); 146270#L1192-1 assume !(1 == ~E_M~0); 132419#L1197-1 assume !(1 == ~E_1~0); 132420#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 132817#L1207-1 assume !(1 == ~E_3~0); 132818#L1212-1 assume !(1 == ~E_4~0); 132002#L1217-1 assume !(1 == ~E_5~0); 132003#L1222-1 assume !(1 == ~E_6~0); 132786#L1227-1 assume !(1 == ~E_7~0); 132787#L1232-1 assume !(1 == ~E_8~0); 132883#L1237-1 assume !(1 == ~E_9~0); 147446#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 132862#L1247-1 assume { :end_inline_reset_delta_events } true; 132863#L1553-2 [2023-11-19 08:02:36,013 INFO L750 eck$LassoCheckResult]: Loop: 132863#L1553-2 assume !false; 148001#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 132931#L999-1 assume !false; 147994#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 132136#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 132021#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 132507#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 132508#L854 assume !(0 != eval_~tmp~0#1); 132950#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 148894#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 148889#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 148885#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 148881#L1029-3 assume !(0 == ~T2_E~0); 148877#L1034-3 assume !(0 == ~T3_E~0); 148873#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 148868#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 148863#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 148859#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 148855#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 148851#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 148847#L1069-3 assume !(0 == ~T10_E~0); 148842#L1074-3 assume !(0 == ~E_M~0); 148837#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 148833#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 148829#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 148825#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 148821#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 148816#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 148811#L1109-3 assume !(0 == ~E_7~0); 148807#L1114-3 assume !(0 == ~E_8~0); 148803#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 148799#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 148795#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 148790#L502-36 assume !(1 == ~m_pc~0); 148785#L502-38 is_master_triggered_~__retres1~0#1 := 0; 148781#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 148777#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 148773#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 148769#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 148764#L521-36 assume 1 == ~t1_pc~0; 148758#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 148753#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 148749#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 148745#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 148737#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 133300#L540-36 assume !(1 == ~t2_pc~0); 133301#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 149100#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 149099#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 149098#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 149097#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 149096#L559-36 assume 1 == ~t3_pc~0; 149094#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 149093#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 149092#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 149091#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 149090#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 149089#L578-36 assume !(1 == ~t4_pc~0); 149088#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 149086#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 149085#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 149084#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 149083#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 149082#L597-36 assume !(1 == ~t5_pc~0); 149080#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 149079#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 149078#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 149077#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 149076#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 149075#L616-36 assume !(1 == ~t6_pc~0); 149074#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 149072#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 149071#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 149070#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 149069#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 149068#L635-36 assume !(1 == ~t7_pc~0); 149066#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 149065#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 149064#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 149063#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 149062#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 149061#L654-36 assume 1 == ~t8_pc~0; 149059#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 149058#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 149056#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 149054#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 149052#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 149050#L673-36 assume !(1 == ~t9_pc~0); 149047#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 149045#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 149043#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 149040#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 149038#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 149036#L692-36 assume !(1 == ~t10_pc~0); 149034#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 149031#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 149029#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 149028#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 149026#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 149024#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 142688#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 149021#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 149019#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 142872#L1157-3 assume !(1 == ~T4_E~0); 149015#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 149013#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 149011#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 149009#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 149007#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 149004#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 149002#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 145848#L1197-3 assume !(1 == ~E_1~0); 148999#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 148997#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 148995#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 148992#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 148990#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 148988#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 148986#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 147673#L1237-3 assume !(1 == ~E_9~0); 148983#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 148980#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 148978#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 148966#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 148964#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 132851#L1572 assume !(0 == start_simulation_~tmp~3#1); 132852#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 148065#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 148049#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 148041#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 148035#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 148030#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 148023#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 148016#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 132863#L1553-2 [2023-11-19 08:02:36,014 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:36,014 INFO L85 PathProgramCache]: Analyzing trace with hash 353984391, now seen corresponding path program 1 times [2023-11-19 08:02:36,014 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:36,014 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1663736271] [2023-11-19 08:02:36,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:36,015 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:36,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:36,108 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:36,108 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:36,109 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1663736271] [2023-11-19 08:02:36,109 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1663736271] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:36,109 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:36,109 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:36,109 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1276072410] [2023-11-19 08:02:36,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:36,110 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:36,111 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:36,111 INFO L85 PathProgramCache]: Analyzing trace with hash 1160589027, now seen corresponding path program 1 times [2023-11-19 08:02:36,111 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:36,111 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [500946852] [2023-11-19 08:02:36,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:36,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:36,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:36,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:36,175 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:36,175 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [500946852] [2023-11-19 08:02:36,175 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [500946852] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:36,175 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:36,176 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:36,176 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [519699257] [2023-11-19 08:02:36,176 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:36,177 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:36,177 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:36,177 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 08:02:36,177 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 08:02:36,178 INFO L87 Difference]: Start difference. First operand 31409 states and 45505 transitions. cyclomatic complexity: 14112 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:37,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:37,010 INFO L93 Difference]: Finished difference Result 76233 states and 109613 transitions. [2023-11-19 08:02:37,011 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 76233 states and 109613 transitions. [2023-11-19 08:02:37,671 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 74673 [2023-11-19 08:02:37,918 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 76233 states to 76233 states and 109613 transitions. [2023-11-19 08:02:37,919 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 76233 [2023-11-19 08:02:37,957 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 76233 [2023-11-19 08:02:37,957 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76233 states and 109613 transitions. [2023-11-19 08:02:38,015 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:38,016 INFO L218 hiAutomatonCegarLoop]: Abstraction has 76233 states and 109613 transitions. [2023-11-19 08:02:38,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76233 states and 109613 transitions. [2023-11-19 08:02:38,876 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76233 to 59724. [2023-11-19 08:02:38,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59724 states, 59724 states have (on average 1.4428035630567275) internal successors, (86170), 59723 states have internal predecessors, (86170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:39,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59724 states to 59724 states and 86170 transitions. [2023-11-19 08:02:39,371 INFO L240 hiAutomatonCegarLoop]: Abstraction has 59724 states and 86170 transitions. [2023-11-19 08:02:39,372 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 08:02:39,373 INFO L428 stractBuchiCegarLoop]: Abstraction has 59724 states and 86170 transitions. [2023-11-19 08:02:39,373 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-19 08:02:39,384 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59724 states and 86170 transitions. [2023-11-19 08:02:39,554 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 59484 [2023-11-19 08:02:39,554 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:39,554 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:39,557 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:39,557 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:39,558 INFO L748 eck$LassoCheckResult]: Stem: 239903#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 239904#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 240915#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 240916#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 240529#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 240192#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 240193#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 240494#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 240687#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 240368#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 240369#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 240247#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 240248#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 240632#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 240591#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 240505#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 240506#L1024 assume !(0 == ~M_E~0); 240805#L1024-2 assume !(0 == ~T1_E~0); 239899#L1029-1 assume !(0 == ~T2_E~0); 239900#L1034-1 assume !(0 == ~T3_E~0); 240009#L1039-1 assume !(0 == ~T4_E~0); 240944#L1044-1 assume !(0 == ~T5_E~0); 240268#L1049-1 assume !(0 == ~T6_E~0); 240269#L1054-1 assume !(0 == ~T7_E~0); 240528#L1059-1 assume !(0 == ~T8_E~0); 239954#L1064-1 assume !(0 == ~T9_E~0); 239955#L1069-1 assume !(0 == ~T10_E~0); 240772#L1074-1 assume !(0 == ~E_M~0); 240842#L1079-1 assume !(0 == ~E_1~0); 240808#L1084-1 assume !(0 == ~E_2~0); 240809#L1089-1 assume !(0 == ~E_3~0); 240862#L1094-1 assume !(0 == ~E_4~0); 240359#L1099-1 assume !(0 == ~E_5~0); 240360#L1104-1 assume !(0 == ~E_6~0); 240656#L1109-1 assume !(0 == ~E_7~0); 240130#L1114-1 assume !(0 == ~E_8~0); 240131#L1119-1 assume !(0 == ~E_9~0); 240203#L1124-1 assume !(0 == ~E_10~0); 239597#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 239598#L502 assume !(1 == ~m_pc~0); 239793#L502-2 is_master_triggered_~__retres1~0#1 := 0; 239724#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 239725#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 240585#L1273 assume !(0 != activate_threads_~tmp~1#1); 240586#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 240998#L521 assume !(1 == ~t1_pc~0); 240900#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 239647#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 239613#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 239614#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 239633#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 239634#L540 assume !(1 == ~t2_pc~0); 240477#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 240478#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 240126#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 240127#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 240893#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 239933#L559 assume !(1 == ~t3_pc~0); 239934#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 240225#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 239550#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 239551#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 239742#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 239743#L578 assume !(1 == ~t4_pc~0); 239866#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 239865#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 239680#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 239681#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 240563#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 240564#L597 assume 1 == ~t5_pc~0; 241023#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 239668#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 239669#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 240803#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 240507#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 240508#L616 assume !(1 == ~t6_pc~0); 240523#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 240522#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 240102#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 240103#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 240348#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 240349#L635 assume 1 == ~t7_pc~0; 240568#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 239636#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 240026#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 240858#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 240499#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 240500#L654 assume !(1 == ~t8_pc~0); 240299#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 240300#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 240720#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 240721#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 240770#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 239897#L673 assume 1 == ~t9_pc~0; 239898#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 239588#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 240186#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 240187#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 240670#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 240671#L692 assume !(1 == ~t10_pc~0); 240606#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 240605#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 240351#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 240352#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 240363#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 240745#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 239805#L1142-2 assume !(1 == ~T1_E~0); 239806#L1147-1 assume !(1 == ~T2_E~0); 241065#L1152-1 assume !(1 == ~T3_E~0); 240232#L1157-1 assume !(1 == ~T4_E~0); 240233#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 240387#L1167-1 assume !(1 == ~T6_E~0); 240388#L1172-1 assume !(1 == ~T7_E~0); 240901#L1177-1 assume !(1 == ~T8_E~0); 240902#L1182-1 assume !(1 == ~T9_E~0); 240661#L1187-1 assume !(1 == ~T10_E~0); 240662#L1192-1 assume !(1 == ~E_M~0); 255239#L1197-1 assume !(1 == ~E_1~0); 255237#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 255235#L1207-1 assume !(1 == ~E_3~0); 255233#L1212-1 assume !(1 == ~E_4~0); 255231#L1217-1 assume !(1 == ~E_5~0); 255229#L1222-1 assume !(1 == ~E_6~0); 255227#L1227-1 assume !(1 == ~E_7~0); 255223#L1232-1 assume !(1 == ~E_8~0); 255220#L1237-1 assume !(1 == ~E_9~0); 255219#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 255217#L1247-1 assume { :end_inline_reset_delta_events } true; 255205#L1553-2 [2023-11-19 08:02:39,559 INFO L750 eck$LassoCheckResult]: Loop: 255205#L1553-2 assume !false; 255203#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 255198#L999-1 assume !false; 255196#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 255194#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 255182#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 255180#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 255177#L854 assume !(0 != eval_~tmp~0#1); 255178#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 257288#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 257286#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 257284#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 257282#L1029-3 assume !(0 == ~T2_E~0); 257268#L1034-3 assume !(0 == ~T3_E~0); 257263#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 257261#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 256781#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 256778#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 256776#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 256774#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 256772#L1069-3 assume !(0 == ~T10_E~0); 256770#L1074-3 assume !(0 == ~E_M~0); 256768#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 256765#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 256763#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 256761#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 256759#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 256757#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 256755#L1109-3 assume !(0 == ~E_7~0); 256752#L1114-3 assume !(0 == ~E_8~0); 256750#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 256748#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 256746#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 256744#L502-36 assume !(1 == ~m_pc~0); 256742#L502-38 is_master_triggered_~__retres1~0#1 := 0; 256741#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 256740#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 256739#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 256737#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 256735#L521-36 assume !(1 == ~t1_pc~0); 256733#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 256730#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 256728#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 256682#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 256675#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 256270#L540-36 assume !(1 == ~t2_pc~0); 256268#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 256266#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 256264#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 256262#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 256260#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 256257#L559-36 assume !(1 == ~t3_pc~0); 253125#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 256254#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 256252#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 256250#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 256248#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 256245#L578-36 assume !(1 == ~t4_pc~0); 256243#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 256240#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 256238#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 256236#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 256234#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 256233#L597-36 assume !(1 == ~t5_pc~0); 256231#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 256230#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 256229#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 256228#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 256226#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 256224#L616-36 assume !(1 == ~t6_pc~0); 256222#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 256219#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 256217#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 256215#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 256213#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 256212#L635-36 assume 1 == ~t7_pc~0; 256210#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 256207#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 256205#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 256203#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 256201#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 256200#L654-36 assume !(1 == ~t8_pc~0); 256198#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 256195#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 255825#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 255822#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 255820#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 255818#L673-36 assume !(1 == ~t9_pc~0); 255815#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 255813#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 255811#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 255808#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 255806#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 255804#L692-36 assume !(1 == ~t10_pc~0); 255801#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 255798#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 255795#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 255764#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 255754#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 255745#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 255730#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 255726#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 255717#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 255704#L1157-3 assume !(1 == ~T4_E~0); 255694#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 255687#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 255679#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 255671#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 255664#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 255656#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 255648#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 255636#L1197-3 assume !(1 == ~E_1~0); 255629#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 255622#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 255616#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 255609#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 255602#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 255596#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 255591#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 255583#L1237-3 assume !(1 == ~E_9~0); 255578#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 255572#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 255351#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 255335#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 255329#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 255323#L1572 assume !(0 == start_simulation_~tmp~3#1); 255318#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 255307#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 255269#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 255254#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 255249#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 255244#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 255224#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 255218#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 255205#L1553-2 [2023-11-19 08:02:39,559 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:39,559 INFO L85 PathProgramCache]: Analyzing trace with hash -1601336824, now seen corresponding path program 1 times [2023-11-19 08:02:39,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:39,560 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1132439814] [2023-11-19 08:02:39,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:39,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:39,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:39,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:39,640 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:39,640 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1132439814] [2023-11-19 08:02:39,640 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1132439814] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:39,641 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:39,641 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 08:02:39,641 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1539215491] [2023-11-19 08:02:39,641 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:39,642 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:39,642 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:39,642 INFO L85 PathProgramCache]: Analyzing trace with hash 390917157, now seen corresponding path program 1 times [2023-11-19 08:02:39,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:39,642 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1196023764] [2023-11-19 08:02:39,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:39,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:39,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:39,695 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:39,696 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:39,696 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1196023764] [2023-11-19 08:02:39,696 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1196023764] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:39,696 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:39,696 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:39,696 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1512320195] [2023-11-19 08:02:39,697 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:39,697 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:39,697 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:39,698 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 08:02:39,698 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 08:02:39,698 INFO L87 Difference]: Start difference. First operand 59724 states and 86170 transitions. cyclomatic complexity: 26462 Second operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:41,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:41,060 INFO L93 Difference]: Finished difference Result 144064 states and 206185 transitions. [2023-11-19 08:02:41,060 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 144064 states and 206185 transitions. [2023-11-19 08:02:41,861 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 143608 [2023-11-19 08:02:42,478 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 144064 states to 144064 states and 206185 transitions. [2023-11-19 08:02:42,478 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 144064 [2023-11-19 08:02:42,565 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 144064 [2023-11-19 08:02:42,565 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144064 states and 206185 transitions. [2023-11-19 08:02:42,734 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:42,735 INFO L218 hiAutomatonCegarLoop]: Abstraction has 144064 states and 206185 transitions. [2023-11-19 08:02:42,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144064 states and 206185 transitions. [2023-11-19 08:02:43,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144064 to 61575. [2023-11-19 08:02:43,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61575 states, 61575 states have (on average 1.4294924888347544) internal successors, (88021), 61574 states have internal predecessors, (88021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:44,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61575 states to 61575 states and 88021 transitions. [2023-11-19 08:02:44,079 INFO L240 hiAutomatonCegarLoop]: Abstraction has 61575 states and 88021 transitions. [2023-11-19 08:02:44,079 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-19 08:02:44,081 INFO L428 stractBuchiCegarLoop]: Abstraction has 61575 states and 88021 transitions. [2023-11-19 08:02:44,081 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-19 08:02:44,081 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 61575 states and 88021 transitions. [2023-11-19 08:02:44,286 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 61332 [2023-11-19 08:02:44,286 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:44,286 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:44,290 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:44,290 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:44,290 INFO L748 eck$LassoCheckResult]: Stem: 443705#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 443706#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 444773#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 444774#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 444347#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 443994#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 443995#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 444311#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 444519#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 444182#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 444183#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 444048#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 444049#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 444454#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 444410#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 444320#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 444321#L1024 assume !(0 == ~M_E~0); 444643#L1024-2 assume !(0 == ~T1_E~0); 443701#L1029-1 assume !(0 == ~T2_E~0); 443702#L1034-1 assume !(0 == ~T3_E~0); 443813#L1039-1 assume !(0 == ~T4_E~0); 444809#L1044-1 assume !(0 == ~T5_E~0); 444072#L1049-1 assume !(0 == ~T6_E~0); 444073#L1054-1 assume !(0 == ~T7_E~0); 444346#L1059-1 assume !(0 == ~T8_E~0); 443757#L1064-1 assume !(0 == ~T9_E~0); 443758#L1069-1 assume !(0 == ~T10_E~0); 444605#L1074-1 assume !(0 == ~E_M~0); 444678#L1079-1 assume !(0 == ~E_1~0); 444647#L1084-1 assume !(0 == ~E_2~0); 444648#L1089-1 assume !(0 == ~E_3~0); 444711#L1094-1 assume !(0 == ~E_4~0); 444172#L1099-1 assume !(0 == ~E_5~0); 444173#L1104-1 assume !(0 == ~E_6~0); 444481#L1109-1 assume !(0 == ~E_7~0); 443934#L1114-1 assume !(0 == ~E_8~0); 443935#L1119-1 assume !(0 == ~E_9~0); 444004#L1124-1 assume !(0 == ~E_10~0); 443398#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 443399#L502 assume !(1 == ~m_pc~0); 443596#L502-2 is_master_triggered_~__retres1~0#1 := 0; 443527#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 443528#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 444404#L1273 assume !(0 != activate_threads_~tmp~1#1); 444405#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 444881#L521 assume !(1 == ~t1_pc~0); 444754#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 443448#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 443414#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 443415#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 443434#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 443435#L540 assume !(1 == ~t2_pc~0); 444294#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 444295#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 443930#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 443931#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 444744#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 443735#L559 assume !(1 == ~t3_pc~0); 443736#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 444025#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 443351#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 443352#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 443545#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 443546#L578 assume !(1 == ~t4_pc~0); 443665#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 444610#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 444639#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 444865#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 444383#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 444384#L597 assume 1 == ~t5_pc~0; 444912#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 443469#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 443470#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 444640#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 444322#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 444323#L616 assume !(1 == ~t6_pc~0); 444341#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 444340#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 443906#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 443907#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 444160#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 444161#L635 assume 1 == ~t7_pc~0; 444388#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 443437#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 443830#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 444704#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 444314#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 444315#L654 assume !(1 == ~t8_pc~0); 444104#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 444105#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 444552#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 444553#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 444603#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 443699#L673 assume 1 == ~t9_pc~0; 443700#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 443389#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 443988#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 443989#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 444495#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 444496#L692 assume !(1 == ~t10_pc~0); 444426#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 444425#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 444163#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 444164#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 444176#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 444576#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 443606#L1142-2 assume !(1 == ~T1_E~0); 443607#L1147-1 assume !(1 == ~T2_E~0); 444981#L1152-1 assume !(1 == ~T3_E~0); 444982#L1157-1 assume !(1 == ~T4_E~0); 457044#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 457041#L1167-1 assume !(1 == ~T6_E~0); 457038#L1172-1 assume !(1 == ~T7_E~0); 457036#L1177-1 assume !(1 == ~T8_E~0); 457033#L1182-1 assume !(1 == ~T9_E~0); 457029#L1187-1 assume !(1 == ~T10_E~0); 457012#L1192-1 assume !(1 == ~E_M~0); 457006#L1197-1 assume !(1 == ~E_1~0); 457001#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 456966#L1207-1 assume !(1 == ~E_3~0); 456954#L1212-1 assume !(1 == ~E_4~0); 456952#L1217-1 assume !(1 == ~E_5~0); 456950#L1222-1 assume !(1 == ~E_6~0); 456948#L1227-1 assume !(1 == ~E_7~0); 456946#L1232-1 assume !(1 == ~E_8~0); 450274#L1237-1 assume !(1 == ~E_9~0); 456931#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 456922#L1247-1 assume { :end_inline_reset_delta_events } true; 456915#L1553-2 [2023-11-19 08:02:44,291 INFO L750 eck$LassoCheckResult]: Loop: 456915#L1553-2 assume !false; 456909#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 456905#L999-1 assume !false; 456904#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 456903#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 456891#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 456887#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 456884#L854 assume !(0 != eval_~tmp~0#1); 456885#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 473172#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 473170#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 473169#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 473168#L1029-3 assume !(0 == ~T2_E~0); 473166#L1034-3 assume !(0 == ~T3_E~0); 473164#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 473152#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 473150#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 473148#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 473145#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 473143#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 473141#L1069-3 assume !(0 == ~T10_E~0); 473139#L1074-3 assume !(0 == ~E_M~0); 473137#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 473135#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 473133#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 473131#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 473129#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 473127#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 473125#L1109-3 assume !(0 == ~E_7~0); 473123#L1114-3 assume !(0 == ~E_8~0); 473121#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 473119#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 473117#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 473115#L502-36 assume !(1 == ~m_pc~0); 473113#L502-38 is_master_triggered_~__retres1~0#1 := 0; 473111#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 473109#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 473107#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 473105#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 473103#L521-36 assume !(1 == ~t1_pc~0); 473101#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 473098#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 473096#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 473085#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 473078#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 473071#L540-36 assume !(1 == ~t2_pc~0); 453658#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 473058#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 473050#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 473042#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 473034#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 443326#L559-36 assume !(1 == ~t3_pc~0); 443327#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 445753#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 445752#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 445751#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 445749#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 445750#L578-36 assume !(1 == ~t4_pc~0); 445744#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 445745#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 445736#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 445737#L1305-36 assume !(0 != activate_threads_~tmp___3~0#1); 472958#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 472955#L597-36 assume 1 == ~t5_pc~0; 472953#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 472950#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 472948#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 472946#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 472944#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 472943#L616-36 assume !(1 == ~t6_pc~0); 472940#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 472937#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 472935#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 472933#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 472931#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 472929#L635-36 assume 1 == ~t7_pc~0; 472926#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 472923#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 472921#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 472919#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 472917#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 472915#L654-36 assume !(1 == ~t8_pc~0); 470447#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 457115#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 457113#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 457111#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 457108#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 457106#L673-36 assume 1 == ~t9_pc~0; 457104#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 457101#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 457099#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 457097#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 457094#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 457092#L692-36 assume !(1 == ~t10_pc~0); 457090#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 457087#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 457085#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 457083#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 457080#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 457079#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 445334#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 457078#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 457076#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 457073#L1157-3 assume !(1 == ~T4_E~0); 457071#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 457069#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 457067#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 457065#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 457063#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 457061#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 457059#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 457055#L1197-3 assume !(1 == ~E_1~0); 457053#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 457051#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 457049#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 457047#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 457045#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 457042#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 457039#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 450364#L1237-3 assume !(1 == ~E_9~0); 457034#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 457031#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 457027#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 457010#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 457004#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 456999#L1572 assume !(0 == start_simulation_~tmp~3#1); 456998#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 456961#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 456953#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 456951#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 456949#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 456947#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 456932#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 456923#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 456915#L1553-2 [2023-11-19 08:02:44,292 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:44,292 INFO L85 PathProgramCache]: Analyzing trace with hash 360237834, now seen corresponding path program 1 times [2023-11-19 08:02:44,292 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:44,292 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [535045638] [2023-11-19 08:02:44,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:44,293 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:44,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:44,380 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:44,381 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:44,381 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [535045638] [2023-11-19 08:02:44,381 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [535045638] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:44,381 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:44,381 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 08:02:44,381 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1143669508] [2023-11-19 08:02:44,381 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:44,382 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:44,382 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:44,382 INFO L85 PathProgramCache]: Analyzing trace with hash -1966329307, now seen corresponding path program 1 times [2023-11-19 08:02:44,383 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:44,383 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1503474784] [2023-11-19 08:02:44,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:44,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:44,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:44,445 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:44,445 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:44,446 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1503474784] [2023-11-19 08:02:44,446 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1503474784] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:44,446 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:44,446 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:44,446 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [561719583] [2023-11-19 08:02:44,447 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:44,447 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:44,447 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:44,448 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:02:44,448 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:02:44,448 INFO L87 Difference]: Start difference. First operand 61575 states and 88021 transitions. cyclomatic complexity: 26462 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:45,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:45,563 INFO L93 Difference]: Finished difference Result 117170 states and 166838 transitions. [2023-11-19 08:02:45,564 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117170 states and 166838 transitions. [2023-11-19 08:02:46,073 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 116768 [2023-11-19 08:02:46,934 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117170 states to 117170 states and 166838 transitions. [2023-11-19 08:02:46,948 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117170 [2023-11-19 08:02:47,008 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117170 [2023-11-19 08:02:47,009 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117170 states and 166838 transitions. [2023-11-19 08:02:47,094 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:47,094 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117170 states and 166838 transitions. [2023-11-19 08:02:47,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117170 states and 166838 transitions. [2023-11-19 08:02:48,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117170 to 117042. [2023-11-19 08:02:48,487 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117042 states, 117042 states have (on average 1.424360485979392) internal successors, (166710), 117041 states have internal predecessors, (166710), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:48,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117042 states to 117042 states and 166710 transitions. [2023-11-19 08:02:48,823 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117042 states and 166710 transitions. [2023-11-19 08:02:48,824 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:02:48,824 INFO L428 stractBuchiCegarLoop]: Abstraction has 117042 states and 166710 transitions. [2023-11-19 08:02:48,825 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-19 08:02:48,825 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117042 states and 166710 transitions. [2023-11-19 08:02:49,238 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 116640 [2023-11-19 08:02:49,238 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:49,238 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:49,243 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:49,243 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:49,244 INFO L748 eck$LassoCheckResult]: Stem: 622451#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 622452#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 623510#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 623511#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 623085#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 622739#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 622740#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 623052#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 623267#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 622924#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 622925#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 622798#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 622799#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 623202#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 623146#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 623059#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 623060#L1024 assume !(0 == ~M_E~0); 623398#L1024-2 assume !(0 == ~T1_E~0); 622445#L1029-1 assume !(0 == ~T2_E~0); 622446#L1034-1 assume !(0 == ~T3_E~0); 622554#L1039-1 assume !(0 == ~T4_E~0); 623545#L1044-1 assume !(0 == ~T5_E~0); 622820#L1049-1 assume !(0 == ~T6_E~0); 622821#L1054-1 assume !(0 == ~T7_E~0); 623084#L1059-1 assume !(0 == ~T8_E~0); 622500#L1064-1 assume !(0 == ~T9_E~0); 622501#L1069-1 assume !(0 == ~T10_E~0); 623361#L1074-1 assume !(0 == ~E_M~0); 623434#L1079-1 assume !(0 == ~E_1~0); 623400#L1084-1 assume !(0 == ~E_2~0); 623401#L1089-1 assume !(0 == ~E_3~0); 623463#L1094-1 assume !(0 == ~E_4~0); 622913#L1099-1 assume !(0 == ~E_5~0); 622914#L1104-1 assume !(0 == ~E_6~0); 623228#L1109-1 assume !(0 == ~E_7~0); 622674#L1114-1 assume !(0 == ~E_8~0); 622675#L1119-1 assume !(0 == ~E_9~0); 622754#L1124-1 assume !(0 == ~E_10~0); 622149#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 622150#L502 assume !(1 == ~m_pc~0); 622344#L502-2 is_master_triggered_~__retres1~0#1 := 0; 622276#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 622277#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 623142#L1273 assume !(0 != activate_threads_~tmp~1#1); 623143#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 623615#L521 assume !(1 == ~t1_pc~0); 623497#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 622201#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 622165#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 622166#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 622185#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 622186#L540 assume !(1 == ~t2_pc~0); 623031#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 623032#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 622672#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 622673#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 623491#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 622478#L559 assume !(1 == ~t3_pc~0); 622479#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 622769#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 622102#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 622103#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 622292#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 622293#L578 assume !(1 == ~t4_pc~0); 622417#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 623366#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 622232#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 622233#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 623121#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 623122#L597 assume !(1 == ~t5_pc~0); 623068#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 622219#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 622220#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 623395#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 623061#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 623062#L616 assume !(1 == ~t6_pc~0); 623081#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 623080#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 622646#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 622647#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 622903#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 622904#L635 assume 1 == ~t7_pc~0; 623124#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 622188#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 622573#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 623459#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 623054#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 623055#L654 assume !(1 == ~t8_pc~0); 622848#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 622849#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 623304#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 623305#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 623359#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 622443#L673 assume 1 == ~t9_pc~0; 622444#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 622142#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 622733#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 622734#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 623244#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 623245#L692 assume !(1 == ~t10_pc~0); 623166#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 623165#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 622905#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 622906#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 622918#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 623333#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 622352#L1142-2 assume !(1 == ~T1_E~0); 622353#L1147-1 assume !(1 == ~T2_E~0); 623308#L1152-1 assume !(1 == ~T3_E~0); 623704#L1157-1 assume !(1 == ~T4_E~0); 709907#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 709906#L1167-1 assume !(1 == ~T6_E~0); 709905#L1172-1 assume !(1 == ~T7_E~0); 709904#L1177-1 assume !(1 == ~T8_E~0); 709903#L1182-1 assume !(1 == ~T9_E~0); 709902#L1187-1 assume !(1 == ~T10_E~0); 709901#L1192-1 assume !(1 == ~E_M~0); 709900#L1197-1 assume !(1 == ~E_1~0); 709898#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 709896#L1207-1 assume !(1 == ~E_3~0); 709894#L1212-1 assume !(1 == ~E_4~0); 709892#L1217-1 assume !(1 == ~E_5~0); 709890#L1222-1 assume !(1 == ~E_6~0); 709888#L1227-1 assume !(1 == ~E_7~0); 709887#L1232-1 assume !(1 == ~E_8~0); 709884#L1237-1 assume !(1 == ~E_9~0); 709883#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 701192#L1247-1 assume { :end_inline_reset_delta_events } true; 701189#L1553-2 [2023-11-19 08:02:49,245 INFO L750 eck$LassoCheckResult]: Loop: 701189#L1553-2 assume !false; 701187#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 701182#L999-1 assume !false; 701180#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 701178#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 701166#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 701163#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 701160#L854 assume !(0 != eval_~tmp~0#1); 701161#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 731081#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 731079#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 731077#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 731075#L1029-3 assume !(0 == ~T2_E~0); 731073#L1034-3 assume !(0 == ~T3_E~0); 731071#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 731068#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 731066#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 731064#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 731062#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 731060#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 731058#L1069-3 assume !(0 == ~T10_E~0); 731057#L1074-3 assume !(0 == ~E_M~0); 731056#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 731055#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 731054#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 731053#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 731052#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 731051#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 731050#L1109-3 assume !(0 == ~E_7~0); 731049#L1114-3 assume !(0 == ~E_8~0); 731048#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 731047#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 731046#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 731045#L502-36 assume !(1 == ~m_pc~0); 731044#L502-38 is_master_triggered_~__retres1~0#1 := 0; 731043#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 731042#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 731041#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 731040#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 731039#L521-36 assume !(1 == ~t1_pc~0); 731037#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 731035#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 731034#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 731033#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 731032#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 731031#L540-36 assume !(1 == ~t2_pc~0); 720193#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 731030#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 731029#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 731028#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 731027#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 731026#L559-36 assume !(1 == ~t3_pc~0); 726730#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 731025#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 731024#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 731023#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 731022#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 731021#L578-36 assume 1 == ~t4_pc~0; 731019#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 731020#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 731038#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 731014#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 731013#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 731012#L597-36 assume !(1 == ~t5_pc~0); 731011#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 731010#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 731009#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 731008#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 731007#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 731006#L616-36 assume !(1 == ~t6_pc~0); 731005#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 731003#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 731002#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 731001#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 731000#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 730999#L635-36 assume 1 == ~t7_pc~0; 730998#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 730996#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 730995#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 730994#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 730993#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 730992#L654-36 assume !(1 == ~t8_pc~0); 730991#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 730989#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 730988#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 730987#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 730986#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 730985#L673-36 assume 1 == ~t9_pc~0; 623405#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 622923#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 622772#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 622773#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 730980#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 730978#L692-36 assume !(1 == ~t10_pc~0); 726646#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 726635#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 726625#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 726616#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 726609#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 726583#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 698200#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 726448#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 726155#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 698191#L1157-3 assume !(1 == ~T4_E~0); 726154#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 726153#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 623519#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 622878#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 622763#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 622764#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 623407#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 622780#L1197-3 assume !(1 == ~E_1~0); 730749#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 730747#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 730744#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 730742#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 730740#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 720766#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 701245#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 701241#L1237-3 assume !(1 == ~E_9~0); 701239#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 701237#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 701235#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 701223#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 701221#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 701218#L1572 assume !(0 == start_simulation_~tmp~3#1); 701217#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 701212#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 701203#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 701201#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 701199#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 701197#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 701195#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 701193#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 701189#L1553-2 [2023-11-19 08:02:49,246 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:49,246 INFO L85 PathProgramCache]: Analyzing trace with hash -671092981, now seen corresponding path program 1 times [2023-11-19 08:02:49,246 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:49,246 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1692817778] [2023-11-19 08:02:49,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:49,247 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:49,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:49,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:49,356 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:49,356 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1692817778] [2023-11-19 08:02:49,356 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1692817778] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:49,357 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:49,357 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:49,357 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1323771287] [2023-11-19 08:02:49,357 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:49,358 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:49,358 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:49,359 INFO L85 PathProgramCache]: Analyzing trace with hash -168294173, now seen corresponding path program 1 times [2023-11-19 08:02:49,359 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:49,359 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [611453236] [2023-11-19 08:02:49,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:49,360 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:49,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:49,432 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:49,432 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:49,432 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [611453236] [2023-11-19 08:02:49,433 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [611453236] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:49,433 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:49,433 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:49,433 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1461143586] [2023-11-19 08:02:49,433 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:49,434 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:49,434 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:49,435 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 08:02:49,435 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 08:02:49,435 INFO L87 Difference]: Start difference. First operand 117042 states and 166710 transitions. cyclomatic complexity: 49700 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:51,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:02:51,388 INFO L93 Difference]: Finished difference Result 286421 states and 404927 transitions. [2023-11-19 08:02:51,388 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 286421 states and 404927 transitions. [2023-11-19 08:02:53,230 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 280356 [2023-11-19 08:02:53,866 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 286421 states to 286421 states and 404927 transitions. [2023-11-19 08:02:53,866 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 286421 [2023-11-19 08:02:53,984 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 286421 [2023-11-19 08:02:53,984 INFO L73 IsDeterministic]: Start isDeterministic. Operand 286421 states and 404927 transitions. [2023-11-19 08:02:54,767 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:02:54,768 INFO L218 hiAutomatonCegarLoop]: Abstraction has 286421 states and 404927 transitions. [2023-11-19 08:02:54,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 286421 states and 404927 transitions. [2023-11-19 08:02:57,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 286421 to 227265. [2023-11-19 08:02:57,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 227265 states, 227265 states have (on average 1.4180582139792752) internal successors, (322275), 227264 states have internal predecessors, (322275), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:02:58,977 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227265 states to 227265 states and 322275 transitions. [2023-11-19 08:02:58,977 INFO L240 hiAutomatonCegarLoop]: Abstraction has 227265 states and 322275 transitions. [2023-11-19 08:02:58,988 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 08:02:58,989 INFO L428 stractBuchiCegarLoop]: Abstraction has 227265 states and 322275 transitions. [2023-11-19 08:02:58,990 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-19 08:02:58,990 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 227265 states and 322275 transitions. [2023-11-19 08:02:59,586 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 226672 [2023-11-19 08:02:59,586 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:02:59,586 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:02:59,608 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:59,612 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:02:59,613 INFO L748 eck$LassoCheckResult]: Stem: 1025930#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1025931#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1027014#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1027015#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1026570#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 1026217#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1026218#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1026530#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1026748#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1026400#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1026401#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1026273#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1026274#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1026686#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1026630#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1026542#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1026543#L1024 assume !(0 == ~M_E~0); 1026888#L1024-2 assume !(0 == ~T1_E~0); 1025926#L1029-1 assume !(0 == ~T2_E~0); 1025927#L1034-1 assume !(0 == ~T3_E~0); 1026033#L1039-1 assume !(0 == ~T4_E~0); 1027049#L1044-1 assume !(0 == ~T5_E~0); 1026296#L1049-1 assume !(0 == ~T6_E~0); 1026297#L1054-1 assume !(0 == ~T7_E~0); 1026569#L1059-1 assume !(0 == ~T8_E~0); 1025980#L1064-1 assume !(0 == ~T9_E~0); 1025981#L1069-1 assume !(0 == ~T10_E~0); 1026847#L1074-1 assume !(0 == ~E_M~0); 1026930#L1079-1 assume !(0 == ~E_1~0); 1026892#L1084-1 assume !(0 == ~E_2~0); 1026893#L1089-1 assume !(0 == ~E_3~0); 1026954#L1094-1 assume !(0 == ~E_4~0); 1026391#L1099-1 assume !(0 == ~E_5~0); 1026392#L1104-1 assume !(0 == ~E_6~0); 1026710#L1109-1 assume !(0 == ~E_7~0); 1026154#L1114-1 assume !(0 == ~E_8~0); 1026155#L1119-1 assume !(0 == ~E_9~0); 1026229#L1124-1 assume !(0 == ~E_10~0); 1025622#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1025623#L502 assume !(1 == ~m_pc~0); 1025818#L502-2 is_master_triggered_~__retres1~0#1 := 0; 1025749#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1025750#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1026624#L1273 assume !(0 != activate_threads_~tmp~1#1); 1026625#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1027125#L521 assume !(1 == ~t1_pc~0); 1026999#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1025672#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1025638#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1025639#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 1025658#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1025659#L540 assume !(1 == ~t2_pc~0); 1026513#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1026514#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1026150#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1026151#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 1026988#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1025958#L559 assume !(1 == ~t3_pc~0); 1025959#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1026249#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1025575#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1025576#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 1025767#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1025768#L578 assume !(1 == ~t4_pc~0); 1025891#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1026854#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1026885#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1027103#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 1026604#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1026605#L597 assume !(1 == ~t5_pc~0); 1026552#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1025693#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1025694#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1026886#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 1026544#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1026545#L616 assume !(1 == ~t6_pc~0); 1026564#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1026563#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1026126#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1026127#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 1026379#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1026380#L635 assume !(1 == ~t7_pc~0); 1025660#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1025661#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1026050#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1026948#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 1026537#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1026538#L654 assume !(1 == ~t8_pc~0); 1026325#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1026326#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1026786#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1026787#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 1026844#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1025924#L673 assume 1 == ~t9_pc~0; 1025925#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1025613#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1026211#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1026212#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 1026727#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1026728#L692 assume !(1 == ~t10_pc~0); 1026652#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1026651#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1026383#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1026384#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 1026395#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1026816#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 1025830#L1142-2 assume !(1 == ~T1_E~0); 1025831#L1147-1 assume !(1 == ~T2_E~0); 1027232#L1152-1 assume !(1 == ~T3_E~0); 1026257#L1157-1 assume !(1 == ~T4_E~0); 1026258#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1026422#L1167-1 assume !(1 == ~T6_E~0); 1026423#L1172-1 assume !(1 == ~T7_E~0); 1027000#L1177-1 assume !(1 == ~T8_E~0); 1027001#L1182-1 assume !(1 == ~T9_E~0); 1026717#L1187-1 assume !(1 == ~T10_E~0); 1026718#L1192-1 assume !(1 == ~E_M~0); 1101487#L1197-1 assume !(1 == ~E_1~0); 1101486#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1101485#L1207-1 assume !(1 == ~E_3~0); 1101484#L1212-1 assume !(1 == ~E_4~0); 1101483#L1217-1 assume !(1 == ~E_5~0); 1101482#L1222-1 assume !(1 == ~E_6~0); 1101481#L1227-1 assume !(1 == ~E_7~0); 1101480#L1232-1 assume !(1 == ~E_8~0); 1080817#L1237-1 assume !(1 == ~E_9~0); 1101479#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1101477#L1247-1 assume { :end_inline_reset_delta_events } true; 1101475#L1553-2 [2023-11-19 08:02:59,613 INFO L750 eck$LassoCheckResult]: Loop: 1101475#L1553-2 assume !false; 1101473#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1101467#L999-1 assume !false; 1101465#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1101463#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1101451#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1101449#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1101446#L854 assume !(0 != eval_~tmp~0#1); 1101447#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1129058#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1129056#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1129054#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1129053#L1029-3 assume !(0 == ~T2_E~0); 1129052#L1034-3 assume !(0 == ~T3_E~0); 1129051#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1129050#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1129049#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1129048#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1129046#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1129045#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1129044#L1069-3 assume !(0 == ~T10_E~0); 1129043#L1074-3 assume !(0 == ~E_M~0); 1129042#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1129040#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1129039#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1129038#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1129037#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1129035#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1129033#L1109-3 assume !(0 == ~E_7~0); 1129031#L1114-3 assume !(0 == ~E_8~0); 1129029#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1129027#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1129025#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1129023#L502-36 assume !(1 == ~m_pc~0); 1129022#L502-38 is_master_triggered_~__retres1~0#1 := 0; 1129020#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1129018#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1129016#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1129014#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1129010#L521-36 assume !(1 == ~t1_pc~0); 1129008#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1129005#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1129003#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1129000#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1128998#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1128996#L540-36 assume !(1 == ~t2_pc~0); 1122354#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1128993#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1128991#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1128989#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1128987#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1128985#L559-36 assume !(1 == ~t3_pc~0); 1128492#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1128981#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1128979#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1128977#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 1128975#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1128973#L578-36 assume 1 == ~t4_pc~0; 1128971#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1128972#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1129047#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1128963#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1128961#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1128959#L597-36 assume !(1 == ~t5_pc~0); 1128956#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1128954#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1128952#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1128950#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1128948#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1128946#L616-36 assume !(1 == ~t6_pc~0); 1128943#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1128940#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1128938#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1128936#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1128934#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1128932#L635-36 assume !(1 == ~t7_pc~0); 1070739#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1128928#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1128926#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1128924#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1128922#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1128921#L654-36 assume 1 == ~t8_pc~0; 1128919#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1128918#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1128917#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1128916#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1128915#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1128913#L673-36 assume 1 == ~t9_pc~0; 1128911#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1128908#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1128906#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1128904#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1128901#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1128899#L692-36 assume !(1 == ~t10_pc~0); 1128897#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1128894#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1128892#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1128890#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 1128889#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1128887#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1078643#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1128882#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1128880#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1110439#L1157-3 assume !(1 == ~T4_E~0); 1128878#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1128876#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1128874#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1128872#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1128870#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1128869#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1128865#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1128861#L1197-3 assume !(1 == ~E_1~0); 1128859#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1128857#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1128854#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1128852#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1128850#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1128848#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1128846#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1078597#L1237-3 assume !(1 == ~E_9~0); 1128843#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1128841#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1128839#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1128826#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1128824#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1128727#L1572 assume !(0 == start_simulation_~tmp~3#1); 1128725#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1128712#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1128704#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1128702#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 1128700#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1128698#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1128695#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1101478#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 1101475#L1553-2 [2023-11-19 08:02:59,614 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:59,614 INFO L85 PathProgramCache]: Analyzing trace with hash 1730432140, now seen corresponding path program 1 times [2023-11-19 08:02:59,615 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:59,615 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [373296047] [2023-11-19 08:02:59,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:59,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:59,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:59,732 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:59,732 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:59,732 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [373296047] [2023-11-19 08:02:59,733 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [373296047] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:59,733 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:59,733 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:59,733 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [195725498] [2023-11-19 08:02:59,733 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:59,735 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:02:59,735 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:02:59,735 INFO L85 PathProgramCache]: Analyzing trace with hash -925846493, now seen corresponding path program 1 times [2023-11-19 08:02:59,735 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:02:59,736 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1634389898] [2023-11-19 08:02:59,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:02:59,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:02:59,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:02:59,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:02:59,794 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:02:59,794 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1634389898] [2023-11-19 08:02:59,794 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1634389898] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:02:59,797 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:02:59,797 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:02:59,797 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [671446103] [2023-11-19 08:02:59,797 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:02:59,799 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:02:59,799 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:02:59,799 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 08:02:59,800 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 08:02:59,800 INFO L87 Difference]: Start difference. First operand 227265 states and 322275 transitions. cyclomatic complexity: 95042 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:03:02,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:03:02,573 INFO L93 Difference]: Finished difference Result 541376 states and 762944 transitions. [2023-11-19 08:03:02,573 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 541376 states and 762944 transitions. [2023-11-19 08:03:06,312 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 529520