./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.11.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 9bd2c7ff Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58eeb94c-6488-4a4a-8000-6d88ad22d624/bin/uautomizer-verify-uCwYo4JHxu/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58eeb94c-6488-4a4a-8000-6d88ad22d624/bin/uautomizer-verify-uCwYo4JHxu/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58eeb94c-6488-4a4a-8000-6d88ad22d624/bin/uautomizer-verify-uCwYo4JHxu/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58eeb94c-6488-4a4a-8000-6d88ad22d624/bin/uautomizer-verify-uCwYo4JHxu/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.11.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58eeb94c-6488-4a4a-8000-6d88ad22d624/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58eeb94c-6488-4a4a-8000-6d88ad22d624/bin/uautomizer-verify-uCwYo4JHxu --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c5f603027c62ff37561a520351662dbe2fd253b52e04e36028cb9a624978ef8e --- Real Ultimate output --- This is Ultimate 0.2.3-dev-9bd2c7f [2023-11-19 07:43:35,429 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-19 07:43:35,545 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58eeb94c-6488-4a4a-8000-6d88ad22d624/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-19 07:43:35,553 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-19 07:43:35,554 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-19 07:43:35,591 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-19 07:43:35,593 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-19 07:43:35,594 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-19 07:43:35,595 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-19 07:43:35,599 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-19 07:43:35,600 INFO L153 SettingsManager]: * Use SBE=true [2023-11-19 07:43:35,601 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-19 07:43:35,601 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-19 07:43:35,603 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-19 07:43:35,603 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-19 07:43:35,604 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-19 07:43:35,604 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-19 07:43:35,605 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-19 07:43:35,605 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-19 07:43:35,606 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-19 07:43:35,606 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-19 07:43:35,607 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-19 07:43:35,607 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-19 07:43:35,608 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-19 07:43:35,608 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-19 07:43:35,609 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-19 07:43:35,609 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-19 07:43:35,610 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-19 07:43:35,610 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-19 07:43:35,611 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-19 07:43:35,612 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-19 07:43:35,612 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-19 07:43:35,613 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-19 07:43:35,613 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-19 07:43:35,613 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-19 07:43:35,614 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-19 07:43:35,614 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58eeb94c-6488-4a4a-8000-6d88ad22d624/bin/uautomizer-verify-uCwYo4JHxu/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58eeb94c-6488-4a4a-8000-6d88ad22d624/bin/uautomizer-verify-uCwYo4JHxu Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c5f603027c62ff37561a520351662dbe2fd253b52e04e36028cb9a624978ef8e [2023-11-19 07:43:35,956 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-19 07:43:35,985 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-19 07:43:35,988 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-19 07:43:35,990 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-19 07:43:35,990 INFO L274 PluginConnector]: CDTParser initialized [2023-11-19 07:43:35,992 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58eeb94c-6488-4a4a-8000-6d88ad22d624/bin/uautomizer-verify-uCwYo4JHxu/../../sv-benchmarks/c/systemc/token_ring.11.cil-2.c [2023-11-19 07:43:39,117 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-19 07:43:39,505 INFO L384 CDTParser]: Found 1 translation units. [2023-11-19 07:43:39,508 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58eeb94c-6488-4a4a-8000-6d88ad22d624/sv-benchmarks/c/systemc/token_ring.11.cil-2.c [2023-11-19 07:43:39,533 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58eeb94c-6488-4a4a-8000-6d88ad22d624/bin/uautomizer-verify-uCwYo4JHxu/data/56b20bcb8/ea4e47a3600b449385ff50363d8f14a8/FLAG2c8f6f565 [2023-11-19 07:43:39,554 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58eeb94c-6488-4a4a-8000-6d88ad22d624/bin/uautomizer-verify-uCwYo4JHxu/data/56b20bcb8/ea4e47a3600b449385ff50363d8f14a8 [2023-11-19 07:43:39,561 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-19 07:43:39,563 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-19 07:43:39,568 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-19 07:43:39,569 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-19 07:43:39,576 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-19 07:43:39,576 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:43:39" (1/1) ... [2023-11-19 07:43:39,578 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@374172d4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:39, skipping insertion in model container [2023-11-19 07:43:39,578 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:43:39" (1/1) ... [2023-11-19 07:43:39,658 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-19 07:43:40,028 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:43:40,046 INFO L202 MainTranslator]: Completed pre-run [2023-11-19 07:43:40,134 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:43:40,162 INFO L206 MainTranslator]: Completed translation [2023-11-19 07:43:40,162 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:40 WrapperNode [2023-11-19 07:43:40,163 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-19 07:43:40,164 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-19 07:43:40,164 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-19 07:43:40,164 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-19 07:43:40,173 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:40" (1/1) ... [2023-11-19 07:43:40,192 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:40" (1/1) ... [2023-11-19 07:43:40,334 INFO L138 Inliner]: procedures = 50, calls = 65, calls flagged for inlining = 60, calls inlined = 239, statements flattened = 3670 [2023-11-19 07:43:40,335 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-19 07:43:40,336 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-19 07:43:40,336 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-19 07:43:40,336 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-19 07:43:40,352 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:40" (1/1) ... [2023-11-19 07:43:40,352 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:40" (1/1) ... [2023-11-19 07:43:40,367 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:40" (1/1) ... [2023-11-19 07:43:40,367 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:40" (1/1) ... [2023-11-19 07:43:40,509 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:40" (1/1) ... [2023-11-19 07:43:40,576 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:40" (1/1) ... [2023-11-19 07:43:40,596 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:40" (1/1) ... [2023-11-19 07:43:40,611 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:40" (1/1) ... [2023-11-19 07:43:40,633 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-19 07:43:40,635 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-19 07:43:40,635 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-19 07:43:40,635 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-19 07:43:40,636 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:40" (1/1) ... [2023-11-19 07:43:40,644 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 07:43:40,658 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58eeb94c-6488-4a4a-8000-6d88ad22d624/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:43:40,672 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58eeb94c-6488-4a4a-8000-6d88ad22d624/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 07:43:40,702 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58eeb94c-6488-4a4a-8000-6d88ad22d624/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-19 07:43:40,726 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-19 07:43:40,727 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-19 07:43:40,727 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-19 07:43:40,728 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-19 07:43:40,901 INFO L236 CfgBuilder]: Building ICFG [2023-11-19 07:43:40,904 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-19 07:43:43,559 INFO L277 CfgBuilder]: Performing block encoding [2023-11-19 07:43:43,590 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-19 07:43:43,590 INFO L302 CfgBuilder]: Removed 14 assume(true) statements. [2023-11-19 07:43:43,614 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:43:43 BoogieIcfgContainer [2023-11-19 07:43:43,615 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-19 07:43:43,616 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-19 07:43:43,617 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-19 07:43:43,620 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-19 07:43:43,621 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:43:43,622 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 07:43:39" (1/3) ... [2023-11-19 07:43:43,623 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@eeaef1f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:43:43, skipping insertion in model container [2023-11-19 07:43:43,623 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:43:43,624 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:40" (2/3) ... [2023-11-19 07:43:43,625 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@eeaef1f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:43:43, skipping insertion in model container [2023-11-19 07:43:43,625 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:43:43,625 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:43:43" (3/3) ... [2023-11-19 07:43:43,626 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.11.cil-2.c [2023-11-19 07:43:43,745 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-19 07:43:43,746 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-19 07:43:43,746 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-19 07:43:43,746 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-19 07:43:43,746 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-19 07:43:43,746 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-19 07:43:43,747 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-19 07:43:43,747 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-19 07:43:43,759 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1585 states, 1584 states have (on average 1.4981060606060606) internal successors, (2373), 1584 states have internal predecessors, (2373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:43,868 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1430 [2023-11-19 07:43:43,868 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:43,868 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:43,888 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:43,889 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:43,889 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-19 07:43:43,894 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1585 states, 1584 states have (on average 1.4981060606060606) internal successors, (2373), 1584 states have internal predecessors, (2373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:43,926 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1430 [2023-11-19 07:43:43,926 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:43,926 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:43,947 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:43,948 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:43,992 INFO L748 eck$LassoCheckResult]: Stem: 123#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 1525#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 608#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1521#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 109#L780true assume !(1 == ~m_i~0);~m_st~0 := 2; 1157#L780-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1415#L785-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1091#L790-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1413#L795-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 302#L800-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 581#L805-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1101#L810-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1030#L815-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 250#L820-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 730#L825-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 193#L830-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 921#L835-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1471#L1109true assume !(0 == ~M_E~0); 956#L1109-2true assume !(0 == ~T1_E~0); 198#L1114-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1542#L1119-1true assume !(0 == ~T3_E~0); 1035#L1124-1true assume !(0 == ~T4_E~0); 21#L1129-1true assume !(0 == ~T5_E~0); 353#L1134-1true assume !(0 == ~T6_E~0); 940#L1139-1true assume !(0 == ~T7_E~0); 1013#L1144-1true assume !(0 == ~T8_E~0); 780#L1149-1true assume !(0 == ~T9_E~0); 72#L1154-1true assume 0 == ~T10_E~0;~T10_E~0 := 1; 915#L1159-1true assume !(0 == ~T11_E~0); 769#L1164-1true assume !(0 == ~E_M~0); 279#L1169-1true assume !(0 == ~E_1~0); 224#L1174-1true assume !(0 == ~E_2~0); 151#L1179-1true assume !(0 == ~E_3~0); 112#L1184-1true assume !(0 == ~E_4~0); 130#L1189-1true assume !(0 == ~E_5~0); 174#L1194-1true assume 0 == ~E_6~0;~E_6~0 := 1; 788#L1199-1true assume !(0 == ~E_7~0); 964#L1204-1true assume !(0 == ~E_8~0); 726#L1209-1true assume !(0 == ~E_9~0); 1183#L1214-1true assume !(0 == ~E_10~0); 1544#L1219-1true assume !(0 == ~E_11~0); 1489#L1224-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 290#L544true assume 1 == ~m_pc~0; 1026#L545true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1193#L555true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 516#is_master_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 92#L1379true assume !(0 != activate_threads_~tmp~1#1); 1408#L1379-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 567#L563true assume !(1 == ~t1_pc~0); 1189#L563-2true is_transmit1_triggered_~__retres1~1#1 := 0; 26#L574true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 825#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 671#L1387true assume !(0 != activate_threads_~tmp___0~0#1); 24#L1387-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 414#L582true assume 1 == ~t2_pc~0; 884#L583true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 679#L593true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 196#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 838#L1395true assume !(0 != activate_threads_~tmp___1~0#1); 40#L1395-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 759#L601true assume !(1 == ~t3_pc~0); 473#L601-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1008#L612true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 806#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 708#L1403true assume !(0 != activate_threads_~tmp___2~0#1); 1426#L1403-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 660#L620true assume 1 == ~t4_pc~0; 31#L621true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 370#L631true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 578#L1411true assume !(0 != activate_threads_~tmp___3~0#1); 760#L1411-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 743#L639true assume 1 == ~t5_pc~0; 637#L640true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 177#L650true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1281#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 593#L1419true assume !(0 != activate_threads_~tmp___4~0#1); 846#L1419-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 537#L658true assume !(1 == ~t6_pc~0); 288#L658-2true is_transmit6_triggered_~__retres1~6#1 := 0; 700#L669true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 191#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1497#L1427true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 712#L1427-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 203#L677true assume 1 == ~t7_pc~0; 1251#L678true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 887#L688true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1536#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1076#L1435true assume !(0 != activate_threads_~tmp___6~0#1); 1234#L1435-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1314#L696true assume !(1 == ~t8_pc~0); 325#L696-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1154#L707true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1237#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1360#L1443true assume !(0 != activate_threads_~tmp___7~0#1); 1540#L1443-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 628#L715true assume 1 == ~t9_pc~0; 1225#L716true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 387#L726true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 223#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 613#L1451true assume !(0 != activate_threads_~tmp___8~0#1); 1406#L1451-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 885#L734true assume !(1 == ~t10_pc~0); 1036#L734-2true is_transmit10_triggered_~__retres1~10#1 := 0; 264#L745true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1088#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 810#L1459true assume !(0 != activate_threads_~tmp___9~0#1); 1263#L1459-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 310#L753true assume 1 == ~t11_pc~0; 718#L754true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1583#L764true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1171#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 486#L1467true assume !(0 != activate_threads_~tmp___10~0#1); 774#L1467-2true havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 521#L1237true assume !(1 == ~M_E~0); 1307#L1237-2true assume !(1 == ~T1_E~0); 1438#L1242-1true assume !(1 == ~T2_E~0); 367#L1247-1true assume !(1 == ~T3_E~0); 1072#L1252-1true assume !(1 == ~T4_E~0); 232#L1257-1true assume !(1 == ~T5_E~0); 905#L1262-1true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1058#L1267-1true assume !(1 == ~T7_E~0); 1059#L1272-1true assume !(1 == ~T8_E~0); 421#L1277-1true assume !(1 == ~T9_E~0); 818#L1282-1true assume !(1 == ~T10_E~0); 754#L1287-1true assume !(1 == ~T11_E~0); 789#L1292-1true assume !(1 == ~E_M~0); 711#L1297-1true assume !(1 == ~E_1~0); 304#L1302-1true assume 1 == ~E_2~0;~E_2~0 := 2; 1039#L1307-1true assume !(1 == ~E_3~0); 1371#L1312-1true assume !(1 == ~E_4~0); 449#L1317-1true assume !(1 == ~E_5~0); 622#L1322-1true assume !(1 == ~E_6~0); 272#L1327-1true assume !(1 == ~E_7~0); 670#L1332-1true assume !(1 == ~E_8~0); 1350#L1337-1true assume !(1 == ~E_9~0); 617#L1342-1true assume 1 == ~E_10~0;~E_10~0 := 2; 1240#L1347-1true assume !(1 == ~E_11~0); 1038#L1352-1true assume { :end_inline_reset_delta_events } true; 1580#L1678-2true [2023-11-19 07:43:43,996 INFO L750 eck$LassoCheckResult]: Loop: 1580#L1678-2true assume !false; 662#L1679true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1286#L1084-1true assume !true; 477#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 301#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1442#L1109-3true assume 0 == ~M_E~0;~M_E~0 := 1; 32#L1109-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1218#L1114-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 713#L1119-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1575#L1124-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 740#L1129-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 948#L1134-3true assume !(0 == ~T6_E~0); 1122#L1139-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1024#L1144-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 295#L1149-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1569#L1154-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 453#L1159-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1553#L1164-3true assume 0 == ~E_M~0;~E_M~0 := 1; 657#L1169-3true assume 0 == ~E_1~0;~E_1~0 := 1; 980#L1174-3true assume !(0 == ~E_2~0); 702#L1179-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1316#L1184-3true assume 0 == ~E_4~0;~E_4~0 := 1; 865#L1189-3true assume 0 == ~E_5~0;~E_5~0 := 1; 561#L1194-3true assume 0 == ~E_6~0;~E_6~0 := 1; 163#L1199-3true assume 0 == ~E_7~0;~E_7~0 := 1; 791#L1204-3true assume 0 == ~E_8~0;~E_8~0 := 1; 284#L1209-3true assume 0 == ~E_9~0;~E_9~0 := 1; 10#L1214-3true assume !(0 == ~E_10~0); 607#L1219-3true assume 0 == ~E_11~0;~E_11~0 := 1; 395#L1224-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 650#L544-39true assume !(1 == ~m_pc~0); 4#L544-41true is_master_triggered_~__retres1~0#1 := 0; 742#L555-13true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 629#is_master_triggered_returnLabel#14true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 207#L1379-39true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 845#L1379-41true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1327#L563-39true assume !(1 == ~t1_pc~0); 70#L563-41true is_transmit1_triggered_~__retres1~1#1 := 0; 1554#L574-13true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1419#is_transmit1_triggered_returnLabel#14true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1453#L1387-39true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1464#L1387-41true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 994#L582-39true assume !(1 == ~t2_pc~0); 1248#L582-41true is_transmit2_triggered_~__retres1~2#1 := 0; 761#L593-13true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 434#is_transmit2_triggered_returnLabel#14true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 966#L1395-39true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 117#L1395-41true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15#L601-39true assume !(1 == ~t3_pc~0); 37#L601-41true is_transmit3_triggered_~__retres1~3#1 := 0; 803#L612-13true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1565#is_transmit3_triggered_returnLabel#14true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1510#L1403-39true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 853#L1403-41true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 535#L620-39true assume !(1 == ~t4_pc~0); 1560#L620-41true is_transmit4_triggered_~__retres1~4#1 := 0; 934#L631-13true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 553#is_transmit4_triggered_returnLabel#14true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 814#L1411-39true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1563#L1411-41true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1558#L639-39true assume !(1 == ~t5_pc~0); 1295#L639-41true is_transmit5_triggered_~__retres1~5#1 := 0; 371#L650-13true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 570#is_transmit5_triggered_returnLabel#14true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27#L1419-39true assume !(0 != activate_threads_~tmp___4~0#1); 1391#L1419-41true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 565#L658-39true assume !(1 == ~t6_pc~0); 1447#L658-41true is_transmit6_triggered_~__retres1~6#1 := 0; 1070#L669-13true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1494#is_transmit6_triggered_returnLabel#14true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 723#L1427-39true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 696#L1427-41true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1244#L677-39true assume 1 == ~t7_pc~0; 664#L678-13true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 111#L688-13true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 815#is_transmit7_triggered_returnLabel#14true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 141#L1435-39true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1381#L1435-41true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 488#L696-39true assume 1 == ~t8_pc~0; 460#L697-13true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 382#L707-13true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 935#is_transmit8_triggered_returnLabel#14true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 588#L1443-39true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 557#L1443-41true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 471#L715-39true assume 1 == ~t9_pc~0; 17#L716-13true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 812#L726-13true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53#is_transmit9_triggered_returnLabel#14true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1582#L1451-39true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 746#L1451-41true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1146#L734-39true assume !(1 == ~t10_pc~0); 278#L734-41true is_transmit10_triggered_~__retres1~10#1 := 0; 490#L745-13true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1167#is_transmit10_triggered_returnLabel#14true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 87#L1459-39true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1476#L1459-41true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1097#L753-39true assume !(1 == ~t11_pc~0); 51#L753-41true is_transmit11_triggered_~__retres1~11#1 := 0; 1010#L764-13true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 586#is_transmit11_triggered_returnLabel#14true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 464#L1467-39true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 753#L1467-41true havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 533#L1237-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1092#L1237-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 771#L1242-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1529#L1247-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1057#L1252-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 692#L1257-3true assume !(1 == ~T5_E~0); 1016#L1262-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1104#L1267-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1545#L1272-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1348#L1277-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 126#L1282-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 672#L1287-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 79#L1292-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1507#L1297-3true assume !(1 == ~E_1~0); 899#L1302-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1231#L1307-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1527#L1312-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1518#L1317-3true assume 1 == ~E_5~0;~E_5~0 := 2; 792#L1322-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1573#L1327-3true assume 1 == ~E_7~0;~E_7~0 := 2; 107#L1332-3true assume 1 == ~E_8~0;~E_8~0 := 2; 95#L1337-3true assume !(1 == ~E_9~0); 512#L1342-3true assume 1 == ~E_10~0;~E_10~0 := 2; 938#L1347-3true assume 1 == ~E_11~0;~E_11~0 := 2; 612#L1352-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 889#L848-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 212#L910-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 178#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 744#L1697true assume !(0 == start_simulation_~tmp~3#1); 528#L1697-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1319#L848-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 854#L910-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 1126#L1652true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 584#L1659true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1107#stop_simulation_returnLabel#1true start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 886#L1710true assume !(0 != start_simulation_~tmp___0~1#1); 1580#L1678-2true [2023-11-19 07:43:44,017 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:44,029 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 1 times [2023-11-19 07:43:44,040 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:44,041 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1622999241] [2023-11-19 07:43:44,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:44,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:44,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:44,461 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:44,462 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:44,463 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1622999241] [2023-11-19 07:43:44,463 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1622999241] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:44,464 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:44,464 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:44,466 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1543165194] [2023-11-19 07:43:44,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:44,472 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:44,473 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:44,473 INFO L85 PathProgramCache]: Analyzing trace with hash -784888959, now seen corresponding path program 1 times [2023-11-19 07:43:44,474 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:44,474 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [515935444] [2023-11-19 07:43:44,474 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:44,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:44,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:44,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:44,590 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:44,590 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [515935444] [2023-11-19 07:43:44,591 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [515935444] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:44,591 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:44,591 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:43:44,591 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [323584882] [2023-11-19 07:43:44,592 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:44,593 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:44,594 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:44,630 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2023-11-19 07:43:44,631 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2023-11-19 07:43:44,637 INFO L87 Difference]: Start difference. First operand has 1585 states, 1584 states have (on average 1.4981060606060606) internal successors, (2373), 1584 states have internal predecessors, (2373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 69.5) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:44,706 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:44,707 INFO L93 Difference]: Finished difference Result 1583 states and 2342 transitions. [2023-11-19 07:43:44,708 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1583 states and 2342 transitions. [2023-11-19 07:43:44,727 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2023-11-19 07:43:44,747 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1583 states to 1578 states and 2337 transitions. [2023-11-19 07:43:44,748 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2023-11-19 07:43:44,751 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2023-11-19 07:43:44,751 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2337 transitions. [2023-11-19 07:43:44,759 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:44,759 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2337 transitions. [2023-11-19 07:43:44,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2337 transitions. [2023-11-19 07:43:44,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2023-11-19 07:43:44,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.4809885931558935) internal successors, (2337), 1577 states have internal predecessors, (2337), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:44,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2337 transitions. [2023-11-19 07:43:44,855 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2337 transitions. [2023-11-19 07:43:44,856 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2023-11-19 07:43:44,859 INFO L428 stractBuchiCegarLoop]: Abstraction has 1578 states and 2337 transitions. [2023-11-19 07:43:44,860 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-19 07:43:44,860 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2337 transitions. [2023-11-19 07:43:44,872 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2023-11-19 07:43:44,872 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:44,872 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:44,876 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:44,876 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:44,876 INFO L748 eck$LassoCheckResult]: Stem: 3433#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 3434#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4214#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4215#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3407#L780 assume !(1 == ~m_i~0);~m_st~0 := 2; 3408#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4648#L785-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4617#L790-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4618#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3766#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3767#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4182#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4584#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3670#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3671#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 3561#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 3562#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4515#L1109 assume !(0 == ~M_E~0); 4532#L1109-2 assume !(0 == ~T1_E~0); 3570#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3571#L1119-1 assume !(0 == ~T3_E~0); 4587#L1124-1 assume !(0 == ~T4_E~0); 3221#L1129-1 assume !(0 == ~T5_E~0); 3222#L1134-1 assume !(0 == ~T6_E~0); 3853#L1139-1 assume !(0 == ~T7_E~0); 4523#L1144-1 assume !(0 == ~T8_E~0); 4393#L1149-1 assume !(0 == ~T9_E~0); 3332#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3333#L1159-1 assume !(0 == ~T11_E~0); 4383#L1164-1 assume !(0 == ~E_M~0); 3728#L1169-1 assume !(0 == ~E_1~0); 3622#L1174-1 assume !(0 == ~E_2~0); 3486#L1179-1 assume !(0 == ~E_3~0); 3413#L1184-1 assume !(0 == ~E_4~0); 3414#L1189-1 assume !(0 == ~E_5~0); 3446#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 3529#L1199-1 assume !(0 == ~E_7~0); 4402#L1204-1 assume !(0 == ~E_8~0); 4343#L1209-1 assume !(0 == ~E_9~0); 4344#L1214-1 assume !(0 == ~E_10~0); 4661#L1219-1 assume !(0 == ~E_11~0); 4748#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3745#L544 assume 1 == ~m_pc~0; 3746#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4571#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4101#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3375#L1379 assume !(0 != activate_threads_~tmp~1#1); 3376#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4169#L563 assume !(1 == ~t1_pc~0); 3975#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3231#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3232#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4291#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 3227#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3228#L582 assume 1 == ~t2_pc~0; 3953#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4296#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3566#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3567#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 3260#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3261#L601 assume !(1 == ~t3_pc~0); 3970#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3969#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4423#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4328#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 4329#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4277#L620 assume 1 == ~t4_pc~0; 3241#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3242#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3274#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3275#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 4179#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4361#L639 assume 1 == ~t5_pc~0; 4251#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3534#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3535#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4199#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 4200#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4134#L658 assume !(1 == ~t6_pc~0); 3742#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3743#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3558#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3559#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4332#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3581#L677 assume 1 == ~t7_pc~0; 3582#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3479#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4489#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4610#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 4611#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4681#L696 assume !(1 == ~t8_pc~0); 3806#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3807#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4646#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4684#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 4729#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4238#L715 assume 1 == ~t9_pc~0; 4239#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3906#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3620#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3621#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 4221#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4484#L734 assume !(1 == ~t10_pc~0); 4485#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3698#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3699#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4427#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 4428#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3780#L753 assume 1 == ~t11_pc~0; 3781#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4337#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4655#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4056#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 4057#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4108#L1237 assume !(1 == ~M_E~0); 4109#L1237-2 assume !(1 == ~T1_E~0); 4712#L1242-1 assume !(1 == ~T2_E~0); 3874#L1247-1 assume !(1 == ~T3_E~0); 3875#L1252-1 assume !(1 == ~T4_E~0); 3639#L1257-1 assume !(1 == ~T5_E~0); 3640#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4504#L1267-1 assume !(1 == ~T7_E~0); 4602#L1272-1 assume !(1 == ~T8_E~0); 3964#L1277-1 assume !(1 == ~T9_E~0); 3965#L1282-1 assume !(1 == ~T10_E~0); 4370#L1287-1 assume !(1 == ~T11_E~0); 4371#L1292-1 assume !(1 == ~E_M~0); 4331#L1297-1 assume !(1 == ~E_1~0); 3771#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3772#L1307-1 assume !(1 == ~E_3~0); 4591#L1312-1 assume !(1 == ~E_4~0); 4010#L1317-1 assume !(1 == ~E_5~0); 4011#L1322-1 assume !(1 == ~E_6~0); 3715#L1327-1 assume !(1 == ~E_7~0); 3716#L1332-1 assume !(1 == ~E_8~0); 4290#L1337-1 assume !(1 == ~E_9~0); 4224#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 4225#L1347-1 assume !(1 == ~E_11~0); 4590#L1352-1 assume { :end_inline_reset_delta_events } true; 4488#L1678-2 [2023-11-19 07:43:44,878 INFO L750 eck$LassoCheckResult]: Loop: 4488#L1678-2 assume !false; 4280#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4281#L1084-1 assume !false; 4077#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4078#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3351#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4576#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3271#L925 assume !(0 != eval_~tmp~0#1); 3273#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3764#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3765#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3244#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3245#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4333#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4334#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4358#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4359#L1134-3 assume !(0 == ~T6_E~0); 4528#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4579#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3755#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3756#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4017#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4018#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4273#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4274#L1174-3 assume !(0 == ~E_2~0); 4321#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4322#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4467#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4163#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3508#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3509#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3735#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3194#L1214-3 assume !(0 == ~E_10~0); 3195#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3918#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3919#L544-39 assume 1 == ~m_pc~0; 4265#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3183#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4241#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3589#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3590#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4454#L563-39 assume 1 == ~t1_pc~0; 4460#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3328#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4739#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4740#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4743#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4562#L582-39 assume 1 == ~t2_pc~0; 3651#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3652#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3987#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3988#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3422#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3206#L601-39 assume 1 == ~t3_pc~0; 3207#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3255#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4421#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4750#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4458#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4129#L620-39 assume 1 == ~t4_pc~0; 4130#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4319#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4154#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4155#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4431#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4754#L639-39 assume 1 == ~t5_pc~0; 4545#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3877#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3878#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3233#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 3234#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4166#L658-39 assume 1 == ~t6_pc~0; 4149#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4150#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4606#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4342#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4316#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4317#L677-39 assume !(1 == ~t7_pc~0); 3962#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 3411#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3412#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3467#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3468#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4059#L696-39 assume 1 == ~t8_pc~0; 4025#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3900#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3901#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4191#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4159#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4039#L715-39 assume 1 == ~t9_pc~0; 3211#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3213#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3288#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3289#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4364#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4365#L734-39 assume 1 == ~t10_pc~0; 4294#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3727#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4062#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3365#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3366#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4620#L753-39 assume !(1 == ~t11_pc~0); 3284#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 3285#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4188#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4030#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4031#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4126#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4127#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4385#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4386#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4601#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4309#L1257-3 assume !(1 == ~T5_E~0); 4310#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4574#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4623#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4726#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3438#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3439#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3348#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3349#L1297-3 assume !(1 == ~E_1~0); 4497#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4498#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4678#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4751#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4405#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4406#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3404#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3381#L1337-3 assume !(1 == ~E_9~0); 3382#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4097#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4219#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4220#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3330#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3536#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3537#L1697 assume !(0 == start_simulation_~tmp~3#1); 4116#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4117#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3455#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3223#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 3224#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4185#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4186#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 4487#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 4488#L1678-2 [2023-11-19 07:43:44,879 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:44,879 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 2 times [2023-11-19 07:43:44,879 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:44,879 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1622694756] [2023-11-19 07:43:44,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:44,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:44,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:45,031 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:45,031 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:45,031 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1622694756] [2023-11-19 07:43:45,032 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1622694756] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:45,032 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:45,032 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:45,033 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1851971777] [2023-11-19 07:43:45,033 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:45,033 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:45,034 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:45,034 INFO L85 PathProgramCache]: Analyzing trace with hash 705815280, now seen corresponding path program 1 times [2023-11-19 07:43:45,035 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:45,035 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [698218877] [2023-11-19 07:43:45,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:45,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:45,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:45,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:45,250 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:45,250 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [698218877] [2023-11-19 07:43:45,250 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [698218877] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:45,251 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:45,251 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:45,251 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [875297081] [2023-11-19 07:43:45,252 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:45,252 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:45,253 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:45,253 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:43:45,253 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:43:45,254 INFO L87 Difference]: Start difference. First operand 1578 states and 2337 transitions. cyclomatic complexity: 760 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:45,313 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:45,313 INFO L93 Difference]: Finished difference Result 1578 states and 2336 transitions. [2023-11-19 07:43:45,313 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2336 transitions. [2023-11-19 07:43:45,330 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2023-11-19 07:43:45,345 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2336 transitions. [2023-11-19 07:43:45,345 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2023-11-19 07:43:45,347 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2023-11-19 07:43:45,347 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2336 transitions. [2023-11-19 07:43:45,350 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:45,350 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2336 transitions. [2023-11-19 07:43:45,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2336 transitions. [2023-11-19 07:43:45,380 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2023-11-19 07:43:45,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.4803548795944232) internal successors, (2336), 1577 states have internal predecessors, (2336), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:45,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2336 transitions. [2023-11-19 07:43:45,392 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2336 transitions. [2023-11-19 07:43:45,394 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:43:45,396 INFO L428 stractBuchiCegarLoop]: Abstraction has 1578 states and 2336 transitions. [2023-11-19 07:43:45,396 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-19 07:43:45,396 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2336 transitions. [2023-11-19 07:43:45,409 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2023-11-19 07:43:45,410 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:45,410 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:45,414 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:45,420 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:45,422 INFO L748 eck$LassoCheckResult]: Stem: 6596#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 6597#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 7377#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7378#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6570#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 6571#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7811#L785-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 7780#L790-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7781#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6929#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6930#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7345#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7747#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6833#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6834#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 6724#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 6725#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7678#L1109 assume !(0 == ~M_E~0); 7695#L1109-2 assume !(0 == ~T1_E~0); 6733#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6734#L1119-1 assume !(0 == ~T3_E~0); 7750#L1124-1 assume !(0 == ~T4_E~0); 6384#L1129-1 assume !(0 == ~T5_E~0); 6385#L1134-1 assume !(0 == ~T6_E~0); 7016#L1139-1 assume !(0 == ~T7_E~0); 7686#L1144-1 assume !(0 == ~T8_E~0); 7556#L1149-1 assume !(0 == ~T9_E~0); 6495#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6496#L1159-1 assume !(0 == ~T11_E~0); 7546#L1164-1 assume !(0 == ~E_M~0); 6891#L1169-1 assume !(0 == ~E_1~0); 6785#L1174-1 assume !(0 == ~E_2~0); 6649#L1179-1 assume !(0 == ~E_3~0); 6576#L1184-1 assume !(0 == ~E_4~0); 6577#L1189-1 assume !(0 == ~E_5~0); 6609#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 6692#L1199-1 assume !(0 == ~E_7~0); 7565#L1204-1 assume !(0 == ~E_8~0); 7506#L1209-1 assume !(0 == ~E_9~0); 7507#L1214-1 assume !(0 == ~E_10~0); 7824#L1219-1 assume !(0 == ~E_11~0); 7911#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6908#L544 assume 1 == ~m_pc~0; 6909#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7734#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7264#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6538#L1379 assume !(0 != activate_threads_~tmp~1#1); 6539#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7332#L563 assume !(1 == ~t1_pc~0); 7138#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6394#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6395#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7454#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 6390#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6391#L582 assume 1 == ~t2_pc~0; 7116#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7459#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6729#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6730#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 6423#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6424#L601 assume !(1 == ~t3_pc~0); 7133#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7132#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7586#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7491#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 7492#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7440#L620 assume 1 == ~t4_pc~0; 6404#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6405#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6437#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6438#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 7342#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7524#L639 assume 1 == ~t5_pc~0; 7414#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6697#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6698#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7362#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 7363#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7297#L658 assume !(1 == ~t6_pc~0); 6905#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6906#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6721#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6722#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7495#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6744#L677 assume 1 == ~t7_pc~0; 6745#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6642#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7652#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7773#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 7774#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7844#L696 assume !(1 == ~t8_pc~0); 6969#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6970#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7809#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7847#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 7892#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7401#L715 assume 1 == ~t9_pc~0; 7402#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7069#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6783#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6784#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 7384#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7647#L734 assume !(1 == ~t10_pc~0); 7648#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6861#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6862#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7590#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 7591#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6943#L753 assume 1 == ~t11_pc~0; 6944#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7500#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7818#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7219#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 7220#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7271#L1237 assume !(1 == ~M_E~0); 7272#L1237-2 assume !(1 == ~T1_E~0); 7875#L1242-1 assume !(1 == ~T2_E~0); 7037#L1247-1 assume !(1 == ~T3_E~0); 7038#L1252-1 assume !(1 == ~T4_E~0); 6802#L1257-1 assume !(1 == ~T5_E~0); 6803#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7667#L1267-1 assume !(1 == ~T7_E~0); 7765#L1272-1 assume !(1 == ~T8_E~0); 7127#L1277-1 assume !(1 == ~T9_E~0); 7128#L1282-1 assume !(1 == ~T10_E~0); 7533#L1287-1 assume !(1 == ~T11_E~0); 7534#L1292-1 assume !(1 == ~E_M~0); 7494#L1297-1 assume !(1 == ~E_1~0); 6934#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6935#L1307-1 assume !(1 == ~E_3~0); 7754#L1312-1 assume !(1 == ~E_4~0); 7173#L1317-1 assume !(1 == ~E_5~0); 7174#L1322-1 assume !(1 == ~E_6~0); 6878#L1327-1 assume !(1 == ~E_7~0); 6879#L1332-1 assume !(1 == ~E_8~0); 7453#L1337-1 assume !(1 == ~E_9~0); 7387#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 7388#L1347-1 assume !(1 == ~E_11~0); 7753#L1352-1 assume { :end_inline_reset_delta_events } true; 7651#L1678-2 [2023-11-19 07:43:45,423 INFO L750 eck$LassoCheckResult]: Loop: 7651#L1678-2 assume !false; 7443#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7444#L1084-1 assume !false; 7240#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7241#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6514#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 7739#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6434#L925 assume !(0 != eval_~tmp~0#1); 6436#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6927#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6928#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6407#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6408#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7496#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7497#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7521#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7522#L1134-3 assume !(0 == ~T6_E~0); 7691#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7742#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6918#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6919#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7180#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 7181#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7436#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7437#L1174-3 assume !(0 == ~E_2~0); 7484#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7485#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7630#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7326#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6671#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6672#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6898#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6357#L1214-3 assume !(0 == ~E_10~0); 6358#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7081#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7082#L544-39 assume 1 == ~m_pc~0; 7428#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6346#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7404#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6752#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6753#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7617#L563-39 assume 1 == ~t1_pc~0; 7623#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6491#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7902#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7903#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7906#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7725#L582-39 assume !(1 == ~t2_pc~0); 6816#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 6815#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7150#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7151#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6585#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6369#L601-39 assume 1 == ~t3_pc~0; 6370#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6418#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7584#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7913#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7621#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7292#L620-39 assume 1 == ~t4_pc~0; 7293#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7482#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7317#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7318#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7594#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7917#L639-39 assume 1 == ~t5_pc~0; 7708#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7040#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7041#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6396#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 6397#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7329#L658-39 assume 1 == ~t6_pc~0; 7312#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7313#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7769#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7505#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7479#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7480#L677-39 assume !(1 == ~t7_pc~0); 7125#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 6574#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6575#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6630#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6631#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7222#L696-39 assume 1 == ~t8_pc~0; 7188#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7063#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7064#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7354#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7322#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7202#L715-39 assume 1 == ~t9_pc~0; 6374#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6376#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6451#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6452#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7527#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7528#L734-39 assume 1 == ~t10_pc~0; 7457#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 6890#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7225#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6528#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6529#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7783#L753-39 assume !(1 == ~t11_pc~0); 6447#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 6448#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7351#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7193#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7194#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7289#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7290#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7548#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7549#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7764#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7472#L1257-3 assume !(1 == ~T5_E~0); 7473#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7737#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7786#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7889#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6601#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6602#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 6511#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6512#L1297-3 assume !(1 == ~E_1~0); 7660#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7661#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7841#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7914#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7568#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7569#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6567#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6544#L1337-3 assume !(1 == ~E_9~0); 6545#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7260#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 7382#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7383#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6493#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6699#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 6700#L1697 assume !(0 == start_simulation_~tmp~3#1); 7279#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7280#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6618#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6386#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 6387#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7348#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7349#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 7650#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 7651#L1678-2 [2023-11-19 07:43:45,424 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:45,424 INFO L85 PathProgramCache]: Analyzing trace with hash -968871490, now seen corresponding path program 1 times [2023-11-19 07:43:45,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:45,425 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [374776135] [2023-11-19 07:43:45,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:45,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:45,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:45,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:45,528 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:45,528 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [374776135] [2023-11-19 07:43:45,528 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [374776135] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:45,528 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:45,529 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:45,529 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1531281101] [2023-11-19 07:43:45,529 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:45,530 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:45,531 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:45,531 INFO L85 PathProgramCache]: Analyzing trace with hash -1155596751, now seen corresponding path program 1 times [2023-11-19 07:43:45,531 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:45,532 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [111130879] [2023-11-19 07:43:45,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:45,533 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:45,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:45,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:45,643 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:45,643 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [111130879] [2023-11-19 07:43:45,644 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [111130879] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:45,672 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:45,672 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:45,672 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [419089147] [2023-11-19 07:43:45,672 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:45,673 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:45,673 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:45,673 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:43:45,674 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:43:45,674 INFO L87 Difference]: Start difference. First operand 1578 states and 2336 transitions. cyclomatic complexity: 759 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:45,716 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:45,716 INFO L93 Difference]: Finished difference Result 1578 states and 2335 transitions. [2023-11-19 07:43:45,717 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2335 transitions. [2023-11-19 07:43:45,731 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2023-11-19 07:43:45,745 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2335 transitions. [2023-11-19 07:43:45,745 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2023-11-19 07:43:45,747 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2023-11-19 07:43:45,747 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2335 transitions. [2023-11-19 07:43:45,750 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:45,750 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2335 transitions. [2023-11-19 07:43:45,753 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2335 transitions. [2023-11-19 07:43:45,776 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2023-11-19 07:43:45,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.479721166032953) internal successors, (2335), 1577 states have internal predecessors, (2335), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:45,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2335 transitions. [2023-11-19 07:43:45,788 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2335 transitions. [2023-11-19 07:43:45,788 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:43:45,790 INFO L428 stractBuchiCegarLoop]: Abstraction has 1578 states and 2335 transitions. [2023-11-19 07:43:45,791 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-19 07:43:45,791 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2335 transitions. [2023-11-19 07:43:45,803 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2023-11-19 07:43:45,803 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:45,803 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:45,806 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:45,806 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:45,807 INFO L748 eck$LassoCheckResult]: Stem: 9759#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 9760#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 10541#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10542#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9733#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 9734#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10974#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10943#L790-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10944#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10092#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10093#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10508#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10910#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9998#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9999#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9887#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9888#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10843#L1109 assume !(0 == ~M_E~0); 10858#L1109-2 assume !(0 == ~T1_E~0); 9896#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9897#L1119-1 assume !(0 == ~T3_E~0); 10913#L1124-1 assume !(0 == ~T4_E~0); 9547#L1129-1 assume !(0 == ~T5_E~0); 9548#L1134-1 assume !(0 == ~T6_E~0); 10179#L1139-1 assume !(0 == ~T7_E~0); 10849#L1144-1 assume !(0 == ~T8_E~0); 10719#L1149-1 assume !(0 == ~T9_E~0); 9660#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9661#L1159-1 assume !(0 == ~T11_E~0); 10709#L1164-1 assume !(0 == ~E_M~0); 10054#L1169-1 assume !(0 == ~E_1~0); 9948#L1174-1 assume !(0 == ~E_2~0); 9817#L1179-1 assume !(0 == ~E_3~0); 9739#L1184-1 assume !(0 == ~E_4~0); 9740#L1189-1 assume !(0 == ~E_5~0); 9772#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 9859#L1199-1 assume !(0 == ~E_7~0); 10728#L1204-1 assume !(0 == ~E_8~0); 10670#L1209-1 assume !(0 == ~E_9~0); 10671#L1214-1 assume !(0 == ~E_10~0); 10987#L1219-1 assume !(0 == ~E_11~0); 11074#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10073#L544 assume 1 == ~m_pc~0; 10074#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10897#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10427#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9701#L1379 assume !(0 != activate_threads_~tmp~1#1); 9702#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10497#L563 assume !(1 == ~t1_pc~0); 10301#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9557#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9558#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10617#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 9553#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9554#L582 assume 1 == ~t2_pc~0; 10279#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10622#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9892#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9893#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 9586#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9587#L601 assume !(1 == ~t3_pc~0); 10296#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10295#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10749#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10654#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 10655#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10603#L620 assume 1 == ~t4_pc~0; 9567#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9568#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9600#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9601#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 10505#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10688#L639 assume 1 == ~t5_pc~0; 10577#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9862#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9863#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10525#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 10526#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10462#L658 assume !(1 == ~t6_pc~0); 10068#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10069#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9884#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9885#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10658#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9909#L677 assume 1 == ~t7_pc~0; 9910#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9808#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10815#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10936#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 10937#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11007#L696 assume !(1 == ~t8_pc~0); 10133#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10134#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10972#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11010#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 11055#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10564#L715 assume 1 == ~t9_pc~0; 10565#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10232#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9946#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9947#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 10547#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10812#L734 assume !(1 == ~t10_pc~0); 10813#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 10024#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10025#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10753#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 10754#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10106#L753 assume 1 == ~t11_pc~0; 10107#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10663#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10981#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10384#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 10385#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10436#L1237 assume !(1 == ~M_E~0); 10437#L1237-2 assume !(1 == ~T1_E~0); 11039#L1242-1 assume !(1 == ~T2_E~0); 10200#L1247-1 assume !(1 == ~T3_E~0); 10201#L1252-1 assume !(1 == ~T4_E~0); 9965#L1257-1 assume !(1 == ~T5_E~0); 9966#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10830#L1267-1 assume !(1 == ~T7_E~0); 10928#L1272-1 assume !(1 == ~T8_E~0); 10290#L1277-1 assume !(1 == ~T9_E~0); 10291#L1282-1 assume !(1 == ~T10_E~0); 10696#L1287-1 assume !(1 == ~T11_E~0); 10697#L1292-1 assume !(1 == ~E_M~0); 10657#L1297-1 assume !(1 == ~E_1~0); 10097#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 10098#L1307-1 assume !(1 == ~E_3~0); 10917#L1312-1 assume !(1 == ~E_4~0); 10336#L1317-1 assume !(1 == ~E_5~0); 10337#L1322-1 assume !(1 == ~E_6~0); 10043#L1327-1 assume !(1 == ~E_7~0); 10044#L1332-1 assume !(1 == ~E_8~0); 10616#L1337-1 assume !(1 == ~E_9~0); 10550#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 10551#L1347-1 assume !(1 == ~E_11~0); 10916#L1352-1 assume { :end_inline_reset_delta_events } true; 10811#L1678-2 [2023-11-19 07:43:45,807 INFO L750 eck$LassoCheckResult]: Loop: 10811#L1678-2 assume !false; 10608#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10609#L1084-1 assume !false; 10403#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10404#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9677#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10902#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9597#L925 assume !(0 != eval_~tmp~0#1); 9599#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10090#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10091#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9570#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9571#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10659#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10660#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10685#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10686#L1134-3 assume !(0 == ~T6_E~0); 10854#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10905#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10081#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10082#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 10343#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 10344#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10599#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10600#L1174-3 assume !(0 == ~E_2~0); 10647#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10648#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10793#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10489#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9834#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9835#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10061#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9520#L1214-3 assume !(0 == ~E_10~0); 9521#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10244#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10245#L544-39 assume !(1 == ~m_pc~0); 9508#L544-41 is_master_triggered_~__retres1~0#1 := 0; 9509#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10567#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9915#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9916#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10780#L563-39 assume 1 == ~t1_pc~0; 10786#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9654#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11065#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11066#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11069#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10888#L582-39 assume 1 == ~t2_pc~0; 9977#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9978#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10313#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10314#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9748#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9532#L601-39 assume 1 == ~t3_pc~0; 9533#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9581#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10747#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11076#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10784#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10455#L620-39 assume 1 == ~t4_pc~0; 10456#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10645#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10480#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10481#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10757#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11080#L639-39 assume 1 == ~t5_pc~0; 10871#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10203#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10204#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9559#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 9560#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10492#L658-39 assume 1 == ~t6_pc~0; 10475#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10476#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10932#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10668#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10642#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10643#L677-39 assume !(1 == ~t7_pc~0); 10288#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 9737#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9738#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9793#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9794#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10383#L696-39 assume !(1 == ~t8_pc~0); 10352#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 10226#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10227#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10517#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10485#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10365#L715-39 assume 1 == ~t9_pc~0; 9537#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9539#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9614#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9615#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10690#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10691#L734-39 assume !(1 == ~t10_pc~0); 10052#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 10053#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10388#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9691#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9692#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10946#L753-39 assume !(1 == ~t11_pc~0); 9610#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 9611#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10514#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10356#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 10357#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10452#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10453#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10711#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10712#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10927#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10635#L1257-3 assume !(1 == ~T5_E~0); 10636#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10900#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10949#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11052#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9764#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9765#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9674#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9675#L1297-3 assume !(1 == ~E_1~0); 10823#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10824#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11004#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11077#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10731#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10732#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9730#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9707#L1337-3 assume !(1 == ~E_9~0); 9708#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10423#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 10545#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10546#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9656#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9860#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 9861#L1697 assume !(0 == start_simulation_~tmp~3#1); 10442#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10443#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9781#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9549#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 9550#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10511#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10512#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 10810#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 10811#L1678-2 [2023-11-19 07:43:45,808 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:45,808 INFO L85 PathProgramCache]: Analyzing trace with hash -1332337988, now seen corresponding path program 1 times [2023-11-19 07:43:45,808 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:45,809 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [922387540] [2023-11-19 07:43:45,809 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:45,809 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:45,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:45,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:45,868 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:45,869 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [922387540] [2023-11-19 07:43:45,869 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [922387540] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:45,869 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:45,869 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:45,870 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1609853218] [2023-11-19 07:43:45,870 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:45,870 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:45,871 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:45,871 INFO L85 PathProgramCache]: Analyzing trace with hash -2057024077, now seen corresponding path program 1 times [2023-11-19 07:43:45,871 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:45,876 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1242939620] [2023-11-19 07:43:45,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:45,876 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:45,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:45,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:45,967 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:45,967 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1242939620] [2023-11-19 07:43:45,967 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1242939620] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:45,968 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:45,968 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:45,968 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1464313680] [2023-11-19 07:43:45,968 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:45,969 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:45,969 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:45,969 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:43:45,970 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:43:45,970 INFO L87 Difference]: Start difference. First operand 1578 states and 2335 transitions. cyclomatic complexity: 758 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:46,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:46,021 INFO L93 Difference]: Finished difference Result 1578 states and 2334 transitions. [2023-11-19 07:43:46,021 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2334 transitions. [2023-11-19 07:43:46,036 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2023-11-19 07:43:46,050 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2334 transitions. [2023-11-19 07:43:46,050 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2023-11-19 07:43:46,052 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2023-11-19 07:43:46,052 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2334 transitions. [2023-11-19 07:43:46,055 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:46,056 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2334 transitions. [2023-11-19 07:43:46,059 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2334 transitions. [2023-11-19 07:43:46,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2023-11-19 07:43:46,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.479087452471483) internal successors, (2334), 1577 states have internal predecessors, (2334), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:46,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2334 transitions. [2023-11-19 07:43:46,093 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2334 transitions. [2023-11-19 07:43:46,093 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:43:46,095 INFO L428 stractBuchiCegarLoop]: Abstraction has 1578 states and 2334 transitions. [2023-11-19 07:43:46,095 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-19 07:43:46,098 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2334 transitions. [2023-11-19 07:43:46,109 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2023-11-19 07:43:46,109 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:46,109 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:46,112 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:46,112 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:46,112 INFO L748 eck$LassoCheckResult]: Stem: 12922#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 12923#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 13703#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13704#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12896#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 12897#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14137#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14106#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14107#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13255#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13256#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13671#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14073#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13159#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13160#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13050#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13051#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14004#L1109 assume !(0 == ~M_E~0); 14021#L1109-2 assume !(0 == ~T1_E~0); 13059#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13060#L1119-1 assume !(0 == ~T3_E~0); 14076#L1124-1 assume !(0 == ~T4_E~0); 12710#L1129-1 assume !(0 == ~T5_E~0); 12711#L1134-1 assume !(0 == ~T6_E~0); 13342#L1139-1 assume !(0 == ~T7_E~0); 14012#L1144-1 assume !(0 == ~T8_E~0); 13882#L1149-1 assume !(0 == ~T9_E~0); 12821#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12822#L1159-1 assume !(0 == ~T11_E~0); 13872#L1164-1 assume !(0 == ~E_M~0); 13217#L1169-1 assume !(0 == ~E_1~0); 13111#L1174-1 assume !(0 == ~E_2~0); 12977#L1179-1 assume !(0 == ~E_3~0); 12902#L1184-1 assume !(0 == ~E_4~0); 12903#L1189-1 assume !(0 == ~E_5~0); 12935#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 13018#L1199-1 assume !(0 == ~E_7~0); 13891#L1204-1 assume !(0 == ~E_8~0); 13832#L1209-1 assume !(0 == ~E_9~0); 13833#L1214-1 assume !(0 == ~E_10~0); 14150#L1219-1 assume !(0 == ~E_11~0); 14237#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13234#L544 assume 1 == ~m_pc~0; 13235#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14060#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13590#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12864#L1379 assume !(0 != activate_threads_~tmp~1#1); 12865#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13658#L563 assume !(1 == ~t1_pc~0); 13464#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12720#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12721#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13780#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 12716#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12717#L582 assume 1 == ~t2_pc~0; 13442#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13785#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13055#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13056#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 12749#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12750#L601 assume !(1 == ~t3_pc~0); 13459#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13458#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13912#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13817#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 13818#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13766#L620 assume 1 == ~t4_pc~0; 12730#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12731#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12763#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12764#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 13668#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13851#L639 assume 1 == ~t5_pc~0; 13740#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13025#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13026#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13688#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 13689#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13623#L658 assume !(1 == ~t6_pc~0); 13231#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 13232#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13047#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13048#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13821#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13070#L677 assume 1 == ~t7_pc~0; 13071#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12968#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13978#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14099#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 14100#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14170#L696 assume !(1 == ~t8_pc~0); 13295#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 13296#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14135#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14173#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 14218#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13727#L715 assume 1 == ~t9_pc~0; 13728#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13395#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13109#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13110#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 13710#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13975#L734 assume !(1 == ~t10_pc~0); 13976#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 13187#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13188#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13916#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 13917#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13269#L753 assume 1 == ~t11_pc~0; 13270#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13826#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14144#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13546#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 13547#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13597#L1237 assume !(1 == ~M_E~0); 13598#L1237-2 assume !(1 == ~T1_E~0); 14201#L1242-1 assume !(1 == ~T2_E~0); 13363#L1247-1 assume !(1 == ~T3_E~0); 13364#L1252-1 assume !(1 == ~T4_E~0); 13128#L1257-1 assume !(1 == ~T5_E~0); 13129#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13993#L1267-1 assume !(1 == ~T7_E~0); 14091#L1272-1 assume !(1 == ~T8_E~0); 13453#L1277-1 assume !(1 == ~T9_E~0); 13454#L1282-1 assume !(1 == ~T10_E~0); 13859#L1287-1 assume !(1 == ~T11_E~0); 13860#L1292-1 assume !(1 == ~E_M~0); 13820#L1297-1 assume !(1 == ~E_1~0); 13260#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 13261#L1307-1 assume !(1 == ~E_3~0); 14080#L1312-1 assume !(1 == ~E_4~0); 13499#L1317-1 assume !(1 == ~E_5~0); 13500#L1322-1 assume !(1 == ~E_6~0); 13204#L1327-1 assume !(1 == ~E_7~0); 13205#L1332-1 assume !(1 == ~E_8~0); 13779#L1337-1 assume !(1 == ~E_9~0); 13713#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 13714#L1347-1 assume !(1 == ~E_11~0); 14079#L1352-1 assume { :end_inline_reset_delta_events } true; 13974#L1678-2 [2023-11-19 07:43:46,113 INFO L750 eck$LassoCheckResult]: Loop: 13974#L1678-2 assume !false; 13769#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13770#L1084-1 assume !false; 13566#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13567#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12840#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 14065#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12760#L925 assume !(0 != eval_~tmp~0#1); 12762#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13253#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13254#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12733#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12734#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13822#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13823#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13847#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13848#L1134-3 assume !(0 == ~T6_E~0); 14017#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14068#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13244#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13245#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13506#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13507#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13762#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13763#L1174-3 assume !(0 == ~E_2~0); 13810#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13811#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13956#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13652#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13000#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13001#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13226#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12686#L1214-3 assume !(0 == ~E_10~0); 12687#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 13407#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13408#L544-39 assume 1 == ~m_pc~0; 13755#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12672#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13730#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13078#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13079#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13943#L563-39 assume !(1 == ~t1_pc~0); 12819#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 12820#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14228#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14229#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14232#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14051#L582-39 assume 1 == ~t2_pc~0; 13140#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13141#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13476#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13477#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12911#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12695#L601-39 assume 1 == ~t3_pc~0; 12696#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12744#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13910#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14239#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13947#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13620#L620-39 assume 1 == ~t4_pc~0; 13621#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13808#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13643#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13644#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13920#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14243#L639-39 assume 1 == ~t5_pc~0; 14034#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13366#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13367#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12722#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 12723#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13655#L658-39 assume 1 == ~t6_pc~0; 13638#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13639#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14095#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13831#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13805#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13806#L677-39 assume !(1 == ~t7_pc~0); 13448#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 12898#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12899#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12956#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12957#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13545#L696-39 assume 1 == ~t8_pc~0; 13514#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13389#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13390#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13680#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13648#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13526#L715-39 assume 1 == ~t9_pc~0; 12698#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12700#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12775#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12776#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13853#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13854#L734-39 assume 1 == ~t10_pc~0; 13783#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13216#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13551#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12854#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12855#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14109#L753-39 assume !(1 == ~t11_pc~0); 12773#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 12774#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13677#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13519#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 13520#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13611#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13612#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13874#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13875#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14089#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13798#L1257-3 assume !(1 == ~T5_E~0); 13799#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14062#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14112#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14215#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12926#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12927#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12837#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12838#L1297-3 assume !(1 == ~E_1~0); 13983#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13984#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14167#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14240#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13894#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13895#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12893#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12870#L1337-3 assume !(1 == ~E_9~0); 12871#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13586#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 13706#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13707#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12814#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13023#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 13024#L1697 assume !(0 == start_simulation_~tmp~3#1); 13605#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13606#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12944#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12712#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 12713#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13674#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13675#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 13973#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 13974#L1678-2 [2023-11-19 07:43:46,115 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:46,115 INFO L85 PathProgramCache]: Analyzing trace with hash -1621157378, now seen corresponding path program 1 times [2023-11-19 07:43:46,116 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:46,116 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1240160168] [2023-11-19 07:43:46,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:46,116 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:46,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:46,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:46,205 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:46,206 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1240160168] [2023-11-19 07:43:46,206 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1240160168] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:46,206 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:46,206 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:46,206 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1102351331] [2023-11-19 07:43:46,206 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:46,207 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:46,207 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:46,207 INFO L85 PathProgramCache]: Analyzing trace with hash -1273771663, now seen corresponding path program 1 times [2023-11-19 07:43:46,207 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:46,208 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [798979143] [2023-11-19 07:43:46,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:46,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:46,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:46,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:46,276 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:46,276 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [798979143] [2023-11-19 07:43:46,276 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [798979143] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:46,277 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:46,277 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:46,277 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [736044723] [2023-11-19 07:43:46,277 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:46,277 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:46,278 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:46,278 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:43:46,278 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:43:46,278 INFO L87 Difference]: Start difference. First operand 1578 states and 2334 transitions. cyclomatic complexity: 757 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:46,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:46,320 INFO L93 Difference]: Finished difference Result 1578 states and 2333 transitions. [2023-11-19 07:43:46,320 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2333 transitions. [2023-11-19 07:43:46,334 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2023-11-19 07:43:46,348 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2333 transitions. [2023-11-19 07:43:46,349 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2023-11-19 07:43:46,350 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2023-11-19 07:43:46,351 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2333 transitions. [2023-11-19 07:43:46,353 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:46,353 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2333 transitions. [2023-11-19 07:43:46,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2333 transitions. [2023-11-19 07:43:46,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2023-11-19 07:43:46,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.4784537389100127) internal successors, (2333), 1577 states have internal predecessors, (2333), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:46,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2333 transitions. [2023-11-19 07:43:46,388 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2333 transitions. [2023-11-19 07:43:46,389 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:43:46,390 INFO L428 stractBuchiCegarLoop]: Abstraction has 1578 states and 2333 transitions. [2023-11-19 07:43:46,390 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-19 07:43:46,390 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2333 transitions. [2023-11-19 07:43:46,400 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2023-11-19 07:43:46,400 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:46,400 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:46,403 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:46,403 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:46,404 INFO L748 eck$LassoCheckResult]: Stem: 16085#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 16086#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 16866#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16867#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16059#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 16060#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17300#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17269#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17270#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16418#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 16419#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 16834#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17236#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16322#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16323#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16213#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16214#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17167#L1109 assume !(0 == ~M_E~0); 17184#L1109-2 assume !(0 == ~T1_E~0); 16222#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16223#L1119-1 assume !(0 == ~T3_E~0); 17239#L1124-1 assume !(0 == ~T4_E~0); 15873#L1129-1 assume !(0 == ~T5_E~0); 15874#L1134-1 assume !(0 == ~T6_E~0); 16505#L1139-1 assume !(0 == ~T7_E~0); 17175#L1144-1 assume !(0 == ~T8_E~0); 17045#L1149-1 assume !(0 == ~T9_E~0); 15984#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15985#L1159-1 assume !(0 == ~T11_E~0); 17035#L1164-1 assume !(0 == ~E_M~0); 16380#L1169-1 assume !(0 == ~E_1~0); 16274#L1174-1 assume !(0 == ~E_2~0); 16138#L1179-1 assume !(0 == ~E_3~0); 16065#L1184-1 assume !(0 == ~E_4~0); 16066#L1189-1 assume !(0 == ~E_5~0); 16098#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 16181#L1199-1 assume !(0 == ~E_7~0); 17054#L1204-1 assume !(0 == ~E_8~0); 16995#L1209-1 assume !(0 == ~E_9~0); 16996#L1214-1 assume !(0 == ~E_10~0); 17313#L1219-1 assume !(0 == ~E_11~0); 17400#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16397#L544 assume 1 == ~m_pc~0; 16398#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17223#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16753#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16027#L1379 assume !(0 != activate_threads_~tmp~1#1); 16028#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16821#L563 assume !(1 == ~t1_pc~0); 16627#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15883#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15884#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16943#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 15879#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15880#L582 assume 1 == ~t2_pc~0; 16605#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16948#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16218#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16219#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 15912#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15913#L601 assume !(1 == ~t3_pc~0); 16622#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16621#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17075#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16980#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 16981#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16929#L620 assume 1 == ~t4_pc~0; 15893#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15894#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15926#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15927#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 16831#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17013#L639 assume 1 == ~t5_pc~0; 16903#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16186#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16187#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16851#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 16852#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16786#L658 assume !(1 == ~t6_pc~0); 16394#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16395#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16210#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16211#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16984#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16233#L677 assume 1 == ~t7_pc~0; 16234#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16131#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17141#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17262#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 17263#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17333#L696 assume !(1 == ~t8_pc~0); 16458#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16459#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17298#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17336#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 17381#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16890#L715 assume 1 == ~t9_pc~0; 16891#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16558#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16272#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16273#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 16873#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17136#L734 assume !(1 == ~t10_pc~0); 17137#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16350#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16351#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17079#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 17080#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16432#L753 assume 1 == ~t11_pc~0; 16433#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16989#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17307#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16708#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 16709#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16760#L1237 assume !(1 == ~M_E~0); 16761#L1237-2 assume !(1 == ~T1_E~0); 17364#L1242-1 assume !(1 == ~T2_E~0); 16526#L1247-1 assume !(1 == ~T3_E~0); 16527#L1252-1 assume !(1 == ~T4_E~0); 16291#L1257-1 assume !(1 == ~T5_E~0); 16292#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17156#L1267-1 assume !(1 == ~T7_E~0); 17254#L1272-1 assume !(1 == ~T8_E~0); 16616#L1277-1 assume !(1 == ~T9_E~0); 16617#L1282-1 assume !(1 == ~T10_E~0); 17022#L1287-1 assume !(1 == ~T11_E~0); 17023#L1292-1 assume !(1 == ~E_M~0); 16983#L1297-1 assume !(1 == ~E_1~0); 16423#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 16424#L1307-1 assume !(1 == ~E_3~0); 17243#L1312-1 assume !(1 == ~E_4~0); 16662#L1317-1 assume !(1 == ~E_5~0); 16663#L1322-1 assume !(1 == ~E_6~0); 16367#L1327-1 assume !(1 == ~E_7~0); 16368#L1332-1 assume !(1 == ~E_8~0); 16942#L1337-1 assume !(1 == ~E_9~0); 16876#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 16877#L1347-1 assume !(1 == ~E_11~0); 17242#L1352-1 assume { :end_inline_reset_delta_events } true; 17140#L1678-2 [2023-11-19 07:43:46,404 INFO L750 eck$LassoCheckResult]: Loop: 17140#L1678-2 assume !false; 16932#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16933#L1084-1 assume !false; 16729#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16730#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 16003#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 17228#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15923#L925 assume !(0 != eval_~tmp~0#1); 15925#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16416#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16417#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15896#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15897#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16985#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16986#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17010#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17011#L1134-3 assume !(0 == ~T6_E~0); 17180#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17231#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16407#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16408#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16669#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 16670#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16925#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16926#L1174-3 assume !(0 == ~E_2~0); 16973#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16974#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17119#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16815#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16160#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16161#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16387#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15846#L1214-3 assume !(0 == ~E_10~0); 15847#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16570#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16571#L544-39 assume 1 == ~m_pc~0; 16917#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15835#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16893#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16241#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16242#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17106#L563-39 assume 1 == ~t1_pc~0; 17112#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15980#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17391#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17392#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17395#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17214#L582-39 assume !(1 == ~t2_pc~0); 16305#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 16304#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16639#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16640#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16074#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15858#L601-39 assume 1 == ~t3_pc~0; 15859#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15907#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17073#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17402#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17110#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16781#L620-39 assume 1 == ~t4_pc~0; 16782#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16971#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16806#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16807#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17083#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17406#L639-39 assume 1 == ~t5_pc~0; 17197#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16529#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16530#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15885#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 15886#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16818#L658-39 assume 1 == ~t6_pc~0; 16801#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16802#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17258#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16994#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16968#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16969#L677-39 assume !(1 == ~t7_pc~0); 16614#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 16063#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16064#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16119#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16120#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16711#L696-39 assume 1 == ~t8_pc~0; 16677#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16552#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16553#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16843#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16811#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16691#L715-39 assume 1 == ~t9_pc~0; 15863#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15865#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15940#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15941#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17016#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17017#L734-39 assume 1 == ~t10_pc~0; 16946#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16379#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16714#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16017#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16018#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17272#L753-39 assume !(1 == ~t11_pc~0); 15936#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 15937#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16840#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16682#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16683#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16778#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16779#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17037#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17038#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17253#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16961#L1257-3 assume !(1 == ~T5_E~0); 16962#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17226#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17275#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17378#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16090#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16091#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16000#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16001#L1297-3 assume !(1 == ~E_1~0); 17149#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17150#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17330#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17403#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17057#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17058#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16056#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16033#L1337-3 assume !(1 == ~E_9~0); 16034#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16749#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 16871#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16872#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15982#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16188#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 16189#L1697 assume !(0 == start_simulation_~tmp~3#1); 16768#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16769#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 16107#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15875#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 15876#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16837#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16838#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 17139#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 17140#L1678-2 [2023-11-19 07:43:46,405 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:46,405 INFO L85 PathProgramCache]: Analyzing trace with hash -1076284804, now seen corresponding path program 1 times [2023-11-19 07:43:46,405 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:46,405 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1095655897] [2023-11-19 07:43:46,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:46,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:46,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:46,457 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:46,457 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:46,457 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1095655897] [2023-11-19 07:43:46,457 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1095655897] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:46,458 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:46,458 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:46,458 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1085105516] [2023-11-19 07:43:46,458 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:46,458 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:46,459 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:46,459 INFO L85 PathProgramCache]: Analyzing trace with hash -1155596751, now seen corresponding path program 2 times [2023-11-19 07:43:46,459 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:46,459 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1703003541] [2023-11-19 07:43:46,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:46,460 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:46,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:46,528 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:46,529 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:46,529 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1703003541] [2023-11-19 07:43:46,529 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1703003541] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:46,529 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:46,529 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:46,530 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [669490236] [2023-11-19 07:43:46,530 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:46,530 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:46,530 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:46,531 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:43:46,531 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:43:46,531 INFO L87 Difference]: Start difference. First operand 1578 states and 2333 transitions. cyclomatic complexity: 756 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:46,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:46,571 INFO L93 Difference]: Finished difference Result 1578 states and 2332 transitions. [2023-11-19 07:43:46,571 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2332 transitions. [2023-11-19 07:43:46,583 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2023-11-19 07:43:46,596 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2332 transitions. [2023-11-19 07:43:46,596 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2023-11-19 07:43:46,598 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2023-11-19 07:43:46,599 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2332 transitions. [2023-11-19 07:43:46,601 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:46,601 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2332 transitions. [2023-11-19 07:43:46,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2332 transitions. [2023-11-19 07:43:46,625 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2023-11-19 07:43:46,628 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.4778200253485425) internal successors, (2332), 1577 states have internal predecessors, (2332), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:46,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2332 transitions. [2023-11-19 07:43:46,636 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2332 transitions. [2023-11-19 07:43:46,636 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:43:46,637 INFO L428 stractBuchiCegarLoop]: Abstraction has 1578 states and 2332 transitions. [2023-11-19 07:43:46,637 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-19 07:43:46,637 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2332 transitions. [2023-11-19 07:43:46,645 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2023-11-19 07:43:46,645 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:46,645 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:46,648 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:46,648 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:46,649 INFO L748 eck$LassoCheckResult]: Stem: 19248#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 19249#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 20029#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20030#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19222#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 19223#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20463#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20432#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20433#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19581#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19582#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 19997#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20399#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19485#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19486#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 19376#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 19377#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20330#L1109 assume !(0 == ~M_E~0); 20347#L1109-2 assume !(0 == ~T1_E~0); 19385#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19386#L1119-1 assume !(0 == ~T3_E~0); 20402#L1124-1 assume !(0 == ~T4_E~0); 19036#L1129-1 assume !(0 == ~T5_E~0); 19037#L1134-1 assume !(0 == ~T6_E~0); 19668#L1139-1 assume !(0 == ~T7_E~0); 20338#L1144-1 assume !(0 == ~T8_E~0); 20208#L1149-1 assume !(0 == ~T9_E~0); 19147#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19148#L1159-1 assume !(0 == ~T11_E~0); 20198#L1164-1 assume !(0 == ~E_M~0); 19543#L1169-1 assume !(0 == ~E_1~0); 19437#L1174-1 assume !(0 == ~E_2~0); 19301#L1179-1 assume !(0 == ~E_3~0); 19228#L1184-1 assume !(0 == ~E_4~0); 19229#L1189-1 assume !(0 == ~E_5~0); 19261#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 19344#L1199-1 assume !(0 == ~E_7~0); 20217#L1204-1 assume !(0 == ~E_8~0); 20158#L1209-1 assume !(0 == ~E_9~0); 20159#L1214-1 assume !(0 == ~E_10~0); 20476#L1219-1 assume !(0 == ~E_11~0); 20563#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19560#L544 assume 1 == ~m_pc~0; 19561#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20386#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19916#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19190#L1379 assume !(0 != activate_threads_~tmp~1#1); 19191#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19984#L563 assume !(1 == ~t1_pc~0); 19790#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19046#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19047#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20106#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 19042#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19043#L582 assume 1 == ~t2_pc~0; 19768#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20111#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19381#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19382#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 19075#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19076#L601 assume !(1 == ~t3_pc~0); 19785#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19784#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20238#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20143#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 20144#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20092#L620 assume 1 == ~t4_pc~0; 19056#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19057#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19089#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19090#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 19994#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20176#L639 assume 1 == ~t5_pc~0; 20066#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19349#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19350#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20014#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 20015#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19949#L658 assume !(1 == ~t6_pc~0); 19557#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19558#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19373#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19374#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20147#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19396#L677 assume 1 == ~t7_pc~0; 19397#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19294#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20304#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20425#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 20426#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20496#L696 assume !(1 == ~t8_pc~0); 19621#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19622#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20461#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20499#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 20544#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20053#L715 assume 1 == ~t9_pc~0; 20054#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19721#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19435#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19436#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 20036#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20299#L734 assume !(1 == ~t10_pc~0); 20300#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19513#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19514#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20242#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 20243#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19595#L753 assume 1 == ~t11_pc~0; 19596#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 20152#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20470#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19871#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 19872#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19923#L1237 assume !(1 == ~M_E~0); 19924#L1237-2 assume !(1 == ~T1_E~0); 20527#L1242-1 assume !(1 == ~T2_E~0); 19689#L1247-1 assume !(1 == ~T3_E~0); 19690#L1252-1 assume !(1 == ~T4_E~0); 19454#L1257-1 assume !(1 == ~T5_E~0); 19455#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20319#L1267-1 assume !(1 == ~T7_E~0); 20417#L1272-1 assume !(1 == ~T8_E~0); 19779#L1277-1 assume !(1 == ~T9_E~0); 19780#L1282-1 assume !(1 == ~T10_E~0); 20185#L1287-1 assume !(1 == ~T11_E~0); 20186#L1292-1 assume !(1 == ~E_M~0); 20146#L1297-1 assume !(1 == ~E_1~0); 19586#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 19587#L1307-1 assume !(1 == ~E_3~0); 20406#L1312-1 assume !(1 == ~E_4~0); 19825#L1317-1 assume !(1 == ~E_5~0); 19826#L1322-1 assume !(1 == ~E_6~0); 19530#L1327-1 assume !(1 == ~E_7~0); 19531#L1332-1 assume !(1 == ~E_8~0); 20105#L1337-1 assume !(1 == ~E_9~0); 20039#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 20040#L1347-1 assume !(1 == ~E_11~0); 20405#L1352-1 assume { :end_inline_reset_delta_events } true; 20303#L1678-2 [2023-11-19 07:43:46,649 INFO L750 eck$LassoCheckResult]: Loop: 20303#L1678-2 assume !false; 20095#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20096#L1084-1 assume !false; 19892#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19893#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19166#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 20391#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19086#L925 assume !(0 != eval_~tmp~0#1); 19088#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19579#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19580#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19059#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19060#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20148#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20149#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20173#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20174#L1134-3 assume !(0 == ~T6_E~0); 20343#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20394#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19570#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19571#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19832#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 19833#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20088#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20089#L1174-3 assume !(0 == ~E_2~0); 20136#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20137#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20282#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19978#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19323#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19324#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19550#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19009#L1214-3 assume !(0 == ~E_10~0); 19010#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 19733#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19734#L544-39 assume 1 == ~m_pc~0; 20080#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18998#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20056#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19404#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19405#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20269#L563-39 assume 1 == ~t1_pc~0; 20275#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19143#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20554#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20555#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20558#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20377#L582-39 assume 1 == ~t2_pc~0; 19466#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19467#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19802#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19803#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19237#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19021#L601-39 assume 1 == ~t3_pc~0; 19022#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19070#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20236#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20565#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20273#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19944#L620-39 assume 1 == ~t4_pc~0; 19945#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20134#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19969#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19970#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20246#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20569#L639-39 assume 1 == ~t5_pc~0; 20360#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19692#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19693#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19048#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 19049#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19981#L658-39 assume 1 == ~t6_pc~0; 19964#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19965#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20421#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20157#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20131#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20132#L677-39 assume !(1 == ~t7_pc~0); 19777#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 19226#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19227#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19282#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19283#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19874#L696-39 assume 1 == ~t8_pc~0; 19840#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19715#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19716#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20006#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19974#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19854#L715-39 assume 1 == ~t9_pc~0; 19026#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19028#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19103#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19104#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20179#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20180#L734-39 assume !(1 == ~t10_pc~0); 19541#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 19542#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19877#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19180#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19181#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20435#L753-39 assume !(1 == ~t11_pc~0); 19099#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 19100#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20003#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19845#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19846#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19941#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19942#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20200#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20201#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20416#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20124#L1257-3 assume !(1 == ~T5_E~0); 20125#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20389#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20438#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 20541#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19253#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19254#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 19163#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19164#L1297-3 assume !(1 == ~E_1~0); 20312#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20313#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20493#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20566#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20220#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20221#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19219#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19196#L1337-3 assume !(1 == ~E_9~0); 19197#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 19912#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 20034#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 20035#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19145#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19351#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 19352#L1697 assume !(0 == start_simulation_~tmp~3#1); 19931#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19932#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19270#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19038#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 19039#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20000#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20001#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 20302#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 20303#L1678-2 [2023-11-19 07:43:46,649 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:46,650 INFO L85 PathProgramCache]: Analyzing trace with hash -1751444930, now seen corresponding path program 1 times [2023-11-19 07:43:46,650 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:46,650 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [47077124] [2023-11-19 07:43:46,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:46,650 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:46,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:46,742 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:46,743 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:46,743 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [47077124] [2023-11-19 07:43:46,743 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [47077124] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:46,743 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:46,743 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:46,743 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1843167464] [2023-11-19 07:43:46,744 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:46,744 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:46,744 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:46,745 INFO L85 PathProgramCache]: Analyzing trace with hash -2120948687, now seen corresponding path program 1 times [2023-11-19 07:43:46,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:46,745 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1513449253] [2023-11-19 07:43:46,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:46,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:46,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:46,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:46,819 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:46,819 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1513449253] [2023-11-19 07:43:46,819 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1513449253] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:46,819 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:46,819 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:46,820 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1709948306] [2023-11-19 07:43:46,820 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:46,820 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:46,820 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:46,821 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:43:46,821 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:43:46,821 INFO L87 Difference]: Start difference. First operand 1578 states and 2332 transitions. cyclomatic complexity: 755 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:46,864 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:46,864 INFO L93 Difference]: Finished difference Result 1578 states and 2331 transitions. [2023-11-19 07:43:46,864 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2331 transitions. [2023-11-19 07:43:46,876 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2023-11-19 07:43:46,890 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2331 transitions. [2023-11-19 07:43:46,891 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2023-11-19 07:43:46,893 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2023-11-19 07:43:46,893 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2331 transitions. [2023-11-19 07:43:46,895 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:46,896 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2331 transitions. [2023-11-19 07:43:46,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2331 transitions. [2023-11-19 07:43:46,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2023-11-19 07:43:46,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.4771863117870723) internal successors, (2331), 1577 states have internal predecessors, (2331), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:46,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2331 transitions. [2023-11-19 07:43:46,935 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2331 transitions. [2023-11-19 07:43:46,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:43:46,936 INFO L428 stractBuchiCegarLoop]: Abstraction has 1578 states and 2331 transitions. [2023-11-19 07:43:46,936 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-19 07:43:46,937 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2331 transitions. [2023-11-19 07:43:46,946 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2023-11-19 07:43:46,947 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:46,947 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:46,950 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:46,950 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:46,950 INFO L748 eck$LassoCheckResult]: Stem: 22411#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 22412#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 23192#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23193#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22385#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 22386#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23626#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23595#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23596#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22744#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22745#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23160#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23562#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 22648#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22649#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22539#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 22540#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23493#L1109 assume !(0 == ~M_E~0); 23510#L1109-2 assume !(0 == ~T1_E~0); 22548#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22549#L1119-1 assume !(0 == ~T3_E~0); 23565#L1124-1 assume !(0 == ~T4_E~0); 22199#L1129-1 assume !(0 == ~T5_E~0); 22200#L1134-1 assume !(0 == ~T6_E~0); 22831#L1139-1 assume !(0 == ~T7_E~0); 23501#L1144-1 assume !(0 == ~T8_E~0); 23371#L1149-1 assume !(0 == ~T9_E~0); 22310#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22311#L1159-1 assume !(0 == ~T11_E~0); 23361#L1164-1 assume !(0 == ~E_M~0); 22706#L1169-1 assume !(0 == ~E_1~0); 22600#L1174-1 assume !(0 == ~E_2~0); 22464#L1179-1 assume !(0 == ~E_3~0); 22391#L1184-1 assume !(0 == ~E_4~0); 22392#L1189-1 assume !(0 == ~E_5~0); 22424#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 22507#L1199-1 assume !(0 == ~E_7~0); 23380#L1204-1 assume !(0 == ~E_8~0); 23321#L1209-1 assume !(0 == ~E_9~0); 23322#L1214-1 assume !(0 == ~E_10~0); 23639#L1219-1 assume !(0 == ~E_11~0); 23726#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22723#L544 assume 1 == ~m_pc~0; 22724#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23549#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23079#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22353#L1379 assume !(0 != activate_threads_~tmp~1#1); 22354#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23147#L563 assume !(1 == ~t1_pc~0); 22953#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22209#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22210#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23269#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 22205#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22206#L582 assume 1 == ~t2_pc~0; 22931#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23274#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22544#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22545#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 22238#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22239#L601 assume !(1 == ~t3_pc~0); 22948#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22947#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23401#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23306#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 23307#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23255#L620 assume 1 == ~t4_pc~0; 22219#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22220#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22252#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22253#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 23157#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23339#L639 assume 1 == ~t5_pc~0; 23229#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22512#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22513#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23177#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 23178#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23112#L658 assume !(1 == ~t6_pc~0); 22720#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22721#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22536#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22537#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23310#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22559#L677 assume 1 == ~t7_pc~0; 22560#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22457#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23467#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23588#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 23589#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23659#L696 assume !(1 == ~t8_pc~0); 22784#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22785#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23624#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23662#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 23707#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23216#L715 assume 1 == ~t9_pc~0; 23217#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22884#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22598#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22599#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 23199#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23462#L734 assume !(1 == ~t10_pc~0); 23463#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 22676#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22677#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23405#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 23406#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22758#L753 assume 1 == ~t11_pc~0; 22759#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23315#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23633#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23034#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 23035#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23086#L1237 assume !(1 == ~M_E~0); 23087#L1237-2 assume !(1 == ~T1_E~0); 23690#L1242-1 assume !(1 == ~T2_E~0); 22852#L1247-1 assume !(1 == ~T3_E~0); 22853#L1252-1 assume !(1 == ~T4_E~0); 22617#L1257-1 assume !(1 == ~T5_E~0); 22618#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23482#L1267-1 assume !(1 == ~T7_E~0); 23580#L1272-1 assume !(1 == ~T8_E~0); 22942#L1277-1 assume !(1 == ~T9_E~0); 22943#L1282-1 assume !(1 == ~T10_E~0); 23348#L1287-1 assume !(1 == ~T11_E~0); 23349#L1292-1 assume !(1 == ~E_M~0); 23309#L1297-1 assume !(1 == ~E_1~0); 22749#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22750#L1307-1 assume !(1 == ~E_3~0); 23569#L1312-1 assume !(1 == ~E_4~0); 22988#L1317-1 assume !(1 == ~E_5~0); 22989#L1322-1 assume !(1 == ~E_6~0); 22693#L1327-1 assume !(1 == ~E_7~0); 22694#L1332-1 assume !(1 == ~E_8~0); 23268#L1337-1 assume !(1 == ~E_9~0); 23202#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 23203#L1347-1 assume !(1 == ~E_11~0); 23568#L1352-1 assume { :end_inline_reset_delta_events } true; 23466#L1678-2 [2023-11-19 07:43:46,951 INFO L750 eck$LassoCheckResult]: Loop: 23466#L1678-2 assume !false; 23258#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23259#L1084-1 assume !false; 23055#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 23056#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22329#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 23554#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22249#L925 assume !(0 != eval_~tmp~0#1); 22251#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22742#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22743#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22222#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22223#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23311#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23312#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23336#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23337#L1134-3 assume !(0 == ~T6_E~0); 23506#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23557#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22733#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22734#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22995#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 22996#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23251#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23252#L1174-3 assume !(0 == ~E_2~0); 23299#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23300#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23445#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23141#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22486#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22487#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22713#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22172#L1214-3 assume !(0 == ~E_10~0); 22173#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22896#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22897#L544-39 assume !(1 == ~m_pc~0); 22160#L544-41 is_master_triggered_~__retres1~0#1 := 0; 22161#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23219#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22567#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22568#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23432#L563-39 assume !(1 == ~t1_pc~0); 22305#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 22306#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23717#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23718#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23721#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23540#L582-39 assume 1 == ~t2_pc~0; 22629#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22630#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22965#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22966#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22400#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22184#L601-39 assume 1 == ~t3_pc~0; 22185#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22233#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23399#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23728#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23436#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23107#L620-39 assume 1 == ~t4_pc~0; 23108#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23297#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23132#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23133#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23409#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23732#L639-39 assume 1 == ~t5_pc~0; 23523#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22855#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22856#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22211#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 22212#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23144#L658-39 assume 1 == ~t6_pc~0; 23127#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23128#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23584#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23320#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23294#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23295#L677-39 assume !(1 == ~t7_pc~0); 22940#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 22389#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22390#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22445#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22446#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23037#L696-39 assume 1 == ~t8_pc~0; 23003#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22878#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22879#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23169#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 23137#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23017#L715-39 assume 1 == ~t9_pc~0; 22189#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22191#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22266#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22267#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 23342#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23343#L734-39 assume !(1 == ~t10_pc~0); 22704#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 22705#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23040#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22343#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22344#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23598#L753-39 assume !(1 == ~t11_pc~0); 22262#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 22263#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23166#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23008#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23009#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23104#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 23105#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23363#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23364#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23579#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23287#L1257-3 assume !(1 == ~T5_E~0); 23288#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23552#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23601#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 23704#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22416#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22417#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22326#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22327#L1297-3 assume !(1 == ~E_1~0); 23475#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23476#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23656#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23729#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23383#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23384#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22382#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22359#L1337-3 assume !(1 == ~E_9~0); 22360#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 23075#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 23197#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 23198#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22308#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22514#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 22515#L1697 assume !(0 == start_simulation_~tmp~3#1); 23094#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 23095#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22433#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22201#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 22202#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23163#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23164#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 23465#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 23466#L1678-2 [2023-11-19 07:43:46,952 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:46,952 INFO L85 PathProgramCache]: Analyzing trace with hash -803392964, now seen corresponding path program 1 times [2023-11-19 07:43:46,952 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:46,952 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1957115211] [2023-11-19 07:43:46,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:46,953 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:46,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:47,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:47,009 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:47,010 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1957115211] [2023-11-19 07:43:47,011 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1957115211] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:47,011 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:47,011 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:47,014 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1724846383] [2023-11-19 07:43:47,014 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:47,015 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:47,019 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:47,019 INFO L85 PathProgramCache]: Analyzing trace with hash -770175885, now seen corresponding path program 1 times [2023-11-19 07:43:47,019 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:47,022 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [441128584] [2023-11-19 07:43:47,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:47,026 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:47,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:47,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:47,112 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:47,112 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [441128584] [2023-11-19 07:43:47,115 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [441128584] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:47,115 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:47,115 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:47,115 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [232439355] [2023-11-19 07:43:47,116 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:47,116 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:47,116 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:47,117 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:43:47,117 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:43:47,118 INFO L87 Difference]: Start difference. First operand 1578 states and 2331 transitions. cyclomatic complexity: 754 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:47,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:47,162 INFO L93 Difference]: Finished difference Result 1578 states and 2330 transitions. [2023-11-19 07:43:47,162 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2330 transitions. [2023-11-19 07:43:47,174 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2023-11-19 07:43:47,188 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2330 transitions. [2023-11-19 07:43:47,188 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2023-11-19 07:43:47,193 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2023-11-19 07:43:47,193 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2330 transitions. [2023-11-19 07:43:47,196 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:47,196 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2330 transitions. [2023-11-19 07:43:47,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2330 transitions. [2023-11-19 07:43:47,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2023-11-19 07:43:47,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.476552598225602) internal successors, (2330), 1577 states have internal predecessors, (2330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:47,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2330 transitions. [2023-11-19 07:43:47,247 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2330 transitions. [2023-11-19 07:43:47,248 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:43:47,252 INFO L428 stractBuchiCegarLoop]: Abstraction has 1578 states and 2330 transitions. [2023-11-19 07:43:47,252 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-19 07:43:47,252 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2330 transitions. [2023-11-19 07:43:47,260 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2023-11-19 07:43:47,260 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:47,260 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:47,263 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:47,263 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:47,264 INFO L748 eck$LassoCheckResult]: Stem: 25574#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 25575#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 26355#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26356#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25548#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 25549#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26789#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26758#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26759#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25907#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25908#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26323#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26725#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25811#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25812#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25702#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25703#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26656#L1109 assume !(0 == ~M_E~0); 26673#L1109-2 assume !(0 == ~T1_E~0); 25711#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25712#L1119-1 assume !(0 == ~T3_E~0); 26728#L1124-1 assume !(0 == ~T4_E~0); 25362#L1129-1 assume !(0 == ~T5_E~0); 25363#L1134-1 assume !(0 == ~T6_E~0); 25994#L1139-1 assume !(0 == ~T7_E~0); 26664#L1144-1 assume !(0 == ~T8_E~0); 26534#L1149-1 assume !(0 == ~T9_E~0); 25475#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25476#L1159-1 assume !(0 == ~T11_E~0); 26524#L1164-1 assume !(0 == ~E_M~0); 25869#L1169-1 assume !(0 == ~E_1~0); 25763#L1174-1 assume !(0 == ~E_2~0); 25629#L1179-1 assume !(0 == ~E_3~0); 25554#L1184-1 assume !(0 == ~E_4~0); 25555#L1189-1 assume !(0 == ~E_5~0); 25587#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 25672#L1199-1 assume !(0 == ~E_7~0); 26543#L1204-1 assume !(0 == ~E_8~0); 26484#L1209-1 assume !(0 == ~E_9~0); 26485#L1214-1 assume !(0 == ~E_10~0); 26802#L1219-1 assume !(0 == ~E_11~0); 26889#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25886#L544 assume 1 == ~m_pc~0; 25887#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26712#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26242#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25516#L1379 assume !(0 != activate_threads_~tmp~1#1); 25517#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26312#L563 assume !(1 == ~t1_pc~0); 26116#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25372#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25373#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26432#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 25368#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25369#L582 assume 1 == ~t2_pc~0; 26094#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26437#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25707#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25708#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 25401#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25402#L601 assume !(1 == ~t3_pc~0); 26111#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26110#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26564#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26469#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 26470#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26418#L620 assume 1 == ~t4_pc~0; 25382#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25383#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25415#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25416#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 26320#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26503#L639 assume 1 == ~t5_pc~0; 26392#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25677#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25678#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26340#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 26341#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26275#L658 assume !(1 == ~t6_pc~0); 25883#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25884#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25699#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25700#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26473#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25724#L677 assume 1 == ~t7_pc~0; 25725#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25623#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26630#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26751#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 26752#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26822#L696 assume !(1 == ~t8_pc~0); 25948#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25949#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26787#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26825#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 26870#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26379#L715 assume 1 == ~t9_pc~0; 26380#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26047#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25761#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25762#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 26362#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26627#L734 assume !(1 == ~t10_pc~0); 26628#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25839#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25840#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26568#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 26569#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25921#L753 assume 1 == ~t11_pc~0; 25922#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26478#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26796#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26199#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 26200#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26251#L1237 assume !(1 == ~M_E~0); 26252#L1237-2 assume !(1 == ~T1_E~0); 26854#L1242-1 assume !(1 == ~T2_E~0); 26015#L1247-1 assume !(1 == ~T3_E~0); 26016#L1252-1 assume !(1 == ~T4_E~0); 25780#L1257-1 assume !(1 == ~T5_E~0); 25781#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26645#L1267-1 assume !(1 == ~T7_E~0); 26743#L1272-1 assume !(1 == ~T8_E~0); 26105#L1277-1 assume !(1 == ~T9_E~0); 26106#L1282-1 assume !(1 == ~T10_E~0); 26511#L1287-1 assume !(1 == ~T11_E~0); 26512#L1292-1 assume !(1 == ~E_M~0); 26472#L1297-1 assume !(1 == ~E_1~0); 25912#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25913#L1307-1 assume !(1 == ~E_3~0); 26732#L1312-1 assume !(1 == ~E_4~0); 26151#L1317-1 assume !(1 == ~E_5~0); 26152#L1322-1 assume !(1 == ~E_6~0); 25856#L1327-1 assume !(1 == ~E_7~0); 25857#L1332-1 assume !(1 == ~E_8~0); 26431#L1337-1 assume !(1 == ~E_9~0); 26365#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 26366#L1347-1 assume !(1 == ~E_11~0); 26731#L1352-1 assume { :end_inline_reset_delta_events } true; 26626#L1678-2 [2023-11-19 07:43:47,265 INFO L750 eck$LassoCheckResult]: Loop: 26626#L1678-2 assume !false; 26421#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26422#L1084-1 assume !false; 26218#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26219#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25492#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 26717#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 25412#L925 assume !(0 != eval_~tmp~0#1); 25414#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25905#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25906#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25385#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25386#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26474#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26475#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26499#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26500#L1134-3 assume !(0 == ~T6_E~0); 26669#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 26720#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25896#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25897#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 26159#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26160#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26414#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26415#L1174-3 assume !(0 == ~E_2~0); 26462#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26463#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26608#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26304#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25652#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25653#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25880#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25340#L1214-3 assume !(0 == ~E_10~0); 25341#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 26059#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26060#L544-39 assume 1 == ~m_pc~0; 26407#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25324#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26382#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25730#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25731#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26595#L563-39 assume 1 == ~t1_pc~0; 26601#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25472#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26880#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26881#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26884#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26703#L582-39 assume 1 == ~t2_pc~0; 25792#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25793#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26128#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26129#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25565#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25347#L601-39 assume 1 == ~t3_pc~0; 25348#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25393#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26562#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26891#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26599#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26269#L620-39 assume 1 == ~t4_pc~0; 26270#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26460#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26295#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26296#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26572#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26894#L639-39 assume 1 == ~t5_pc~0; 26686#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26018#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26019#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25374#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 25375#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26307#L658-39 assume 1 == ~t6_pc~0; 26290#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26291#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26747#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26483#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26457#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26458#L677-39 assume !(1 == ~t7_pc~0); 26101#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 25552#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25553#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25608#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25609#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26198#L696-39 assume 1 == ~t8_pc~0; 26166#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26041#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26042#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26332#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26300#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26180#L715-39 assume 1 == ~t9_pc~0; 25350#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25352#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25429#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25430#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 26505#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26506#L734-39 assume 1 == ~t10_pc~0; 26435#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25868#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26203#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25506#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25507#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26761#L753-39 assume !(1 == ~t11_pc~0); 25425#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 25426#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26329#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26171#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 26172#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26263#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26264#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26526#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26527#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26742#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26450#L1257-3 assume !(1 == ~T5_E~0); 26451#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26714#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26764#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26867#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25579#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25580#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25489#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25490#L1297-3 assume !(1 == ~E_1~0); 26638#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26639#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26819#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26892#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26546#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26547#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25545#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25522#L1337-3 assume !(1 == ~E_9~0); 25523#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 26238#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 26360#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26361#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25466#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 25675#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 25676#L1697 assume !(0 == start_simulation_~tmp~3#1); 26257#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26258#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25596#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 25364#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 25365#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26326#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26327#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 26625#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 26626#L1678-2 [2023-11-19 07:43:47,265 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:47,266 INFO L85 PathProgramCache]: Analyzing trace with hash -218621314, now seen corresponding path program 1 times [2023-11-19 07:43:47,266 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:47,266 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [663436328] [2023-11-19 07:43:47,266 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:47,267 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:47,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:47,357 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:47,358 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:47,358 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [663436328] [2023-11-19 07:43:47,358 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [663436328] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:47,358 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:47,359 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:47,359 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [94967522] [2023-11-19 07:43:47,359 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:47,360 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:47,360 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:47,361 INFO L85 PathProgramCache]: Analyzing trace with hash 705815280, now seen corresponding path program 2 times [2023-11-19 07:43:47,361 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:47,361 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1667130192] [2023-11-19 07:43:47,361 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:47,362 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:47,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:47,451 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:47,452 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:47,452 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1667130192] [2023-11-19 07:43:47,452 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1667130192] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:47,452 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:47,453 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:47,453 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1471571036] [2023-11-19 07:43:47,453 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:47,454 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:47,454 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:47,455 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:43:47,455 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:43:47,455 INFO L87 Difference]: Start difference. First operand 1578 states and 2330 transitions. cyclomatic complexity: 753 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:47,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:47,512 INFO L93 Difference]: Finished difference Result 1578 states and 2329 transitions. [2023-11-19 07:43:47,512 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2329 transitions. [2023-11-19 07:43:47,526 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2023-11-19 07:43:47,543 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2329 transitions. [2023-11-19 07:43:47,544 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2023-11-19 07:43:47,546 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2023-11-19 07:43:47,546 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2329 transitions. [2023-11-19 07:43:47,549 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:47,549 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2329 transitions. [2023-11-19 07:43:47,553 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2329 transitions. [2023-11-19 07:43:47,576 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2023-11-19 07:43:47,580 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.4759188846641318) internal successors, (2329), 1577 states have internal predecessors, (2329), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:47,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2329 transitions. [2023-11-19 07:43:47,588 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2329 transitions. [2023-11-19 07:43:47,588 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:43:47,590 INFO L428 stractBuchiCegarLoop]: Abstraction has 1578 states and 2329 transitions. [2023-11-19 07:43:47,590 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-19 07:43:47,590 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2329 transitions. [2023-11-19 07:43:47,598 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2023-11-19 07:43:47,598 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:47,598 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:47,601 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:47,602 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:47,602 INFO L748 eck$LassoCheckResult]: Stem: 28737#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 28738#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 29518#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29519#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28711#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 28712#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29952#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29921#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29922#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29070#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29071#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29486#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29888#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 28974#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28975#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28865#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28866#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29819#L1109 assume !(0 == ~M_E~0); 29836#L1109-2 assume !(0 == ~T1_E~0); 28874#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28875#L1119-1 assume !(0 == ~T3_E~0); 29891#L1124-1 assume !(0 == ~T4_E~0); 28525#L1129-1 assume !(0 == ~T5_E~0); 28526#L1134-1 assume !(0 == ~T6_E~0); 29157#L1139-1 assume !(0 == ~T7_E~0); 29827#L1144-1 assume !(0 == ~T8_E~0); 29697#L1149-1 assume !(0 == ~T9_E~0); 28636#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28637#L1159-1 assume !(0 == ~T11_E~0); 29687#L1164-1 assume !(0 == ~E_M~0); 29032#L1169-1 assume !(0 == ~E_1~0); 28926#L1174-1 assume !(0 == ~E_2~0); 28790#L1179-1 assume !(0 == ~E_3~0); 28717#L1184-1 assume !(0 == ~E_4~0); 28718#L1189-1 assume !(0 == ~E_5~0); 28750#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 28833#L1199-1 assume !(0 == ~E_7~0); 29706#L1204-1 assume !(0 == ~E_8~0); 29647#L1209-1 assume !(0 == ~E_9~0); 29648#L1214-1 assume !(0 == ~E_10~0); 29965#L1219-1 assume !(0 == ~E_11~0); 30052#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29049#L544 assume 1 == ~m_pc~0; 29050#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29875#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29405#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28679#L1379 assume !(0 != activate_threads_~tmp~1#1); 28680#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29473#L563 assume !(1 == ~t1_pc~0); 29279#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28535#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28536#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29595#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 28531#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28532#L582 assume 1 == ~t2_pc~0; 29257#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29600#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28870#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28871#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 28564#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28565#L601 assume !(1 == ~t3_pc~0); 29274#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29273#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29727#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29632#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 29633#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29581#L620 assume 1 == ~t4_pc~0; 28545#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28546#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28578#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28579#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 29483#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29665#L639 assume 1 == ~t5_pc~0; 29555#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28838#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28839#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29503#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 29504#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29438#L658 assume !(1 == ~t6_pc~0); 29046#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 29047#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28862#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28863#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29636#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28885#L677 assume 1 == ~t7_pc~0; 28886#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28783#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29793#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29914#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 29915#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29985#L696 assume !(1 == ~t8_pc~0); 29110#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29111#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29950#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29988#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 30033#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29542#L715 assume 1 == ~t9_pc~0; 29543#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29210#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28924#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28925#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 29525#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29788#L734 assume !(1 == ~t10_pc~0); 29789#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29002#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29003#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29731#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 29732#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29084#L753 assume 1 == ~t11_pc~0; 29085#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29641#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29959#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29360#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 29361#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29412#L1237 assume !(1 == ~M_E~0); 29413#L1237-2 assume !(1 == ~T1_E~0); 30016#L1242-1 assume !(1 == ~T2_E~0); 29178#L1247-1 assume !(1 == ~T3_E~0); 29179#L1252-1 assume !(1 == ~T4_E~0); 28943#L1257-1 assume !(1 == ~T5_E~0); 28944#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29808#L1267-1 assume !(1 == ~T7_E~0); 29906#L1272-1 assume !(1 == ~T8_E~0); 29268#L1277-1 assume !(1 == ~T9_E~0); 29269#L1282-1 assume !(1 == ~T10_E~0); 29674#L1287-1 assume !(1 == ~T11_E~0); 29675#L1292-1 assume !(1 == ~E_M~0); 29635#L1297-1 assume !(1 == ~E_1~0); 29075#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 29076#L1307-1 assume !(1 == ~E_3~0); 29895#L1312-1 assume !(1 == ~E_4~0); 29314#L1317-1 assume !(1 == ~E_5~0); 29315#L1322-1 assume !(1 == ~E_6~0); 29019#L1327-1 assume !(1 == ~E_7~0); 29020#L1332-1 assume !(1 == ~E_8~0); 29594#L1337-1 assume !(1 == ~E_9~0); 29528#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 29529#L1347-1 assume !(1 == ~E_11~0); 29894#L1352-1 assume { :end_inline_reset_delta_events } true; 29792#L1678-2 [2023-11-19 07:43:47,603 INFO L750 eck$LassoCheckResult]: Loop: 29792#L1678-2 assume !false; 29584#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29585#L1084-1 assume !false; 29381#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29382#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28655#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29880#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 28575#L925 assume !(0 != eval_~tmp~0#1); 28577#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29068#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29069#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28548#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28549#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29637#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29638#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29662#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29663#L1134-3 assume !(0 == ~T6_E~0); 29832#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29883#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29059#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29060#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29321#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29322#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29577#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29578#L1174-3 assume !(0 == ~E_2~0); 29625#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29626#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29771#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29467#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28812#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28813#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29039#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28498#L1214-3 assume !(0 == ~E_10~0); 28499#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 29222#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29223#L544-39 assume 1 == ~m_pc~0; 29569#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28487#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29545#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28893#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28894#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29758#L563-39 assume 1 == ~t1_pc~0; 29764#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28632#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30043#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30044#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30047#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29866#L582-39 assume 1 == ~t2_pc~0; 28955#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28956#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29291#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29292#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28726#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28510#L601-39 assume !(1 == ~t3_pc~0); 28512#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 28559#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29725#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30054#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29762#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29433#L620-39 assume 1 == ~t4_pc~0; 29434#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29623#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29458#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29459#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29735#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30058#L639-39 assume 1 == ~t5_pc~0; 29849#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29181#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29182#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28537#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 28538#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29470#L658-39 assume 1 == ~t6_pc~0; 29453#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29454#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29910#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29646#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29620#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29621#L677-39 assume !(1 == ~t7_pc~0); 29266#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 28715#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28716#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28771#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28772#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29363#L696-39 assume 1 == ~t8_pc~0; 29329#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29204#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29205#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29495#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29463#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29343#L715-39 assume 1 == ~t9_pc~0; 28515#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28517#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28592#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28593#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29668#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29669#L734-39 assume !(1 == ~t10_pc~0); 29030#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 29031#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29366#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28669#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28670#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29924#L753-39 assume !(1 == ~t11_pc~0); 28588#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 28589#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29492#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29334#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 29335#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29430#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29431#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29689#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29690#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29905#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29613#L1257-3 assume !(1 == ~T5_E~0); 29614#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29878#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 29927#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30030#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28742#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28743#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28652#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28653#L1297-3 assume !(1 == ~E_1~0); 29801#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29802#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29982#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30055#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29709#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29710#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28708#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28685#L1337-3 assume !(1 == ~E_9~0); 28686#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29401#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29523#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29524#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28634#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 28840#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 28841#L1697 assume !(0 == start_simulation_~tmp~3#1); 29420#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29421#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28759#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 28527#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 28528#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29489#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29490#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 29791#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 29792#L1678-2 [2023-11-19 07:43:47,604 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:47,604 INFO L85 PathProgramCache]: Analyzing trace with hash 215884284, now seen corresponding path program 1 times [2023-11-19 07:43:47,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:47,605 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [503339682] [2023-11-19 07:43:47,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:47,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:47,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:47,669 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:47,669 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:47,670 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [503339682] [2023-11-19 07:43:47,670 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [503339682] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:47,670 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:47,670 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:47,671 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [569688280] [2023-11-19 07:43:47,671 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:47,672 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:47,673 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:47,673 INFO L85 PathProgramCache]: Analyzing trace with hash 1013171250, now seen corresponding path program 1 times [2023-11-19 07:43:47,674 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:47,674 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [132031722] [2023-11-19 07:43:47,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:47,674 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:47,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:47,754 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:47,754 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:47,755 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [132031722] [2023-11-19 07:43:47,755 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [132031722] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:47,755 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:47,755 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:47,756 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1880837956] [2023-11-19 07:43:47,756 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:47,756 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:47,757 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:47,758 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:43:47,758 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:43:47,758 INFO L87 Difference]: Start difference. First operand 1578 states and 2329 transitions. cyclomatic complexity: 752 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:47,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:47,811 INFO L93 Difference]: Finished difference Result 1578 states and 2328 transitions. [2023-11-19 07:43:47,811 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2328 transitions. [2023-11-19 07:43:47,823 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2023-11-19 07:43:47,836 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2328 transitions. [2023-11-19 07:43:47,837 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2023-11-19 07:43:47,839 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2023-11-19 07:43:47,839 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2328 transitions. [2023-11-19 07:43:47,842 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:47,843 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2328 transitions. [2023-11-19 07:43:47,847 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2328 transitions. [2023-11-19 07:43:47,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2023-11-19 07:43:47,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.4752851711026616) internal successors, (2328), 1577 states have internal predecessors, (2328), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:47,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2328 transitions. [2023-11-19 07:43:47,884 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2328 transitions. [2023-11-19 07:43:47,884 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:43:47,885 INFO L428 stractBuchiCegarLoop]: Abstraction has 1578 states and 2328 transitions. [2023-11-19 07:43:47,885 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-19 07:43:47,885 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2328 transitions. [2023-11-19 07:43:47,895 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2023-11-19 07:43:47,895 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:47,895 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:47,898 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:47,899 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:47,899 INFO L748 eck$LassoCheckResult]: Stem: 31900#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 31901#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 32681#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32682#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31874#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 31875#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33115#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33084#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33085#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32233#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32234#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32649#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33051#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 32137#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 32138#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 32028#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32029#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32982#L1109 assume !(0 == ~M_E~0); 32999#L1109-2 assume !(0 == ~T1_E~0); 32037#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32038#L1119-1 assume !(0 == ~T3_E~0); 33054#L1124-1 assume !(0 == ~T4_E~0); 31688#L1129-1 assume !(0 == ~T5_E~0); 31689#L1134-1 assume !(0 == ~T6_E~0); 32320#L1139-1 assume !(0 == ~T7_E~0); 32990#L1144-1 assume !(0 == ~T8_E~0); 32860#L1149-1 assume !(0 == ~T9_E~0); 31799#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 31800#L1159-1 assume !(0 == ~T11_E~0); 32850#L1164-1 assume !(0 == ~E_M~0); 32195#L1169-1 assume !(0 == ~E_1~0); 32089#L1174-1 assume !(0 == ~E_2~0); 31953#L1179-1 assume !(0 == ~E_3~0); 31880#L1184-1 assume !(0 == ~E_4~0); 31881#L1189-1 assume !(0 == ~E_5~0); 31913#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 31996#L1199-1 assume !(0 == ~E_7~0); 32869#L1204-1 assume !(0 == ~E_8~0); 32810#L1209-1 assume !(0 == ~E_9~0); 32811#L1214-1 assume !(0 == ~E_10~0); 33128#L1219-1 assume !(0 == ~E_11~0); 33215#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32212#L544 assume 1 == ~m_pc~0; 32213#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33038#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32568#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31842#L1379 assume !(0 != activate_threads_~tmp~1#1); 31843#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32636#L563 assume !(1 == ~t1_pc~0); 32442#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31698#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31699#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32758#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 31694#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31695#L582 assume 1 == ~t2_pc~0; 32420#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32763#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32033#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32034#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 31727#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31728#L601 assume !(1 == ~t3_pc~0); 32437#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 32436#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32890#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32795#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 32796#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32744#L620 assume 1 == ~t4_pc~0; 31708#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31709#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31741#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31742#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 32646#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32828#L639 assume 1 == ~t5_pc~0; 32718#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32001#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32002#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32666#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 32667#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32601#L658 assume !(1 == ~t6_pc~0); 32209#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 32210#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32025#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32026#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32799#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32048#L677 assume 1 == ~t7_pc~0; 32049#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31946#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32956#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33077#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 33078#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33148#L696 assume !(1 == ~t8_pc~0); 32273#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 32274#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33113#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33151#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 33196#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32705#L715 assume 1 == ~t9_pc~0; 32706#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32373#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32087#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32088#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 32688#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32951#L734 assume !(1 == ~t10_pc~0); 32952#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32165#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32166#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32894#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 32895#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32247#L753 assume 1 == ~t11_pc~0; 32248#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32804#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33122#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32523#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 32524#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32575#L1237 assume !(1 == ~M_E~0); 32576#L1237-2 assume !(1 == ~T1_E~0); 33179#L1242-1 assume !(1 == ~T2_E~0); 32341#L1247-1 assume !(1 == ~T3_E~0); 32342#L1252-1 assume !(1 == ~T4_E~0); 32106#L1257-1 assume !(1 == ~T5_E~0); 32107#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32971#L1267-1 assume !(1 == ~T7_E~0); 33069#L1272-1 assume !(1 == ~T8_E~0); 32431#L1277-1 assume !(1 == ~T9_E~0); 32432#L1282-1 assume !(1 == ~T10_E~0); 32837#L1287-1 assume !(1 == ~T11_E~0); 32838#L1292-1 assume !(1 == ~E_M~0); 32798#L1297-1 assume !(1 == ~E_1~0); 32238#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 32239#L1307-1 assume !(1 == ~E_3~0); 33058#L1312-1 assume !(1 == ~E_4~0); 32477#L1317-1 assume !(1 == ~E_5~0); 32478#L1322-1 assume !(1 == ~E_6~0); 32182#L1327-1 assume !(1 == ~E_7~0); 32183#L1332-1 assume !(1 == ~E_8~0); 32757#L1337-1 assume !(1 == ~E_9~0); 32691#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 32692#L1347-1 assume !(1 == ~E_11~0); 33057#L1352-1 assume { :end_inline_reset_delta_events } true; 32955#L1678-2 [2023-11-19 07:43:47,900 INFO L750 eck$LassoCheckResult]: Loop: 32955#L1678-2 assume !false; 32747#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32748#L1084-1 assume !false; 32544#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32545#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31818#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 33043#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 31738#L925 assume !(0 != eval_~tmp~0#1); 31740#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32231#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32232#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 31711#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31712#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32800#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32801#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32825#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32826#L1134-3 assume !(0 == ~T6_E~0); 32995#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33046#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32222#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32223#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32484#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32485#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32740#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32741#L1174-3 assume !(0 == ~E_2~0); 32788#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32789#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32934#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32630#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31975#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 31976#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 32202#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 31661#L1214-3 assume !(0 == ~E_10~0); 31662#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32385#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32386#L544-39 assume !(1 == ~m_pc~0); 31649#L544-41 is_master_triggered_~__retres1~0#1 := 0; 31650#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32708#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32056#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32057#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32921#L563-39 assume !(1 == ~t1_pc~0); 31794#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 31795#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33206#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33207#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33210#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33029#L582-39 assume 1 == ~t2_pc~0; 32118#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32119#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32454#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32455#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31889#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31673#L601-39 assume 1 == ~t3_pc~0; 31674#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31722#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32888#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33217#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32925#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32596#L620-39 assume 1 == ~t4_pc~0; 32597#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32786#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32621#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32622#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32898#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33221#L639-39 assume 1 == ~t5_pc~0; 33012#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32344#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32345#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31700#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 31701#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32633#L658-39 assume 1 == ~t6_pc~0; 32616#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32617#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33073#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32809#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32783#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32784#L677-39 assume !(1 == ~t7_pc~0); 32429#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 31878#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31879#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31934#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 31935#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32526#L696-39 assume 1 == ~t8_pc~0; 32492#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32367#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32368#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32658#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32626#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32506#L715-39 assume 1 == ~t9_pc~0; 31678#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31680#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31755#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31756#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32831#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32832#L734-39 assume !(1 == ~t10_pc~0); 32193#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 32194#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32529#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31832#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 31833#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33087#L753-39 assume !(1 == ~t11_pc~0); 31751#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 31752#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32655#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32497#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32498#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32593#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32594#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32852#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32853#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33068#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32776#L1257-3 assume !(1 == ~T5_E~0); 32777#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33041#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33090#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33193#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 31905#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 31906#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31815#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 31816#L1297-3 assume !(1 == ~E_1~0); 32964#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32965#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33145#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33218#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32872#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32873#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 31871#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31848#L1337-3 assume !(1 == ~E_9~0); 31849#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32564#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32686#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32687#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31797#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32003#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 32004#L1697 assume !(0 == start_simulation_~tmp~3#1); 32583#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32584#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31922#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 31690#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 31691#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32652#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32653#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 32954#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 32955#L1678-2 [2023-11-19 07:43:47,901 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:47,902 INFO L85 PathProgramCache]: Analyzing trace with hash 922480890, now seen corresponding path program 1 times [2023-11-19 07:43:47,902 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:47,902 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1775833343] [2023-11-19 07:43:47,902 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:47,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:47,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:47,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:47,967 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:47,967 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1775833343] [2023-11-19 07:43:47,967 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1775833343] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:47,968 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:47,968 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:47,968 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1331137357] [2023-11-19 07:43:47,968 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:47,969 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:47,969 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:47,969 INFO L85 PathProgramCache]: Analyzing trace with hash -770175885, now seen corresponding path program 2 times [2023-11-19 07:43:47,970 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:47,970 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1979542200] [2023-11-19 07:43:47,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:47,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:47,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:48,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:48,086 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:48,086 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1979542200] [2023-11-19 07:43:48,087 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1979542200] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:48,087 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:48,087 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:48,087 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [22277392] [2023-11-19 07:43:48,087 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:48,088 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:48,088 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:48,088 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:43:48,089 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:43:48,089 INFO L87 Difference]: Start difference. First operand 1578 states and 2328 transitions. cyclomatic complexity: 751 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:48,131 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:48,131 INFO L93 Difference]: Finished difference Result 1578 states and 2327 transitions. [2023-11-19 07:43:48,131 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2327 transitions. [2023-11-19 07:43:48,142 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2023-11-19 07:43:48,155 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2327 transitions. [2023-11-19 07:43:48,155 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2023-11-19 07:43:48,157 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2023-11-19 07:43:48,157 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2327 transitions. [2023-11-19 07:43:48,160 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:48,160 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2327 transitions. [2023-11-19 07:43:48,164 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2327 transitions. [2023-11-19 07:43:48,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2023-11-19 07:43:48,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.4746514575411913) internal successors, (2327), 1577 states have internal predecessors, (2327), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:48,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2327 transitions. [2023-11-19 07:43:48,199 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2327 transitions. [2023-11-19 07:43:48,199 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:43:48,200 INFO L428 stractBuchiCegarLoop]: Abstraction has 1578 states and 2327 transitions. [2023-11-19 07:43:48,200 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-19 07:43:48,200 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2327 transitions. [2023-11-19 07:43:48,208 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2023-11-19 07:43:48,208 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:48,209 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:48,211 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:48,212 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:48,212 INFO L748 eck$LassoCheckResult]: Stem: 35063#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 35064#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 35844#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35845#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35037#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 35038#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36278#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36247#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36248#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35396#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35397#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35812#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36214#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35300#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35301#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 35191#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 35192#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36145#L1109 assume !(0 == ~M_E~0); 36162#L1109-2 assume !(0 == ~T1_E~0); 35200#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35201#L1119-1 assume !(0 == ~T3_E~0); 36217#L1124-1 assume !(0 == ~T4_E~0); 34851#L1129-1 assume !(0 == ~T5_E~0); 34852#L1134-1 assume !(0 == ~T6_E~0); 35483#L1139-1 assume !(0 == ~T7_E~0); 36153#L1144-1 assume !(0 == ~T8_E~0); 36023#L1149-1 assume !(0 == ~T9_E~0); 34962#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34963#L1159-1 assume !(0 == ~T11_E~0); 36013#L1164-1 assume !(0 == ~E_M~0); 35358#L1169-1 assume !(0 == ~E_1~0); 35252#L1174-1 assume !(0 == ~E_2~0); 35116#L1179-1 assume !(0 == ~E_3~0); 35043#L1184-1 assume !(0 == ~E_4~0); 35044#L1189-1 assume !(0 == ~E_5~0); 35076#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 35159#L1199-1 assume !(0 == ~E_7~0); 36032#L1204-1 assume !(0 == ~E_8~0); 35973#L1209-1 assume !(0 == ~E_9~0); 35974#L1214-1 assume !(0 == ~E_10~0); 36291#L1219-1 assume !(0 == ~E_11~0); 36378#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35375#L544 assume 1 == ~m_pc~0; 35376#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36201#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35731#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35005#L1379 assume !(0 != activate_threads_~tmp~1#1); 35006#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35799#L563 assume !(1 == ~t1_pc~0); 35605#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34861#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34862#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35921#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 34857#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34858#L582 assume 1 == ~t2_pc~0; 35583#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35926#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35196#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35197#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 34890#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34891#L601 assume !(1 == ~t3_pc~0); 35600#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 35599#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36053#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35958#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 35959#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35907#L620 assume 1 == ~t4_pc~0; 34871#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34872#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34904#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34905#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 35809#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35991#L639 assume 1 == ~t5_pc~0; 35881#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35164#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35165#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35829#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 35830#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35764#L658 assume !(1 == ~t6_pc~0); 35372#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 35373#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35188#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35189#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35962#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35211#L677 assume 1 == ~t7_pc~0; 35212#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35109#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36119#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36240#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 36241#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36311#L696 assume !(1 == ~t8_pc~0); 35436#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35437#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36276#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36314#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 36359#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35868#L715 assume 1 == ~t9_pc~0; 35869#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35536#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35250#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35251#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 35851#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36114#L734 assume !(1 == ~t10_pc~0); 36115#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35328#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35329#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36057#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 36058#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35410#L753 assume 1 == ~t11_pc~0; 35411#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 35967#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36285#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35686#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 35687#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35738#L1237 assume !(1 == ~M_E~0); 35739#L1237-2 assume !(1 == ~T1_E~0); 36342#L1242-1 assume !(1 == ~T2_E~0); 35504#L1247-1 assume !(1 == ~T3_E~0); 35505#L1252-1 assume !(1 == ~T4_E~0); 35269#L1257-1 assume !(1 == ~T5_E~0); 35270#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36134#L1267-1 assume !(1 == ~T7_E~0); 36232#L1272-1 assume !(1 == ~T8_E~0); 35594#L1277-1 assume !(1 == ~T9_E~0); 35595#L1282-1 assume !(1 == ~T10_E~0); 36000#L1287-1 assume !(1 == ~T11_E~0); 36001#L1292-1 assume !(1 == ~E_M~0); 35961#L1297-1 assume !(1 == ~E_1~0); 35401#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 35402#L1307-1 assume !(1 == ~E_3~0); 36221#L1312-1 assume !(1 == ~E_4~0); 35640#L1317-1 assume !(1 == ~E_5~0); 35641#L1322-1 assume !(1 == ~E_6~0); 35345#L1327-1 assume !(1 == ~E_7~0); 35346#L1332-1 assume !(1 == ~E_8~0); 35920#L1337-1 assume !(1 == ~E_9~0); 35854#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 35855#L1347-1 assume !(1 == ~E_11~0); 36220#L1352-1 assume { :end_inline_reset_delta_events } true; 36118#L1678-2 [2023-11-19 07:43:48,212 INFO L750 eck$LassoCheckResult]: Loop: 36118#L1678-2 assume !false; 35910#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35911#L1084-1 assume !false; 35707#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35708#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34981#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 36206#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 34901#L925 assume !(0 != eval_~tmp~0#1); 34903#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35394#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35395#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34874#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34875#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35963#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35964#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35988#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35989#L1134-3 assume !(0 == ~T6_E~0); 36158#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36209#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 35385#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35386#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 35647#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 35648#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35903#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35904#L1174-3 assume !(0 == ~E_2~0); 35951#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35952#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36097#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35793#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 35138#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 35139#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35365#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 34824#L1214-3 assume !(0 == ~E_10~0); 34825#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 35548#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35549#L544-39 assume 1 == ~m_pc~0; 35895#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 34813#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35871#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35219#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35220#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36084#L563-39 assume 1 == ~t1_pc~0; 36090#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34958#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36369#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36370#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36373#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36192#L582-39 assume 1 == ~t2_pc~0; 35281#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35282#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35617#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35618#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35052#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34836#L601-39 assume 1 == ~t3_pc~0; 34837#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34885#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36051#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36380#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36088#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35759#L620-39 assume 1 == ~t4_pc~0; 35760#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35949#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35784#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35785#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36061#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36384#L639-39 assume !(1 == ~t5_pc~0); 36176#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 35507#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35508#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34863#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 34864#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35796#L658-39 assume 1 == ~t6_pc~0; 35779#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 35780#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36236#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35972#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35946#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35947#L677-39 assume !(1 == ~t7_pc~0); 35592#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 35041#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35042#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35097#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35098#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35689#L696-39 assume 1 == ~t8_pc~0; 35655#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35530#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35531#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35821#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35789#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35669#L715-39 assume 1 == ~t9_pc~0; 34841#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34843#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34918#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34919#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35994#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35995#L734-39 assume 1 == ~t10_pc~0; 35924#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35357#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35692#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34995#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34996#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36250#L753-39 assume !(1 == ~t11_pc~0); 34914#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 34915#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35818#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35660#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35661#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35756#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35757#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36015#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36016#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36231#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35939#L1257-3 assume !(1 == ~T5_E~0); 35940#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36204#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36253#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36356#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 35068#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 35069#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34978#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 34979#L1297-3 assume !(1 == ~E_1~0); 36127#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36128#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36308#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36381#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36035#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36036#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35034#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35011#L1337-3 assume !(1 == ~E_9~0); 35012#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35727#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 35849#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35850#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34960#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35166#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 35167#L1697 assume !(0 == start_simulation_~tmp~3#1); 35746#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35747#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 35085#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 34853#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 34854#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35815#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35816#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 36117#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 36118#L1678-2 [2023-11-19 07:43:48,213 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:48,213 INFO L85 PathProgramCache]: Analyzing trace with hash -24556996, now seen corresponding path program 1 times [2023-11-19 07:43:48,213 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:48,214 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [634633780] [2023-11-19 07:43:48,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:48,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:48,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:48,321 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:48,321 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:48,322 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [634633780] [2023-11-19 07:43:48,322 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [634633780] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:48,322 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:48,322 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:48,322 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [302667822] [2023-11-19 07:43:48,323 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:48,323 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:48,323 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:48,324 INFO L85 PathProgramCache]: Analyzing trace with hash -231211919, now seen corresponding path program 1 times [2023-11-19 07:43:48,324 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:48,324 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [483254263] [2023-11-19 07:43:48,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:48,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:48,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:48,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:48,399 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:48,399 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [483254263] [2023-11-19 07:43:48,399 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [483254263] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:48,400 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:48,400 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:48,400 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1613087610] [2023-11-19 07:43:48,400 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:48,401 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:48,401 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:48,401 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:43:48,401 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:43:48,401 INFO L87 Difference]: Start difference. First operand 1578 states and 2327 transitions. cyclomatic complexity: 750 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:48,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:48,640 INFO L93 Difference]: Finished difference Result 2919 states and 4289 transitions. [2023-11-19 07:43:48,640 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2919 states and 4289 transitions. [2023-11-19 07:43:48,662 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2744 [2023-11-19 07:43:48,689 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2919 states to 2919 states and 4289 transitions. [2023-11-19 07:43:48,690 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2919 [2023-11-19 07:43:48,694 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2919 [2023-11-19 07:43:48,694 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2919 states and 4289 transitions. [2023-11-19 07:43:48,699 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:48,700 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2919 states and 4289 transitions. [2023-11-19 07:43:48,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2919 states and 4289 transitions. [2023-11-19 07:43:48,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2919 to 2919. [2023-11-19 07:43:48,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2919 states, 2919 states have (on average 1.4693388146625557) internal successors, (4289), 2918 states have internal predecessors, (4289), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:48,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2919 states to 2919 states and 4289 transitions. [2023-11-19 07:43:48,788 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2919 states and 4289 transitions. [2023-11-19 07:43:48,788 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:43:48,789 INFO L428 stractBuchiCegarLoop]: Abstraction has 2919 states and 4289 transitions. [2023-11-19 07:43:48,789 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-19 07:43:48,790 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2919 states and 4289 transitions. [2023-11-19 07:43:48,806 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2744 [2023-11-19 07:43:48,806 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:48,807 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:48,810 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:48,810 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:48,811 INFO L748 eck$LassoCheckResult]: Stem: 39570#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 39571#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 40373#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40374#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39544#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 39545#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40886#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40845#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40846#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39906#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39907#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40339#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40803#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 39811#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 39812#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 39699#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 39700#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40715#L1109 assume !(0 == ~M_E~0); 40734#L1109-2 assume !(0 == ~T1_E~0); 39708#L1114-1 assume !(0 == ~T2_E~0); 39709#L1119-1 assume !(0 == ~T3_E~0); 40808#L1124-1 assume !(0 == ~T4_E~0); 39358#L1129-1 assume !(0 == ~T5_E~0); 39359#L1134-1 assume !(0 == ~T6_E~0); 39993#L1139-1 assume !(0 == ~T7_E~0); 40721#L1144-1 assume !(0 == ~T8_E~0); 40567#L1149-1 assume !(0 == ~T9_E~0); 39471#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 39472#L1159-1 assume !(0 == ~T11_E~0); 40555#L1164-1 assume !(0 == ~E_M~0); 39867#L1169-1 assume !(0 == ~E_1~0); 39760#L1174-1 assume !(0 == ~E_2~0); 39628#L1179-1 assume !(0 == ~E_3~0); 39550#L1184-1 assume !(0 == ~E_4~0); 39551#L1189-1 assume !(0 == ~E_5~0); 39583#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 39670#L1199-1 assume !(0 == ~E_7~0); 40576#L1204-1 assume !(0 == ~E_8~0); 40510#L1209-1 assume !(0 == ~E_9~0); 40511#L1214-1 assume !(0 == ~E_10~0); 40901#L1219-1 assume !(0 == ~E_11~0); 41046#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39887#L544 assume 1 == ~m_pc~0; 39888#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 40783#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40251#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39512#L1379 assume !(0 != activate_threads_~tmp~1#1); 39513#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40328#L563 assume !(1 == ~t1_pc~0); 40119#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39368#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39369#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40453#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 39364#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39365#L582 assume 1 == ~t2_pc~0; 40097#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 40458#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39704#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39705#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 39397#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39398#L601 assume !(1 == ~t3_pc~0); 40114#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 40113#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40598#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40494#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 40495#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40438#L620 assume 1 == ~t4_pc~0; 39378#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39379#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39411#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39412#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 40336#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40532#L639 assume 1 == ~t5_pc~0; 40410#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39673#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39674#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40356#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 40357#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40289#L658 assume !(1 == ~t6_pc~0); 39882#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 39883#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39696#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39697#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40498#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39721#L677 assume 1 == ~t7_pc~0; 39722#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39619#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40676#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40837#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 40838#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40931#L696 assume !(1 == ~t8_pc~0); 39947#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39948#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40884#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40934#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 41011#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40396#L715 assume 1 == ~t9_pc~0; 40397#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40050#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39758#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39759#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 40379#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40673#L734 assume !(1 == ~t10_pc~0); 40674#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 39837#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39838#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40602#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 40603#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39920#L753 assume 1 == ~t11_pc~0; 39921#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 40503#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40893#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40206#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 40207#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40260#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 40261#L1237-2 assume !(1 == ~T1_E~0); 40982#L1242-1 assume !(1 == ~T2_E~0); 40017#L1247-1 assume !(1 == ~T3_E~0); 40018#L1252-1 assume !(1 == ~T4_E~0); 39777#L1257-1 assume !(1 == ~T5_E~0); 39778#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40697#L1267-1 assume !(1 == ~T7_E~0); 40828#L1272-1 assume !(1 == ~T8_E~0); 40108#L1277-1 assume !(1 == ~T9_E~0); 40109#L1282-1 assume !(1 == ~T10_E~0); 40542#L1287-1 assume !(1 == ~T11_E~0); 40543#L1292-1 assume !(1 == ~E_M~0); 40497#L1297-1 assume !(1 == ~E_1~0); 39911#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 39912#L1307-1 assume !(1 == ~E_3~0); 40812#L1312-1 assume !(1 == ~E_4~0); 40155#L1317-1 assume !(1 == ~E_5~0); 40156#L1322-1 assume !(1 == ~E_6~0); 39854#L1327-1 assume !(1 == ~E_7~0); 39855#L1332-1 assume !(1 == ~E_8~0); 40452#L1337-1 assume !(1 == ~E_9~0); 40382#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 40383#L1347-1 assume !(1 == ~E_11~0); 40936#L1352-1 assume { :end_inline_reset_delta_events } true; 41081#L1678-2 [2023-11-19 07:43:48,812 INFO L750 eck$LassoCheckResult]: Loop: 41081#L1678-2 assume !false; 40443#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40444#L1084-1 assume !false; 41079#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40923#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 39488#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 41027#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 41065#L925 assume !(0 != eval_~tmp~0#1); 40193#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40194#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41064#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 39381#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 39382#L1114-3 assume !(0 == ~T2_E~0); 40499#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40500#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40529#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40530#L1134-3 assume !(0 == ~T6_E~0); 40727#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40797#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 39895#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 39896#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 40162#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40163#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 40434#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40435#L1174-3 assume !(0 == ~E_2~0); 40486#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40487#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40646#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40317#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 39645#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 39646#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 39875#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39331#L1214-3 assume !(0 == ~E_10~0); 39332#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 40062#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40063#L544-39 assume !(1 == ~m_pc~0); 39319#L544-41 is_master_triggered_~__retres1~0#1 := 0; 39320#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40399#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39727#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39728#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40630#L563-39 assume !(1 == ~t1_pc~0); 39464#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 39465#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41030#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41031#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41038#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40774#L582-39 assume 1 == ~t2_pc~0; 39789#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39790#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40131#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40132#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 39559#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39343#L601-39 assume 1 == ~t3_pc~0; 39344#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39392#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40596#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41050#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40635#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40282#L620-39 assume 1 == ~t4_pc~0; 40283#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 40482#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40308#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40309#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40606#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41060#L639-39 assume 1 == ~t5_pc~0; 40749#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40021#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40022#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39370#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 39371#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41025#L658-39 assume !(1 == ~t6_pc~0); 40305#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 40304#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40833#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40508#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40478#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40479#L677-39 assume 1 == ~t7_pc~0; 42021#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42019#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42017#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42015#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 42013#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42011#L696-39 assume 1 == ~t8_pc~0; 42007#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42005#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42003#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42001#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41999#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41998#L715-39 assume !(1 == ~t9_pc~0); 41994#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 41992#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41990#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41989#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41988#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41987#L734-39 assume !(1 == ~t10_pc~0); 41984#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 41982#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41981#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41980#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41979#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41978#L753-39 assume !(1 == ~t11_pc~0); 41976#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 41975#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41974#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41973#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 41972#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41971#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 40279#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41970#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40558#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41969#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41968#L1257-3 assume !(1 == ~T5_E~0); 41967#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41966#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41965#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41964#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41963#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 41962#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41961#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41960#L1297-3 assume !(1 == ~E_1~0); 41959#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41958#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41957#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41956#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41955#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 41954#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41953#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41952#L1337-3 assume !(1 == ~E_9~0); 41951#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 41950#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41949#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41945#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 41936#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 41935#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 41934#L1697 assume !(0 == start_simulation_~tmp~3#1); 40769#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41924#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 41921#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 41920#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 41919#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41918#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40857#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 40858#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 41081#L1678-2 [2023-11-19 07:43:48,813 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:48,813 INFO L85 PathProgramCache]: Analyzing trace with hash -1257740808, now seen corresponding path program 1 times [2023-11-19 07:43:48,813 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:48,813 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [241502673] [2023-11-19 07:43:48,814 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:48,814 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:48,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:48,955 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:48,955 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:48,956 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [241502673] [2023-11-19 07:43:48,956 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [241502673] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:48,956 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:48,956 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:48,956 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1201550311] [2023-11-19 07:43:48,957 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:48,957 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:48,957 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:48,958 INFO L85 PathProgramCache]: Analyzing trace with hash -1594991374, now seen corresponding path program 1 times [2023-11-19 07:43:48,958 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:48,958 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [602473691] [2023-11-19 07:43:48,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:48,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:48,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:49,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:49,038 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:49,038 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [602473691] [2023-11-19 07:43:49,038 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [602473691] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:49,038 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:49,038 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:49,039 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1010548368] [2023-11-19 07:43:49,039 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:49,039 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:49,040 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:49,040 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:43:49,041 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:43:49,041 INFO L87 Difference]: Start difference. First operand 2919 states and 4289 transitions. cyclomatic complexity: 1372 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:49,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:49,214 INFO L93 Difference]: Finished difference Result 5589 states and 8190 transitions. [2023-11-19 07:43:49,214 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5589 states and 8190 transitions. [2023-11-19 07:43:49,255 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5378 [2023-11-19 07:43:49,293 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5589 states to 5589 states and 8190 transitions. [2023-11-19 07:43:49,293 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5589 [2023-11-19 07:43:49,301 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5589 [2023-11-19 07:43:49,301 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5589 states and 8190 transitions. [2023-11-19 07:43:49,310 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:49,310 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5589 states and 8190 transitions. [2023-11-19 07:43:49,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5589 states and 8190 transitions. [2023-11-19 07:43:49,426 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5589 to 5589. [2023-11-19 07:43:49,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5589 states, 5589 states have (on average 1.465378421900161) internal successors, (8190), 5588 states have internal predecessors, (8190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:49,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5589 states to 5589 states and 8190 transitions. [2023-11-19 07:43:49,455 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5589 states and 8190 transitions. [2023-11-19 07:43:49,455 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:43:49,456 INFO L428 stractBuchiCegarLoop]: Abstraction has 5589 states and 8190 transitions. [2023-11-19 07:43:49,456 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-19 07:43:49,456 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5589 states and 8190 transitions. [2023-11-19 07:43:49,483 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5378 [2023-11-19 07:43:49,483 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:49,484 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:49,487 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:49,487 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:49,488 INFO L748 eck$LassoCheckResult]: Stem: 48088#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 48089#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 48873#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48874#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48062#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 48063#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49318#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49287#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49288#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48422#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48423#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48841#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49251#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 48326#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 48327#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 48217#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 48218#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49179#L1109 assume !(0 == ~M_E~0); 49196#L1109-2 assume !(0 == ~T1_E~0); 48226#L1114-1 assume !(0 == ~T2_E~0); 48227#L1119-1 assume !(0 == ~T3_E~0); 49254#L1124-1 assume !(0 == ~T4_E~0); 47876#L1129-1 assume !(0 == ~T5_E~0); 47877#L1134-1 assume !(0 == ~T6_E~0); 48510#L1139-1 assume !(0 == ~T7_E~0); 49187#L1144-1 assume !(0 == ~T8_E~0); 49052#L1149-1 assume !(0 == ~T9_E~0); 47987#L1154-1 assume !(0 == ~T10_E~0); 47988#L1159-1 assume !(0 == ~T11_E~0); 49042#L1164-1 assume !(0 == ~E_M~0); 48384#L1169-1 assume !(0 == ~E_1~0); 48278#L1174-1 assume !(0 == ~E_2~0); 48142#L1179-1 assume !(0 == ~E_3~0); 48068#L1184-1 assume !(0 == ~E_4~0); 48069#L1189-1 assume !(0 == ~E_5~0); 48102#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 48185#L1199-1 assume !(0 == ~E_7~0); 49061#L1204-1 assume !(0 == ~E_8~0); 49002#L1209-1 assume !(0 == ~E_9~0); 49003#L1214-1 assume !(0 == ~E_10~0); 49331#L1219-1 assume !(0 == ~E_11~0); 49423#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48401#L544 assume 1 == ~m_pc~0; 48402#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49237#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48759#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 48030#L1379 assume !(0 != activate_threads_~tmp~1#1); 48031#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48828#L563 assume !(1 == ~t1_pc~0); 48633#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47886#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47887#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 48950#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 47882#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47883#L582 assume 1 == ~t2_pc~0; 48610#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 48955#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48222#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48223#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 47915#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47916#L601 assume !(1 == ~t3_pc~0); 48628#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 48627#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49082#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48987#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 48988#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48936#L620 assume 1 == ~t4_pc~0; 47896#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 47897#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47929#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47930#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 48838#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49020#L639 assume 1 == ~t5_pc~0; 48910#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48190#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48191#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48858#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 48859#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48793#L658 assume !(1 == ~t6_pc~0); 48398#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 48399#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48214#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48215#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 48991#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48237#L677 assume 1 == ~t7_pc~0; 48238#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 48135#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49150#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49280#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 49281#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49351#L696 assume !(1 == ~t8_pc~0); 48462#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 48463#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49316#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49354#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 49400#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48897#L715 assume 1 == ~t9_pc~0; 48898#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48563#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48276#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48277#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 48880#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49145#L734 assume !(1 == ~t10_pc~0); 49146#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 48354#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48355#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49086#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 49087#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48436#L753 assume 1 == ~t11_pc~0; 48437#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 48996#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49325#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48714#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 48715#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48766#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 48767#L1237-2 assume !(1 == ~T1_E~0); 49382#L1242-1 assume !(1 == ~T2_E~0); 50175#L1247-1 assume !(1 == ~T3_E~0); 50154#L1252-1 assume !(1 == ~T4_E~0); 48295#L1257-1 assume !(1 == ~T5_E~0); 48296#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49168#L1267-1 assume !(1 == ~T7_E~0); 49269#L1272-1 assume !(1 == ~T8_E~0); 48622#L1277-1 assume !(1 == ~T9_E~0); 48623#L1282-1 assume !(1 == ~T10_E~0); 49833#L1287-1 assume !(1 == ~T11_E~0); 49832#L1292-1 assume !(1 == ~E_M~0); 49831#L1297-1 assume !(1 == ~E_1~0); 49829#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 49826#L1307-1 assume !(1 == ~E_3~0); 49824#L1312-1 assume !(1 == ~E_4~0); 49823#L1317-1 assume !(1 == ~E_5~0); 49553#L1322-1 assume !(1 == ~E_6~0); 49534#L1327-1 assume !(1 == ~E_7~0); 49513#L1332-1 assume !(1 == ~E_8~0); 49495#L1337-1 assume !(1 == ~E_9~0); 49483#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 49474#L1347-1 assume !(1 == ~E_11~0); 49466#L1352-1 assume { :end_inline_reset_delta_events } true; 49460#L1678-2 [2023-11-19 07:43:49,488 INFO L750 eck$LassoCheckResult]: Loop: 49460#L1678-2 assume !false; 49456#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49455#L1084-1 assume !false; 49454#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49444#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49441#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49440#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 49438#L925 assume !(0 != eval_~tmp~0#1); 49437#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49436#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49435#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 47899#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 47900#L1114-3 assume !(0 == ~T2_E~0); 48992#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 48993#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49017#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49018#L1134-3 assume !(0 == ~T6_E~0); 49192#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49245#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48411#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 48412#L1154-3 assume !(0 == ~T10_E~0); 48675#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 48676#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 53327#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53326#L1174-3 assume !(0 == ~E_2~0); 53325#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 53324#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 53323#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53322#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53321#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 53320#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53319#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 53318#L1214-3 assume !(0 == ~E_10~0); 53317#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 53316#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53315#L544-39 assume !(1 == ~m_pc~0); 53313#L544-41 is_master_triggered_~__retres1~0#1 := 0; 53312#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53311#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 53310#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53309#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53308#L563-39 assume 1 == ~t1_pc~0; 53306#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53305#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53304#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 53303#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53302#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53301#L582-39 assume !(1 == ~t2_pc~0); 53299#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 53298#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53297#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53296#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 53295#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53294#L601-39 assume 1 == ~t3_pc~0; 53292#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 53291#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53290#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53289#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53288#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53287#L620-39 assume !(1 == ~t4_pc~0); 53285#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 53284#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53283#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53282#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53281#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53280#L639-39 assume 1 == ~t5_pc~0; 53278#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53277#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53276#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53275#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 53274#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53273#L658-39 assume 1 == ~t6_pc~0; 53271#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53270#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53269#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53268#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 53267#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53266#L677-39 assume 1 == ~t7_pc~0; 53264#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 48066#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48067#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48123#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 48124#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48717#L696-39 assume 1 == ~t8_pc~0; 48683#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 48557#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48558#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48850#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 48818#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48697#L715-39 assume 1 == ~t9_pc~0; 47866#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47868#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47943#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47944#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49023#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49024#L734-39 assume 1 == ~t10_pc~0; 48953#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 48383#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48720#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48020#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48021#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49290#L753-39 assume !(1 == ~t11_pc~0); 47939#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 47940#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48847#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48688#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 48689#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48785#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 48786#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49044#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 49045#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53357#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53356#L1257-3 assume !(1 == ~T5_E~0); 53355#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 53354#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49431#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49396#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49397#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50060#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50058#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50056#L1297-3 assume !(1 == ~E_1~0); 50054#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50051#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50049#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50047#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50045#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50043#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50041#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50038#L1337-3 assume !(1 == ~E_9~0); 50036#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 50034#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 50032#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 50024#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 50014#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 50012#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 50010#L1697 assume !(0 == start_simulation_~tmp~3#1); 49224#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49556#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49535#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49514#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 49496#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49484#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49475#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 49467#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 49460#L1678-2 [2023-11-19 07:43:49,489 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:49,489 INFO L85 PathProgramCache]: Analyzing trace with hash -786384458, now seen corresponding path program 1 times [2023-11-19 07:43:49,490 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:49,490 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1620316197] [2023-11-19 07:43:49,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:49,490 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:49,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:49,590 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:49,590 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:49,590 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1620316197] [2023-11-19 07:43:49,590 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1620316197] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:49,591 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:49,591 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:49,591 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [760017865] [2023-11-19 07:43:49,591 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:49,594 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:49,594 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:49,595 INFO L85 PathProgramCache]: Analyzing trace with hash 55939374, now seen corresponding path program 1 times [2023-11-19 07:43:49,595 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:49,595 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [840303375] [2023-11-19 07:43:49,595 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:49,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:49,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:49,729 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:49,729 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:49,729 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [840303375] [2023-11-19 07:43:49,729 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [840303375] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:49,730 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:49,730 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:49,730 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [208808633] [2023-11-19 07:43:49,730 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:49,731 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:49,731 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:49,731 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:43:49,732 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:43:49,732 INFO L87 Difference]: Start difference. First operand 5589 states and 8190 transitions. cyclomatic complexity: 2605 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:50,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:50,008 INFO L93 Difference]: Finished difference Result 10549 states and 15425 transitions. [2023-11-19 07:43:50,008 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10549 states and 15425 transitions. [2023-11-19 07:43:50,077 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10302 [2023-11-19 07:43:50,131 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10549 states to 10549 states and 15425 transitions. [2023-11-19 07:43:50,131 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10549 [2023-11-19 07:43:50,144 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10549 [2023-11-19 07:43:50,144 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10549 states and 15425 transitions. [2023-11-19 07:43:50,159 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:50,159 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10549 states and 15425 transitions. [2023-11-19 07:43:50,173 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10549 states and 15425 transitions. [2023-11-19 07:43:50,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10549 to 10545. [2023-11-19 07:43:50,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10545 states, 10545 states have (on average 1.4623992413466098) internal successors, (15421), 10544 states have internal predecessors, (15421), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:50,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10545 states to 10545 states and 15421 transitions. [2023-11-19 07:43:50,499 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10545 states and 15421 transitions. [2023-11-19 07:43:50,500 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:43:50,501 INFO L428 stractBuchiCegarLoop]: Abstraction has 10545 states and 15421 transitions. [2023-11-19 07:43:50,501 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-19 07:43:50,501 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10545 states and 15421 transitions. [2023-11-19 07:43:50,558 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10302 [2023-11-19 07:43:50,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:50,559 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:50,562 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:50,562 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:50,563 INFO L748 eck$LassoCheckResult]: Stem: 64236#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 64237#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 65022#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 65023#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64210#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 64211#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 65474#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 65440#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 65441#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 64571#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64572#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 64990#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 65404#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 64475#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 64476#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 64365#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 64366#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 65333#L1109 assume !(0 == ~M_E~0); 65350#L1109-2 assume !(0 == ~T1_E~0); 64374#L1114-1 assume !(0 == ~T2_E~0); 64375#L1119-1 assume !(0 == ~T3_E~0); 65407#L1124-1 assume !(0 == ~T4_E~0); 64024#L1129-1 assume !(0 == ~T5_E~0); 64025#L1134-1 assume !(0 == ~T6_E~0); 64658#L1139-1 assume !(0 == ~T7_E~0); 65341#L1144-1 assume !(0 == ~T8_E~0); 65207#L1149-1 assume !(0 == ~T9_E~0); 64135#L1154-1 assume !(0 == ~T10_E~0); 64136#L1159-1 assume !(0 == ~T11_E~0); 65196#L1164-1 assume !(0 == ~E_M~0); 64533#L1169-1 assume !(0 == ~E_1~0); 64427#L1174-1 assume !(0 == ~E_2~0); 64289#L1179-1 assume !(0 == ~E_3~0); 64216#L1184-1 assume !(0 == ~E_4~0); 64217#L1189-1 assume !(0 == ~E_5~0); 64249#L1194-1 assume !(0 == ~E_6~0); 64332#L1199-1 assume !(0 == ~E_7~0); 65216#L1204-1 assume !(0 == ~E_8~0); 65156#L1209-1 assume !(0 == ~E_9~0); 65157#L1214-1 assume !(0 == ~E_10~0); 65489#L1219-1 assume !(0 == ~E_11~0); 65584#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64550#L544 assume 1 == ~m_pc~0; 64551#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 65391#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64907#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 64178#L1379 assume !(0 != activate_threads_~tmp~1#1); 64179#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64977#L563 assume !(1 == ~t1_pc~0); 64780#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 64034#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64035#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 65103#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 64030#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64031#L582 assume 1 == ~t2_pc~0; 64758#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 65109#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64370#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64371#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 64063#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64064#L601 assume !(1 == ~t3_pc~0); 64775#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 64774#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65237#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65141#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 65142#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65089#L620 assume 1 == ~t4_pc~0; 64044#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 64045#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64077#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64078#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 64987#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65174#L639 assume 1 == ~t5_pc~0; 65063#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64337#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64338#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65007#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 65008#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64942#L658 assume !(1 == ~t6_pc~0); 64547#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 64548#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64362#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64363#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 65145#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64385#L677 assume 1 == ~t7_pc~0; 64386#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 64282#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65305#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65431#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 65432#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 65509#L696 assume !(1 == ~t8_pc~0); 64611#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 64612#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65472#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65512#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 65560#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 65050#L715 assume 1 == ~t9_pc~0; 65051#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 64711#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64425#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 64426#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 65030#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 65300#L734 assume !(1 == ~t10_pc~0); 65301#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 64503#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 64504#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65241#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 65242#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 64585#L753 assume 1 == ~t11_pc~0; 64586#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 65150#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 65483#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 64862#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 64863#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64914#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 64915#L1237-2 assume !(1 == ~T1_E~0); 65543#L1242-1 assume !(1 == ~T2_E~0); 65917#L1247-1 assume !(1 == ~T3_E~0); 65866#L1252-1 assume !(1 == ~T4_E~0); 65864#L1257-1 assume !(1 == ~T5_E~0); 65862#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 65828#L1267-1 assume !(1 == ~T7_E~0); 65826#L1272-1 assume !(1 == ~T8_E~0); 65792#L1277-1 assume !(1 == ~T9_E~0); 65790#L1282-1 assume !(1 == ~T10_E~0); 65788#L1287-1 assume !(1 == ~T11_E~0); 65785#L1292-1 assume !(1 == ~E_M~0); 65783#L1297-1 assume !(1 == ~E_1~0); 65781#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 65746#L1307-1 assume !(1 == ~E_3~0); 65715#L1312-1 assume !(1 == ~E_4~0); 65702#L1317-1 assume !(1 == ~E_5~0); 65682#L1322-1 assume !(1 == ~E_6~0); 65679#L1327-1 assume !(1 == ~E_7~0); 65657#L1332-1 assume !(1 == ~E_8~0); 65655#L1337-1 assume !(1 == ~E_9~0); 65643#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 65634#L1347-1 assume !(1 == ~E_11~0); 65626#L1352-1 assume { :end_inline_reset_delta_events } true; 65620#L1678-2 [2023-11-19 07:43:50,564 INFO L750 eck$LassoCheckResult]: Loop: 65620#L1678-2 assume !false; 65616#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65615#L1084-1 assume !false; 65614#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65604#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65601#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65600#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 65598#L925 assume !(0 != eval_~tmp~0#1); 65597#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 65596#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 65594#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 65595#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 69762#L1114-3 assume !(0 == ~T2_E~0); 69760#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 69758#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 69756#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 69754#L1134-3 assume !(0 == ~T6_E~0); 69751#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 69749#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 69747#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 69745#L1154-3 assume !(0 == ~T10_E~0); 69743#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 69741#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 69738#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 69736#L1174-3 assume !(0 == ~E_2~0); 69647#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 69637#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 69629#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 69621#L1194-3 assume !(0 == ~E_6~0); 69615#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 66960#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 66957#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 66955#L1214-3 assume !(0 == ~E_10~0); 66953#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 66951#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66949#L544-39 assume !(1 == ~m_pc~0); 66945#L544-41 is_master_triggered_~__retres1~0#1 := 0; 66943#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66941#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 66939#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 66937#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66935#L563-39 assume 1 == ~t1_pc~0; 66931#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 66928#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66926#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 66925#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 66858#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66750#L582-39 assume !(1 == ~t2_pc~0); 66747#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 66744#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66742#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 66740#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 66738#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66736#L601-39 assume 1 == ~t3_pc~0; 66733#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 66730#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66728#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66642#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 66639#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66548#L620-39 assume !(1 == ~t4_pc~0); 66505#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 66503#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66501#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 66499#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66497#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66494#L639-39 assume 1 == ~t5_pc~0; 66491#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 66490#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66489#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 66488#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 66487#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66485#L658-39 assume !(1 == ~t6_pc~0); 66483#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 66480#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66477#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 66475#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 66473#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 66471#L677-39 assume 1 == ~t7_pc~0; 66397#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 66395#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66393#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66391#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 66389#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 66387#L696-39 assume !(1 == ~t8_pc~0); 66384#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 66381#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66379#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66377#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 66375#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 66373#L715-39 assume !(1 == ~t9_pc~0); 66297#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 66214#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66211#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 66209#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 66207#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 66205#L734-39 assume 1 == ~t10_pc~0; 66199#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 66197#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 66195#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 66193#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 66191#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 66189#L753-39 assume !(1 == ~t11_pc~0); 66099#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 66097#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 66095#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 66043#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 65978#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65933#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 64934#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 65930#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 65928#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 65927#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 65926#L1257-3 assume !(1 == ~T5_E~0); 65925#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 65874#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 65872#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 65870#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 65868#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 65865#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 65863#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 65861#L1297-3 assume !(1 == ~E_1~0); 65827#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 65793#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 65791#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 65789#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 65787#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 65784#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 65782#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 65780#L1337-3 assume !(1 == ~E_9~0); 65779#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 65778#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 65777#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65742#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65733#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65732#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 65731#L1697 assume !(0 == start_simulation_~tmp~3#1); 65378#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65705#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65683#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65658#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 65656#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 65644#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 65635#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 65627#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 65620#L1678-2 [2023-11-19 07:43:50,565 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:50,565 INFO L85 PathProgramCache]: Analyzing trace with hash 602909556, now seen corresponding path program 1 times [2023-11-19 07:43:50,565 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:50,566 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [522865820] [2023-11-19 07:43:50,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:50,566 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:50,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:50,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:50,719 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:50,719 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [522865820] [2023-11-19 07:43:50,719 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [522865820] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:50,719 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:50,719 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:43:50,719 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1763382533] [2023-11-19 07:43:50,720 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:50,720 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:50,721 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:50,721 INFO L85 PathProgramCache]: Analyzing trace with hash 1775687791, now seen corresponding path program 1 times [2023-11-19 07:43:50,721 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:50,721 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1979023978] [2023-11-19 07:43:50,721 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:50,722 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:50,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:50,805 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:50,805 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:50,806 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1979023978] [2023-11-19 07:43:50,806 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1979023978] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:50,806 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:50,806 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:50,806 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [183290998] [2023-11-19 07:43:50,807 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:50,807 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:50,807 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:50,808 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:43:50,808 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:43:50,808 INFO L87 Difference]: Start difference. First operand 10545 states and 15421 transitions. cyclomatic complexity: 4884 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:51,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:51,093 INFO L93 Difference]: Finished difference Result 20721 states and 30086 transitions. [2023-11-19 07:43:51,093 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20721 states and 30086 transitions. [2023-11-19 07:43:51,347 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 20471 [2023-11-19 07:43:51,442 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20721 states to 20721 states and 30086 transitions. [2023-11-19 07:43:51,442 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20721 [2023-11-19 07:43:51,469 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20721 [2023-11-19 07:43:51,469 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20721 states and 30086 transitions. [2023-11-19 07:43:51,492 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:51,492 INFO L218 hiAutomatonCegarLoop]: Abstraction has 20721 states and 30086 transitions. [2023-11-19 07:43:51,518 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20721 states and 30086 transitions. [2023-11-19 07:43:51,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20721 to 20057. [2023-11-19 07:43:51,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20057 states, 20057 states have (on average 1.4533579298997856) internal successors, (29150), 20056 states have internal predecessors, (29150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:52,124 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20057 states to 20057 states and 29150 transitions. [2023-11-19 07:43:52,124 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20057 states and 29150 transitions. [2023-11-19 07:43:52,125 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:43:52,126 INFO L428 stractBuchiCegarLoop]: Abstraction has 20057 states and 29150 transitions. [2023-11-19 07:43:52,126 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-19 07:43:52,126 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20057 states and 29150 transitions. [2023-11-19 07:43:52,299 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19807 [2023-11-19 07:43:52,299 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:52,299 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:52,301 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:52,302 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:52,302 INFO L748 eck$LassoCheckResult]: Stem: 95510#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 95511#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 96336#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 96337#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 95483#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 95484#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 96858#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 96816#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 96817#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 95854#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 95855#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 96295#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 96769#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 95755#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 95756#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 95641#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 95642#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 96683#L1109 assume !(0 == ~M_E~0); 96704#L1109-2 assume !(0 == ~T1_E~0); 95650#L1114-1 assume !(0 == ~T2_E~0); 95651#L1119-1 assume !(0 == ~T3_E~0); 96772#L1124-1 assume !(0 == ~T4_E~0); 95297#L1129-1 assume !(0 == ~T5_E~0); 95298#L1134-1 assume !(0 == ~T6_E~0); 95944#L1139-1 assume !(0 == ~T7_E~0); 96693#L1144-1 assume !(0 == ~T8_E~0); 96537#L1149-1 assume !(0 == ~T9_E~0); 95408#L1154-1 assume !(0 == ~T10_E~0); 95409#L1159-1 assume !(0 == ~T11_E~0); 96526#L1164-1 assume !(0 == ~E_M~0); 95815#L1169-1 assume !(0 == ~E_1~0); 95704#L1174-1 assume !(0 == ~E_2~0); 95565#L1179-1 assume !(0 == ~E_3~0); 95489#L1184-1 assume !(0 == ~E_4~0); 95490#L1189-1 assume !(0 == ~E_5~0); 95524#L1194-1 assume !(0 == ~E_6~0); 95608#L1199-1 assume !(0 == ~E_7~0); 96546#L1204-1 assume !(0 == ~E_8~0); 96482#L1209-1 assume !(0 == ~E_9~0); 96483#L1214-1 assume !(0 == ~E_10~0); 96878#L1219-1 assume !(0 == ~E_11~0); 97042#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95832#L544 assume !(1 == ~m_pc~0); 95833#L544-2 is_master_triggered_~__retres1~0#1 := 0; 96752#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96203#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 95450#L1379 assume !(0 != activate_threads_~tmp~1#1); 95451#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96279#L563 assume !(1 == ~t1_pc~0); 96071#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 95307#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95308#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 96425#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 95303#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95304#L582 assume 1 == ~t2_pc~0; 96048#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 96431#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95646#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 95647#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 95336#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95337#L601 assume !(1 == ~t3_pc~0); 96066#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 96065#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 96569#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 96467#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 96468#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96411#L620 assume 1 == ~t4_pc~0; 95317#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 95318#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95350#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 95351#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 96289#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 96503#L639 assume 1 == ~t5_pc~0; 96382#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 95613#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 95614#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 96314#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 96315#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 96242#L658 assume !(1 == ~t6_pc~0); 95829#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 95830#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95638#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 95639#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 96471#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 95661#L677 assume 1 == ~t7_pc~0; 95662#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 95557#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 96650#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 96804#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 96805#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 96912#L696 assume !(1 == ~t8_pc~0); 95896#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 95897#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96856#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 96915#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 96993#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 96366#L715 assume 1 == ~t9_pc~0; 96367#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 95999#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 95702#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 95703#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 96343#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 96645#L734 assume !(1 == ~t10_pc~0); 96646#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 95785#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 95786#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 96574#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 96575#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 95869#L753 assume 1 == ~t11_pc~0; 95870#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 96476#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 96868#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 96157#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 96158#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96210#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 96211#L1237-2 assume !(1 == ~T1_E~0); 96961#L1242-1 assume !(1 == ~T2_E~0); 95966#L1247-1 assume !(1 == ~T3_E~0); 95967#L1252-1 assume !(1 == ~T4_E~0); 95721#L1257-1 assume !(1 == ~T5_E~0); 95722#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 96666#L1267-1 assume !(1 == ~T7_E~0); 96792#L1272-1 assume !(1 == ~T8_E~0); 96060#L1277-1 assume !(1 == ~T9_E~0); 96061#L1282-1 assume !(1 == ~T10_E~0); 98575#L1287-1 assume !(1 == ~T11_E~0); 98521#L1292-1 assume !(1 == ~E_M~0); 98469#L1297-1 assume !(1 == ~E_1~0); 98467#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 98408#L1307-1 assume !(1 == ~E_3~0); 98406#L1312-1 assume !(1 == ~E_4~0); 98342#L1317-1 assume !(1 == ~E_5~0); 98283#L1322-1 assume !(1 == ~E_6~0); 98238#L1327-1 assume !(1 == ~E_7~0); 98211#L1332-1 assume !(1 == ~E_8~0); 98183#L1337-1 assume !(1 == ~E_9~0); 98181#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 98158#L1347-1 assume !(1 == ~E_11~0); 98146#L1352-1 assume { :end_inline_reset_delta_events } true; 98130#L1678-2 [2023-11-19 07:43:52,302 INFO L750 eck$LassoCheckResult]: Loop: 98130#L1678-2 assume !false; 98108#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 98101#L1084-1 assume !false; 98099#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 98078#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 98063#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 98061#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 98058#L925 assume !(0 != eval_~tmp~0#1); 98053#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 98054#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 103710#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 103708#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 103706#L1114-3 assume !(0 == ~T2_E~0); 103704#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 103702#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 103699#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 103697#L1134-3 assume !(0 == ~T6_E~0); 103695#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 103693#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 103691#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 103689#L1154-3 assume !(0 == ~T10_E~0); 103686#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 103685#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 103684#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 103682#L1174-3 assume !(0 == ~E_2~0); 103680#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 103678#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 103676#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 103674#L1194-3 assume !(0 == ~E_6~0); 103672#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 103670#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 103667#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 103665#L1214-3 assume !(0 == ~E_10~0); 103663#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 103661#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 103659#L544-39 assume !(1 == ~m_pc~0); 103657#L544-41 is_master_triggered_~__retres1~0#1 := 0; 103654#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103652#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 103651#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 103650#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 103649#L563-39 assume !(1 == ~t1_pc~0); 103648#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 103646#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 103645#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 103644#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 103643#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 103642#L582-39 assume 1 == ~t2_pc~0; 103639#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 103636#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 103634#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 103631#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 103629#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 103627#L601-39 assume !(1 == ~t3_pc~0); 103625#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 103622#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 103620#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 103619#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 103616#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 103614#L620-39 assume !(1 == ~t4_pc~0); 103611#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 103609#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 103607#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 103605#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 103602#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 103600#L639-39 assume 1 == ~t5_pc~0; 103595#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 103592#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 103590#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 103588#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 103586#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 103584#L658-39 assume 1 == ~t6_pc~0; 103581#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 103578#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 103576#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 103574#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 103572#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 103097#L677-39 assume 1 == ~t7_pc~0; 103093#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 102524#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 102521#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 102519#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 102517#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 102515#L696-39 assume !(1 == ~t8_pc~0); 102513#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 102510#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 102507#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 102505#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 102503#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 102501#L715-39 assume 1 == ~t9_pc~0; 102499#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 102496#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 102493#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 102491#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 102489#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 102487#L734-39 assume !(1 == ~t10_pc~0); 102485#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 102482#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 102480#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 102479#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 102478#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 102477#L753-39 assume !(1 == ~t11_pc~0); 102475#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 102473#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 102471#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 102469#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 102467#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 102465#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 98805#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 102460#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 102455#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 102453#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 102451#L1257-3 assume !(1 == ~T5_E~0); 102449#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 102447#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 102445#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 102442#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 102440#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 102436#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 98571#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 98518#L1297-3 assume !(1 == ~E_1~0); 98515#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 98463#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 98461#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 98459#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 98457#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 98453#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 98452#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 98451#L1337-3 assume !(1 == ~E_9~0); 98450#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 98449#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 98445#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 98397#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 98345#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 98344#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 98343#L1697 assume !(0 == start_simulation_~tmp~3#1); 96735#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 98286#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 98239#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 98214#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 98187#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 98161#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 98159#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 98147#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 98130#L1678-2 [2023-11-19 07:43:52,303 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:52,303 INFO L85 PathProgramCache]: Analyzing trace with hash -1258502475, now seen corresponding path program 1 times [2023-11-19 07:43:52,303 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:52,303 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1635170491] [2023-11-19 07:43:52,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:52,304 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:52,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:52,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:52,397 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:52,397 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1635170491] [2023-11-19 07:43:52,397 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1635170491] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:52,398 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:52,398 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:52,398 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1510752332] [2023-11-19 07:43:52,398 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:52,399 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:52,399 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:52,399 INFO L85 PathProgramCache]: Analyzing trace with hash 941009455, now seen corresponding path program 1 times [2023-11-19 07:43:52,400 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:52,400 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1350480667] [2023-11-19 07:43:52,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:52,400 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:52,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:52,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:52,486 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:52,486 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1350480667] [2023-11-19 07:43:52,486 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1350480667] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:52,487 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:52,487 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:52,487 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [232970088] [2023-11-19 07:43:52,487 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:52,488 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:52,488 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:52,489 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:43:52,489 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:43:52,489 INFO L87 Difference]: Start difference. First operand 20057 states and 29150 transitions. cyclomatic complexity: 9109 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:53,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:53,124 INFO L93 Difference]: Finished difference Result 48809 states and 70369 transitions. [2023-11-19 07:43:53,124 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48809 states and 70369 transitions. [2023-11-19 07:43:53,616 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 47832 [2023-11-19 07:43:53,832 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48809 states to 48809 states and 70369 transitions. [2023-11-19 07:43:53,832 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48809 [2023-11-19 07:43:53,875 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48809 [2023-11-19 07:43:53,875 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48809 states and 70369 transitions. [2023-11-19 07:43:53,980 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:53,980 INFO L218 hiAutomatonCegarLoop]: Abstraction has 48809 states and 70369 transitions. [2023-11-19 07:43:54,024 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48809 states and 70369 transitions. [2023-11-19 07:43:54,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48809 to 38277. [2023-11-19 07:43:54,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38277 states, 38277 states have (on average 1.4464038456514356) internal successors, (55364), 38276 states have internal predecessors, (55364), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:54,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38277 states to 38277 states and 55364 transitions. [2023-11-19 07:43:54,969 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38277 states and 55364 transitions. [2023-11-19 07:43:54,970 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:43:54,970 INFO L428 stractBuchiCegarLoop]: Abstraction has 38277 states and 55364 transitions. [2023-11-19 07:43:54,970 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-19 07:43:54,971 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38277 states and 55364 transitions. [2023-11-19 07:43:55,091 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 38020 [2023-11-19 07:43:55,091 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:55,092 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:55,095 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:55,095 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:55,096 INFO L748 eck$LassoCheckResult]: Stem: 164388#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 164389#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 165179#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 165180#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 164362#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 164363#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 165672#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 165637#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 165638#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 164724#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 164725#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 165146#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 165593#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 164631#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 164632#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 164518#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 164519#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 165504#L1109 assume !(0 == ~M_E~0); 165527#L1109-2 assume !(0 == ~T1_E~0); 164527#L1114-1 assume !(0 == ~T2_E~0); 164528#L1119-1 assume !(0 == ~T3_E~0); 165598#L1124-1 assume !(0 == ~T4_E~0); 164173#L1129-1 assume !(0 == ~T5_E~0); 164174#L1134-1 assume !(0 == ~T6_E~0); 164812#L1139-1 assume !(0 == ~T7_E~0); 165511#L1144-1 assume !(0 == ~T8_E~0); 165371#L1149-1 assume !(0 == ~T9_E~0); 164286#L1154-1 assume !(0 == ~T10_E~0); 164287#L1159-1 assume !(0 == ~T11_E~0); 165360#L1164-1 assume !(0 == ~E_M~0); 164687#L1169-1 assume !(0 == ~E_1~0); 164579#L1174-1 assume !(0 == ~E_2~0); 164447#L1179-1 assume !(0 == ~E_3~0); 164368#L1184-1 assume !(0 == ~E_4~0); 164369#L1189-1 assume !(0 == ~E_5~0); 164402#L1194-1 assume !(0 == ~E_6~0); 164490#L1199-1 assume !(0 == ~E_7~0); 165380#L1204-1 assume !(0 == ~E_8~0); 165316#L1209-1 assume !(0 == ~E_9~0); 165317#L1214-1 assume !(0 == ~E_10~0); 165685#L1219-1 assume !(0 == ~E_11~0); 165799#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 164706#L544 assume !(1 == ~m_pc~0); 164707#L544-2 is_master_triggered_~__retres1~0#1 := 0; 165575#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 165061#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 164330#L1379 assume !(0 != activate_threads_~tmp~1#1); 164331#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 165135#L563 assume !(1 == ~t1_pc~0); 164933#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 164183#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 164184#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 165260#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 164179#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 164180#L582 assume !(1 == ~t2_pc~0); 164912#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 165265#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 164523#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 164524#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 164212#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 164213#L601 assume !(1 == ~t3_pc~0); 164928#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 164927#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 165403#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 165297#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 165298#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 165245#L620 assume 1 == ~t4_pc~0; 164195#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 164196#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 164226#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 164227#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 165143#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 165335#L639 assume 1 == ~t5_pc~0; 165219#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 164493#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 164494#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 165163#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 165164#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 165098#L658 assume !(1 == ~t6_pc~0); 164701#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 164702#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 164515#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 164516#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 165302#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 164540#L677 assume 1 == ~t7_pc~0; 164541#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 164439#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 165473#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 165629#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 165630#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 165709#L696 assume !(1 == ~t8_pc~0); 164764#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 164765#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 165670#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 165712#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 165767#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 165205#L715 assume 1 == ~t9_pc~0; 165206#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 164865#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 164577#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 164578#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 165185#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 165470#L734 assume !(1 == ~t10_pc~0); 165471#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 164657#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 164658#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 165407#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 165408#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 164738#L753 assume 1 == ~t11_pc~0; 164739#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 165307#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 165679#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 165018#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 165019#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 165070#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 165071#L1237-2 assume !(1 == ~T1_E~0); 165784#L1242-1 assume !(1 == ~T2_E~0); 165785#L1247-1 assume !(1 == ~T3_E~0); 176164#L1252-1 assume !(1 == ~T4_E~0); 176155#L1257-1 assume !(1 == ~T5_E~0); 176153#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 176151#L1267-1 assume !(1 == ~T7_E~0); 176149#L1272-1 assume !(1 == ~T8_E~0); 164922#L1277-1 assume !(1 == ~T9_E~0); 164923#L1282-1 assume !(1 == ~T10_E~0); 176130#L1287-1 assume !(1 == ~T11_E~0); 176128#L1292-1 assume !(1 == ~E_M~0); 176126#L1297-1 assume !(1 == ~E_1~0); 176124#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 176122#L1307-1 assume !(1 == ~E_3~0); 176120#L1312-1 assume !(1 == ~E_4~0); 176118#L1317-1 assume !(1 == ~E_5~0); 176108#L1322-1 assume !(1 == ~E_6~0); 176105#L1327-1 assume !(1 == ~E_7~0); 176104#L1332-1 assume !(1 == ~E_8~0); 176103#L1337-1 assume !(1 == ~E_9~0); 176102#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 176101#L1347-1 assume !(1 == ~E_11~0); 176099#L1352-1 assume { :end_inline_reset_delta_events } true; 176091#L1678-2 [2023-11-19 07:43:55,097 INFO L750 eck$LassoCheckResult]: Loop: 176091#L1678-2 assume !false; 176086#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 176084#L1084-1 assume !false; 176083#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 176072#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 176068#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 176064#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 176061#L925 assume !(0 != eval_~tmp~0#1); 176062#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 185169#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 185168#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 185167#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 185166#L1114-3 assume !(0 == ~T2_E~0); 185165#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 185164#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 185163#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 185162#L1134-3 assume !(0 == ~T6_E~0); 185161#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 185160#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 185159#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 185158#L1154-3 assume !(0 == ~T10_E~0); 185157#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 185156#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 185155#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 185154#L1174-3 assume !(0 == ~E_2~0); 185153#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 185152#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 185151#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 185150#L1194-3 assume !(0 == ~E_6~0); 185149#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 185148#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 185147#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 185146#L1214-3 assume !(0 == ~E_10~0); 185145#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 185144#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 185143#L544-39 assume !(1 == ~m_pc~0); 185142#L544-41 is_master_triggered_~__retres1~0#1 := 0; 185141#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 185140#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 185139#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 185138#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 185137#L563-39 assume !(1 == ~t1_pc~0); 185136#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 185134#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 185133#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 185132#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 185131#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 165561#L582-39 assume !(1 == ~t2_pc~0); 165562#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 165352#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 164946#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 164947#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 164379#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 164155#L601-39 assume 1 == ~t3_pc~0; 164156#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 164204#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 165400#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 165805#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 165806#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 178995#L620-39 assume !(1 == ~t4_pc~0); 178992#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 178990#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 178989#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 178986#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 178985#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 178981#L639-39 assume 1 == ~t5_pc~0; 178976#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 178972#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 178968#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 178964#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 178960#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 178956#L658-39 assume 1 == ~t6_pc~0; 178950#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 178948#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 178946#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 178945#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 178944#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 178943#L677-39 assume !(1 == ~t7_pc~0); 178942#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 178940#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 178939#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 178938#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 178937#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 178936#L696-39 assume 1 == ~t8_pc~0; 178934#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 178933#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 178576#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 178573#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 178571#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 178569#L715-39 assume !(1 == ~t9_pc~0); 178566#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 178564#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 178542#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 178536#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 178530#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 178523#L734-39 assume 1 == ~t10_pc~0; 178516#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 178507#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 178501#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 178494#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 178488#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 178482#L753-39 assume !(1 == ~t11_pc~0); 178475#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 178466#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 178460#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 178455#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 178449#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 178443#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 165083#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 178431#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 165363#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 178420#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 178415#L1257-3 assume !(1 == ~T5_E~0); 178410#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 178405#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 178399#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 178394#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 178388#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 178382#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 178378#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 178374#L1297-3 assume !(1 == ~E_1~0); 178369#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 178365#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 178360#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 178359#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 178358#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 177900#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 178357#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 178356#L1337-3 assume !(1 == ~E_9~0); 178355#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 178354#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 178353#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 178349#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 178340#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 178324#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 176453#L1697 assume !(0 == start_simulation_~tmp~3#1); 176450#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 176361#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 176353#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 176163#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 176146#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 176142#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 176116#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 176100#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 176091#L1678-2 [2023-11-19 07:43:55,098 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:55,098 INFO L85 PathProgramCache]: Analyzing trace with hash 1819278198, now seen corresponding path program 1 times [2023-11-19 07:43:55,098 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:55,098 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [842070848] [2023-11-19 07:43:55,099 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:55,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:55,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:55,341 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:55,342 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:55,342 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [842070848] [2023-11-19 07:43:55,342 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [842070848] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:55,343 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:55,343 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:43:55,343 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [125066893] [2023-11-19 07:43:55,344 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:55,344 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:55,345 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:55,345 INFO L85 PathProgramCache]: Analyzing trace with hash -1226925073, now seen corresponding path program 1 times [2023-11-19 07:43:55,345 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:55,346 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1482630844] [2023-11-19 07:43:55,346 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:55,346 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:55,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:55,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:55,437 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:55,438 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1482630844] [2023-11-19 07:43:55,438 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1482630844] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:55,438 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:55,439 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:55,439 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [705903953] [2023-11-19 07:43:55,439 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:55,440 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:55,440 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:55,440 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:43:55,441 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:43:55,441 INFO L87 Difference]: Start difference. First operand 38277 states and 55364 transitions. cyclomatic complexity: 17103 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:56,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:56,038 INFO L93 Difference]: Finished difference Result 73220 states and 105429 transitions. [2023-11-19 07:43:56,038 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 73220 states and 105429 transitions. [2023-11-19 07:43:56,825 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 72884 [2023-11-19 07:43:57,139 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 73220 states to 73220 states and 105429 transitions. [2023-11-19 07:43:57,140 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 73220 [2023-11-19 07:43:57,192 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 73220 [2023-11-19 07:43:57,193 INFO L73 IsDeterministic]: Start isDeterministic. Operand 73220 states and 105429 transitions. [2023-11-19 07:43:57,263 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:57,263 INFO L218 hiAutomatonCegarLoop]: Abstraction has 73220 states and 105429 transitions. [2023-11-19 07:43:57,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73220 states and 105429 transitions. [2023-11-19 07:43:58,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73220 to 73156. [2023-11-19 07:43:58,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73156 states, 73156 states have (on average 1.4402783093662856) internal successors, (105365), 73155 states have internal predecessors, (105365), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:58,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73156 states to 73156 states and 105365 transitions. [2023-11-19 07:43:58,662 INFO L240 hiAutomatonCegarLoop]: Abstraction has 73156 states and 105365 transitions. [2023-11-19 07:43:58,663 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:43:58,663 INFO L428 stractBuchiCegarLoop]: Abstraction has 73156 states and 105365 transitions. [2023-11-19 07:43:58,664 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-19 07:43:58,664 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73156 states and 105365 transitions. [2023-11-19 07:43:59,323 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 72820 [2023-11-19 07:43:59,323 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:59,323 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:59,327 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:59,327 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:59,328 INFO L748 eck$LassoCheckResult]: Stem: 275887#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 275888#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 276690#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 276691#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 275860#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 275861#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 277242#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 277203#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 277204#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 276220#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 276221#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 276657#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 277154#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 276124#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 276125#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 276014#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 276015#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 277049#L1109 assume !(0 == ~M_E~0); 277084#L1109-2 assume !(0 == ~T1_E~0); 276023#L1114-1 assume !(0 == ~T2_E~0); 276024#L1119-1 assume !(0 == ~T3_E~0); 277158#L1124-1 assume !(0 == ~T4_E~0); 275676#L1129-1 assume !(0 == ~T5_E~0); 275677#L1134-1 assume !(0 == ~T6_E~0); 276308#L1139-1 assume !(0 == ~T7_E~0); 277064#L1144-1 assume !(0 == ~T8_E~0); 276902#L1149-1 assume !(0 == ~T9_E~0); 275786#L1154-1 assume !(0 == ~T10_E~0); 275787#L1159-1 assume !(0 == ~T11_E~0); 276891#L1164-1 assume !(0 == ~E_M~0); 276183#L1169-1 assume !(0 == ~E_1~0); 276076#L1174-1 assume !(0 == ~E_2~0); 275942#L1179-1 assume !(0 == ~E_3~0); 275866#L1184-1 assume !(0 == ~E_4~0); 275867#L1189-1 assume !(0 == ~E_5~0); 275900#L1194-1 assume !(0 == ~E_6~0); 275981#L1199-1 assume !(0 == ~E_7~0); 276912#L1204-1 assume !(0 == ~E_8~0); 276838#L1209-1 assume !(0 == ~E_9~0); 276839#L1214-1 assume !(0 == ~E_10~0); 277259#L1219-1 assume !(0 == ~E_11~0); 277405#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 276200#L544 assume !(1 == ~m_pc~0); 276201#L544-2 is_master_triggered_~__retres1~0#1 := 0; 277138#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 276568#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 275827#L1379 assume !(0 != activate_threads_~tmp~1#1); 275828#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 276645#L563 assume !(1 == ~t1_pc~0); 276434#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 275686#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 275687#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 276781#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 275682#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 275683#L582 assume !(1 == ~t2_pc~0); 276412#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 276786#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 276019#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 276020#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 275712#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 275713#L601 assume !(1 == ~t3_pc~0); 276428#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 276427#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 276934#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 276820#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 276821#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 276764#L620 assume !(1 == ~t4_pc~0); 276765#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 276332#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 275726#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 275727#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 276654#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 276864#L639 assume 1 == ~t5_pc~0; 276732#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 275988#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 275989#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 276674#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 276675#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 276606#L658 assume !(1 == ~t6_pc~0); 276197#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 276198#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 276011#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 276012#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 276827#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 276034#L677 assume 1 == ~t7_pc~0; 276035#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 275933#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 277020#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 277186#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 277187#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 277295#L696 assume !(1 == ~t8_pc~0); 276260#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 276261#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 277240#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 277298#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 277364#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 276716#L715 assume 1 == ~t9_pc~0; 276717#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 276363#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 276074#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 276075#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 276697#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 277017#L734 assume !(1 == ~t10_pc~0); 277018#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 276153#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 276154#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 276938#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 276939#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 276233#L753 assume 1 == ~t11_pc~0; 276234#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 276832#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 277252#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 276523#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 276524#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 276577#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 276578#L1237-2 assume !(1 == ~T1_E~0); 277343#L1242-1 assume !(1 == ~T2_E~0); 276329#L1247-1 assume !(1 == ~T3_E~0); 276330#L1252-1 assume !(1 == ~T4_E~0); 276093#L1257-1 assume !(1 == ~T5_E~0); 276094#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 277037#L1267-1 assume !(1 == ~T7_E~0); 277177#L1272-1 assume !(1 == ~T8_E~0); 276422#L1277-1 assume !(1 == ~T9_E~0); 276423#L1282-1 assume !(1 == ~T10_E~0); 276944#L1287-1 assume !(1 == ~T11_E~0); 345602#L1292-1 assume !(1 == ~E_M~0); 345600#L1297-1 assume !(1 == ~E_1~0); 345597#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 345595#L1307-1 assume !(1 == ~E_3~0); 345593#L1312-1 assume !(1 == ~E_4~0); 345591#L1317-1 assume !(1 == ~E_5~0); 345589#L1322-1 assume !(1 == ~E_6~0); 276708#L1327-1 assume !(1 == ~E_7~0); 345572#L1332-1 assume !(1 == ~E_8~0); 345570#L1337-1 assume !(1 == ~E_9~0); 345568#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 345566#L1347-1 assume !(1 == ~E_11~0); 345563#L1352-1 assume { :end_inline_reset_delta_events } true; 345558#L1678-2 [2023-11-19 07:43:59,329 INFO L750 eck$LassoCheckResult]: Loop: 345558#L1678-2 assume !false; 345395#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 345393#L1084-1 assume !false; 345390#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 345372#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 277380#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 277381#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 345360#L925 assume !(0 != eval_~tmp~0#1); 345361#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 346050#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 346049#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 346048#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 346047#L1114-3 assume !(0 == ~T2_E~0); 346046#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 346045#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 346044#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 346043#L1134-3 assume !(0 == ~T6_E~0); 346042#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 346041#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 346040#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 346039#L1154-3 assume !(0 == ~T10_E~0); 346038#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 346037#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 346036#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 346035#L1174-3 assume !(0 == ~E_2~0); 346034#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 346033#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 346032#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 346031#L1194-3 assume !(0 == ~E_6~0); 346030#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 346029#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 346028#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 346027#L1214-3 assume !(0 == ~E_10~0); 346026#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 346025#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 346024#L544-39 assume !(1 == ~m_pc~0); 346023#L544-41 is_master_triggered_~__retres1~0#1 := 0; 346022#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 346021#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 346020#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 278262#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 278263#L563-39 assume 1 == ~t1_pc~0; 346013#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 346012#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 346011#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 346010#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 346009#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 346008#L582-39 assume !(1 == ~t2_pc~0); 333964#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 346007#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 346006#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 346005#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 346004#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 346003#L601-39 assume !(1 == ~t3_pc~0); 346001#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 345999#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 345998#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 345997#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 345996#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 345995#L620-39 assume !(1 == ~t4_pc~0); 345994#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 345993#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 345992#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 345991#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 345990#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 345989#L639-39 assume !(1 == ~t5_pc~0); 345987#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 345985#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 345984#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 345983#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 345982#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 345981#L658-39 assume !(1 == ~t6_pc~0); 345979#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 345977#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 345976#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 345975#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 345974#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 277780#L677-39 assume !(1 == ~t7_pc~0); 277781#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 345971#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 345970#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 345969#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 345968#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 345967#L696-39 assume 1 == ~t8_pc~0; 345965#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 345964#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 345963#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 345962#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 345961#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 345960#L715-39 assume 1 == ~t9_pc~0; 345959#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 345957#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 345956#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 345955#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 345954#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 345953#L734-39 assume !(1 == ~t10_pc~0); 345952#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 345950#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 345949#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 277718#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 277716#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 277713#L753-39 assume !(1 == ~t11_pc~0); 277710#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 277707#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 277705#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 277702#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 277700#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 277697#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 277694#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 277691#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 277688#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 277685#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 277682#L1257-3 assume !(1 == ~T5_E~0); 277679#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 277676#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 277673#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 277670#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 277667#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 277664#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 277660#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 277661#L1297-3 assume !(1 == ~E_1~0); 345917#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 345915#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 345913#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 345911#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 345909#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 277642#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 345675#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 277633#L1337-3 assume !(1 == ~E_9~0); 277631#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 277632#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 277627#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 277628#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 345619#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 345617#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 345609#L1697 assume !(0 == start_simulation_~tmp~3#1); 277114#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 345576#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 345573#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 345571#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 345569#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 345567#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 345565#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 345564#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 345558#L1678-2 [2023-11-19 07:43:59,330 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:59,330 INFO L85 PathProgramCache]: Analyzing trace with hash -343701065, now seen corresponding path program 1 times [2023-11-19 07:43:59,331 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:59,331 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1997108948] [2023-11-19 07:43:59,331 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:59,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:59,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:59,438 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:59,438 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:59,439 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1997108948] [2023-11-19 07:43:59,439 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1997108948] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:59,439 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:59,439 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:43:59,440 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1142595626] [2023-11-19 07:43:59,440 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:59,441 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:59,441 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:59,442 INFO L85 PathProgramCache]: Analyzing trace with hash -931859983, now seen corresponding path program 1 times [2023-11-19 07:43:59,442 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:59,442 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [942445209] [2023-11-19 07:43:59,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:59,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:59,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:59,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:59,530 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:59,530 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [942445209] [2023-11-19 07:43:59,530 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [942445209] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:59,531 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:59,531 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:59,531 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1558432382] [2023-11-19 07:43:59,532 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:59,532 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:59,533 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:59,533 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:43:59,533 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:43:59,534 INFO L87 Difference]: Start difference. First operand 73156 states and 105365 transitions. cyclomatic complexity: 32241 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:44:00,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:44:00,432 INFO L93 Difference]: Finished difference Result 142623 states and 204398 transitions. [2023-11-19 07:44:00,432 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 142623 states and 204398 transitions. [2023-11-19 07:44:01,712 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 142064 [2023-11-19 07:44:02,246 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 142623 states to 142623 states and 204398 transitions. [2023-11-19 07:44:02,247 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 142623 [2023-11-19 07:44:02,346 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 142623 [2023-11-19 07:44:02,346 INFO L73 IsDeterministic]: Start isDeterministic. Operand 142623 states and 204398 transitions. [2023-11-19 07:44:02,582 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:44:02,591 INFO L218 hiAutomatonCegarLoop]: Abstraction has 142623 states and 204398 transitions. [2023-11-19 07:44:02,718 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142623 states and 204398 transitions. [2023-11-19 07:44:04,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142623 to 142495. [2023-11-19 07:44:04,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 142495 states, 142495 states have (on average 1.4335239832976596) internal successors, (204270), 142494 states have internal predecessors, (204270), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:44:05,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142495 states to 142495 states and 204270 transitions. [2023-11-19 07:44:05,376 INFO L240 hiAutomatonCegarLoop]: Abstraction has 142495 states and 204270 transitions. [2023-11-19 07:44:05,377 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:44:05,378 INFO L428 stractBuchiCegarLoop]: Abstraction has 142495 states and 204270 transitions. [2023-11-19 07:44:05,378 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-19 07:44:05,378 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 142495 states and 204270 transitions. [2023-11-19 07:44:05,742 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 141936 [2023-11-19 07:44:05,742 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:44:05,742 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:44:05,745 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:44:05,746 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:44:05,746 INFO L748 eck$LassoCheckResult]: Stem: 491674#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 491675#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 492484#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 492485#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 491648#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 491649#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 493001#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 492967#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 492968#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 492012#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 492013#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 492450#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 492916#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 491914#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 491915#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 491803#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 491804#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 492822#L1109 assume !(0 == ~M_E~0); 492853#L1109-2 assume !(0 == ~T1_E~0); 491812#L1114-1 assume !(0 == ~T2_E~0); 491813#L1119-1 assume !(0 == ~T3_E~0); 492919#L1124-1 assume !(0 == ~T4_E~0); 491463#L1129-1 assume !(0 == ~T5_E~0); 491464#L1134-1 assume !(0 == ~T6_E~0); 492099#L1139-1 assume !(0 == ~T7_E~0); 492836#L1144-1 assume !(0 == ~T8_E~0); 492686#L1149-1 assume !(0 == ~T9_E~0); 491572#L1154-1 assume !(0 == ~T10_E~0); 491573#L1159-1 assume !(0 == ~T11_E~0); 492675#L1164-1 assume !(0 == ~E_M~0); 491973#L1169-1 assume !(0 == ~E_1~0); 491866#L1174-1 assume !(0 == ~E_2~0); 491728#L1179-1 assume !(0 == ~E_3~0); 491654#L1184-1 assume !(0 == ~E_4~0); 491655#L1189-1 assume !(0 == ~E_5~0); 491687#L1194-1 assume !(0 == ~E_6~0); 491770#L1199-1 assume !(0 == ~E_7~0); 492695#L1204-1 assume !(0 == ~E_8~0); 492623#L1209-1 assume !(0 == ~E_9~0); 492624#L1214-1 assume !(0 == ~E_10~0); 493019#L1219-1 assume !(0 == ~E_11~0); 493151#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 491992#L544 assume !(1 == ~m_pc~0); 491993#L544-2 is_master_triggered_~__retres1~0#1 := 0; 492902#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 492362#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 491615#L1379 assume !(0 != activate_threads_~tmp~1#1); 491616#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 492435#L563 assume !(1 == ~t1_pc~0); 492228#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 491473#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 491474#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 492566#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 491469#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 491470#L582 assume !(1 == ~t2_pc~0); 492204#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 492573#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 491808#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 491809#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 491500#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 491501#L601 assume !(1 == ~t3_pc~0); 492222#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 492221#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 492718#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 492608#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 492609#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 492551#L620 assume !(1 == ~t4_pc~0); 492552#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 492123#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 491514#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 491515#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 492445#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 492645#L639 assume !(1 == ~t5_pc~0); 492646#L639-2 is_transmit5_triggered_~__retres1~5#1 := 0; 491775#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 491776#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 492468#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 492469#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 492395#L658 assume !(1 == ~t6_pc~0); 491988#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 491989#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 491800#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 491801#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 492612#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 491823#L677 assume 1 == ~t7_pc~0; 491824#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 491721#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 492795#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 492954#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 492955#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 493045#L696 assume !(1 == ~t8_pc~0); 492052#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 492053#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 492998#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 493048#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 493116#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 492509#L715 assume 1 == ~t9_pc~0; 492510#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 492155#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 491864#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 491865#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 492491#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 492790#L734 assume !(1 == ~t10_pc~0); 492791#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 491943#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 491944#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 492722#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 492723#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 492026#L753 assume 1 == ~t11_pc~0; 492027#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 492617#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 493012#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 492317#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 492318#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 492369#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 492370#L1237-2 assume !(1 == ~T1_E~0); 493094#L1242-1 assume !(1 == ~T2_E~0); 492120#L1247-1 assume !(1 == ~T3_E~0); 492121#L1252-1 assume !(1 == ~T4_E~0); 491883#L1257-1 assume !(1 == ~T5_E~0); 491884#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 492811#L1267-1 assume !(1 == ~T7_E~0); 492943#L1272-1 assume !(1 == ~T8_E~0); 492216#L1277-1 assume !(1 == ~T9_E~0); 492217#L1282-1 assume !(1 == ~T10_E~0); 492662#L1287-1 assume !(1 == ~T11_E~0); 492663#L1292-1 assume !(1 == ~E_M~0); 492611#L1297-1 assume !(1 == ~E_1~0); 492017#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 492018#L1307-1 assume !(1 == ~E_3~0); 492924#L1312-1 assume !(1 == ~E_4~0); 492265#L1317-1 assume !(1 == ~E_5~0); 492266#L1322-1 assume !(1 == ~E_6~0); 491960#L1327-1 assume !(1 == ~E_7~0); 491961#L1332-1 assume !(1 == ~E_8~0); 492565#L1337-1 assume !(1 == ~E_9~0); 492495#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 492496#L1347-1 assume !(1 == ~E_11~0); 492922#L1352-1 assume { :end_inline_reset_delta_events } true; 492923#L1678-2 [2023-11-19 07:44:05,747 INFO L750 eck$LassoCheckResult]: Loop: 492923#L1678-2 assume !false; 559314#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 557628#L1084-1 assume !false; 557625#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 557256#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 557214#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 557204#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 557193#L925 assume !(0 != eval_~tmp~0#1); 557194#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 562258#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 562255#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 562252#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 562250#L1114-3 assume !(0 == ~T2_E~0); 562248#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 562246#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 562244#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 562242#L1134-3 assume !(0 == ~T6_E~0); 562239#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 562237#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 562235#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 562233#L1154-3 assume !(0 == ~T10_E~0); 562231#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 562229#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 562226#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 562224#L1174-3 assume !(0 == ~E_2~0); 562222#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 562220#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 562218#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 562216#L1194-3 assume !(0 == ~E_6~0); 562215#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 562185#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 562175#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 562165#L1214-3 assume !(0 == ~E_10~0); 562157#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 562149#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 562146#L544-39 assume !(1 == ~m_pc~0); 562143#L544-41 is_master_triggered_~__retres1~0#1 := 0; 562137#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 562136#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 562135#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 562134#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 562133#L563-39 assume 1 == ~t1_pc~0; 562129#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 562127#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 562124#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 562122#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 562120#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 562118#L582-39 assume !(1 == ~t2_pc~0); 554957#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 562115#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 562112#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 562110#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 562108#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 562106#L601-39 assume 1 == ~t3_pc~0; 562100#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 562083#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 562079#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 562076#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 562073#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 562067#L620-39 assume !(1 == ~t4_pc~0); 562063#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 562059#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 562047#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 562030#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 493707#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 493704#L639-39 assume !(1 == ~t5_pc~0); 493701#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 493702#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 554150#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 554148#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 554147#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 554146#L658-39 assume 1 == ~t6_pc~0; 554144#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 554143#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 554142#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 554141#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 554140#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 554139#L677-39 assume 1 == ~t7_pc~0; 554137#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 554136#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 554135#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 554133#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 554131#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 554129#L696-39 assume 1 == ~t8_pc~0; 554126#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 554124#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 554122#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 554120#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 554118#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 554116#L715-39 assume !(1 == ~t9_pc~0); 554112#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 554110#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 554108#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 554106#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 554104#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 554103#L734-39 assume 1 == ~t10_pc~0; 554101#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 554100#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 554099#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 554098#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 554097#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 554095#L753-39 assume !(1 == ~t11_pc~0); 554092#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 554090#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 554088#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 554086#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 554084#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 554082#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 493609#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 554078#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 551014#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 554075#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 554073#L1257-3 assume !(1 == ~T5_E~0); 493595#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 493593#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 493591#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 493589#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 493587#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 493585#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 493583#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 493581#L1297-3 assume !(1 == ~E_1~0); 493580#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 493579#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 493578#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 493577#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 493564#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 493562#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 493560#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 493559#L1337-3 assume !(1 == ~E_9~0); 493558#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 493557#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 493556#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 493453#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 493436#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 493428#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 493426#L1697 assume !(0 == start_simulation_~tmp~3#1); 493427#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 559363#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 559359#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 559357#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 559355#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 559343#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 559334#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 559325#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 492923#L1678-2 [2023-11-19 07:44:05,748 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:44:05,748 INFO L85 PathProgramCache]: Analyzing trace with hash 1793793208, now seen corresponding path program 1 times [2023-11-19 07:44:05,748 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:44:05,748 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [545453159] [2023-11-19 07:44:05,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:44:05,749 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:44:05,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:44:06,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:44:06,425 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:44:06,426 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [545453159] [2023-11-19 07:44:06,426 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [545453159] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:44:06,426 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:44:06,426 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:44:06,426 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [813402766] [2023-11-19 07:44:06,427 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:44:06,427 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:44:06,428 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:44:06,428 INFO L85 PathProgramCache]: Analyzing trace with hash 1973107694, now seen corresponding path program 1 times [2023-11-19 07:44:06,428 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:44:06,428 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [140215972] [2023-11-19 07:44:06,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:44:06,429 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:44:06,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:44:06,556 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:44:06,557 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:44:06,557 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [140215972] [2023-11-19 07:44:06,557 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [140215972] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:44:06,560 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:44:06,560 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:44:06,560 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [384886250] [2023-11-19 07:44:06,561 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:44:06,562 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:44:06,563 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:44:06,563 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 07:44:06,563 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 07:44:06,564 INFO L87 Difference]: Start difference. First operand 142495 states and 204270 transitions. cyclomatic complexity: 61839 Second operand has 5 states, 5 states have (on average 27.8) internal successors, (139), 5 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:44:08,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:44:08,211 INFO L93 Difference]: Finished difference Result 330879 states and 471113 transitions. [2023-11-19 07:44:08,211 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 330879 states and 471113 transitions. [2023-11-19 07:44:10,197 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 329808 [2023-11-19 07:44:11,630 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 330879 states to 330879 states and 471113 transitions. [2023-11-19 07:44:11,630 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 330879 [2023-11-19 07:44:11,746 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 330879 [2023-11-19 07:44:11,746 INFO L73 IsDeterministic]: Start isDeterministic. Operand 330879 states and 471113 transitions. [2023-11-19 07:44:11,877 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:44:11,878 INFO L218 hiAutomatonCegarLoop]: Abstraction has 330879 states and 471113 transitions. [2023-11-19 07:44:12,048 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 330879 states and 471113 transitions. [2023-11-19 07:44:14,501 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 330879 to 146674. [2023-11-19 07:44:14,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 146674 states, 146674 states have (on average 1.4211721232120211) internal successors, (208449), 146673 states have internal predecessors, (208449), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:44:15,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146674 states to 146674 states and 208449 transitions. [2023-11-19 07:44:15,096 INFO L240 hiAutomatonCegarLoop]: Abstraction has 146674 states and 208449 transitions. [2023-11-19 07:44:15,096 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-19 07:44:15,097 INFO L428 stractBuchiCegarLoop]: Abstraction has 146674 states and 208449 transitions. [2023-11-19 07:44:15,097 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-19 07:44:15,097 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 146674 states and 208449 transitions. [2023-11-19 07:44:15,584 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 146112 [2023-11-19 07:44:15,590 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:44:15,599 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:44:15,602 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:44:15,606 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:44:15,606 INFO L748 eck$LassoCheckResult]: Stem: 965061#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 965062#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 965901#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 965902#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 965034#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 965035#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 966457#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 966414#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 966415#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 965402#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 965403#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 965858#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 966360#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 965305#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 965306#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 965190#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 965191#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 966263#L1109 assume !(0 == ~M_E~0); 966292#L1109-2 assume !(0 == ~T1_E~0); 965199#L1114-1 assume !(0 == ~T2_E~0); 965200#L1119-1 assume !(0 == ~T3_E~0); 966363#L1124-1 assume !(0 == ~T4_E~0); 964850#L1129-1 assume !(0 == ~T5_E~0); 964851#L1134-1 assume !(0 == ~T6_E~0); 965497#L1139-1 assume !(0 == ~T7_E~0); 966275#L1144-1 assume !(0 == ~T8_E~0); 966109#L1149-1 assume !(0 == ~T9_E~0); 964959#L1154-1 assume !(0 == ~T10_E~0); 964960#L1159-1 assume !(0 == ~T11_E~0); 966097#L1164-1 assume !(0 == ~E_M~0); 965363#L1169-1 assume !(0 == ~E_1~0); 965253#L1174-1 assume !(0 == ~E_2~0); 965115#L1179-1 assume !(0 == ~E_3~0); 965040#L1184-1 assume !(0 == ~E_4~0); 965041#L1189-1 assume !(0 == ~E_5~0); 965075#L1194-1 assume !(0 == ~E_6~0); 965157#L1199-1 assume !(0 == ~E_7~0); 966118#L1204-1 assume !(0 == ~E_8~0); 966047#L1209-1 assume !(0 == ~E_9~0); 966048#L1214-1 assume !(0 == ~E_10~0); 966480#L1219-1 assume !(0 == ~E_11~0); 966676#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 965380#L544 assume !(1 == ~m_pc~0); 965381#L544-2 is_master_triggered_~__retres1~0#1 := 0; 966343#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 965759#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 965002#L1379 assume !(0 != activate_threads_~tmp~1#1); 965003#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 965838#L563 assume !(1 == ~t1_pc~0); 965626#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 964860#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 964861#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 965990#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 964856#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 964857#L582 assume !(1 == ~t2_pc~0); 965604#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 965997#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 965195#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 965196#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 964886#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 964887#L601 assume !(1 == ~t3_pc~0); 965621#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 965620#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 966142#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 966031#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 966032#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 965975#L620 assume !(1 == ~t4_pc~0); 965976#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 965527#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 964900#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 964901#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 965852#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 966067#L639 assume !(1 == ~t5_pc~0); 966068#L639-2 is_transmit5_triggered_~__retres1~5#1 := 0; 965162#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 965163#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 965879#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 965880#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 965794#L658 assume !(1 == ~t6_pc~0); 965377#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 965378#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 966022#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 966680#L1427 assume !(0 != activate_threads_~tmp___5~0#1); 966036#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 965210#L677 assume 1 == ~t7_pc~0; 965211#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 965108#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 966228#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 966402#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 966403#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 966507#L696 assume !(1 == ~t8_pc~0); 965444#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 965445#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 966455#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 966510#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 966607#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 965927#L715 assume 1 == ~t9_pc~0; 965928#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 965557#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 965251#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 965252#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 965908#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 966223#L734 assume !(1 == ~t10_pc~0); 966224#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 965333#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 965334#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 966147#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 966148#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 965417#L753 assume 1 == ~t11_pc~0; 965418#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 966041#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 966470#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 965712#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 965713#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 965766#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 965767#L1237-2 assume !(1 == ~T1_E~0); 966643#L1242-1 assume !(1 == ~T2_E~0); 965522#L1247-1 assume !(1 == ~T3_E~0); 965523#L1252-1 assume !(1 == ~T4_E~0); 965270#L1257-1 assume !(1 == ~T5_E~0); 965271#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 966247#L1267-1 assume !(1 == ~T7_E~0); 966392#L1272-1 assume !(1 == ~T8_E~0); 965615#L1277-1 assume !(1 == ~T9_E~0); 965616#L1282-1 assume !(1 == ~T10_E~0); 966083#L1287-1 assume !(1 == ~T11_E~0); 966084#L1292-1 assume !(1 == ~E_M~0); 966035#L1297-1 assume !(1 == ~E_1~0); 965407#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 965408#L1307-1 assume !(1 == ~E_3~0); 966368#L1312-1 assume !(1 == ~E_4~0); 965663#L1317-1 assume !(1 == ~E_5~0); 965664#L1322-1 assume !(1 == ~E_6~0); 965350#L1327-1 assume !(1 == ~E_7~0); 965351#L1332-1 assume !(1 == ~E_8~0); 965989#L1337-1 assume !(1 == ~E_9~0); 965912#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 965913#L1347-1 assume !(1 == ~E_11~0); 966366#L1352-1 assume { :end_inline_reset_delta_events } true; 966367#L1678-2 [2023-11-19 07:44:15,607 INFO L750 eck$LassoCheckResult]: Loop: 966367#L1678-2 assume !false; 996659#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 996657#L1084-1 assume !false; 996656#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 996645#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 996640#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 996635#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 996631#L925 assume !(0 != eval_~tmp~0#1); 996632#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1031171#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1031170#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1031169#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1031168#L1114-3 assume !(0 == ~T2_E~0); 1031167#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1031166#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1031165#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1031164#L1134-3 assume !(0 == ~T6_E~0); 1031163#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1031162#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1031161#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1031160#L1154-3 assume !(0 == ~T10_E~0); 1031159#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1031158#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1031157#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1031156#L1174-3 assume !(0 == ~E_2~0); 1031155#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1031154#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1031153#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1031152#L1194-3 assume !(0 == ~E_6~0); 1031151#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1031150#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1031149#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1031148#L1214-3 assume !(0 == ~E_10~0); 1031147#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1031145#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1031142#L544-39 assume !(1 == ~m_pc~0); 1031140#L544-41 is_master_triggered_~__retres1~0#1 := 0; 1031138#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1031136#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1031134#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1031132#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1031129#L563-39 assume !(1 == ~t1_pc~0); 1031127#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 1031124#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1031122#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1031120#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1031118#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1031117#L582-39 assume !(1 == ~t2_pc~0); 988545#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 1031114#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1031112#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1031110#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1031108#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1031105#L601-39 assume !(1 == ~t3_pc~0); 1031102#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 1031098#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1031095#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1031092#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1031089#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1031086#L620-39 assume !(1 == ~t4_pc~0); 1031082#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 1031079#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1031076#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1031073#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1031070#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1031066#L639-39 assume !(1 == ~t5_pc~0); 1031063#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1031056#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1031040#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1031037#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 1031035#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1031034#L658-39 assume !(1 == ~t6_pc~0); 1031033#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 1031031#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1031029#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1031027#L1427-39 assume !(0 != activate_threads_~tmp___5~0#1); 1031024#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1031021#L677-39 assume !(1 == ~t7_pc~0); 1031019#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 1031016#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1031014#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1031012#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1031010#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1031007#L696-39 assume !(1 == ~t8_pc~0); 1031005#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 1031002#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1020633#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1020632#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1020631#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1020630#L715-39 assume 1 == ~t9_pc~0; 1020629#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1020627#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1020626#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1020625#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1020624#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1020623#L734-39 assume !(1 == ~t10_pc~0); 1020622#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 1020620#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1020619#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1020236#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1020234#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1020232#L753-39 assume 1 == ~t11_pc~0; 1020229#L754-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1020226#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1020224#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1020222#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 967256#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 967253#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 967251#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 967248#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 967246#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 967244#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 967242#L1257-3 assume !(1 == ~T5_E~0); 967240#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 967238#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 967236#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 967234#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 967232#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 967230#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 967228#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 967226#L1297-3 assume !(1 == ~E_1~0); 967224#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 967222#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 967220#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 967218#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 967216#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 967214#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 967212#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 967210#L1337-3 assume !(1 == ~E_9~0); 967208#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 967206#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 967204#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 967070#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 967049#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 967046#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 967042#L1697 assume !(0 == start_simulation_~tmp~3#1); 967043#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 996730#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 996726#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 996712#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 996699#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 996687#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 996678#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 996670#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 966367#L1678-2 [2023-11-19 07:44:15,608 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:44:15,608 INFO L85 PathProgramCache]: Analyzing trace with hash -1240256838, now seen corresponding path program 1 times [2023-11-19 07:44:15,608 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:44:15,609 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364210850] [2023-11-19 07:44:15,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:44:15,609 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:44:15,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:44:15,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:44:15,724 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:44:15,724 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [364210850] [2023-11-19 07:44:15,724 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [364210850] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:44:15,725 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:44:15,725 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:44:15,725 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [731454800] [2023-11-19 07:44:15,725 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:44:15,726 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:44:15,726 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:44:15,726 INFO L85 PathProgramCache]: Analyzing trace with hash 20896052, now seen corresponding path program 1 times [2023-11-19 07:44:15,727 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:44:15,727 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [185343567] [2023-11-19 07:44:15,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:44:15,727 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:44:15,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:44:15,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:44:15,813 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:44:15,813 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [185343567] [2023-11-19 07:44:15,813 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [185343567] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:44:15,813 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:44:15,813 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:44:15,814 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1294101076] [2023-11-19 07:44:15,814 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:44:15,814 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:44:15,815 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:44:15,815 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:44:15,815 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:44:15,815 INFO L87 Difference]: Start difference. First operand 146674 states and 208449 transitions. cyclomatic complexity: 61839 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:44:18,216 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:44:18,217 INFO L93 Difference]: Finished difference Result 354125 states and 500058 transitions. [2023-11-19 07:44:18,217 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 354125 states and 500058 transitions. [2023-11-19 07:44:20,317 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 347260 [2023-11-19 07:44:21,079 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 354125 states to 354125 states and 500058 transitions. [2023-11-19 07:44:21,080 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 354125 [2023-11-19 07:44:21,220 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 354125 [2023-11-19 07:44:21,220 INFO L73 IsDeterministic]: Start isDeterministic. Operand 354125 states and 500058 transitions.