./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.01.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 9bd2c7ff Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_138d3320-eb15-480c-abed-f63e41f5ebe4/bin/uautomizer-verify-uCwYo4JHxu/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_138d3320-eb15-480c-abed-f63e41f5ebe4/bin/uautomizer-verify-uCwYo4JHxu/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_138d3320-eb15-480c-abed-f63e41f5ebe4/bin/uautomizer-verify-uCwYo4JHxu/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_138d3320-eb15-480c-abed-f63e41f5ebe4/bin/uautomizer-verify-uCwYo4JHxu/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.01.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_138d3320-eb15-480c-abed-f63e41f5ebe4/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_138d3320-eb15-480c-abed-f63e41f5ebe4/bin/uautomizer-verify-uCwYo4JHxu --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe --- Real Ultimate output --- This is Ultimate 0.2.3-dev-9bd2c7f [2023-11-19 07:47:00,870 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-19 07:47:00,988 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_138d3320-eb15-480c-abed-f63e41f5ebe4/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-19 07:47:00,993 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-19 07:47:00,994 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-19 07:47:01,032 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-19 07:47:01,033 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-19 07:47:01,034 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-19 07:47:01,035 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-19 07:47:01,041 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-19 07:47:01,041 INFO L153 SettingsManager]: * Use SBE=true [2023-11-19 07:47:01,042 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-19 07:47:01,042 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-19 07:47:01,044 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-19 07:47:01,044 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-19 07:47:01,045 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-19 07:47:01,045 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-19 07:47:01,046 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-19 07:47:01,046 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-19 07:47:01,047 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-19 07:47:01,047 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-19 07:47:01,048 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-19 07:47:01,048 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-19 07:47:01,049 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-19 07:47:01,049 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-19 07:47:01,049 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-19 07:47:01,050 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-19 07:47:01,050 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-19 07:47:01,051 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-19 07:47:01,051 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-19 07:47:01,052 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-19 07:47:01,053 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-19 07:47:01,053 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-19 07:47:01,053 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-19 07:47:01,053 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-19 07:47:01,054 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-19 07:47:01,054 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_138d3320-eb15-480c-abed-f63e41f5ebe4/bin/uautomizer-verify-uCwYo4JHxu/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_138d3320-eb15-480c-abed-f63e41f5ebe4/bin/uautomizer-verify-uCwYo4JHxu Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe [2023-11-19 07:47:01,351 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-19 07:47:01,386 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-19 07:47:01,389 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-19 07:47:01,391 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-19 07:47:01,391 INFO L274 PluginConnector]: CDTParser initialized [2023-11-19 07:47:01,393 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_138d3320-eb15-480c-abed-f63e41f5ebe4/bin/uautomizer-verify-uCwYo4JHxu/../../sv-benchmarks/c/systemc/transmitter.01.cil.c [2023-11-19 07:47:04,459 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-19 07:47:04,650 INFO L384 CDTParser]: Found 1 translation units. [2023-11-19 07:47:04,651 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_138d3320-eb15-480c-abed-f63e41f5ebe4/sv-benchmarks/c/systemc/transmitter.01.cil.c [2023-11-19 07:47:04,661 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_138d3320-eb15-480c-abed-f63e41f5ebe4/bin/uautomizer-verify-uCwYo4JHxu/data/4e866827f/dbaf36840dc24661997568e8a0862421/FLAGea8e1c046 [2023-11-19 07:47:04,680 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_138d3320-eb15-480c-abed-f63e41f5ebe4/bin/uautomizer-verify-uCwYo4JHxu/data/4e866827f/dbaf36840dc24661997568e8a0862421 [2023-11-19 07:47:04,683 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-19 07:47:04,690 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-19 07:47:04,695 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-19 07:47:04,696 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-19 07:47:04,702 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-19 07:47:04,703 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:47:04" (1/1) ... [2023-11-19 07:47:04,704 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@e1ad7ed and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:47:04, skipping insertion in model container [2023-11-19 07:47:04,704 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:47:04" (1/1) ... [2023-11-19 07:47:04,764 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-19 07:47:04,958 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:47:04,974 INFO L202 MainTranslator]: Completed pre-run [2023-11-19 07:47:05,005 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:47:05,023 INFO L206 MainTranslator]: Completed translation [2023-11-19 07:47:05,024 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:47:05 WrapperNode [2023-11-19 07:47:05,024 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-19 07:47:05,025 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-19 07:47:05,025 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-19 07:47:05,026 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-19 07:47:05,033 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:47:05" (1/1) ... [2023-11-19 07:47:05,042 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:47:05" (1/1) ... [2023-11-19 07:47:05,073 INFO L138 Inliner]: procedures = 30, calls = 34, calls flagged for inlining = 29, calls inlined = 35, statements flattened = 361 [2023-11-19 07:47:05,074 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-19 07:47:05,074 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-19 07:47:05,074 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-19 07:47:05,075 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-19 07:47:05,084 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:47:05" (1/1) ... [2023-11-19 07:47:05,084 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:47:05" (1/1) ... [2023-11-19 07:47:05,087 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:47:05" (1/1) ... [2023-11-19 07:47:05,088 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:47:05" (1/1) ... [2023-11-19 07:47:05,095 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:47:05" (1/1) ... [2023-11-19 07:47:05,102 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:47:05" (1/1) ... [2023-11-19 07:47:05,105 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:47:05" (1/1) ... [2023-11-19 07:47:05,117 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:47:05" (1/1) ... [2023-11-19 07:47:05,121 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-19 07:47:05,122 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-19 07:47:05,123 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-19 07:47:05,123 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-19 07:47:05,124 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:47:05" (1/1) ... [2023-11-19 07:47:05,130 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 07:47:05,145 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_138d3320-eb15-480c-abed-f63e41f5ebe4/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:47:05,161 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_138d3320-eb15-480c-abed-f63e41f5ebe4/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 07:47:05,172 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_138d3320-eb15-480c-abed-f63e41f5ebe4/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-19 07:47:05,193 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-19 07:47:05,194 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-19 07:47:05,194 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-19 07:47:05,194 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-19 07:47:05,263 INFO L236 CfgBuilder]: Building ICFG [2023-11-19 07:47:05,266 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-19 07:47:05,657 INFO L277 CfgBuilder]: Performing block encoding [2023-11-19 07:47:05,669 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-19 07:47:05,669 INFO L302 CfgBuilder]: Removed 5 assume(true) statements. [2023-11-19 07:47:05,674 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:47:05 BoogieIcfgContainer [2023-11-19 07:47:05,674 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-19 07:47:05,675 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-19 07:47:05,676 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-19 07:47:05,680 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-19 07:47:05,681 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:47:05,681 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 07:47:04" (1/3) ... [2023-11-19 07:47:05,689 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@44aa59b8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:47:05, skipping insertion in model container [2023-11-19 07:47:05,689 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:47:05,689 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:47:05" (2/3) ... [2023-11-19 07:47:05,689 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@44aa59b8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:47:05, skipping insertion in model container [2023-11-19 07:47:05,690 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:47:05,690 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:47:05" (3/3) ... [2023-11-19 07:47:05,691 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.01.cil.c [2023-11-19 07:47:05,781 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-19 07:47:05,781 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-19 07:47:05,782 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-19 07:47:05,782 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-19 07:47:05,782 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-19 07:47:05,782 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-19 07:47:05,782 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-19 07:47:05,783 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-19 07:47:05,788 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 136 states, 135 states have (on average 1.511111111111111) internal successors, (204), 135 states have internal predecessors, (204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:47:05,839 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 103 [2023-11-19 07:47:05,839 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:47:05,839 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:47:05,849 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:47:05,850 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:47:05,850 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-19 07:47:05,854 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 136 states, 135 states have (on average 1.511111111111111) internal successors, (204), 135 states have internal predecessors, (204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:47:05,870 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 103 [2023-11-19 07:47:05,870 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:47:05,871 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:47:05,873 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:47:05,873 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:47:05,892 INFO L748 eck$LassoCheckResult]: Stem: 31#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 48#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 134#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13#L161true assume !(1 == ~m_i~0);~m_st~0 := 2; 5#L161-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 80#L166-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 89#L250true assume !(0 == ~M_E~0); 108#L250-2true assume !(0 == ~T1_E~0); 39#L255-1true assume !(0 == ~E_1~0); 81#L260-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55#L115true assume !(1 == ~m_pc~0); 59#L115-2true is_master_triggered_~__retres1~0#1 := 0; 69#L126true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8#is_master_triggered_returnLabel#1true activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 66#L300true assume !(0 != activate_threads_~tmp~1#1); 107#L300-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 121#L134true assume 1 == ~t1_pc~0; 109#L135true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 57#L145true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10#L308true assume !(0 != activate_threads_~tmp___0~0#1); 62#L308-2true havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60#L273true assume !(1 == ~M_E~0); 113#L273-2true assume !(1 == ~T1_E~0); 102#L278-1true assume !(1 == ~E_1~0); 72#L283-1true assume { :end_inline_reset_delta_events } true; 58#L404-2true [2023-11-19 07:47:05,895 INFO L750 eck$LassoCheckResult]: Loop: 58#L404-2true assume !false; 82#L405true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 96#L225-1true assume false; 85#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 117#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 120#L250-3true assume 0 == ~M_E~0;~M_E~0 := 1; 98#L250-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 104#L255-3true assume 0 == ~E_1~0;~E_1~0 := 1; 6#L260-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49#L115-6true assume 1 == ~m_pc~0; 116#L116-2true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 135#L126-2true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54#is_master_triggered_returnLabel#3true activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 74#L300-6true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 118#L300-8true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 133#L134-6true assume !(1 == ~t1_pc~0); 32#L134-8true is_transmit1_triggered_~__retres1~1#1 := 0; 53#L145-2true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 125#is_transmit1_triggered_returnLabel#3true activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 50#L308-6true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7#L308-8true havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 130#L273-3true assume 1 == ~M_E~0;~M_E~0 := 2; 45#L273-5true assume !(1 == ~T1_E~0); 33#L278-3true assume 1 == ~E_1~0;~E_1~0 := 2; 95#L283-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 76#L179-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 114#L191-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 100#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 19#L423true assume !(0 == start_simulation_~tmp~3#1); 18#L423-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 22#L179-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 73#L191-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 37#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 16#L378true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17#L385true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 136#stop_simulation_returnLabel#1true start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 44#L436true assume !(0 != start_simulation_~tmp___0~1#1); 58#L404-2true [2023-11-19 07:47:05,900 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:47:05,901 INFO L85 PathProgramCache]: Analyzing trace with hash 920294251, now seen corresponding path program 1 times [2023-11-19 07:47:05,910 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:47:05,911 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [458936667] [2023-11-19 07:47:05,911 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:47:05,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:47:06,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:47:06,092 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:47:06,093 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:47:06,093 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [458936667] [2023-11-19 07:47:06,094 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [458936667] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:47:06,094 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:47:06,095 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:47:06,096 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2059611213] [2023-11-19 07:47:06,097 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:47:06,102 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:47:06,103 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:47:06,103 INFO L85 PathProgramCache]: Analyzing trace with hash 1288992519, now seen corresponding path program 1 times [2023-11-19 07:47:06,104 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:47:06,104 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [173625685] [2023-11-19 07:47:06,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:47:06,105 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:47:06,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:47:06,139 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:47:06,140 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:47:06,140 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [173625685] [2023-11-19 07:47:06,140 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [173625685] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:47:06,140 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:47:06,141 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:47:06,141 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [198655331] [2023-11-19 07:47:06,141 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:47:06,143 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:47:06,144 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:47:06,178 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:47:06,179 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:47:06,185 INFO L87 Difference]: Start difference. First operand has 136 states, 135 states have (on average 1.511111111111111) internal successors, (204), 135 states have internal predecessors, (204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:47:06,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:47:06,226 INFO L93 Difference]: Finished difference Result 134 states and 190 transitions. [2023-11-19 07:47:06,228 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 134 states and 190 transitions. [2023-11-19 07:47:06,232 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 99 [2023-11-19 07:47:06,237 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 134 states to 128 states and 184 transitions. [2023-11-19 07:47:06,238 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128 [2023-11-19 07:47:06,239 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128 [2023-11-19 07:47:06,240 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128 states and 184 transitions. [2023-11-19 07:47:06,241 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:47:06,241 INFO L218 hiAutomatonCegarLoop]: Abstraction has 128 states and 184 transitions. [2023-11-19 07:47:06,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states and 184 transitions. [2023-11-19 07:47:06,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 128. [2023-11-19 07:47:06,273 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 128 states, 128 states have (on average 1.4375) internal successors, (184), 127 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:47:06,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 184 transitions. [2023-11-19 07:47:06,276 INFO L240 hiAutomatonCegarLoop]: Abstraction has 128 states and 184 transitions. [2023-11-19 07:47:06,278 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:47:06,282 INFO L428 stractBuchiCegarLoop]: Abstraction has 128 states and 184 transitions. [2023-11-19 07:47:06,282 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-19 07:47:06,282 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 128 states and 184 transitions. [2023-11-19 07:47:06,285 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 99 [2023-11-19 07:47:06,285 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:47:06,285 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:47:06,287 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:47:06,287 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:47:06,288 INFO L748 eck$LassoCheckResult]: Stem: 329#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 330#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 352#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 348#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 298#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 283#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 284#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 381#L250 assume !(0 == ~M_E~0); 390#L250-2 assume !(0 == ~T1_E~0); 342#L255-1 assume !(0 == ~E_1~0); 343#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 359#L115 assume !(1 == ~m_pc~0); 325#L115-2 is_master_triggered_~__retres1~0#1 := 0; 326#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 289#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 290#L300 assume !(0 != activate_threads_~tmp~1#1); 368#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 400#L134 assume 1 == ~t1_pc~0; 401#L135 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 361#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 341#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 292#L308 assume !(0 != activate_threads_~tmp___0~0#1); 293#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 363#L273 assume !(1 == ~M_E~0); 364#L273-2 assume !(1 == ~T1_E~0); 398#L278-1 assume !(1 == ~E_1~0); 372#L283-1 assume { :end_inline_reset_delta_events } true; 347#L404-2 [2023-11-19 07:47:06,288 INFO L750 eck$LassoCheckResult]: Loop: 347#L404-2 assume !false; 362#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 380#L225-1 assume !false; 386#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 387#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 328#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 299#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 300#L206 assume !(0 != eval_~tmp~0#1); 338#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 383#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 405#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 395#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 396#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 285#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 286#L115-6 assume !(1 == ~m_pc~0); 353#L115-8 is_master_triggered_~__retres1~0#1 := 0; 404#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 357#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 358#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 373#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 406#L134-6 assume !(1 == ~t1_pc~0); 331#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 332#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 356#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 355#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 287#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 288#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 349#L273-5 assume !(1 == ~T1_E~0); 333#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 334#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 375#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 376#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 397#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 309#L423 assume !(0 == start_simulation_~tmp~3#1); 307#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 308#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 313#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 340#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 301#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 302#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 306#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 346#L436 assume !(0 != start_simulation_~tmp___0~1#1); 347#L404-2 [2023-11-19 07:47:06,289 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:47:06,289 INFO L85 PathProgramCache]: Analyzing trace with hash -1569234711, now seen corresponding path program 1 times [2023-11-19 07:47:06,289 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:47:06,289 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1016693997] [2023-11-19 07:47:06,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:47:06,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:47:06,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:47:06,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:47:06,459 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:47:06,460 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1016693997] [2023-11-19 07:47:06,460 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1016693997] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:47:06,460 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:47:06,460 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:47:06,461 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [763680084] [2023-11-19 07:47:06,461 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:47:06,461 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:47:06,462 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:47:06,462 INFO L85 PathProgramCache]: Analyzing trace with hash 487194975, now seen corresponding path program 1 times [2023-11-19 07:47:06,462 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:47:06,463 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [775181323] [2023-11-19 07:47:06,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:47:06,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:47:06,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:47:06,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:47:06,542 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:47:06,542 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [775181323] [2023-11-19 07:47:06,542 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [775181323] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:47:06,542 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:47:06,543 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:47:06,543 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2103782931] [2023-11-19 07:47:06,543 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:47:06,543 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:47:06,544 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:47:06,544 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:47:06,545 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:47:06,545 INFO L87 Difference]: Start difference. First operand 128 states and 184 transitions. cyclomatic complexity: 57 Second operand has 4 states, 4 states have (on average 6.75) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:47:06,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:47:06,686 INFO L93 Difference]: Finished difference Result 310 states and 429 transitions. [2023-11-19 07:47:06,687 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 310 states and 429 transitions. [2023-11-19 07:47:06,692 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 260 [2023-11-19 07:47:06,698 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 310 states to 310 states and 429 transitions. [2023-11-19 07:47:06,698 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 310 [2023-11-19 07:47:06,699 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 310 [2023-11-19 07:47:06,699 INFO L73 IsDeterministic]: Start isDeterministic. Operand 310 states and 429 transitions. [2023-11-19 07:47:06,705 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:47:06,706 INFO L218 hiAutomatonCegarLoop]: Abstraction has 310 states and 429 transitions. [2023-11-19 07:47:06,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 310 states and 429 transitions. [2023-11-19 07:47:06,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 310 to 290. [2023-11-19 07:47:06,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 290 states, 290 states have (on average 1.396551724137931) internal successors, (405), 289 states have internal predecessors, (405), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:47:06,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 290 states to 290 states and 405 transitions. [2023-11-19 07:47:06,734 INFO L240 hiAutomatonCegarLoop]: Abstraction has 290 states and 405 transitions. [2023-11-19 07:47:06,734 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:47:06,735 INFO L428 stractBuchiCegarLoop]: Abstraction has 290 states and 405 transitions. [2023-11-19 07:47:06,736 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-19 07:47:06,736 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 290 states and 405 transitions. [2023-11-19 07:47:06,739 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 258 [2023-11-19 07:47:06,739 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:47:06,739 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:47:06,741 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:47:06,741 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:47:06,742 INFO L748 eck$LassoCheckResult]: Stem: 775#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 776#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 800#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 794#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 748#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 731#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 732#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 832#L250 assume !(0 == ~M_E~0); 846#L250-2 assume !(0 == ~T1_E~0); 788#L255-1 assume !(0 == ~E_1~0); 789#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 806#L115 assume !(1 == ~m_pc~0); 807#L115-2 is_master_triggered_~__retres1~0#1 := 0; 810#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 737#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 738#L300 assume !(0 != activate_threads_~tmp~1#1); 819#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 855#L134 assume !(1 == ~t1_pc~0); 816#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 808#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 787#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 742#L308 assume !(0 != activate_threads_~tmp___0~0#1); 743#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 811#L273 assume !(1 == ~M_E~0); 812#L273-2 assume !(1 == ~T1_E~0); 851#L278-1 assume !(1 == ~E_1~0); 822#L283-1 assume { :end_inline_reset_delta_events } true; 793#L404-2 [2023-11-19 07:47:06,742 INFO L750 eck$LassoCheckResult]: Loop: 793#L404-2 assume !false; 809#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 831#L225-1 assume !false; 837#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 838#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 773#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 746#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 747#L206 assume !(0 != eval_~tmp~0#1); 784#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 836#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 863#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 848#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 849#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 733#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 734#L115-6 assume !(1 == ~m_pc~0); 801#L115-8 is_master_triggered_~__retres1~0#1 := 0; 866#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 804#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 805#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 823#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 864#L134-6 assume !(1 == ~t1_pc~0); 777#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 778#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 803#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 802#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 735#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 736#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 795#L273-5 assume !(1 == ~T1_E~0); 779#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 780#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 826#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 827#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 850#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 757#L423 assume !(0 == start_simulation_~tmp~3#1); 755#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 756#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 761#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 786#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 752#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 753#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 754#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 792#L436 assume !(0 != start_simulation_~tmp___0~1#1); 793#L404-2 [2023-11-19 07:47:06,743 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:47:06,743 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 1 times [2023-11-19 07:47:06,743 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:47:06,744 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [890301986] [2023-11-19 07:47:06,744 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:47:06,744 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:47:06,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:47:06,759 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:47:06,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:47:06,795 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:47:06,796 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:47:06,796 INFO L85 PathProgramCache]: Analyzing trace with hash 487194975, now seen corresponding path program 2 times [2023-11-19 07:47:06,797 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:47:06,797 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [563659390] [2023-11-19 07:47:06,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:47:06,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:47:06,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:47:06,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:47:06,855 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:47:06,855 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [563659390] [2023-11-19 07:47:06,855 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [563659390] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:47:06,856 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:47:06,856 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:47:06,856 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [3716337] [2023-11-19 07:47:06,856 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:47:06,857 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:47:06,857 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:47:06,858 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:47:06,858 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:47:06,858 INFO L87 Difference]: Start difference. First operand 290 states and 405 transitions. cyclomatic complexity: 117 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:47:06,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:47:06,884 INFO L93 Difference]: Finished difference Result 357 states and 494 transitions. [2023-11-19 07:47:06,884 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 357 states and 494 transitions. [2023-11-19 07:47:06,888 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 309 [2023-11-19 07:47:06,926 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 357 states to 357 states and 494 transitions. [2023-11-19 07:47:06,926 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 357 [2023-11-19 07:47:06,927 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 357 [2023-11-19 07:47:06,928 INFO L73 IsDeterministic]: Start isDeterministic. Operand 357 states and 494 transitions. [2023-11-19 07:47:06,930 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:47:06,931 INFO L218 hiAutomatonCegarLoop]: Abstraction has 357 states and 494 transitions. [2023-11-19 07:47:06,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 357 states and 494 transitions. [2023-11-19 07:47:06,960 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 357 to 357. [2023-11-19 07:47:06,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 357 states, 357 states have (on average 1.3837535014005602) internal successors, (494), 356 states have internal predecessors, (494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:47:06,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 357 states to 357 states and 494 transitions. [2023-11-19 07:47:06,969 INFO L240 hiAutomatonCegarLoop]: Abstraction has 357 states and 494 transitions. [2023-11-19 07:47:06,969 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:47:06,970 INFO L428 stractBuchiCegarLoop]: Abstraction has 357 states and 494 transitions. [2023-11-19 07:47:06,971 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-19 07:47:06,971 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 357 states and 494 transitions. [2023-11-19 07:47:06,974 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 309 [2023-11-19 07:47:06,974 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:47:06,974 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:47:06,976 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:47:06,976 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:47:06,977 INFO L748 eck$LassoCheckResult]: Stem: 1428#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 1429#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 1453#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1445#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1399#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 1384#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1385#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1486#L250 assume !(0 == ~M_E~0); 1496#L250-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1511#L255-1 assume !(0 == ~E_1~0); 1561#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1558#L115 assume !(1 == ~m_pc~0); 1555#L115-2 is_master_triggered_~__retres1~0#1 := 0; 1551#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1549#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1547#L300 assume !(0 != activate_threads_~tmp~1#1); 1545#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1544#L134 assume !(1 == ~t1_pc~0); 1541#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1539#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1537#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1535#L308 assume !(0 != activate_threads_~tmp___0~0#1); 1533#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1530#L273 assume !(1 == ~M_E~0); 1514#L273-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1506#L278-1 assume !(1 == ~E_1~0); 1477#L283-1 assume { :end_inline_reset_delta_events } true; 1447#L404-2 [2023-11-19 07:47:06,977 INFO L750 eck$LassoCheckResult]: Loop: 1447#L404-2 assume !false; 1464#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1485#L225-1 assume !false; 1490#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1491#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1426#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1400#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1401#L206 assume !(0 != eval_~tmp~0#1); 1437#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1489#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1519#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1501#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1502#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1386#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1387#L115-6 assume !(1 == ~m_pc~0); 1454#L115-8 is_master_triggered_~__retres1~0#1 := 0; 1527#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1459#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1460#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1478#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1520#L134-6 assume !(1 == ~t1_pc~0); 1526#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 1457#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1458#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1455#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1456#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1525#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1448#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1432#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1433#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1480#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1481#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1504#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 1410#L423 assume !(0 == start_simulation_~tmp~3#1); 1408#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1409#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1414#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1439#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 1405#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1406#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1407#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 1446#L436 assume !(0 != start_simulation_~tmp___0~1#1); 1447#L404-2 [2023-11-19 07:47:06,978 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:47:06,978 INFO L85 PathProgramCache]: Analyzing trace with hash 784287684, now seen corresponding path program 1 times [2023-11-19 07:47:06,978 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:47:06,979 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [892016850] [2023-11-19 07:47:06,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:47:06,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:47:06,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:47:07,023 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:47:07,024 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:47:07,024 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [892016850] [2023-11-19 07:47:07,024 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [892016850] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:47:07,025 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:47:07,025 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:47:07,025 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [223646062] [2023-11-19 07:47:07,025 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:47:07,026 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:47:07,026 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:47:07,027 INFO L85 PathProgramCache]: Analyzing trace with hash 1767058653, now seen corresponding path program 1 times [2023-11-19 07:47:07,027 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:47:07,027 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1334763935] [2023-11-19 07:47:07,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:47:07,028 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:47:07,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:47:07,102 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:47:07,106 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:47:07,106 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1334763935] [2023-11-19 07:47:07,107 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1334763935] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:47:07,107 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:47:07,107 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:47:07,107 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1368189509] [2023-11-19 07:47:07,108 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:47:07,108 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:47:07,108 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:47:07,109 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:47:07,117 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:47:07,117 INFO L87 Difference]: Start difference. First operand 357 states and 494 transitions. cyclomatic complexity: 139 Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 2 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:47:07,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:47:07,138 INFO L93 Difference]: Finished difference Result 290 states and 394 transitions. [2023-11-19 07:47:07,138 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 290 states and 394 transitions. [2023-11-19 07:47:07,142 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 258 [2023-11-19 07:47:07,145 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 290 states to 290 states and 394 transitions. [2023-11-19 07:47:07,146 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 290 [2023-11-19 07:47:07,147 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 290 [2023-11-19 07:47:07,147 INFO L73 IsDeterministic]: Start isDeterministic. Operand 290 states and 394 transitions. [2023-11-19 07:47:07,148 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:47:07,148 INFO L218 hiAutomatonCegarLoop]: Abstraction has 290 states and 394 transitions. [2023-11-19 07:47:07,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 290 states and 394 transitions. [2023-11-19 07:47:07,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 290 to 290. [2023-11-19 07:47:07,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 290 states, 290 states have (on average 1.3586206896551725) internal successors, (394), 289 states have internal predecessors, (394), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:47:07,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 290 states to 290 states and 394 transitions. [2023-11-19 07:47:07,178 INFO L240 hiAutomatonCegarLoop]: Abstraction has 290 states and 394 transitions. [2023-11-19 07:47:07,179 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:47:07,179 INFO L428 stractBuchiCegarLoop]: Abstraction has 290 states and 394 transitions. [2023-11-19 07:47:07,181 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-19 07:47:07,182 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 290 states and 394 transitions. [2023-11-19 07:47:07,184 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 258 [2023-11-19 07:47:07,187 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:47:07,187 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:47:07,189 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:47:07,193 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:47:07,193 INFO L748 eck$LassoCheckResult]: Stem: 2085#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 2086#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 2110#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2102#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2055#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 2040#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2041#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2141#L250 assume !(0 == ~M_E~0); 2152#L250-2 assume !(0 == ~T1_E~0); 2098#L255-1 assume !(0 == ~E_1~0); 2099#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2116#L115 assume !(1 == ~m_pc~0); 2117#L115-2 is_master_triggered_~__retres1~0#1 := 0; 2120#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2046#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2047#L300 assume !(0 != activate_threads_~tmp~1#1); 2127#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2164#L134 assume !(1 == ~t1_pc~0); 2123#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2118#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2097#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2049#L308 assume !(0 != activate_threads_~tmp___0~0#1); 2050#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2121#L273 assume !(1 == ~M_E~0); 2122#L273-2 assume !(1 == ~T1_E~0); 2161#L278-1 assume !(1 == ~E_1~0); 2131#L283-1 assume { :end_inline_reset_delta_events } true; 2132#L404-2 [2023-11-19 07:47:07,194 INFO L750 eck$LassoCheckResult]: Loop: 2132#L404-2 assume !false; 2307#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2157#L225-1 assume !false; 2146#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2147#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2083#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2056#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2057#L206 assume !(0 != eval_~tmp~0#1); 2094#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2300#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2298#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2158#L250-5 assume !(0 == ~T1_E~0); 2159#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2042#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2043#L115-6 assume !(1 == ~m_pc~0); 2111#L115-8 is_master_triggered_~__retres1~0#1 := 0; 2176#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2114#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2115#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2133#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2173#L134-6 assume !(1 == ~t1_pc~0); 2087#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 2088#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2113#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2112#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2044#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2045#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2105#L273-5 assume !(1 == ~T1_E~0); 2089#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2090#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2135#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2136#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2160#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 2066#L423 assume !(0 == start_simulation_~tmp~3#1); 2067#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2316#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2315#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2314#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 2313#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2312#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2311#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 2310#L436 assume !(0 != start_simulation_~tmp___0~1#1); 2132#L404-2 [2023-11-19 07:47:07,194 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:47:07,194 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 2 times [2023-11-19 07:47:07,194 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:47:07,195 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [434496562] [2023-11-19 07:47:07,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:47:07,195 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:47:07,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:47:07,207 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:47:07,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:47:07,219 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:47:07,220 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:47:07,220 INFO L85 PathProgramCache]: Analyzing trace with hash 1188794849, now seen corresponding path program 1 times [2023-11-19 07:47:07,220 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:47:07,221 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [99000382] [2023-11-19 07:47:07,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:47:07,221 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:47:07,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:47:07,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:47:07,284 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:47:07,284 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [99000382] [2023-11-19 07:47:07,284 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [99000382] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:47:07,284 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:47:07,284 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:47:07,285 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [806278997] [2023-11-19 07:47:07,285 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:47:07,285 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:47:07,285 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:47:07,286 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 07:47:07,286 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 07:47:07,286 INFO L87 Difference]: Start difference. First operand 290 states and 394 transitions. cyclomatic complexity: 106 Second operand has 5 states, 5 states have (on average 8.4) internal successors, (42), 5 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:47:07,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:47:07,406 INFO L93 Difference]: Finished difference Result 490 states and 652 transitions. [2023-11-19 07:47:07,406 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 490 states and 652 transitions. [2023-11-19 07:47:07,411 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 453 [2023-11-19 07:47:07,416 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 490 states to 490 states and 652 transitions. [2023-11-19 07:47:07,416 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 490 [2023-11-19 07:47:07,416 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 490 [2023-11-19 07:47:07,417 INFO L73 IsDeterministic]: Start isDeterministic. Operand 490 states and 652 transitions. [2023-11-19 07:47:07,418 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:47:07,418 INFO L218 hiAutomatonCegarLoop]: Abstraction has 490 states and 652 transitions. [2023-11-19 07:47:07,419 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 490 states and 652 transitions. [2023-11-19 07:47:07,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 490 to 299. [2023-11-19 07:47:07,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 299 states, 299 states have (on average 1.3478260869565217) internal successors, (403), 298 states have internal predecessors, (403), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:47:07,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 299 states to 299 states and 403 transitions. [2023-11-19 07:47:07,431 INFO L240 hiAutomatonCegarLoop]: Abstraction has 299 states and 403 transitions. [2023-11-19 07:47:07,432 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-19 07:47:07,432 INFO L428 stractBuchiCegarLoop]: Abstraction has 299 states and 403 transitions. [2023-11-19 07:47:07,433 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-19 07:47:07,433 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 299 states and 403 transitions. [2023-11-19 07:47:07,435 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 267 [2023-11-19 07:47:07,435 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:47:07,435 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:47:07,437 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:47:07,437 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:47:07,437 INFO L748 eck$LassoCheckResult]: Stem: 2884#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 2885#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 2909#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2901#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2852#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 2837#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2838#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2943#L250 assume !(0 == ~M_E~0); 2954#L250-2 assume !(0 == ~T1_E~0); 2897#L255-1 assume !(0 == ~E_1~0); 2898#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2915#L115 assume !(1 == ~m_pc~0); 2916#L115-2 is_master_triggered_~__retres1~0#1 := 0; 2919#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2843#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2844#L300 assume !(0 != activate_threads_~tmp~1#1); 2927#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2968#L134 assume !(1 == ~t1_pc~0); 2922#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2917#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2896#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2846#L308 assume !(0 != activate_threads_~tmp___0~0#1); 2847#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2920#L273 assume !(1 == ~M_E~0); 2921#L273-2 assume !(1 == ~T1_E~0); 2963#L278-1 assume !(1 == ~E_1~0); 2931#L283-1 assume { :end_inline_reset_delta_events } true; 2932#L404-2 [2023-11-19 07:47:07,438 INFO L750 eck$LassoCheckResult]: Loop: 2932#L404-2 assume !false; 3073#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3061#L225-1 assume !false; 2948#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2949#L179 assume !(0 == ~m_st~0); 2880#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 2882#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3049#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3048#L206 assume !(0 != eval_~tmp~0#1); 2946#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2947#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2976#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2960#L250-5 assume !(0 == ~T1_E~0); 2961#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2839#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2840#L115-6 assume !(1 == ~m_pc~0); 2910#L115-8 is_master_triggered_~__retres1~0#1 := 0; 2982#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2983#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2933#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2934#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2981#L134-6 assume !(1 == ~t1_pc~0); 2886#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 2887#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2912#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2911#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2841#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2842#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2904#L273-5 assume !(1 == ~T1_E~0); 2888#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2889#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2936#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2937#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2962#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 2863#L423 assume !(0 == start_simulation_~tmp~3#1); 2864#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3093#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3092#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3091#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 3090#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3089#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3088#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 3087#L436 assume !(0 != start_simulation_~tmp___0~1#1); 2932#L404-2 [2023-11-19 07:47:07,438 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:47:07,439 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 3 times [2023-11-19 07:47:07,439 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:47:07,439 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [294086122] [2023-11-19 07:47:07,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:47:07,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:47:07,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:47:07,453 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:47:07,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:47:07,473 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:47:07,473 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:47:07,474 INFO L85 PathProgramCache]: Analyzing trace with hash 1260103574, now seen corresponding path program 1 times [2023-11-19 07:47:07,474 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:47:07,474 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1926707519] [2023-11-19 07:47:07,474 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:47:07,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:47:07,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:47:07,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:47:07,620 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:47:07,621 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1926707519] [2023-11-19 07:47:07,621 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1926707519] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:47:07,623 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:47:07,624 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:47:07,624 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [26640644] [2023-11-19 07:47:07,624 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:47:07,625 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:47:07,625 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:47:07,626 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 07:47:07,626 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 07:47:07,627 INFO L87 Difference]: Start difference. First operand 299 states and 403 transitions. cyclomatic complexity: 106 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:47:07,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:47:07,731 INFO L93 Difference]: Finished difference Result 522 states and 690 transitions. [2023-11-19 07:47:07,731 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 522 states and 690 transitions. [2023-11-19 07:47:07,737 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 490 [2023-11-19 07:47:07,741 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 522 states to 522 states and 690 transitions. [2023-11-19 07:47:07,742 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 522 [2023-11-19 07:47:07,742 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 522 [2023-11-19 07:47:07,743 INFO L73 IsDeterministic]: Start isDeterministic. Operand 522 states and 690 transitions. [2023-11-19 07:47:07,744 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:47:07,744 INFO L218 hiAutomatonCegarLoop]: Abstraction has 522 states and 690 transitions. [2023-11-19 07:47:07,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 522 states and 690 transitions. [2023-11-19 07:47:07,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 522 to 317. [2023-11-19 07:47:07,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 317 states, 317 states have (on average 1.3186119873817035) internal successors, (418), 316 states have internal predecessors, (418), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:47:07,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 317 states to 317 states and 418 transitions. [2023-11-19 07:47:07,754 INFO L240 hiAutomatonCegarLoop]: Abstraction has 317 states and 418 transitions. [2023-11-19 07:47:07,754 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-19 07:47:07,757 INFO L428 stractBuchiCegarLoop]: Abstraction has 317 states and 418 transitions. [2023-11-19 07:47:07,757 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-19 07:47:07,757 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 317 states and 418 transitions. [2023-11-19 07:47:07,759 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 285 [2023-11-19 07:47:07,760 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:47:07,760 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:47:07,762 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:47:07,762 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:47:07,763 INFO L748 eck$LassoCheckResult]: Stem: 3716#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 3717#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 3741#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3733#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3685#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 3670#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3671#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3780#L250 assume !(0 == ~M_E~0); 3791#L250-2 assume !(0 == ~T1_E~0); 3728#L255-1 assume !(0 == ~E_1~0); 3729#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3751#L115 assume !(1 == ~m_pc~0); 3752#L115-2 is_master_triggered_~__retres1~0#1 := 0; 3756#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3676#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3677#L300 assume !(0 != activate_threads_~tmp~1#1); 3763#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3804#L134 assume !(1 == ~t1_pc~0); 3759#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3754#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3727#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3679#L308 assume !(0 != activate_threads_~tmp___0~0#1); 3680#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3757#L273 assume !(1 == ~M_E~0); 3758#L273-2 assume !(1 == ~T1_E~0); 3800#L278-1 assume !(1 == ~E_1~0); 3768#L283-1 assume { :end_inline_reset_delta_events } true; 3769#L404-2 [2023-11-19 07:47:07,763 INFO L750 eck$LassoCheckResult]: Loop: 3769#L404-2 assume !false; 3857#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3856#L225-1 assume !false; 3855#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3853#L179 assume !(0 == ~m_st~0); 3854#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 3852#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3838#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3839#L206 assume !(0 != eval_~tmp~0#1); 3851#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3850#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3849#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3848#L250-5 assume !(0 == ~T1_E~0); 3847#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3846#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3742#L115-6 assume !(1 == ~m_pc~0); 3743#L115-8 is_master_triggered_~__retres1~0#1 := 0; 3901#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3900#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3899#L300-6 assume !(0 != activate_threads_~tmp~1#1); 3898#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3896#L134-6 assume !(1 == ~t1_pc~0); 3894#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 3892#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3890#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3888#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3886#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3884#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3882#L273-5 assume !(1 == ~T1_E~0); 3880#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3878#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3876#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3873#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3871#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 3869#L423 assume !(0 == start_simulation_~tmp~3#1); 3868#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3866#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3865#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3864#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 3863#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3862#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3861#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 3860#L436 assume !(0 != start_simulation_~tmp___0~1#1); 3769#L404-2 [2023-11-19 07:47:07,763 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:47:07,763 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 4 times [2023-11-19 07:47:07,764 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:47:07,764 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1232719790] [2023-11-19 07:47:07,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:47:07,764 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:47:07,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:47:07,773 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:47:07,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:47:07,785 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:47:07,786 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:47:07,787 INFO L85 PathProgramCache]: Analyzing trace with hash 1126090068, now seen corresponding path program 1 times [2023-11-19 07:47:07,787 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:47:07,788 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [475323220] [2023-11-19 07:47:07,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:47:07,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:47:07,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:47:07,844 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:47:07,846 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:47:07,846 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [475323220] [2023-11-19 07:47:07,848 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [475323220] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:47:07,848 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:47:07,849 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:47:07,855 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [914346160] [2023-11-19 07:47:07,856 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:47:07,856 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:47:07,857 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:47:07,858 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:47:07,858 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:47:07,858 INFO L87 Difference]: Start difference. First operand 317 states and 418 transitions. cyclomatic complexity: 103 Second operand has 3 states, 3 states have (on average 14.333333333333334) internal successors, (43), 3 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:47:07,894 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:47:07,895 INFO L93 Difference]: Finished difference Result 471 states and 607 transitions. [2023-11-19 07:47:07,895 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 471 states and 607 transitions. [2023-11-19 07:47:07,900 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 437 [2023-11-19 07:47:07,904 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 471 states to 471 states and 607 transitions. [2023-11-19 07:47:07,904 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 471 [2023-11-19 07:47:07,905 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 471 [2023-11-19 07:47:07,905 INFO L73 IsDeterministic]: Start isDeterministic. Operand 471 states and 607 transitions. [2023-11-19 07:47:07,906 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:47:07,906 INFO L218 hiAutomatonCegarLoop]: Abstraction has 471 states and 607 transitions. [2023-11-19 07:47:07,907 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 471 states and 607 transitions. [2023-11-19 07:47:07,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 471 to 450. [2023-11-19 07:47:07,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 450 states, 450 states have (on average 1.2933333333333332) internal successors, (582), 449 states have internal predecessors, (582), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:47:07,920 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 450 states to 450 states and 582 transitions. [2023-11-19 07:47:07,920 INFO L240 hiAutomatonCegarLoop]: Abstraction has 450 states and 582 transitions. [2023-11-19 07:47:07,920 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:47:07,923 INFO L428 stractBuchiCegarLoop]: Abstraction has 450 states and 582 transitions. [2023-11-19 07:47:07,923 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-19 07:47:07,923 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 450 states and 582 transitions. [2023-11-19 07:47:07,927 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 416 [2023-11-19 07:47:07,927 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:47:07,927 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:47:07,928 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:47:07,928 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:47:07,928 INFO L748 eck$LassoCheckResult]: Stem: 4509#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 4510#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 4535#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4529#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4481#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 4464#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4465#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4569#L250 assume !(0 == ~M_E~0); 4585#L250-2 assume !(0 == ~T1_E~0); 4522#L255-1 assume !(0 == ~E_1~0); 4523#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4543#L115 assume !(1 == ~m_pc~0); 4544#L115-2 is_master_triggered_~__retres1~0#1 := 0; 4547#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4470#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 4471#L300 assume !(0 != activate_threads_~tmp~1#1); 4555#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4594#L134 assume !(1 == ~t1_pc~0); 4553#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4545#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4521#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4475#L308 assume !(0 != activate_threads_~tmp___0~0#1); 4476#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4548#L273 assume !(1 == ~M_E~0); 4549#L273-2 assume !(1 == ~T1_E~0); 4590#L278-1 assume !(1 == ~E_1~0); 4559#L283-1 assume { :end_inline_reset_delta_events } true; 4560#L404-2 assume !false; 4880#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4769#L225-1 [2023-11-19 07:47:07,928 INFO L750 eck$LassoCheckResult]: Loop: 4769#L225-1 assume !false; 4882#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4881#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4568#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4479#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4480#L206 assume 0 != eval_~tmp~0#1; 4879#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 4608#L214 assume !(0 != eval_~tmp_ndt_1~0#1); 4609#L214-2 havoc eval_~tmp_ndt_1~0#1; 4768#L211-1 assume !(0 == ~t1_st~0); 4769#L225-1 [2023-11-19 07:47:07,929 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:47:07,929 INFO L85 PathProgramCache]: Analyzing trace with hash -1789227190, now seen corresponding path program 1 times [2023-11-19 07:47:07,929 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:47:07,929 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1918631870] [2023-11-19 07:47:07,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:47:07,930 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:47:07,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:47:07,945 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:47:07,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:47:07,972 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:47:07,973 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:47:07,973 INFO L85 PathProgramCache]: Analyzing trace with hash 722519487, now seen corresponding path program 1 times [2023-11-19 07:47:07,973 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:47:07,973 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [753348433] [2023-11-19 07:47:07,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:47:07,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:47:07,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:47:07,977 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:47:07,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:47:07,984 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:47:07,986 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:47:07,986 INFO L85 PathProgramCache]: Analyzing trace with hash -1929671224, now seen corresponding path program 1 times [2023-11-19 07:47:07,987 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:47:07,987 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [259620262] [2023-11-19 07:47:07,987 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:47:07,987 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:47:08,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:47:08,068 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:47:08,069 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:47:08,069 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [259620262] [2023-11-19 07:47:08,069 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [259620262] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:47:08,069 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:47:08,069 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:47:08,070 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1298675138] [2023-11-19 07:47:08,070 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:47:08,152 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:47:08,153 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:47:08,153 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:47:08,154 INFO L87 Difference]: Start difference. First operand 450 states and 582 transitions. cyclomatic complexity: 135 Second operand has 3 states, 2 states have (on average 19.5) internal successors, (39), 3 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:47:08,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:47:08,202 INFO L93 Difference]: Finished difference Result 783 states and 999 transitions. [2023-11-19 07:47:08,202 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 783 states and 999 transitions. [2023-11-19 07:47:08,210 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 683 [2023-11-19 07:47:08,217 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 783 states to 783 states and 999 transitions. [2023-11-19 07:47:08,217 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 783 [2023-11-19 07:47:08,219 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 783 [2023-11-19 07:47:08,219 INFO L73 IsDeterministic]: Start isDeterministic. Operand 783 states and 999 transitions. [2023-11-19 07:47:08,220 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:47:08,221 INFO L218 hiAutomatonCegarLoop]: Abstraction has 783 states and 999 transitions. [2023-11-19 07:47:08,222 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 783 states and 999 transitions. [2023-11-19 07:47:08,235 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 783 to 705. [2023-11-19 07:47:08,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 705 states, 705 states have (on average 1.2907801418439717) internal successors, (910), 704 states have internal predecessors, (910), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:47:08,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 705 states to 705 states and 910 transitions. [2023-11-19 07:47:08,241 INFO L240 hiAutomatonCegarLoop]: Abstraction has 705 states and 910 transitions. [2023-11-19 07:47:08,241 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:47:08,242 INFO L428 stractBuchiCegarLoop]: Abstraction has 705 states and 910 transitions. [2023-11-19 07:47:08,242 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-19 07:47:08,242 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 705 states and 910 transitions. [2023-11-19 07:47:08,247 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 631 [2023-11-19 07:47:08,247 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:47:08,247 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:47:08,248 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:47:08,248 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:47:08,248 INFO L748 eck$LassoCheckResult]: Stem: 5750#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 5751#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 5777#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5768#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5722#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 5705#L161-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 5706#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5828#L250 assume !(0 == ~M_E~0); 5829#L250-2 assume !(0 == ~T1_E~0); 5853#L255-1 assume !(0 == ~E_1~0); 5817#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5818#L115 assume !(1 == ~m_pc~0); 5791#L115-2 is_master_triggered_~__retres1~0#1 := 0; 5792#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5803#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5800#L300 assume !(0 != activate_threads_~tmp~1#1); 5801#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5868#L134 assume !(1 == ~t1_pc~0); 5869#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5788#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5789#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5715#L308 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5716#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5795#L273 assume !(1 == ~M_E~0); 5856#L273-2 assume !(1 == ~T1_E~0); 5857#L278-1 assume !(1 == ~E_1~0); 5807#L283-1 assume { :end_inline_reset_delta_events } true; 5808#L404-2 assume !false; 6358#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6356#L225-1 [2023-11-19 07:47:08,249 INFO L750 eck$LassoCheckResult]: Loop: 6356#L225-1 assume !false; 6355#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6354#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6353#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6352#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6351#L206 assume 0 != eval_~tmp~0#1; 6350#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 5877#L214 assume !(0 != eval_~tmp_ndt_1~0#1); 5878#L214-2 havoc eval_~tmp_ndt_1~0#1; 6253#L211-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 5825#L228 assume !(0 != eval_~tmp_ndt_2~0#1); 5827#L228-2 havoc eval_~tmp_ndt_2~0#1; 6356#L225-1 [2023-11-19 07:47:08,249 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:47:08,249 INFO L85 PathProgramCache]: Analyzing trace with hash -1113894070, now seen corresponding path program 1 times [2023-11-19 07:47:08,250 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:47:08,250 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [690085438] [2023-11-19 07:47:08,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:47:08,250 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:47:08,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:47:08,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:47:08,272 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:47:08,272 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [690085438] [2023-11-19 07:47:08,272 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [690085438] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:47:08,272 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:47:08,273 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:47:08,273 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [804088366] [2023-11-19 07:47:08,273 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:47:08,273 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:47:08,274 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:47:08,274 INFO L85 PathProgramCache]: Analyzing trace with hash -1443506858, now seen corresponding path program 1 times [2023-11-19 07:47:08,274 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:47:08,274 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2064700979] [2023-11-19 07:47:08,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:47:08,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:47:08,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:47:08,278 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:47:08,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:47:08,282 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:47:08,339 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:47:08,339 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:47:08,339 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:47:08,340 INFO L87 Difference]: Start difference. First operand 705 states and 910 transitions. cyclomatic complexity: 209 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:47:08,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:47:08,350 INFO L93 Difference]: Finished difference Result 591 states and 767 transitions. [2023-11-19 07:47:08,350 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 591 states and 767 transitions. [2023-11-19 07:47:08,355 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 557 [2023-11-19 07:47:08,360 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 591 states to 591 states and 767 transitions. [2023-11-19 07:47:08,360 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 591 [2023-11-19 07:47:08,361 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 591 [2023-11-19 07:47:08,361 INFO L73 IsDeterministic]: Start isDeterministic. Operand 591 states and 767 transitions. [2023-11-19 07:47:08,362 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:47:08,363 INFO L218 hiAutomatonCegarLoop]: Abstraction has 591 states and 767 transitions. [2023-11-19 07:47:08,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 591 states and 767 transitions. [2023-11-19 07:47:08,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 591 to 591. [2023-11-19 07:47:08,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 591 states, 591 states have (on average 1.2978003384094754) internal successors, (767), 590 states have internal predecessors, (767), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:47:08,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 591 states to 591 states and 767 transitions. [2023-11-19 07:47:08,378 INFO L240 hiAutomatonCegarLoop]: Abstraction has 591 states and 767 transitions. [2023-11-19 07:47:08,379 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:47:08,379 INFO L428 stractBuchiCegarLoop]: Abstraction has 591 states and 767 transitions. [2023-11-19 07:47:08,380 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-19 07:47:08,380 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 591 states and 767 transitions. [2023-11-19 07:47:08,384 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 557 [2023-11-19 07:47:08,384 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:47:08,384 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:47:08,385 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:47:08,385 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:47:08,385 INFO L748 eck$LassoCheckResult]: Stem: 7049#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 7050#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 7074#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7066#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7022#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 7007#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7008#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7109#L250 assume !(0 == ~M_E~0); 7119#L250-2 assume !(0 == ~T1_E~0); 7061#L255-1 assume !(0 == ~E_1~0); 7062#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7083#L115 assume !(1 == ~m_pc~0); 7084#L115-2 is_master_triggered_~__retres1~0#1 := 0; 7087#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7013#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 7014#L300 assume !(0 != activate_threads_~tmp~1#1); 7095#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7137#L134 assume !(1 == ~t1_pc~0); 7090#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7085#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7060#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 7016#L308 assume !(0 != activate_threads_~tmp___0~0#1); 7017#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7088#L273 assume !(1 == ~M_E~0); 7089#L273-2 assume !(1 == ~T1_E~0); 7129#L278-1 assume !(1 == ~E_1~0); 7099#L283-1 assume { :end_inline_reset_delta_events } true; 7100#L404-2 assume !false; 7540#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7539#L225-1 [2023-11-19 07:47:08,385 INFO L750 eck$LassoCheckResult]: Loop: 7539#L225-1 assume !false; 7538#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 7536#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 7534#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 7532#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7531#L206 assume 0 != eval_~tmp~0#1; 7529#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 7148#L214 assume !(0 != eval_~tmp_ndt_1~0#1); 7149#L214-2 havoc eval_~tmp_ndt_1~0#1; 7543#L211-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 7542#L228 assume !(0 != eval_~tmp_ndt_2~0#1); 7541#L228-2 havoc eval_~tmp_ndt_2~0#1; 7539#L225-1 [2023-11-19 07:47:08,386 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:47:08,386 INFO L85 PathProgramCache]: Analyzing trace with hash -1789227190, now seen corresponding path program 2 times [2023-11-19 07:47:08,386 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:47:08,386 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1560207813] [2023-11-19 07:47:08,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:47:08,387 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:47:08,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:47:08,394 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:47:08,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:47:08,402 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:47:08,403 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:47:08,403 INFO L85 PathProgramCache]: Analyzing trace with hash -1443506858, now seen corresponding path program 2 times [2023-11-19 07:47:08,403 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:47:08,404 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [720198564] [2023-11-19 07:47:08,404 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:47:08,404 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:47:08,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:47:08,408 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:47:08,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:47:08,412 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:47:08,412 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:47:08,413 INFO L85 PathProgramCache]: Analyzing trace with hash 1011793695, now seen corresponding path program 1 times [2023-11-19 07:47:08,413 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:47:08,413 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [368604028] [2023-11-19 07:47:08,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:47:08,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:47:08,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:47:08,421 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:47:08,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:47:08,440 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:47:09,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:47:09,043 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:47:09,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:47:09,169 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 19.11 07:47:09 BoogieIcfgContainer [2023-11-19 07:47:09,169 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-19 07:47:09,169 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-19 07:47:09,169 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-19 07:47:09,170 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-19 07:47:09,170 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:47:05" (3/4) ... [2023-11-19 07:47:09,172 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-19 07:47:09,236 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_138d3320-eb15-480c-abed-f63e41f5ebe4/bin/uautomizer-verify-uCwYo4JHxu/witness.graphml [2023-11-19 07:47:09,236 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-19 07:47:09,237 INFO L158 Benchmark]: Toolchain (without parser) took 4552.80ms. Allocated memory was 169.9MB in the beginning and 205.5MB in the end (delta: 35.7MB). Free memory was 129.3MB in the beginning and 145.8MB in the end (delta: -16.5MB). Peak memory consumption was 20.7MB. Max. memory is 16.1GB. [2023-11-19 07:47:09,237 INFO L158 Benchmark]: CDTParser took 0.66ms. Allocated memory is still 113.2MB. Free memory was 62.6MB in the beginning and 62.4MB in the end (delta: 134.3kB). There was no memory consumed. Max. memory is 16.1GB. [2023-11-19 07:47:09,238 INFO L158 Benchmark]: CACSL2BoogieTranslator took 329.35ms. Allocated memory is still 169.9MB. Free memory was 129.0MB in the beginning and 116.4MB in the end (delta: 12.6MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2023-11-19 07:47:09,238 INFO L158 Benchmark]: Boogie Procedure Inliner took 48.51ms. Allocated memory is still 169.9MB. Free memory was 116.4MB in the beginning and 113.8MB in the end (delta: 2.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-19 07:47:09,239 INFO L158 Benchmark]: Boogie Preprocessor took 47.46ms. Allocated memory is still 169.9MB. Free memory was 113.8MB in the beginning and 112.0MB in the end (delta: 1.8MB). There was no memory consumed. Max. memory is 16.1GB. [2023-11-19 07:47:09,239 INFO L158 Benchmark]: RCFGBuilder took 552.02ms. Allocated memory is still 169.9MB. Free memory was 112.0MB in the beginning and 92.1MB in the end (delta: 19.8MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. [2023-11-19 07:47:09,239 INFO L158 Benchmark]: BuchiAutomizer took 3493.44ms. Allocated memory was 169.9MB in the beginning and 205.5MB in the end (delta: 35.7MB). Free memory was 92.1MB in the beginning and 148.9MB in the end (delta: -56.8MB). There was no memory consumed. Max. memory is 16.1GB. [2023-11-19 07:47:09,240 INFO L158 Benchmark]: Witness Printer took 66.87ms. Allocated memory is still 205.5MB. Free memory was 148.9MB in the beginning and 145.8MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-19 07:47:09,242 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.66ms. Allocated memory is still 113.2MB. Free memory was 62.6MB in the beginning and 62.4MB in the end (delta: 134.3kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 329.35ms. Allocated memory is still 169.9MB. Free memory was 129.0MB in the beginning and 116.4MB in the end (delta: 12.6MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 48.51ms. Allocated memory is still 169.9MB. Free memory was 116.4MB in the beginning and 113.8MB in the end (delta: 2.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 47.46ms. Allocated memory is still 169.9MB. Free memory was 113.8MB in the beginning and 112.0MB in the end (delta: 1.8MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 552.02ms. Allocated memory is still 169.9MB. Free memory was 112.0MB in the beginning and 92.1MB in the end (delta: 19.8MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. * BuchiAutomizer took 3493.44ms. Allocated memory was 169.9MB in the beginning and 205.5MB in the end (delta: 35.7MB). Free memory was 92.1MB in the beginning and 148.9MB in the end (delta: -56.8MB). There was no memory consumed. Max. memory is 16.1GB. * Witness Printer took 66.87ms. Allocated memory is still 205.5MB. Free memory was 148.9MB in the beginning and 145.8MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 9 terminating modules (9 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.9 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 591 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.3s and 10 iterations. TraceHistogramMax:1. Analysis of lassos took 2.1s. Construction of modules took 0.2s. Büchi inclusion checks took 0.7s. Highest rank in rank-based complementation 0. Minimization of det autom 9. Minimization of nondet autom 0. Automata minimization 0.2s AutomataMinimizationTime, 9 MinimizatonAttempts, 515 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1510 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1510 mSDsluCounter, 3347 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1747 mSDsCounter, 68 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 209 IncrementalHoareTripleChecker+Invalid, 277 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 68 mSolverCounterUnsat, 1600 mSDtfsCounter, 209 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc1 concLT0 SILN1 SILU0 SILI3 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 201]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int M_E = 2; [L32] int T1_E = 2; [L33] int E_1 = 2; VAL [E_1=2, M_E=2, T1_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0] [L449] int __retres1 ; [L453] CALL init_model() [L364] m_i = 1 [L365] t1_i = 1 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L453] RET init_model() [L454] CALL start_simulation() [L390] int kernel_st ; [L391] int tmp ; [L392] int tmp___0 ; [L396] kernel_st = 0 [L397] FCALL update_channels() [L398] CALL init_threads() [L161] COND TRUE m_i == 1 [L162] m_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L166] COND TRUE t1_i == 1 [L167] t1_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L398] RET init_threads() [L399] CALL fire_delta_events() [L250] COND FALSE !(M_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L255] COND FALSE !(T1_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L260] COND FALSE !(E_1 == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L399] RET fire_delta_events() [L400] CALL activate_threads() [L293] int tmp ; [L294] int tmp___0 ; [L298] CALL, EXPR is_master_triggered() [L112] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L115] COND FALSE !(m_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L125] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L127] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L298] RET, EXPR is_master_triggered() [L298] tmp = is_master_triggered() [L300] COND FALSE !(\read(tmp)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, tmp=0] [L306] CALL, EXPR is_transmit1_triggered() [L131] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L134] COND FALSE !(t1_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L144] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L146] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] RET, EXPR is_transmit1_triggered() [L306] tmp___0 = is_transmit1_triggered() [L308] COND FALSE !(\read(tmp___0)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, tmp=0, tmp___0=0] [L400] RET activate_threads() [L401] CALL reset_delta_events() [L273] COND FALSE !(M_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L278] COND FALSE !(T1_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L283] COND FALSE !(E_1 == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L401] RET reset_delta_events() [L404] COND TRUE 1 VAL [E_1=2, M_E=2, T1_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L407] kernel_st = 1 [L408] CALL eval() [L197] int tmp ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] Loop: [L201] COND TRUE 1 [L204] CALL, EXPR exists_runnable_thread() [L176] int __retres1 ; [L179] COND TRUE m_st == 0 [L180] __retres1 = 1 [L192] return (__retres1); [L204] RET, EXPR exists_runnable_thread() [L204] tmp = exists_runnable_thread() [L206] COND TRUE \read(tmp) [L211] COND TRUE m_st == 0 [L212] int tmp_ndt_1; [L213] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L214] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L211-L222] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L225] COND TRUE t1_st == 0 [L226] int tmp_ndt_2; [L227] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L228] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L225-L236] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 201]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int M_E = 2; [L32] int T1_E = 2; [L33] int E_1 = 2; VAL [E_1=2, M_E=2, T1_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0] [L449] int __retres1 ; [L453] CALL init_model() [L364] m_i = 1 [L365] t1_i = 1 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L453] RET init_model() [L454] CALL start_simulation() [L390] int kernel_st ; [L391] int tmp ; [L392] int tmp___0 ; [L396] kernel_st = 0 [L397] FCALL update_channels() [L398] CALL init_threads() [L161] COND TRUE m_i == 1 [L162] m_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L166] COND TRUE t1_i == 1 [L167] t1_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L398] RET init_threads() [L399] CALL fire_delta_events() [L250] COND FALSE !(M_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L255] COND FALSE !(T1_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L260] COND FALSE !(E_1 == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L399] RET fire_delta_events() [L400] CALL activate_threads() [L293] int tmp ; [L294] int tmp___0 ; [L298] CALL, EXPR is_master_triggered() [L112] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L115] COND FALSE !(m_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L125] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L127] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L298] RET, EXPR is_master_triggered() [L298] tmp = is_master_triggered() [L300] COND FALSE !(\read(tmp)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, tmp=0] [L306] CALL, EXPR is_transmit1_triggered() [L131] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L134] COND FALSE !(t1_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L144] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L146] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] RET, EXPR is_transmit1_triggered() [L306] tmp___0 = is_transmit1_triggered() [L308] COND FALSE !(\read(tmp___0)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, tmp=0, tmp___0=0] [L400] RET activate_threads() [L401] CALL reset_delta_events() [L273] COND FALSE !(M_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L278] COND FALSE !(T1_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L283] COND FALSE !(E_1 == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L401] RET reset_delta_events() [L404] COND TRUE 1 VAL [E_1=2, M_E=2, T1_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L407] kernel_st = 1 [L408] CALL eval() [L197] int tmp ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] Loop: [L201] COND TRUE 1 [L204] CALL, EXPR exists_runnable_thread() [L176] int __retres1 ; [L179] COND TRUE m_st == 0 [L180] __retres1 = 1 [L192] return (__retres1); [L204] RET, EXPR exists_runnable_thread() [L204] tmp = exists_runnable_thread() [L206] COND TRUE \read(tmp) [L211] COND TRUE m_st == 0 [L212] int tmp_ndt_1; [L213] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L214] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L211-L222] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L225] COND TRUE t1_st == 0 [L226] int tmp_ndt_2; [L227] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L228] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L225-L236] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-19 07:47:09,351 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_138d3320-eb15-480c-abed-f63e41f5ebe4/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)