./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.09.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 9bd2c7ff Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb2b05ce-88b3-40c1-af45-186405aa6e08/bin/uautomizer-verify-uCwYo4JHxu/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb2b05ce-88b3-40c1-af45-186405aa6e08/bin/uautomizer-verify-uCwYo4JHxu/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb2b05ce-88b3-40c1-af45-186405aa6e08/bin/uautomizer-verify-uCwYo4JHxu/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb2b05ce-88b3-40c1-af45-186405aa6e08/bin/uautomizer-verify-uCwYo4JHxu/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.09.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb2b05ce-88b3-40c1-af45-186405aa6e08/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb2b05ce-88b3-40c1-af45-186405aa6e08/bin/uautomizer-verify-uCwYo4JHxu --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 3945fa4b58cef50cb4b44b435a699812e99a1f6375664d08551274c6b50bee45 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-9bd2c7f [2023-11-19 08:04:22,802 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-19 08:04:22,944 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb2b05ce-88b3-40c1-af45-186405aa6e08/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-19 08:04:22,955 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-19 08:04:22,956 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-19 08:04:23,007 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-19 08:04:23,009 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-19 08:04:23,010 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-19 08:04:23,012 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-19 08:04:23,014 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-19 08:04:23,015 INFO L153 SettingsManager]: * Use SBE=true [2023-11-19 08:04:23,015 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-19 08:04:23,016 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-19 08:04:23,016 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-19 08:04:23,019 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-19 08:04:23,020 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-19 08:04:23,020 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-19 08:04:23,021 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-19 08:04:23,022 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-19 08:04:23,022 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-19 08:04:23,023 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-19 08:04:23,023 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-19 08:04:23,024 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-19 08:04:23,024 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-19 08:04:23,025 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-19 08:04:23,025 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-19 08:04:23,025 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-19 08:04:23,026 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-19 08:04:23,026 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-19 08:04:23,027 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-19 08:04:23,028 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-19 08:04:23,029 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-19 08:04:23,029 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-19 08:04:23,029 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-19 08:04:23,030 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-19 08:04:23,030 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-19 08:04:23,030 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb2b05ce-88b3-40c1-af45-186405aa6e08/bin/uautomizer-verify-uCwYo4JHxu/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb2b05ce-88b3-40c1-af45-186405aa6e08/bin/uautomizer-verify-uCwYo4JHxu Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 3945fa4b58cef50cb4b44b435a699812e99a1f6375664d08551274c6b50bee45 [2023-11-19 08:04:23,330 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-19 08:04:23,357 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-19 08:04:23,360 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-19 08:04:23,362 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-19 08:04:23,363 INFO L274 PluginConnector]: CDTParser initialized [2023-11-19 08:04:23,365 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb2b05ce-88b3-40c1-af45-186405aa6e08/bin/uautomizer-verify-uCwYo4JHxu/../../sv-benchmarks/c/systemc/transmitter.09.cil.c [2023-11-19 08:04:26,645 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-19 08:04:27,001 INFO L384 CDTParser]: Found 1 translation units. [2023-11-19 08:04:27,004 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb2b05ce-88b3-40c1-af45-186405aa6e08/sv-benchmarks/c/systemc/transmitter.09.cil.c [2023-11-19 08:04:27,038 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb2b05ce-88b3-40c1-af45-186405aa6e08/bin/uautomizer-verify-uCwYo4JHxu/data/d927079af/b258e4dd2019486b8d39b883ff202e01/FLAG7b6497794 [2023-11-19 08:04:27,064 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb2b05ce-88b3-40c1-af45-186405aa6e08/bin/uautomizer-verify-uCwYo4JHxu/data/d927079af/b258e4dd2019486b8d39b883ff202e01 [2023-11-19 08:04:27,073 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-19 08:04:27,076 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-19 08:04:27,080 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-19 08:04:27,082 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-19 08:04:27,089 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-19 08:04:27,090 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 08:04:27" (1/1) ... [2023-11-19 08:04:27,092 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@652aba8c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:04:27, skipping insertion in model container [2023-11-19 08:04:27,092 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 08:04:27" (1/1) ... [2023-11-19 08:04:27,181 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-19 08:04:27,564 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 08:04:27,583 INFO L202 MainTranslator]: Completed pre-run [2023-11-19 08:04:27,699 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 08:04:27,740 INFO L206 MainTranslator]: Completed translation [2023-11-19 08:04:27,740 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:04:27 WrapperNode [2023-11-19 08:04:27,741 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-19 08:04:27,742 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-19 08:04:27,742 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-19 08:04:27,743 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-19 08:04:27,752 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:04:27" (1/1) ... [2023-11-19 08:04:27,771 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:04:27" (1/1) ... [2023-11-19 08:04:27,906 INFO L138 Inliner]: procedures = 46, calls = 58, calls flagged for inlining = 53, calls inlined = 171, statements flattened = 2601 [2023-11-19 08:04:27,906 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-19 08:04:27,907 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-19 08:04:27,907 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-19 08:04:27,907 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-19 08:04:27,920 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:04:27" (1/1) ... [2023-11-19 08:04:27,921 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:04:27" (1/1) ... [2023-11-19 08:04:27,959 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:04:27" (1/1) ... [2023-11-19 08:04:27,959 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:04:27" (1/1) ... [2023-11-19 08:04:28,042 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:04:27" (1/1) ... [2023-11-19 08:04:28,121 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:04:27" (1/1) ... [2023-11-19 08:04:28,133 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:04:27" (1/1) ... [2023-11-19 08:04:28,154 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:04:27" (1/1) ... [2023-11-19 08:04:28,174 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-19 08:04:28,176 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-19 08:04:28,176 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-19 08:04:28,176 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-19 08:04:28,177 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:04:27" (1/1) ... [2023-11-19 08:04:28,185 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 08:04:28,200 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb2b05ce-88b3-40c1-af45-186405aa6e08/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 08:04:28,221 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb2b05ce-88b3-40c1-af45-186405aa6e08/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 08:04:28,266 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb2b05ce-88b3-40c1-af45-186405aa6e08/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-19 08:04:28,293 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-19 08:04:28,294 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-19 08:04:28,294 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-19 08:04:28,295 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-19 08:04:28,559 INFO L236 CfgBuilder]: Building ICFG [2023-11-19 08:04:28,562 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-19 08:04:30,621 INFO L277 CfgBuilder]: Performing block encoding [2023-11-19 08:04:30,645 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-19 08:04:30,646 INFO L302 CfgBuilder]: Removed 13 assume(true) statements. [2023-11-19 08:04:30,661 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 08:04:30 BoogieIcfgContainer [2023-11-19 08:04:30,662 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-19 08:04:30,663 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-19 08:04:30,664 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-19 08:04:30,669 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-19 08:04:30,670 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 08:04:30,670 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 08:04:27" (1/3) ... [2023-11-19 08:04:30,672 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@24937303 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 08:04:30, skipping insertion in model container [2023-11-19 08:04:30,672 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 08:04:30,672 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 08:04:27" (2/3) ... [2023-11-19 08:04:30,673 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@24937303 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 08:04:30, skipping insertion in model container [2023-11-19 08:04:30,673 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 08:04:30,673 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 08:04:30" (3/3) ... [2023-11-19 08:04:30,675 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.09.cil.c [2023-11-19 08:04:30,791 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-19 08:04:30,791 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-19 08:04:30,791 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-19 08:04:30,791 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-19 08:04:30,792 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-19 08:04:30,792 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-19 08:04:30,792 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-19 08:04:30,792 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-19 08:04:30,808 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1112 states, 1111 states have (on average 1.5085508550855085) internal successors, (1676), 1111 states have internal predecessors, (1676), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:30,892 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 983 [2023-11-19 08:04:30,893 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:04:30,893 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:04:30,913 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:30,914 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:30,914 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-19 08:04:30,918 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1112 states, 1111 states have (on average 1.5085508550855085) internal successors, (1676), 1111 states have internal predecessors, (1676), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:30,942 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 983 [2023-11-19 08:04:30,943 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:04:30,943 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:04:30,950 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:30,951 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:30,962 INFO L748 eck$LassoCheckResult]: Stem: 138#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1013#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 813#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1008#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 733#L641true assume !(1 == ~m_i~0);~m_st~0 := 2; 786#L641-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 705#L646-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 495#L651-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 988#L656-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 333#L661-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 945#L666-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 869#L671-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 684#L676-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 382#L681-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 221#L686-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1102#L922true assume !(0 == ~M_E~0); 1041#L922-2true assume !(0 == ~T1_E~0); 1058#L927-1true assume !(0 == ~T2_E~0); 552#L932-1true assume !(0 == ~T3_E~0); 437#L937-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 494#L942-1true assume !(0 == ~T5_E~0); 736#L947-1true assume !(0 == ~T6_E~0); 556#L952-1true assume !(0 == ~T7_E~0); 627#L957-1true assume !(0 == ~T8_E~0); 982#L962-1true assume !(0 == ~T9_E~0); 420#L967-1true assume !(0 == ~E_1~0); 954#L972-1true assume !(0 == ~E_2~0); 715#L977-1true assume 0 == ~E_3~0;~E_3~0 := 1; 1050#L982-1true assume !(0 == ~E_4~0); 104#L987-1true assume !(0 == ~E_5~0); 107#L992-1true assume !(0 == ~E_6~0); 363#L997-1true assume !(0 == ~E_7~0); 900#L1002-1true assume !(0 == ~E_8~0); 354#L1007-1true assume !(0 == ~E_9~0); 6#L1012-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 891#L443true assume !(1 == ~m_pc~0); 571#L443-2true is_master_triggered_~__retres1~0#1 := 0; 562#L454true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 693#is_master_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 187#L1140true assume !(0 != activate_threads_~tmp~1#1); 55#L1140-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 914#L462true assume 1 == ~t1_pc~0; 459#L463true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 961#L473true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 579#L1148true assume !(0 != activate_threads_~tmp___0~0#1); 318#L1148-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 995#L481true assume !(1 == ~t2_pc~0); 790#L481-2true is_transmit2_triggered_~__retres1~2#1 := 0; 543#L492true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 255#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 234#L1156true assume !(0 != activate_threads_~tmp___1~0#1); 299#L1156-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1094#L500true assume 1 == ~t3_pc~0; 474#L501true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 754#L511true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 781#L1164true assume !(0 != activate_threads_~tmp___2~0#1); 7#L1164-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 766#L519true assume 1 == ~t4_pc~0; 154#L520true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 298#L530true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 206#L1172true assume !(0 != activate_threads_~tmp___3~0#1); 515#L1172-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87#L538true assume !(1 == ~t5_pc~0); 845#L538-2true is_transmit5_triggered_~__retres1~5#1 := 0; 36#L549true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 697#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 176#L1180true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 611#L1180-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1113#L557true assume 1 == ~t6_pc~0; 410#L558true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 824#L568true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 244#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 207#L1188true assume !(0 != activate_threads_~tmp___5~0#1); 948#L1188-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1065#L576true assume !(1 == ~t7_pc~0); 303#L576-2true is_transmit7_triggered_~__retres1~7#1 := 0; 409#L587true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1030#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1059#L1196true assume !(0 != activate_threads_~tmp___6~0#1); 670#L1196-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 257#L595true assume 1 == ~t8_pc~0; 1015#L596true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 700#L606true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 616#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 517#L1204true assume !(0 != activate_threads_~tmp___7~0#1); 952#L1204-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 151#L614true assume !(1 == ~t9_pc~0); 460#L614-2true is_transmit9_triggered_~__retres1~9#1 := 0; 99#L625true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 282#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 682#L1212true assume !(0 != activate_threads_~tmp___8~0#1); 236#L1212-2true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 425#L1025true assume !(1 == ~M_E~0); 473#L1025-2true assume !(1 == ~T1_E~0); 603#L1030-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 761#L1035-1true assume !(1 == ~T3_E~0); 230#L1040-1true assume !(1 == ~T4_E~0); 740#L1045-1true assume !(1 == ~T5_E~0); 181#L1050-1true assume !(1 == ~T6_E~0); 292#L1055-1true assume !(1 == ~T7_E~0); 92#L1060-1true assume !(1 == ~T8_E~0); 123#L1065-1true assume !(1 == ~T9_E~0); 966#L1070-1true assume 1 == ~E_1~0;~E_1~0 := 2; 557#L1075-1true assume !(1 == ~E_2~0); 1098#L1080-1true assume !(1 == ~E_3~0); 549#L1085-1true assume !(1 == ~E_4~0); 858#L1090-1true assume !(1 == ~E_5~0); 980#L1095-1true assume !(1 == ~E_6~0); 586#L1100-1true assume !(1 == ~E_7~0); 591#L1105-1true assume !(1 == ~E_8~0); 79#L1110-1true assume 1 == ~E_9~0;~E_9~0 := 2; 262#L1115-1true assume { :end_inline_reset_delta_events } true; 202#L1396-2true [2023-11-19 08:04:30,966 INFO L750 eck$LassoCheckResult]: Loop: 202#L1396-2true assume !false; 967#L1397true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 946#L897-1true assume false; 621#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 387#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 349#L922-3true assume 0 == ~M_E~0;~M_E~0 := 1; 987#L922-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 172#L927-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 277#L932-3true assume !(0 == ~T3_E~0); 547#L937-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 75#L942-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 632#L947-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 278#L952-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 826#L957-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 850#L962-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 645#L967-3true assume 0 == ~E_1~0;~E_1~0 := 1; 875#L972-3true assume !(0 == ~E_2~0); 551#L977-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1101#L982-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1074#L987-3true assume 0 == ~E_5~0;~E_5~0 := 1; 243#L992-3true assume 0 == ~E_6~0;~E_6~0 := 1; 369#L997-3true assume 0 == ~E_7~0;~E_7~0 := 1; 241#L1002-3true assume 0 == ~E_8~0;~E_8~0 := 1; 507#L1007-3true assume 0 == ~E_9~0;~E_9~0 := 1; 93#L1012-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 269#L443-30true assume !(1 == ~m_pc~0); 691#L443-32true is_master_triggered_~__retres1~0#1 := 0; 260#L454-10true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 265#is_master_triggered_returnLabel#11true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 964#L1140-30true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 721#L1140-32true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 339#L462-30true assume 1 == ~t1_pc~0; 225#L463-10true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 711#L473-10true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 435#is_transmit1_triggered_returnLabel#11true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 757#L1148-30true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1079#L1148-32true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 329#L481-30true assume !(1 == ~t2_pc~0); 726#L481-32true is_transmit2_triggered_~__retres1~2#1 := 0; 679#L492-10true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 204#is_transmit2_triggered_returnLabel#11true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 140#L1156-30true assume !(0 != activate_threads_~tmp___1~0#1); 302#L1156-32true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 567#L500-30true assume !(1 == ~t3_pc~0); 1080#L500-32true is_transmit3_triggered_~__retres1~3#1 := 0; 371#L511-10true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 414#is_transmit3_triggered_returnLabel#11true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1040#L1164-30true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 290#L1164-32true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 651#L519-30true assume !(1 == ~t4_pc~0); 433#L519-32true is_transmit4_triggered_~__retres1~4#1 := 0; 415#L530-10true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 919#is_transmit4_triggered_returnLabel#11true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 422#L1172-30true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 533#L1172-32true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 943#L538-30true assume 1 == ~t5_pc~0; 98#L539-10true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 280#L549-10true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 522#is_transmit5_triggered_returnLabel#11true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 674#L1180-30true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 137#L1180-32true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 143#L557-30true assume 1 == ~t6_pc~0; 2#L558-10true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 399#L568-10true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58#is_transmit6_triggered_returnLabel#11true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1056#L1188-30true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 150#L1188-32true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 525#L576-30true assume 1 == ~t7_pc~0; 1044#L577-10true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 393#L587-10true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 578#is_transmit7_triggered_returnLabel#11true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 855#L1196-30true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 231#L1196-32true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 211#L595-30true assume !(1 == ~t8_pc~0); 772#L595-32true is_transmit8_triggered_~__retres1~8#1 := 0; 178#L606-10true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1071#is_transmit8_triggered_returnLabel#11true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 856#L1204-30true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1104#L1204-32true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 958#L614-30true assume !(1 == ~t9_pc~0); 788#L614-32true is_transmit9_triggered_~__retres1~9#1 := 0; 653#L625-10true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19#is_transmit9_triggered_returnLabel#11true activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 94#L1212-30true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 625#L1212-32true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 508#L1025-3true assume 1 == ~M_E~0;~M_E~0 := 2; 321#L1025-5true assume !(1 == ~T1_E~0); 476#L1030-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 876#L1035-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1033#L1040-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1052#L1045-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 864#L1050-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 698#L1055-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 40#L1060-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 732#L1065-3true assume !(1 == ~T9_E~0); 723#L1070-3true assume 1 == ~E_1~0;~E_1~0 := 2; 536#L1075-3true assume 1 == ~E_2~0;~E_2~0 := 2; 877#L1080-3true assume 1 == ~E_3~0;~E_3~0 := 2; 959#L1085-3true assume 1 == ~E_4~0;~E_4~0 := 2; 708#L1090-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1019#L1095-3true assume 1 == ~E_6~0;~E_6~0 := 2; 738#L1100-3true assume 1 == ~E_7~0;~E_7~0 := 2; 932#L1105-3true assume !(1 == ~E_8~0); 116#L1110-3true assume 1 == ~E_9~0;~E_9~0 := 2; 793#L1115-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 769#L699-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 120#L751-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 222#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 720#L1415true assume !(0 == start_simulation_~tmp~3#1); 419#L1415-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 986#L699-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 423#L751-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 24#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1090#L1370true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1075#L1377true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 411#stop_simulation_returnLabel#1true start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 160#L1428true assume !(0 != start_simulation_~tmp___0~1#1); 202#L1396-2true [2023-11-19 08:04:30,974 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:30,975 INFO L85 PathProgramCache]: Analyzing trace with hash 1400170149, now seen corresponding path program 1 times [2023-11-19 08:04:30,985 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:30,986 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1775391057] [2023-11-19 08:04:30,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:30,987 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:31,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:31,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:31,405 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:31,405 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1775391057] [2023-11-19 08:04:31,406 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1775391057] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:31,406 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:31,407 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:31,409 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1153234719] [2023-11-19 08:04:31,409 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:31,417 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:04:31,421 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:31,421 INFO L85 PathProgramCache]: Analyzing trace with hash -541420616, now seen corresponding path program 1 times [2023-11-19 08:04:31,421 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:31,422 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1199788743] [2023-11-19 08:04:31,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:31,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:31,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:31,522 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:31,522 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:31,522 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1199788743] [2023-11-19 08:04:31,523 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1199788743] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:31,523 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:31,523 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 08:04:31,524 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2127210313] [2023-11-19 08:04:31,524 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:31,529 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:04:31,530 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:04:31,572 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:04:31,573 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:04:31,579 INFO L87 Difference]: Start difference. First operand has 1112 states, 1111 states have (on average 1.5085508550855085) internal successors, (1676), 1111 states have internal predecessors, (1676), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:31,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:04:31,698 INFO L93 Difference]: Finished difference Result 1110 states and 1646 transitions. [2023-11-19 08:04:31,699 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1110 states and 1646 transitions. [2023-11-19 08:04:31,716 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-19 08:04:31,737 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1110 states to 1104 states and 1640 transitions. [2023-11-19 08:04:31,738 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2023-11-19 08:04:31,741 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2023-11-19 08:04:31,742 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1640 transitions. [2023-11-19 08:04:31,749 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:04:31,749 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1640 transitions. [2023-11-19 08:04:31,778 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1640 transitions. [2023-11-19 08:04:31,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2023-11-19 08:04:31,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.4855072463768115) internal successors, (1640), 1103 states have internal predecessors, (1640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:31,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1640 transitions. [2023-11-19 08:04:31,849 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1640 transitions. [2023-11-19 08:04:31,859 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:04:31,863 INFO L428 stractBuchiCegarLoop]: Abstraction has 1104 states and 1640 transitions. [2023-11-19 08:04:31,864 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-19 08:04:31,864 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1640 transitions. [2023-11-19 08:04:31,874 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-19 08:04:31,874 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:04:31,874 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:04:31,878 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:31,879 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:31,879 INFO L748 eck$LassoCheckResult]: Stem: 2514#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 2515#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3273#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3274#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3225#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 3226#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3208#L646-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3030#L651-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3031#L656-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2839#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2840#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3294#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3200#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2899#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2670#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2671#L922 assume !(0 == ~M_E~0); 3331#L922-2 assume !(0 == ~T1_E~0); 3332#L927-1 assume !(0 == ~T2_E~0); 3094#L932-1 assume !(0 == ~T3_E~0); 2969#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2970#L942-1 assume !(0 == ~T5_E~0); 3029#L947-1 assume !(0 == ~T6_E~0); 3098#L952-1 assume !(0 == ~T7_E~0); 3099#L957-1 assume !(0 == ~T8_E~0); 3156#L962-1 assume !(0 == ~T9_E~0); 2948#L967-1 assume !(0 == ~E_1~0); 2949#L972-1 assume !(0 == ~E_2~0); 3212#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 3213#L982-1 assume !(0 == ~E_4~0); 2447#L987-1 assume !(0 == ~E_5~0); 2448#L992-1 assume !(0 == ~E_6~0); 2454#L997-1 assume !(0 == ~E_7~0); 2875#L1002-1 assume !(0 == ~E_8~0); 2864#L1007-1 assume !(0 == ~E_9~0); 2241#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2242#L443 assume !(1 == ~m_pc~0); 3114#L443-2 is_master_triggered_~__retres1~0#1 := 0; 3106#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3107#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2609#L1140 assume !(0 != activate_threads_~tmp~1#1); 2346#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2347#L462 assume 1 == ~t1_pc~0; 2995#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2961#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2283#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2284#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 2818#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2819#L481 assume !(1 == ~t2_pc~0); 2603#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2602#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2729#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2693#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 2694#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2786#L500 assume 1 == ~t3_pc~0; 3014#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3015#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2248#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2249#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 2243#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2244#L519 assume 1 == ~t4_pc~0; 2546#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2547#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2348#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2349#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 2643#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2410#L538 assume !(1 == ~t5_pc~0); 2411#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2308#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2309#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2589#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2590#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3141#L557 assume 1 == ~t6_pc~0; 2936#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2624#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2711#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2644#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 2645#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3318#L576 assume !(1 == ~t7_pc~0); 2613#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2614#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2935#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3328#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 3192#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2730#L595 assume 1 == ~t8_pc~0; 2731#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3205#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3146#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3053#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 3054#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2539#L614 assume !(1 == ~t9_pc~0); 2540#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2436#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2437#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2762#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 2696#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2697#L1025 assume !(1 == ~M_E~0); 2955#L1025-2 assume !(1 == ~T1_E~0); 3013#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3136#L1035-1 assume !(1 == ~T3_E~0); 2689#L1040-1 assume !(1 == ~T4_E~0); 2690#L1045-1 assume !(1 == ~T5_E~0); 2599#L1050-1 assume !(1 == ~T6_E~0); 2600#L1055-1 assume !(1 == ~T7_E~0); 2421#L1060-1 assume !(1 == ~T8_E~0); 2422#L1065-1 assume !(1 == ~T9_E~0); 2486#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3100#L1075-1 assume !(1 == ~E_2~0); 3101#L1080-1 assume !(1 == ~E_3~0); 3089#L1085-1 assume !(1 == ~E_4~0); 3090#L1090-1 assume !(1 == ~E_5~0); 3289#L1095-1 assume !(1 == ~E_6~0); 3123#L1100-1 assume !(1 == ~E_7~0); 3124#L1105-1 assume !(1 == ~E_8~0); 2392#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 2393#L1115-1 assume { :end_inline_reset_delta_events } true; 2558#L1396-2 [2023-11-19 08:04:31,880 INFO L750 eck$LassoCheckResult]: Loop: 2558#L1396-2 assume !false; 2635#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3293#L897-1 assume !false; 3316#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3227#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2266#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2267#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2750#L766 assume !(0 != eval_~tmp~0#1); 3151#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2905#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2857#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2858#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2581#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2582#L932-3 assume !(0 == ~T3_E~0); 2755#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2384#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2385#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2756#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2757#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3278#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3173#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3174#L972-3 assume !(0 == ~E_2~0); 3092#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3093#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3333#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2709#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2710#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2704#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2705#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2423#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2424#L443-30 assume 1 == ~m_pc~0; 2457#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2458#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2736#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2741#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3216#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2846#L462-30 assume 1 == ~t1_pc~0; 2678#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2679#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2965#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2966#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3241#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2831#L481-30 assume 1 == ~t2_pc~0; 2549#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2550#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2639#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2518#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 2519#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2791#L500-30 assume 1 == ~t3_pc~0; 2554#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2555#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2884#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2940#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2775#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2776#L519-30 assume !(1 == ~t4_pc~0); 2964#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2941#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2942#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2952#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2953#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3072#L538-30 assume 1 == ~t5_pc~0; 2432#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2433#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2759#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3059#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2512#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2513#L557-30 assume 1 == ~t6_pc~0; 2231#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2233#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2352#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2353#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2537#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2538#L576-30 assume !(1 == ~t7_pc~0); 2306#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2307#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2914#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3121#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2688#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2652#L595-30 assume !(1 == ~t8_pc~0); 2653#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2591#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2592#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3287#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3288#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3319#L614-30 assume 1 == ~t9_pc~0; 2595#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2596#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2270#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2271#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2425#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3046#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2820#L1025-5 assume !(1 == ~T1_E~0); 2821#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3018#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3297#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3329#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3292#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3204#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2316#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2317#L1065-3 assume !(1 == ~T9_E~0); 3218#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3075#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3076#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3298#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3209#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3210#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3229#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3230#L1105-3 assume !(1 == ~E_8~0); 2471#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2472#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3245#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2327#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2480#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2672#L1415 assume !(0 == start_simulation_~tmp~3#1); 2945#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2946#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2380#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2281#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2282#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3334#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2937#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2557#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 2558#L1396-2 [2023-11-19 08:04:31,882 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:31,882 INFO L85 PathProgramCache]: Analyzing trace with hash -1247434205, now seen corresponding path program 1 times [2023-11-19 08:04:31,883 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:31,883 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [744791803] [2023-11-19 08:04:31,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:31,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:31,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:32,031 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:32,031 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:32,031 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [744791803] [2023-11-19 08:04:32,032 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [744791803] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:32,032 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:32,032 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:32,032 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1734893102] [2023-11-19 08:04:32,033 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:32,033 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:04:32,034 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:32,034 INFO L85 PathProgramCache]: Analyzing trace with hash -2034235564, now seen corresponding path program 1 times [2023-11-19 08:04:32,034 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:32,035 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1429588318] [2023-11-19 08:04:32,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:32,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:32,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:32,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:32,229 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:32,229 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1429588318] [2023-11-19 08:04:32,229 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1429588318] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:32,230 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:32,230 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:32,230 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [315994907] [2023-11-19 08:04:32,230 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:32,231 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:04:32,231 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:04:32,232 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:04:32,232 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:04:32,233 INFO L87 Difference]: Start difference. First operand 1104 states and 1640 transitions. cyclomatic complexity: 537 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:32,267 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:04:32,267 INFO L93 Difference]: Finished difference Result 1104 states and 1639 transitions. [2023-11-19 08:04:32,267 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1639 transitions. [2023-11-19 08:04:32,281 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-19 08:04:32,293 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1639 transitions. [2023-11-19 08:04:32,293 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2023-11-19 08:04:32,295 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2023-11-19 08:04:32,295 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1639 transitions. [2023-11-19 08:04:32,298 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:04:32,298 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1639 transitions. [2023-11-19 08:04:32,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1639 transitions. [2023-11-19 08:04:32,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2023-11-19 08:04:32,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.4846014492753623) internal successors, (1639), 1103 states have internal predecessors, (1639), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:32,330 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1639 transitions. [2023-11-19 08:04:32,330 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1639 transitions. [2023-11-19 08:04:32,331 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:04:32,332 INFO L428 stractBuchiCegarLoop]: Abstraction has 1104 states and 1639 transitions. [2023-11-19 08:04:32,332 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-19 08:04:32,332 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1639 transitions. [2023-11-19 08:04:32,342 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-19 08:04:32,342 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:04:32,342 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:04:32,345 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:32,345 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:32,346 INFO L748 eck$LassoCheckResult]: Stem: 4729#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 4730#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 5488#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5489#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5440#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 5441#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5423#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5245#L651-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5246#L656-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5054#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5055#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5509#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5415#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5114#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4885#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4886#L922 assume !(0 == ~M_E~0); 5546#L922-2 assume !(0 == ~T1_E~0); 5547#L927-1 assume !(0 == ~T2_E~0); 5309#L932-1 assume !(0 == ~T3_E~0); 5184#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5185#L942-1 assume !(0 == ~T5_E~0); 5244#L947-1 assume !(0 == ~T6_E~0); 5313#L952-1 assume !(0 == ~T7_E~0); 5314#L957-1 assume !(0 == ~T8_E~0); 5373#L962-1 assume !(0 == ~T9_E~0); 5163#L967-1 assume !(0 == ~E_1~0); 5164#L972-1 assume !(0 == ~E_2~0); 5427#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5428#L982-1 assume !(0 == ~E_4~0); 4662#L987-1 assume !(0 == ~E_5~0); 4663#L992-1 assume !(0 == ~E_6~0); 4669#L997-1 assume !(0 == ~E_7~0); 5090#L1002-1 assume !(0 == ~E_8~0); 5079#L1007-1 assume !(0 == ~E_9~0); 4456#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4457#L443 assume !(1 == ~m_pc~0); 5329#L443-2 is_master_triggered_~__retres1~0#1 := 0; 5321#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5322#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4824#L1140 assume !(0 != activate_threads_~tmp~1#1); 4561#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4562#L462 assume 1 == ~t1_pc~0; 5210#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5176#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4498#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4499#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 5033#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5034#L481 assume !(1 == ~t2_pc~0); 4818#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4817#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4944#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4908#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 4909#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5003#L500 assume 1 == ~t3_pc~0; 5229#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5230#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4463#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4464#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 4458#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4459#L519 assume 1 == ~t4_pc~0; 4761#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4762#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4563#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4564#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 4860#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4625#L538 assume !(1 == ~t5_pc~0); 4626#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4523#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4524#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4804#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4805#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5358#L557 assume 1 == ~t6_pc~0; 5151#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4839#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4926#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4861#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 4862#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5533#L576 assume !(1 == ~t7_pc~0); 4828#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4829#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5150#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5543#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 5407#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4945#L595 assume 1 == ~t8_pc~0; 4946#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5420#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5361#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5268#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 5269#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4754#L614 assume !(1 == ~t9_pc~0); 4755#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4651#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4652#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4977#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 4911#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4912#L1025 assume !(1 == ~M_E~0); 5170#L1025-2 assume !(1 == ~T1_E~0); 5228#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5351#L1035-1 assume !(1 == ~T3_E~0); 4904#L1040-1 assume !(1 == ~T4_E~0); 4905#L1045-1 assume !(1 == ~T5_E~0); 4814#L1050-1 assume !(1 == ~T6_E~0); 4815#L1055-1 assume !(1 == ~T7_E~0); 4636#L1060-1 assume !(1 == ~T8_E~0); 4637#L1065-1 assume !(1 == ~T9_E~0); 4701#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5315#L1075-1 assume !(1 == ~E_2~0); 5316#L1080-1 assume !(1 == ~E_3~0); 5304#L1085-1 assume !(1 == ~E_4~0); 5305#L1090-1 assume !(1 == ~E_5~0); 5504#L1095-1 assume !(1 == ~E_6~0); 5338#L1100-1 assume !(1 == ~E_7~0); 5339#L1105-1 assume !(1 == ~E_8~0); 4607#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 4608#L1115-1 assume { :end_inline_reset_delta_events } true; 4773#L1396-2 [2023-11-19 08:04:32,347 INFO L750 eck$LassoCheckResult]: Loop: 4773#L1396-2 assume !false; 4850#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5508#L897-1 assume !false; 5531#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5442#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4481#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4482#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4965#L766 assume !(0 != eval_~tmp~0#1); 5366#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5120#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5072#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5073#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4796#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4797#L932-3 assume !(0 == ~T3_E~0); 4970#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4599#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4600#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4971#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4972#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5493#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5388#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5389#L972-3 assume !(0 == ~E_2~0); 5307#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5308#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5548#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4924#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4925#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4922#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4923#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4638#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4639#L443-30 assume 1 == ~m_pc~0; 4672#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4673#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4951#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4956#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5431#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5061#L462-30 assume !(1 == ~t1_pc~0); 4897#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 4896#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5180#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5181#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5456#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5046#L481-30 assume 1 == ~t2_pc~0; 4764#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4765#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4854#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4733#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 4734#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5006#L500-30 assume 1 == ~t3_pc~0; 4769#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4770#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5099#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5155#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4991#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4992#L519-30 assume 1 == ~t4_pc~0; 5344#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5156#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5157#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5167#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5168#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5287#L538-30 assume 1 == ~t5_pc~0; 4647#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4648#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4973#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5273#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4727#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4728#L557-30 assume 1 == ~t6_pc~0; 4446#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4448#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4567#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4568#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4752#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4753#L576-30 assume !(1 == ~t7_pc~0); 4516#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 4517#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5129#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5335#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4903#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4867#L595-30 assume !(1 == ~t8_pc~0); 4868#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 4806#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4807#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5502#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5503#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5534#L614-30 assume 1 == ~t9_pc~0; 4810#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4811#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4485#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4486#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4640#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5261#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5035#L1025-5 assume !(1 == ~T1_E~0); 5036#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5233#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5512#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5544#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5507#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5419#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4531#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4532#L1065-3 assume !(1 == ~T9_E~0); 5433#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5290#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5291#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5513#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5424#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5425#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5444#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5445#L1105-3 assume !(1 == ~E_8~0); 4686#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4687#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5461#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4542#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4695#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 4887#L1415 assume !(0 == start_simulation_~tmp~3#1); 5160#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5161#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4595#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4496#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 4497#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5549#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5152#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 4772#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 4773#L1396-2 [2023-11-19 08:04:32,347 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:32,348 INFO L85 PathProgramCache]: Analyzing trace with hash -208849631, now seen corresponding path program 1 times [2023-11-19 08:04:32,348 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:32,348 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1176936180] [2023-11-19 08:04:32,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:32,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:32,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:32,440 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:32,440 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:32,440 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1176936180] [2023-11-19 08:04:32,441 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1176936180] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:32,441 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:32,441 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:32,441 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [630891419] [2023-11-19 08:04:32,442 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:32,442 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:04:32,443 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:32,443 INFO L85 PathProgramCache]: Analyzing trace with hash 1344839060, now seen corresponding path program 1 times [2023-11-19 08:04:32,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:32,443 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [220776487] [2023-11-19 08:04:32,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:32,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:32,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:32,608 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:32,608 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:32,608 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [220776487] [2023-11-19 08:04:32,609 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [220776487] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:32,609 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:32,609 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:32,610 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [802863919] [2023-11-19 08:04:32,610 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:32,611 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:04:32,611 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:04:32,612 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:04:32,612 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:04:32,612 INFO L87 Difference]: Start difference. First operand 1104 states and 1639 transitions. cyclomatic complexity: 536 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:32,658 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:04:32,659 INFO L93 Difference]: Finished difference Result 1104 states and 1638 transitions. [2023-11-19 08:04:32,659 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1638 transitions. [2023-11-19 08:04:32,674 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-19 08:04:32,688 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1638 transitions. [2023-11-19 08:04:32,688 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2023-11-19 08:04:32,690 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2023-11-19 08:04:32,690 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1638 transitions. [2023-11-19 08:04:32,693 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:04:32,693 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1638 transitions. [2023-11-19 08:04:32,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1638 transitions. [2023-11-19 08:04:32,718 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2023-11-19 08:04:32,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.483695652173913) internal successors, (1638), 1103 states have internal predecessors, (1638), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:32,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1638 transitions. [2023-11-19 08:04:32,730 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1638 transitions. [2023-11-19 08:04:32,731 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:04:32,732 INFO L428 stractBuchiCegarLoop]: Abstraction has 1104 states and 1638 transitions. [2023-11-19 08:04:32,732 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-19 08:04:32,733 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1638 transitions. [2023-11-19 08:04:32,744 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-19 08:04:32,744 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:04:32,744 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:04:32,747 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:32,747 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:32,748 INFO L748 eck$LassoCheckResult]: Stem: 6946#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 6947#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 7703#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7704#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7655#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 7656#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7638#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7460#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7461#L656-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7269#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7270#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7725#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7630#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7329#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7100#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7101#L922 assume !(0 == ~M_E~0); 7761#L922-2 assume !(0 == ~T1_E~0); 7762#L927-1 assume !(0 == ~T2_E~0); 7524#L932-1 assume !(0 == ~T3_E~0); 7399#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7400#L942-1 assume !(0 == ~T5_E~0); 7459#L947-1 assume !(0 == ~T6_E~0); 7528#L952-1 assume !(0 == ~T7_E~0); 7529#L957-1 assume !(0 == ~T8_E~0); 7588#L962-1 assume !(0 == ~T9_E~0); 7378#L967-1 assume !(0 == ~E_1~0); 7379#L972-1 assume !(0 == ~E_2~0); 7642#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 7643#L982-1 assume !(0 == ~E_4~0); 6877#L987-1 assume !(0 == ~E_5~0); 6878#L992-1 assume !(0 == ~E_6~0); 6884#L997-1 assume !(0 == ~E_7~0); 7307#L1002-1 assume !(0 == ~E_8~0); 7294#L1007-1 assume !(0 == ~E_9~0); 6671#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6672#L443 assume !(1 == ~m_pc~0); 7544#L443-2 is_master_triggered_~__retres1~0#1 := 0; 7536#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7537#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7039#L1140 assume !(0 != activate_threads_~tmp~1#1); 6776#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6777#L462 assume 1 == ~t1_pc~0; 7425#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7392#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6713#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6714#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 7248#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7249#L481 assume !(1 == ~t2_pc~0); 7033#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7032#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7159#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7123#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 7124#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7218#L500 assume 1 == ~t3_pc~0; 7444#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7445#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6678#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6679#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 6676#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6677#L519 assume 1 == ~t4_pc~0; 6976#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6977#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6778#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6779#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 7075#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6840#L538 assume !(1 == ~t5_pc~0); 6841#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6738#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6739#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7019#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7020#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7573#L557 assume 1 == ~t6_pc~0; 7366#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7054#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7141#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7076#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 7077#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7748#L576 assume !(1 == ~t7_pc~0); 7043#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 7044#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7365#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7758#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 7622#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7160#L595 assume 1 == ~t8_pc~0; 7161#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7635#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7576#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7483#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 7484#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6969#L614 assume !(1 == ~t9_pc~0); 6970#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 6866#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6867#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7192#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 7126#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7127#L1025 assume !(1 == ~M_E~0); 7385#L1025-2 assume !(1 == ~T1_E~0); 7443#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7566#L1035-1 assume !(1 == ~T3_E~0); 7119#L1040-1 assume !(1 == ~T4_E~0); 7120#L1045-1 assume !(1 == ~T5_E~0); 7029#L1050-1 assume !(1 == ~T6_E~0); 7030#L1055-1 assume !(1 == ~T7_E~0); 6851#L1060-1 assume !(1 == ~T8_E~0); 6852#L1065-1 assume !(1 == ~T9_E~0); 6916#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7531#L1075-1 assume !(1 == ~E_2~0); 7532#L1080-1 assume !(1 == ~E_3~0); 7519#L1085-1 assume !(1 == ~E_4~0); 7520#L1090-1 assume !(1 == ~E_5~0); 7719#L1095-1 assume !(1 == ~E_6~0); 7553#L1100-1 assume !(1 == ~E_7~0); 7554#L1105-1 assume !(1 == ~E_8~0); 6822#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 6823#L1115-1 assume { :end_inline_reset_delta_events } true; 6988#L1396-2 [2023-11-19 08:04:32,749 INFO L750 eck$LassoCheckResult]: Loop: 6988#L1396-2 assume !false; 7065#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7723#L897-1 assume !false; 7746#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7657#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 6696#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 6697#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7180#L766 assume !(0 != eval_~tmp~0#1); 7581#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7335#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7289#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7290#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7011#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7012#L932-3 assume !(0 == ~T3_E~0); 7185#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6814#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6815#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7186#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7187#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7708#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7603#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7604#L972-3 assume !(0 == ~E_2~0); 7522#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7523#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7763#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7139#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7140#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7137#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7138#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6853#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6854#L443-30 assume 1 == ~m_pc~0; 6887#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6888#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7166#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7171#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7647#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7276#L462-30 assume 1 == ~t1_pc~0; 7110#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7111#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7395#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7396#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7671#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7261#L481-30 assume 1 == ~t2_pc~0; 6979#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6980#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7069#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6948#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 6949#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7221#L500-30 assume 1 == ~t3_pc~0; 6984#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6985#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7314#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7370#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7205#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7206#L519-30 assume 1 == ~t4_pc~0; 7558#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7371#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7372#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7382#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7383#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7502#L538-30 assume !(1 == ~t5_pc~0); 6864#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 6863#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7188#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7488#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6942#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6943#L557-30 assume 1 == ~t6_pc~0; 6661#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6663#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6782#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6783#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6967#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6968#L576-30 assume 1 == ~t7_pc~0; 7492#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6735#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7344#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7550#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7118#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7082#L595-30 assume !(1 == ~t8_pc~0); 7083#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 7023#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7024#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7717#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7718#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7749#L614-30 assume 1 == ~t9_pc~0; 7026#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7027#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6700#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6701#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6855#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7476#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7250#L1025-5 assume !(1 == ~T1_E~0); 7251#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7448#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7727#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7759#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7722#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7634#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6746#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6747#L1065-3 assume !(1 == ~T9_E~0); 7648#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7505#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7506#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7728#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7639#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7640#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7659#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7660#L1105-3 assume !(1 == ~E_8~0); 6901#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6902#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7676#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 6757#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 6910#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 7102#L1415 assume !(0 == start_simulation_~tmp~3#1); 7376#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7377#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 6810#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 6711#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 6712#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7764#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7367#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 6987#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 6988#L1396-2 [2023-11-19 08:04:32,750 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:32,750 INFO L85 PathProgramCache]: Analyzing trace with hash 1764315747, now seen corresponding path program 1 times [2023-11-19 08:04:32,750 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:32,751 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1904889903] [2023-11-19 08:04:32,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:32,751 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:32,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:32,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:32,818 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:32,819 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1904889903] [2023-11-19 08:04:32,819 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1904889903] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:32,819 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:32,820 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:32,820 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1630181290] [2023-11-19 08:04:32,820 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:32,821 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:04:32,821 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:32,821 INFO L85 PathProgramCache]: Analyzing trace with hash -321985611, now seen corresponding path program 1 times [2023-11-19 08:04:32,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:32,822 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [402570719] [2023-11-19 08:04:32,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:32,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:32,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:32,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:32,909 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:32,909 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [402570719] [2023-11-19 08:04:32,910 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [402570719] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:32,910 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:32,910 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:32,910 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1681526648] [2023-11-19 08:04:32,910 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:32,911 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:04:32,911 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:04:32,912 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:04:32,912 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:04:32,912 INFO L87 Difference]: Start difference. First operand 1104 states and 1638 transitions. cyclomatic complexity: 535 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:32,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:04:32,951 INFO L93 Difference]: Finished difference Result 1104 states and 1637 transitions. [2023-11-19 08:04:32,951 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1637 transitions. [2023-11-19 08:04:32,963 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-19 08:04:32,974 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1637 transitions. [2023-11-19 08:04:32,974 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2023-11-19 08:04:32,976 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2023-11-19 08:04:32,976 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1637 transitions. [2023-11-19 08:04:32,978 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:04:32,978 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1637 transitions. [2023-11-19 08:04:32,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1637 transitions. [2023-11-19 08:04:32,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2023-11-19 08:04:32,998 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.4827898550724639) internal successors, (1637), 1103 states have internal predecessors, (1637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:33,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1637 transitions. [2023-11-19 08:04:33,004 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1637 transitions. [2023-11-19 08:04:33,004 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:04:33,005 INFO L428 stractBuchiCegarLoop]: Abstraction has 1104 states and 1637 transitions. [2023-11-19 08:04:33,005 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-19 08:04:33,005 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1637 transitions. [2023-11-19 08:04:33,013 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-19 08:04:33,013 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:04:33,014 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:04:33,016 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:33,016 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:33,016 INFO L748 eck$LassoCheckResult]: Stem: 9161#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 9162#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 9918#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9919#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9870#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 9871#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9853#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9675#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9676#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9484#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9485#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9940#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9845#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9544#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9315#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9316#L922 assume !(0 == ~M_E~0); 9976#L922-2 assume !(0 == ~T1_E~0); 9977#L927-1 assume !(0 == ~T2_E~0); 9739#L932-1 assume !(0 == ~T3_E~0); 9614#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9615#L942-1 assume !(0 == ~T5_E~0); 9674#L947-1 assume !(0 == ~T6_E~0); 9743#L952-1 assume !(0 == ~T7_E~0); 9744#L957-1 assume !(0 == ~T8_E~0); 9803#L962-1 assume !(0 == ~T9_E~0); 9593#L967-1 assume !(0 == ~E_1~0); 9594#L972-1 assume !(0 == ~E_2~0); 9857#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 9858#L982-1 assume !(0 == ~E_4~0); 9092#L987-1 assume !(0 == ~E_5~0); 9093#L992-1 assume !(0 == ~E_6~0); 9099#L997-1 assume !(0 == ~E_7~0); 9522#L1002-1 assume !(0 == ~E_8~0); 9509#L1007-1 assume !(0 == ~E_9~0); 8886#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8887#L443 assume !(1 == ~m_pc~0); 9759#L443-2 is_master_triggered_~__retres1~0#1 := 0; 9751#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9752#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9254#L1140 assume !(0 != activate_threads_~tmp~1#1); 8991#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8992#L462 assume 1 == ~t1_pc~0; 9640#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9609#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8930#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8931#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 9463#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9464#L481 assume !(1 == ~t2_pc~0); 9248#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9247#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9374#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9338#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 9339#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9433#L500 assume 1 == ~t3_pc~0; 9659#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9660#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8893#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8894#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 8891#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8892#L519 assume 1 == ~t4_pc~0; 9194#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9195#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8993#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8994#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 9290#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9055#L538 assume !(1 == ~t5_pc~0); 9056#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8953#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8954#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9234#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9235#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9788#L557 assume 1 == ~t6_pc~0; 9581#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9269#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9356#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9291#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 9292#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9963#L576 assume !(1 == ~t7_pc~0); 9258#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 9259#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9580#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9973#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 9837#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9377#L595 assume 1 == ~t8_pc~0; 9378#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9850#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9791#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9698#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 9699#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9184#L614 assume !(1 == ~t9_pc~0); 9185#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 9081#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9082#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9407#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 9341#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9342#L1025 assume !(1 == ~M_E~0); 9600#L1025-2 assume !(1 == ~T1_E~0); 9658#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9781#L1035-1 assume !(1 == ~T3_E~0); 9334#L1040-1 assume !(1 == ~T4_E~0); 9335#L1045-1 assume !(1 == ~T5_E~0); 9244#L1050-1 assume !(1 == ~T6_E~0); 9245#L1055-1 assume !(1 == ~T7_E~0); 9066#L1060-1 assume !(1 == ~T8_E~0); 9067#L1065-1 assume !(1 == ~T9_E~0); 9131#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9746#L1075-1 assume !(1 == ~E_2~0); 9747#L1080-1 assume !(1 == ~E_3~0); 9734#L1085-1 assume !(1 == ~E_4~0); 9735#L1090-1 assume !(1 == ~E_5~0); 9934#L1095-1 assume !(1 == ~E_6~0); 9768#L1100-1 assume !(1 == ~E_7~0); 9769#L1105-1 assume !(1 == ~E_8~0); 9037#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 9038#L1115-1 assume { :end_inline_reset_delta_events } true; 9203#L1396-2 [2023-11-19 08:04:33,017 INFO L750 eck$LassoCheckResult]: Loop: 9203#L1396-2 assume !false; 9283#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9938#L897-1 assume !false; 9961#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9872#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 8911#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 8912#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9395#L766 assume !(0 != eval_~tmp~0#1); 9797#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9552#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9504#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9505#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9226#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9227#L932-3 assume !(0 == ~T3_E~0); 9400#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9029#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9030#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9401#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9402#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9923#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9818#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9819#L972-3 assume !(0 == ~E_2~0); 9737#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9738#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9978#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9354#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9355#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9352#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9353#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9068#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9069#L443-30 assume !(1 == ~m_pc~0); 9104#L443-32 is_master_triggered_~__retres1~0#1 := 0; 9103#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9381#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9386#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9861#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9491#L462-30 assume 1 == ~t1_pc~0; 9323#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9324#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9610#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9611#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9886#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9476#L481-30 assume 1 == ~t2_pc~0; 9191#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9192#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9284#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9163#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 9164#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9436#L500-30 assume !(1 == ~t3_pc~0); 9201#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 9200#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9529#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9585#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9420#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9421#L519-30 assume !(1 == ~t4_pc~0); 9607#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 9586#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9587#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9597#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9598#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9717#L538-30 assume 1 == ~t5_pc~0; 9077#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9078#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9403#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9703#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9157#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9158#L557-30 assume 1 == ~t6_pc~0; 8876#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8878#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8997#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8998#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9182#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9183#L576-30 assume !(1 == ~t7_pc~0); 8949#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 8950#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9559#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9766#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9333#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9297#L595-30 assume !(1 == ~t8_pc~0); 9298#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 9238#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9239#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9932#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9933#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9964#L614-30 assume 1 == ~t9_pc~0; 9241#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9242#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8915#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8916#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9070#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9691#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9465#L1025-5 assume !(1 == ~T1_E~0); 9466#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9663#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9942#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9974#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9937#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9849#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8961#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8962#L1065-3 assume !(1 == ~T9_E~0); 9863#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9720#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9721#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9943#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9854#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9855#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9874#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9875#L1105-3 assume !(1 == ~E_8~0); 9116#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9117#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9891#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 8972#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9125#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 9317#L1415 assume !(0 == start_simulation_~tmp~3#1); 9591#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9592#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9025#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 8926#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 8927#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9979#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9582#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 9202#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 9203#L1396-2 [2023-11-19 08:04:33,018 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:33,018 INFO L85 PathProgramCache]: Analyzing trace with hash -388791071, now seen corresponding path program 1 times [2023-11-19 08:04:33,018 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:33,019 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1132761797] [2023-11-19 08:04:33,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:33,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:33,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:33,067 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:33,067 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:33,067 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1132761797] [2023-11-19 08:04:33,068 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1132761797] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:33,068 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:33,068 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:33,068 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [598797223] [2023-11-19 08:04:33,069 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:33,069 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:04:33,069 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:33,070 INFO L85 PathProgramCache]: Analyzing trace with hash -1993645742, now seen corresponding path program 1 times [2023-11-19 08:04:33,070 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:33,070 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [676056172] [2023-11-19 08:04:33,070 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:33,071 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:33,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:33,133 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:33,134 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:33,134 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [676056172] [2023-11-19 08:04:33,134 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [676056172] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:33,134 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:33,135 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:33,135 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [879709178] [2023-11-19 08:04:33,135 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:33,136 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:04:33,136 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:04:33,136 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:04:33,136 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:04:33,137 INFO L87 Difference]: Start difference. First operand 1104 states and 1637 transitions. cyclomatic complexity: 534 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:33,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:04:33,168 INFO L93 Difference]: Finished difference Result 1104 states and 1636 transitions. [2023-11-19 08:04:33,168 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1636 transitions. [2023-11-19 08:04:33,179 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-19 08:04:33,189 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1636 transitions. [2023-11-19 08:04:33,190 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2023-11-19 08:04:33,191 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2023-11-19 08:04:33,191 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1636 transitions. [2023-11-19 08:04:33,193 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:04:33,193 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1636 transitions. [2023-11-19 08:04:33,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1636 transitions. [2023-11-19 08:04:33,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2023-11-19 08:04:33,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.4818840579710144) internal successors, (1636), 1103 states have internal predecessors, (1636), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:33,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1636 transitions. [2023-11-19 08:04:33,219 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1636 transitions. [2023-11-19 08:04:33,219 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:04:33,220 INFO L428 stractBuchiCegarLoop]: Abstraction has 1104 states and 1636 transitions. [2023-11-19 08:04:33,220 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-19 08:04:33,221 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1636 transitions. [2023-11-19 08:04:33,229 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-19 08:04:33,229 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:04:33,229 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:04:33,231 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:33,231 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:33,232 INFO L748 eck$LassoCheckResult]: Stem: 11376#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 11377#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 12133#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12134#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12085#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 12086#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12068#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11890#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11891#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11699#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11700#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12155#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12060#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11759#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11530#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11531#L922 assume !(0 == ~M_E~0); 12191#L922-2 assume !(0 == ~T1_E~0); 12192#L927-1 assume !(0 == ~T2_E~0); 11954#L932-1 assume !(0 == ~T3_E~0); 11829#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11830#L942-1 assume !(0 == ~T5_E~0); 11889#L947-1 assume !(0 == ~T6_E~0); 11958#L952-1 assume !(0 == ~T7_E~0); 11959#L957-1 assume !(0 == ~T8_E~0); 12019#L962-1 assume !(0 == ~T9_E~0); 11808#L967-1 assume !(0 == ~E_1~0); 11809#L972-1 assume !(0 == ~E_2~0); 12072#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 12073#L982-1 assume !(0 == ~E_4~0); 11309#L987-1 assume !(0 == ~E_5~0); 11310#L992-1 assume !(0 == ~E_6~0); 11314#L997-1 assume !(0 == ~E_7~0); 11737#L1002-1 assume !(0 == ~E_8~0); 11724#L1007-1 assume !(0 == ~E_9~0); 11101#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11102#L443 assume !(1 == ~m_pc~0); 11974#L443-2 is_master_triggered_~__retres1~0#1 := 0; 11966#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11967#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11469#L1140 assume !(0 != activate_threads_~tmp~1#1); 11206#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11207#L462 assume 1 == ~t1_pc~0; 11855#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11824#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11145#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11146#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 11678#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11679#L481 assume !(1 == ~t2_pc~0); 11463#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11462#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11589#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11553#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 11554#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11648#L500 assume 1 == ~t3_pc~0; 11874#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11875#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11108#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11109#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 11106#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11107#L519 assume 1 == ~t4_pc~0; 11409#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11410#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11208#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11209#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 11505#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11270#L538 assume !(1 == ~t5_pc~0); 11271#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11170#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11171#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11449#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11450#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12003#L557 assume 1 == ~t6_pc~0; 11796#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11484#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11571#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11506#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 11507#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12178#L576 assume !(1 == ~t7_pc~0); 11473#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11474#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11795#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12188#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 12052#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11592#L595 assume 1 == ~t8_pc~0; 11593#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12065#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12008#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11913#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 11914#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11399#L614 assume !(1 == ~t9_pc~0); 11400#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 11296#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11297#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11622#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 11556#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11557#L1025 assume !(1 == ~M_E~0); 11815#L1025-2 assume !(1 == ~T1_E~0); 11873#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11997#L1035-1 assume !(1 == ~T3_E~0); 11549#L1040-1 assume !(1 == ~T4_E~0); 11550#L1045-1 assume !(1 == ~T5_E~0); 11459#L1050-1 assume !(1 == ~T6_E~0); 11460#L1055-1 assume !(1 == ~T7_E~0); 11281#L1060-1 assume !(1 == ~T8_E~0); 11282#L1065-1 assume !(1 == ~T9_E~0); 11346#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 11961#L1075-1 assume !(1 == ~E_2~0); 11962#L1080-1 assume !(1 == ~E_3~0); 11949#L1085-1 assume !(1 == ~E_4~0); 11950#L1090-1 assume !(1 == ~E_5~0); 12149#L1095-1 assume !(1 == ~E_6~0); 11983#L1100-1 assume !(1 == ~E_7~0); 11984#L1105-1 assume !(1 == ~E_8~0); 11252#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 11253#L1115-1 assume { :end_inline_reset_delta_events } true; 11418#L1396-2 [2023-11-19 08:04:33,232 INFO L750 eck$LassoCheckResult]: Loop: 11418#L1396-2 assume !false; 11498#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12153#L897-1 assume !false; 12176#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12087#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11126#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11127#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11610#L766 assume !(0 != eval_~tmp~0#1); 12012#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11767#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11719#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11720#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11441#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11442#L932-3 assume !(0 == ~T3_E~0); 11615#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11244#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11245#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11616#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11617#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12138#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12033#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12034#L972-3 assume !(0 == ~E_2~0); 11952#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11953#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12193#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11569#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11570#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11564#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 11565#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11283#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11284#L443-30 assume 1 == ~m_pc~0; 11317#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11318#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11596#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11601#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12076#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11706#L462-30 assume 1 == ~t1_pc~0; 11538#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11539#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11825#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11826#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12101#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11691#L481-30 assume !(1 == ~t2_pc~0); 11408#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 11407#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11499#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11378#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 11379#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11651#L500-30 assume 1 == ~t3_pc~0; 11414#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11415#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11744#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11800#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11635#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11636#L519-30 assume 1 == ~t4_pc~0; 11988#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11801#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11802#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11812#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11813#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11932#L538-30 assume 1 == ~t5_pc~0; 11292#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11293#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11619#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11919#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11372#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11373#L557-30 assume 1 == ~t6_pc~0; 11091#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11093#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11212#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11213#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11397#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11398#L576-30 assume 1 == ~t7_pc~0; 11922#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11167#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11774#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11981#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11548#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11512#L595-30 assume !(1 == ~t8_pc~0); 11513#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 11453#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11454#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12147#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12148#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12179#L614-30 assume 1 == ~t9_pc~0; 11456#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11457#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11130#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11131#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11285#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11906#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11680#L1025-5 assume !(1 == ~T1_E~0); 11681#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11878#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12157#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12189#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12152#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12064#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11176#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11177#L1065-3 assume !(1 == ~T9_E~0); 12078#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11935#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11936#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12158#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12069#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12070#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12089#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12090#L1105-3 assume !(1 == ~E_8~0); 11331#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 11332#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12106#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11187#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11340#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 11532#L1415 assume !(0 == start_simulation_~tmp~3#1); 11806#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 11807#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11240#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11141#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 11142#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12194#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11797#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 11417#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 11418#L1396-2 [2023-11-19 08:04:33,233 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:33,233 INFO L85 PathProgramCache]: Analyzing trace with hash 234490531, now seen corresponding path program 1 times [2023-11-19 08:04:33,234 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:33,234 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1416271796] [2023-11-19 08:04:33,234 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:33,234 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:33,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:33,280 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:33,280 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:33,281 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1416271796] [2023-11-19 08:04:33,281 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1416271796] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:33,281 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:33,281 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:33,282 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1883314099] [2023-11-19 08:04:33,282 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:33,282 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:04:33,283 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:33,283 INFO L85 PathProgramCache]: Analyzing trace with hash -1124783627, now seen corresponding path program 1 times [2023-11-19 08:04:33,283 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:33,283 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950914280] [2023-11-19 08:04:33,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:33,284 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:33,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:33,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:33,374 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:33,375 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1950914280] [2023-11-19 08:04:33,375 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1950914280] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:33,375 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:33,375 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:33,376 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1884886019] [2023-11-19 08:04:33,376 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:33,376 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:04:33,377 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:04:33,377 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:04:33,377 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:04:33,378 INFO L87 Difference]: Start difference. First operand 1104 states and 1636 transitions. cyclomatic complexity: 533 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:33,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:04:33,411 INFO L93 Difference]: Finished difference Result 1104 states and 1635 transitions. [2023-11-19 08:04:33,412 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1635 transitions. [2023-11-19 08:04:33,422 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-19 08:04:33,432 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1635 transitions. [2023-11-19 08:04:33,433 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2023-11-19 08:04:33,434 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2023-11-19 08:04:33,434 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1635 transitions. [2023-11-19 08:04:33,436 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:04:33,436 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1635 transitions. [2023-11-19 08:04:33,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1635 transitions. [2023-11-19 08:04:33,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2023-11-19 08:04:33,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.4809782608695652) internal successors, (1635), 1103 states have internal predecessors, (1635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:33,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1635 transitions. [2023-11-19 08:04:33,463 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1635 transitions. [2023-11-19 08:04:33,463 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:04:33,464 INFO L428 stractBuchiCegarLoop]: Abstraction has 1104 states and 1635 transitions. [2023-11-19 08:04:33,464 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-19 08:04:33,464 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1635 transitions. [2023-11-19 08:04:33,472 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-19 08:04:33,473 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:04:33,473 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:04:33,475 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:33,475 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:33,475 INFO L748 eck$LassoCheckResult]: Stem: 13591#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 13592#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 14348#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14349#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14300#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 14301#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14283#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14105#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14106#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13914#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13915#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14370#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14275#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13974#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13745#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13746#L922 assume !(0 == ~M_E~0); 14406#L922-2 assume !(0 == ~T1_E~0); 14407#L927-1 assume !(0 == ~T2_E~0); 14169#L932-1 assume !(0 == ~T3_E~0); 14044#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14045#L942-1 assume !(0 == ~T5_E~0); 14104#L947-1 assume !(0 == ~T6_E~0); 14173#L952-1 assume !(0 == ~T7_E~0); 14174#L957-1 assume !(0 == ~T8_E~0); 14234#L962-1 assume !(0 == ~T9_E~0); 14025#L967-1 assume !(0 == ~E_1~0); 14026#L972-1 assume !(0 == ~E_2~0); 14287#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 14288#L982-1 assume !(0 == ~E_4~0); 13524#L987-1 assume !(0 == ~E_5~0); 13525#L992-1 assume !(0 == ~E_6~0); 13529#L997-1 assume !(0 == ~E_7~0); 13952#L1002-1 assume !(0 == ~E_8~0); 13939#L1007-1 assume !(0 == ~E_9~0); 13316#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13317#L443 assume !(1 == ~m_pc~0); 14189#L443-2 is_master_triggered_~__retres1~0#1 := 0; 14181#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14182#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13684#L1140 assume !(0 != activate_threads_~tmp~1#1); 13421#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13422#L462 assume 1 == ~t1_pc~0; 14070#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14039#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13360#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13361#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 13893#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13894#L481 assume !(1 == ~t2_pc~0); 13678#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13677#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13804#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13768#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 13769#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13863#L500 assume 1 == ~t3_pc~0; 14089#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14090#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13323#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13324#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 13321#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13322#L519 assume 1 == ~t4_pc~0; 13624#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13625#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13423#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13424#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 13720#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13485#L538 assume !(1 == ~t5_pc~0); 13486#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13385#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13386#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13664#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13665#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14219#L557 assume 1 == ~t6_pc~0; 14011#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13699#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13786#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13721#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 13722#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14393#L576 assume !(1 == ~t7_pc~0); 13688#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13689#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14010#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14403#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 14267#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13805#L595 assume 1 == ~t8_pc~0; 13806#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14280#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14221#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14128#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 14129#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13614#L614 assume !(1 == ~t9_pc~0); 13615#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 13510#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13511#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13837#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 13771#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13772#L1025 assume !(1 == ~M_E~0); 14030#L1025-2 assume !(1 == ~T1_E~0); 14088#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14211#L1035-1 assume !(1 == ~T3_E~0); 13763#L1040-1 assume !(1 == ~T4_E~0); 13764#L1045-1 assume !(1 == ~T5_E~0); 13674#L1050-1 assume !(1 == ~T6_E~0); 13675#L1055-1 assume !(1 == ~T7_E~0); 13496#L1060-1 assume !(1 == ~T8_E~0); 13497#L1065-1 assume !(1 == ~T9_E~0); 13561#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 14175#L1075-1 assume !(1 == ~E_2~0); 14176#L1080-1 assume !(1 == ~E_3~0); 14164#L1085-1 assume !(1 == ~E_4~0); 14165#L1090-1 assume !(1 == ~E_5~0); 14364#L1095-1 assume !(1 == ~E_6~0); 14198#L1100-1 assume !(1 == ~E_7~0); 14199#L1105-1 assume !(1 == ~E_8~0); 13467#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 13468#L1115-1 assume { :end_inline_reset_delta_events } true; 13635#L1396-2 [2023-11-19 08:04:33,476 INFO L750 eck$LassoCheckResult]: Loop: 13635#L1396-2 assume !false; 13710#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14368#L897-1 assume !false; 14391#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14302#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 13339#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13340#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13825#L766 assume !(0 != eval_~tmp~0#1); 14226#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13979#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13931#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13932#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13656#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13657#L932-3 assume !(0 == ~T3_E~0); 13830#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13459#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13460#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13831#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13832#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14353#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14248#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14249#L972-3 assume !(0 == ~E_2~0); 14167#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14168#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14408#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13784#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13785#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13779#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13780#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 13498#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13499#L443-30 assume 1 == ~m_pc~0; 13532#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13533#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13811#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13816#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14291#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13921#L462-30 assume 1 == ~t1_pc~0; 13753#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13754#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14040#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14041#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14316#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13906#L481-30 assume 1 == ~t2_pc~0; 13621#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13622#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13714#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13593#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 13594#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13866#L500-30 assume 1 == ~t3_pc~0; 13629#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13630#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13959#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14015#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13850#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13851#L519-30 assume !(1 == ~t4_pc~0); 14037#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 14016#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14017#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14027#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14028#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14147#L538-30 assume 1 == ~t5_pc~0; 13507#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13508#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13834#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14134#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13587#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13588#L557-30 assume 1 == ~t6_pc~0; 13306#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13308#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13427#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13428#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13612#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13613#L576-30 assume !(1 == ~t7_pc~0); 13381#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 13382#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13989#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14196#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13765#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13727#L595-30 assume !(1 == ~t8_pc~0); 13728#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 13668#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13669#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14362#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14363#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14394#L614-30 assume 1 == ~t9_pc~0; 13671#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13672#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13345#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13346#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13500#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14121#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13895#L1025-5 assume !(1 == ~T1_E~0); 13896#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14093#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14372#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14404#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14367#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14279#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13391#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13392#L1065-3 assume !(1 == ~T9_E~0); 14293#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14150#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14151#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14373#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14284#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14285#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14304#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14305#L1105-3 assume !(1 == ~E_8~0); 13546#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13547#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14321#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 13402#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13555#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 13747#L1415 assume !(0 == start_simulation_~tmp~3#1); 14021#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14022#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 13455#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13356#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 13357#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14409#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14012#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 13634#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 13635#L1396-2 [2023-11-19 08:04:33,477 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:33,477 INFO L85 PathProgramCache]: Analyzing trace with hash 116049057, now seen corresponding path program 1 times [2023-11-19 08:04:33,477 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:33,477 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [35769531] [2023-11-19 08:04:33,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:33,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:33,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:33,523 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:33,523 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:33,523 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [35769531] [2023-11-19 08:04:33,523 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [35769531] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:33,524 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:33,524 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:33,524 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [819374508] [2023-11-19 08:04:33,524 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:33,525 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:04:33,525 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:33,525 INFO L85 PathProgramCache]: Analyzing trace with hash -2034235564, now seen corresponding path program 2 times [2023-11-19 08:04:33,526 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:33,526 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [107542313] [2023-11-19 08:04:33,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:33,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:33,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:33,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:33,588 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:33,588 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [107542313] [2023-11-19 08:04:33,588 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [107542313] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:33,589 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:33,589 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:33,589 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1965954607] [2023-11-19 08:04:33,589 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:33,590 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:04:33,590 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:04:33,590 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:04:33,590 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:04:33,591 INFO L87 Difference]: Start difference. First operand 1104 states and 1635 transitions. cyclomatic complexity: 532 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:33,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:04:33,622 INFO L93 Difference]: Finished difference Result 1104 states and 1634 transitions. [2023-11-19 08:04:33,622 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1634 transitions. [2023-11-19 08:04:33,633 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-19 08:04:33,643 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1634 transitions. [2023-11-19 08:04:33,643 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2023-11-19 08:04:33,644 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2023-11-19 08:04:33,645 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1634 transitions. [2023-11-19 08:04:33,646 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:04:33,647 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1634 transitions. [2023-11-19 08:04:33,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1634 transitions. [2023-11-19 08:04:33,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2023-11-19 08:04:33,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.480072463768116) internal successors, (1634), 1103 states have internal predecessors, (1634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:33,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1634 transitions. [2023-11-19 08:04:33,673 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1634 transitions. [2023-11-19 08:04:33,673 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:04:33,674 INFO L428 stractBuchiCegarLoop]: Abstraction has 1104 states and 1634 transitions. [2023-11-19 08:04:33,674 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-19 08:04:33,674 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1634 transitions. [2023-11-19 08:04:33,683 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-19 08:04:33,683 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:04:33,683 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:04:33,685 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:33,685 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:33,686 INFO L748 eck$LassoCheckResult]: Stem: 15804#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 15805#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 16563#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16564#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16515#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 16516#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16498#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16320#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16321#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16128#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16129#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16584#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16489#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16189#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15960#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15961#L922 assume !(0 == ~M_E~0); 16621#L922-2 assume !(0 == ~T1_E~0); 16622#L927-1 assume !(0 == ~T2_E~0); 16384#L932-1 assume !(0 == ~T3_E~0); 16259#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16260#L942-1 assume !(0 == ~T5_E~0); 16319#L947-1 assume !(0 == ~T6_E~0); 16388#L952-1 assume !(0 == ~T7_E~0); 16389#L957-1 assume !(0 == ~T8_E~0); 16446#L962-1 assume !(0 == ~T9_E~0); 16238#L967-1 assume !(0 == ~E_1~0); 16239#L972-1 assume !(0 == ~E_2~0); 16502#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 16503#L982-1 assume !(0 == ~E_4~0); 15737#L987-1 assume !(0 == ~E_5~0); 15738#L992-1 assume !(0 == ~E_6~0); 15744#L997-1 assume !(0 == ~E_7~0); 16165#L1002-1 assume !(0 == ~E_8~0); 16154#L1007-1 assume !(0 == ~E_9~0); 15531#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15532#L443 assume !(1 == ~m_pc~0); 16404#L443-2 is_master_triggered_~__retres1~0#1 := 0; 16396#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16397#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15899#L1140 assume !(0 != activate_threads_~tmp~1#1); 15636#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15637#L462 assume 1 == ~t1_pc~0; 16285#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16251#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15573#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15574#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 16106#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16107#L481 assume !(1 == ~t2_pc~0); 15893#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15892#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16019#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15983#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 15984#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16076#L500 assume 1 == ~t3_pc~0; 16304#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16305#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15538#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15539#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 15533#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15534#L519 assume 1 == ~t4_pc~0; 15836#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15837#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15638#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15639#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 15933#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15700#L538 assume !(1 == ~t5_pc~0); 15701#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15598#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15599#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15879#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15880#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16431#L557 assume 1 == ~t6_pc~0; 16226#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15914#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16001#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15934#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 15935#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16608#L576 assume !(1 == ~t7_pc~0); 15903#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 15904#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16225#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16618#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 16482#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16020#L595 assume 1 == ~t8_pc~0; 16021#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16495#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16436#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16343#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 16344#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15829#L614 assume !(1 == ~t9_pc~0); 15830#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 15725#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15726#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16052#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 15986#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15987#L1025 assume !(1 == ~M_E~0); 16245#L1025-2 assume !(1 == ~T1_E~0); 16303#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16426#L1035-1 assume !(1 == ~T3_E~0); 15978#L1040-1 assume !(1 == ~T4_E~0); 15979#L1045-1 assume !(1 == ~T5_E~0); 15889#L1050-1 assume !(1 == ~T6_E~0); 15890#L1055-1 assume !(1 == ~T7_E~0); 15711#L1060-1 assume !(1 == ~T8_E~0); 15712#L1065-1 assume !(1 == ~T9_E~0); 15776#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 16390#L1075-1 assume !(1 == ~E_2~0); 16391#L1080-1 assume !(1 == ~E_3~0); 16379#L1085-1 assume !(1 == ~E_4~0); 16380#L1090-1 assume !(1 == ~E_5~0); 16579#L1095-1 assume !(1 == ~E_6~0); 16413#L1100-1 assume !(1 == ~E_7~0); 16414#L1105-1 assume !(1 == ~E_8~0); 15682#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 15683#L1115-1 assume { :end_inline_reset_delta_events } true; 15850#L1396-2 [2023-11-19 08:04:33,686 INFO L750 eck$LassoCheckResult]: Loop: 15850#L1396-2 assume !false; 15925#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16583#L897-1 assume !false; 16606#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16517#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 15554#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15555#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16040#L766 assume !(0 != eval_~tmp~0#1); 16441#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16194#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16146#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16147#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15871#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15872#L932-3 assume !(0 == ~T3_E~0); 16045#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15674#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15675#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16046#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16047#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16568#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16463#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16464#L972-3 assume !(0 == ~E_2~0); 16382#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16383#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16623#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15999#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16000#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15994#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15995#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15713#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15714#L443-30 assume 1 == ~m_pc~0; 15747#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 15748#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16026#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16031#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16506#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16136#L462-30 assume 1 == ~t1_pc~0; 15968#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15969#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16255#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16256#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16531#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16121#L481-30 assume !(1 == ~t2_pc~0); 15841#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 15840#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15929#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15808#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 15809#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16081#L500-30 assume 1 == ~t3_pc~0; 15844#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15845#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16174#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16230#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16065#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16066#L519-30 assume 1 == ~t4_pc~0; 16418#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16231#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16232#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16242#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16243#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16362#L538-30 assume 1 == ~t5_pc~0; 15722#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15723#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16049#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16349#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15802#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15803#L557-30 assume 1 == ~t6_pc~0; 15521#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15523#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15642#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15643#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15827#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15828#L576-30 assume 1 == ~t7_pc~0; 16352#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15597#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16204#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16411#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15980#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15942#L595-30 assume !(1 == ~t8_pc~0); 15943#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 15883#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15884#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16577#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16578#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16609#L614-30 assume !(1 == ~t9_pc~0); 15888#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 15887#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15560#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15561#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15715#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16336#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16110#L1025-5 assume !(1 == ~T1_E~0); 16111#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16308#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16587#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16619#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16582#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16494#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15606#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15607#L1065-3 assume !(1 == ~T9_E~0); 16508#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16365#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16366#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16588#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16499#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16500#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16519#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16520#L1105-3 assume !(1 == ~E_8~0); 15761#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15762#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16536#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 15617#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15770#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 15962#L1415 assume !(0 == start_simulation_~tmp~3#1); 16236#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16237#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 15670#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15571#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 15572#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16624#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16227#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 15849#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 15850#L1396-2 [2023-11-19 08:04:33,687 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:33,687 INFO L85 PathProgramCache]: Analyzing trace with hash -1273244957, now seen corresponding path program 1 times [2023-11-19 08:04:33,687 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:33,688 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [819819587] [2023-11-19 08:04:33,688 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:33,688 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:33,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:33,741 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:33,742 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:33,743 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [819819587] [2023-11-19 08:04:33,744 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [819819587] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:33,744 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:33,744 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:33,748 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1229937075] [2023-11-19 08:04:33,748 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:33,748 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:04:33,749 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:33,749 INFO L85 PathProgramCache]: Analyzing trace with hash -601462956, now seen corresponding path program 1 times [2023-11-19 08:04:33,749 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:33,752 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [486706470] [2023-11-19 08:04:33,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:33,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:33,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:33,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:33,822 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:33,822 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [486706470] [2023-11-19 08:04:33,825 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [486706470] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:33,825 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:33,825 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:33,825 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [717724877] [2023-11-19 08:04:33,826 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:33,826 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:04:33,826 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:04:33,827 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:04:33,827 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:04:33,827 INFO L87 Difference]: Start difference. First operand 1104 states and 1634 transitions. cyclomatic complexity: 531 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:33,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:04:33,858 INFO L93 Difference]: Finished difference Result 1104 states and 1633 transitions. [2023-11-19 08:04:33,858 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1633 transitions. [2023-11-19 08:04:33,869 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-19 08:04:33,879 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1633 transitions. [2023-11-19 08:04:33,879 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2023-11-19 08:04:33,880 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2023-11-19 08:04:33,881 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1633 transitions. [2023-11-19 08:04:33,883 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:04:33,883 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1633 transitions. [2023-11-19 08:04:33,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1633 transitions. [2023-11-19 08:04:33,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2023-11-19 08:04:33,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.4791666666666667) internal successors, (1633), 1103 states have internal predecessors, (1633), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:33,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1633 transitions. [2023-11-19 08:04:33,911 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1633 transitions. [2023-11-19 08:04:33,912 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:04:33,915 INFO L428 stractBuchiCegarLoop]: Abstraction has 1104 states and 1633 transitions. [2023-11-19 08:04:33,916 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-19 08:04:33,916 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1633 transitions. [2023-11-19 08:04:33,922 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-19 08:04:33,922 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:04:33,922 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:04:33,924 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:33,924 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:33,925 INFO L748 eck$LassoCheckResult]: Stem: 18019#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 18020#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 18778#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18779#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18730#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 18731#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18713#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18535#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18536#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18343#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18344#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 18799#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18704#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 18404#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18175#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18176#L922 assume !(0 == ~M_E~0); 18836#L922-2 assume !(0 == ~T1_E~0); 18837#L927-1 assume !(0 == ~T2_E~0); 18599#L932-1 assume !(0 == ~T3_E~0); 18474#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18475#L942-1 assume !(0 == ~T5_E~0); 18534#L947-1 assume !(0 == ~T6_E~0); 18603#L952-1 assume !(0 == ~T7_E~0); 18604#L957-1 assume !(0 == ~T8_E~0); 18661#L962-1 assume !(0 == ~T9_E~0); 18453#L967-1 assume !(0 == ~E_1~0); 18454#L972-1 assume !(0 == ~E_2~0); 18717#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 18718#L982-1 assume !(0 == ~E_4~0); 17952#L987-1 assume !(0 == ~E_5~0); 17953#L992-1 assume !(0 == ~E_6~0); 17959#L997-1 assume !(0 == ~E_7~0); 18380#L1002-1 assume !(0 == ~E_8~0); 18369#L1007-1 assume !(0 == ~E_9~0); 17746#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17747#L443 assume !(1 == ~m_pc~0); 18619#L443-2 is_master_triggered_~__retres1~0#1 := 0; 18611#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18612#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18114#L1140 assume !(0 != activate_threads_~tmp~1#1); 17851#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17852#L462 assume 1 == ~t1_pc~0; 18500#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18466#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17788#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17789#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 18321#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18322#L481 assume !(1 == ~t2_pc~0); 18108#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18107#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18234#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18198#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 18199#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18291#L500 assume 1 == ~t3_pc~0; 18519#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18520#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17753#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17754#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 17748#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17749#L519 assume 1 == ~t4_pc~0; 18051#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18052#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17853#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17854#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 18148#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17915#L538 assume !(1 == ~t5_pc~0); 17916#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17813#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17814#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18094#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18095#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18646#L557 assume 1 == ~t6_pc~0; 18441#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18129#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18216#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18149#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 18150#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18823#L576 assume !(1 == ~t7_pc~0); 18118#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18119#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18440#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18833#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 18697#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18235#L595 assume 1 == ~t8_pc~0; 18236#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18710#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18651#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18558#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 18559#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18044#L614 assume !(1 == ~t9_pc~0); 18045#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 17940#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17941#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18267#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 18201#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18202#L1025 assume !(1 == ~M_E~0); 18460#L1025-2 assume !(1 == ~T1_E~0); 18518#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18641#L1035-1 assume !(1 == ~T3_E~0); 18193#L1040-1 assume !(1 == ~T4_E~0); 18194#L1045-1 assume !(1 == ~T5_E~0); 18104#L1050-1 assume !(1 == ~T6_E~0); 18105#L1055-1 assume !(1 == ~T7_E~0); 17926#L1060-1 assume !(1 == ~T8_E~0); 17927#L1065-1 assume !(1 == ~T9_E~0); 17991#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 18605#L1075-1 assume !(1 == ~E_2~0); 18606#L1080-1 assume !(1 == ~E_3~0); 18594#L1085-1 assume !(1 == ~E_4~0); 18595#L1090-1 assume !(1 == ~E_5~0); 18794#L1095-1 assume !(1 == ~E_6~0); 18628#L1100-1 assume !(1 == ~E_7~0); 18629#L1105-1 assume !(1 == ~E_8~0); 17897#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 17898#L1115-1 assume { :end_inline_reset_delta_events } true; 18065#L1396-2 [2023-11-19 08:04:33,925 INFO L750 eck$LassoCheckResult]: Loop: 18065#L1396-2 assume !false; 18140#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18798#L897-1 assume !false; 18821#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 18732#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 17769#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17770#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18255#L766 assume !(0 != eval_~tmp~0#1); 18656#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18409#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18361#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18362#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18086#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18087#L932-3 assume !(0 == ~T3_E~0); 18260#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17889#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17890#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18261#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18262#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18783#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18678#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18679#L972-3 assume !(0 == ~E_2~0); 18597#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18598#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18838#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18214#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18215#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18209#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18210#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17928#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17929#L443-30 assume 1 == ~m_pc~0; 17962#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17963#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18241#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18246#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18721#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18351#L462-30 assume 1 == ~t1_pc~0; 18183#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18184#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18470#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18471#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18746#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18336#L481-30 assume 1 == ~t2_pc~0; 18054#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18055#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18144#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18023#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 18024#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18296#L500-30 assume 1 == ~t3_pc~0; 18059#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18060#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18389#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18445#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18280#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18281#L519-30 assume !(1 == ~t4_pc~0); 18469#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 18446#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18447#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18457#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18458#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18577#L538-30 assume 1 == ~t5_pc~0; 17937#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17938#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18264#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18564#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18017#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18018#L557-30 assume 1 == ~t6_pc~0; 17736#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17738#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17857#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17858#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18042#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18043#L576-30 assume !(1 == ~t7_pc~0); 17811#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 17812#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18419#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18626#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18195#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18157#L595-30 assume !(1 == ~t8_pc~0); 18158#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 18098#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18099#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18792#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18793#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18824#L614-30 assume 1 == ~t9_pc~0; 18101#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18102#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17775#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17776#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17930#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18551#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18325#L1025-5 assume !(1 == ~T1_E~0); 18326#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18523#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18802#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18834#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18797#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18709#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17821#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17822#L1065-3 assume !(1 == ~T9_E~0); 18723#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18580#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18581#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18803#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18714#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18715#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18734#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18735#L1105-3 assume !(1 == ~E_8~0); 17976#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17977#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 18751#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 17832#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17985#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 18177#L1415 assume !(0 == start_simulation_~tmp~3#1); 18451#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 18452#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 17885#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17786#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 17787#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18839#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18442#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 18064#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 18065#L1396-2 [2023-11-19 08:04:33,926 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:33,926 INFO L85 PathProgramCache]: Analyzing trace with hash 760149089, now seen corresponding path program 1 times [2023-11-19 08:04:33,927 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:33,927 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [388441162] [2023-11-19 08:04:33,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:33,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:33,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:34,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:34,063 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:34,063 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [388441162] [2023-11-19 08:04:34,063 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [388441162] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:34,064 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:34,064 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:34,064 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [290866511] [2023-11-19 08:04:34,064 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:34,065 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:04:34,065 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:34,065 INFO L85 PathProgramCache]: Analyzing trace with hash -2034235564, now seen corresponding path program 3 times [2023-11-19 08:04:34,066 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:34,066 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [858010848] [2023-11-19 08:04:34,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:34,066 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:34,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:34,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:34,136 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:34,136 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [858010848] [2023-11-19 08:04:34,136 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [858010848] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:34,136 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:34,136 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:34,137 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1973675765] [2023-11-19 08:04:34,137 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:34,137 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:04:34,138 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:04:34,138 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 08:04:34,138 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 08:04:34,138 INFO L87 Difference]: Start difference. First operand 1104 states and 1633 transitions. cyclomatic complexity: 530 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:34,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:04:34,330 INFO L93 Difference]: Finished difference Result 2100 states and 3099 transitions. [2023-11-19 08:04:34,330 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2100 states and 3099 transitions. [2023-11-19 08:04:34,350 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1958 [2023-11-19 08:04:34,369 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2100 states to 2100 states and 3099 transitions. [2023-11-19 08:04:34,370 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2100 [2023-11-19 08:04:34,372 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2100 [2023-11-19 08:04:34,372 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2100 states and 3099 transitions. [2023-11-19 08:04:34,376 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:04:34,376 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2100 states and 3099 transitions. [2023-11-19 08:04:34,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2100 states and 3099 transitions. [2023-11-19 08:04:34,421 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2100 to 2100. [2023-11-19 08:04:34,426 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2100 states, 2100 states have (on average 1.4757142857142858) internal successors, (3099), 2099 states have internal predecessors, (3099), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:34,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2100 states to 2100 states and 3099 transitions. [2023-11-19 08:04:34,437 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2100 states and 3099 transitions. [2023-11-19 08:04:34,439 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 08:04:34,440 INFO L428 stractBuchiCegarLoop]: Abstraction has 2100 states and 3099 transitions. [2023-11-19 08:04:34,441 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-19 08:04:34,441 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2100 states and 3099 transitions. [2023-11-19 08:04:34,453 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1958 [2023-11-19 08:04:34,453 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:04:34,453 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:04:34,455 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:34,456 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:34,456 INFO L748 eck$LassoCheckResult]: Stem: 21234#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 21235#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 22035#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22036#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21976#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 21977#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21954#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21757#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21758#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21561#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21562#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22065#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 21944#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 21621#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21390#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21391#L922 assume !(0 == ~M_E~0); 22129#L922-2 assume !(0 == ~T1_E~0); 22130#L927-1 assume !(0 == ~T2_E~0); 21821#L932-1 assume !(0 == ~T3_E~0); 21695#L937-1 assume !(0 == ~T4_E~0); 21696#L942-1 assume !(0 == ~T5_E~0); 21756#L947-1 assume !(0 == ~T6_E~0); 21825#L952-1 assume !(0 == ~T7_E~0); 21826#L957-1 assume !(0 == ~T8_E~0); 21890#L962-1 assume !(0 == ~T9_E~0); 21673#L967-1 assume !(0 == ~E_1~0); 21674#L972-1 assume !(0 == ~E_2~0); 21959#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 21960#L982-1 assume !(0 == ~E_4~0); 21166#L987-1 assume !(0 == ~E_5~0); 21167#L992-1 assume !(0 == ~E_6~0); 21173#L997-1 assume !(0 == ~E_7~0); 21597#L1002-1 assume !(0 == ~E_8~0); 21586#L1007-1 assume !(0 == ~E_9~0); 20960#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20961#L443 assume !(1 == ~m_pc~0); 21841#L443-2 is_master_triggered_~__retres1~0#1 := 0; 21833#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21834#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21329#L1140 assume !(0 != activate_threads_~tmp~1#1); 21065#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21066#L462 assume 1 == ~t1_pc~0; 21721#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21687#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21002#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21003#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 21540#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21541#L481 assume !(1 == ~t2_pc~0); 21323#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21322#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21451#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21414#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 21415#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21508#L500 assume 1 == ~t3_pc~0; 21741#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21742#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20967#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20968#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 20962#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20963#L519 assume 1 == ~t4_pc~0; 21266#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21267#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21067#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21068#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 21363#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21129#L538 assume !(1 == ~t5_pc~0); 21130#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21027#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21028#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21309#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21310#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21872#L557 assume 1 == ~t6_pc~0; 21659#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21344#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21432#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21364#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 21365#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22101#L576 assume !(1 == ~t7_pc~0); 21333#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 21334#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21658#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22126#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 21934#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21452#L595 assume 1 == ~t8_pc~0; 21453#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21951#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21878#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21780#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 21781#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21259#L614 assume !(1 == ~t9_pc~0); 21260#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 21155#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21156#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21484#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 21417#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21418#L1025 assume !(1 == ~M_E~0); 21681#L1025-2 assume !(1 == ~T1_E~0); 21740#L1030-1 assume !(1 == ~T2_E~0); 21866#L1035-1 assume !(1 == ~T3_E~0); 21409#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21410#L1045-1 assume !(1 == ~T5_E~0); 21319#L1050-1 assume !(1 == ~T6_E~0); 21320#L1055-1 assume !(1 == ~T7_E~0); 21140#L1060-1 assume !(1 == ~T8_E~0); 21141#L1065-1 assume !(1 == ~T9_E~0); 21206#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 21827#L1075-1 assume !(1 == ~E_2~0); 21828#L1080-1 assume !(1 == ~E_3~0); 21816#L1085-1 assume !(1 == ~E_4~0); 21817#L1090-1 assume !(1 == ~E_5~0); 22060#L1095-1 assume !(1 == ~E_6~0); 21851#L1100-1 assume !(1 == ~E_7~0); 21852#L1105-1 assume !(1 == ~E_8~0); 21111#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 21112#L1115-1 assume { :end_inline_reset_delta_events } true; 21278#L1396-2 [2023-11-19 08:04:34,457 INFO L750 eck$LassoCheckResult]: Loop: 21278#L1396-2 assume !false; 21355#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22155#L897-1 assume !false; 22154#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22153#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 22143#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 22142#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 22048#L766 assume !(0 != eval_~tmp~0#1); 22050#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22141#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21579#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21580#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22139#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22140#L932-3 assume !(0 == ~T3_E~0); 23023#L937-3 assume !(0 == ~T4_E~0); 23022#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23021#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23020#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23019#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23018#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23017#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23016#L972-3 assume !(0 == ~E_2~0); 23015#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22138#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22135#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21430#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21431#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21425#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 21426#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21142#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21143#L443-30 assume 1 == ~m_pc~0; 21176#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21177#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21458#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21463#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21966#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21568#L462-30 assume 1 == ~t1_pc~0; 21400#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21401#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21691#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21692#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22770#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22768#L481-30 assume 1 == ~t2_pc~0; 22764#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22762#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22760#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22758#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 22756#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22754#L500-30 assume 1 == ~t3_pc~0; 22750#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22749#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22748#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22747#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22746#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22745#L519-30 assume 1 == ~t4_pc~0; 22743#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22742#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22741#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22740#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22739#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22738#L538-30 assume 1 == ~t5_pc~0; 22736#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22735#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22734#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22733#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22732#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22731#L557-30 assume !(1 == ~t6_pc~0); 22729#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 22728#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22727#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22726#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22725#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22724#L576-30 assume 1 == ~t7_pc~0; 22722#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22721#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22720#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22719#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22718#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22717#L595-30 assume !(1 == ~t8_pc~0); 22714#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 22713#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22711#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22058#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22059#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22106#L614-30 assume 1 == ~t9_pc~0; 21315#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21316#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20989#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20990#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21144#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21773#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21542#L1025-5 assume !(1 == ~T1_E~0); 21543#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21745#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22068#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22127#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22063#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21950#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21035#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21036#L1065-3 assume !(1 == ~T9_E~0); 21969#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21802#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21803#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22069#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21956#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21957#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21980#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21981#L1105-3 assume !(1 == ~E_8~0); 21191#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21192#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22000#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 21046#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 21200#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 21392#L1415 assume !(0 == start_simulation_~tmp~3#1); 22520#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22115#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 21099#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 21000#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 21001#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22136#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21660#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 21277#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 21278#L1396-2 [2023-11-19 08:04:34,463 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:34,463 INFO L85 PathProgramCache]: Analyzing trace with hash -1269658465, now seen corresponding path program 1 times [2023-11-19 08:04:34,463 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:34,463 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [202382364] [2023-11-19 08:04:34,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:34,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:34,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:34,557 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:34,558 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:34,558 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [202382364] [2023-11-19 08:04:34,558 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [202382364] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:34,558 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:34,558 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:34,559 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [407993745] [2023-11-19 08:04:34,559 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:34,559 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:04:34,560 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:34,560 INFO L85 PathProgramCache]: Analyzing trace with hash 187840947, now seen corresponding path program 1 times [2023-11-19 08:04:34,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:34,560 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1329949303] [2023-11-19 08:04:34,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:34,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:34,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:34,619 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:34,620 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:34,620 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1329949303] [2023-11-19 08:04:34,620 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1329949303] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:34,620 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:34,621 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:34,621 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1892956607] [2023-11-19 08:04:34,621 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:34,622 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:04:34,622 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:04:34,622 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 08:04:34,622 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 08:04:34,623 INFO L87 Difference]: Start difference. First operand 2100 states and 3099 transitions. cyclomatic complexity: 1001 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:34,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:04:34,824 INFO L93 Difference]: Finished difference Result 3938 states and 5806 transitions. [2023-11-19 08:04:34,824 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3938 states and 5806 transitions. [2023-11-19 08:04:34,855 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3772 [2023-11-19 08:04:34,890 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3938 states to 3938 states and 5806 transitions. [2023-11-19 08:04:34,890 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3938 [2023-11-19 08:04:34,895 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3938 [2023-11-19 08:04:34,895 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3938 states and 5806 transitions. [2023-11-19 08:04:34,901 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:04:34,901 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3938 states and 5806 transitions. [2023-11-19 08:04:34,907 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3938 states and 5806 transitions. [2023-11-19 08:04:35,040 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3938 to 3936. [2023-11-19 08:04:35,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3936 states, 3936 states have (on average 1.4745934959349594) internal successors, (5804), 3935 states have internal predecessors, (5804), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:35,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3936 states to 3936 states and 5804 transitions. [2023-11-19 08:04:35,076 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3936 states and 5804 transitions. [2023-11-19 08:04:35,076 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 08:04:35,077 INFO L428 stractBuchiCegarLoop]: Abstraction has 3936 states and 5804 transitions. [2023-11-19 08:04:35,077 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-19 08:04:35,078 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3936 states and 5804 transitions. [2023-11-19 08:04:35,098 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3772 [2023-11-19 08:04:35,098 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:04:35,098 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:04:35,100 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:35,100 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:35,102 INFO L748 eck$LassoCheckResult]: Stem: 27284#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 27285#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 28099#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28100#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28044#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 28045#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28023#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27817#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27818#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27612#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27613#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 28135#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 28012#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27675#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27439#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27440#L922 assume !(0 == ~M_E~0); 28186#L922-2 assume !(0 == ~T1_E~0); 28187#L927-1 assume !(0 == ~T2_E~0); 27888#L932-1 assume !(0 == ~T3_E~0); 27750#L937-1 assume !(0 == ~T4_E~0); 27751#L942-1 assume !(0 == ~T5_E~0); 27816#L947-1 assume !(0 == ~T6_E~0); 27892#L952-1 assume !(0 == ~T7_E~0); 27893#L957-1 assume !(0 == ~T8_E~0); 27963#L962-1 assume !(0 == ~T9_E~0); 27726#L967-1 assume !(0 == ~E_1~0); 27727#L972-1 assume !(0 == ~E_2~0); 28028#L977-1 assume !(0 == ~E_3~0); 28029#L982-1 assume !(0 == ~E_4~0); 27214#L987-1 assume !(0 == ~E_5~0); 27215#L992-1 assume !(0 == ~E_6~0); 27221#L997-1 assume !(0 == ~E_7~0); 27652#L1002-1 assume !(0 == ~E_8~0); 27637#L1007-1 assume !(0 == ~E_9~0); 27008#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27009#L443 assume !(1 == ~m_pc~0); 27909#L443-2 is_master_triggered_~__retres1~0#1 := 0; 27900#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27901#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 27377#L1140 assume !(0 != activate_threads_~tmp~1#1); 27113#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27114#L462 assume 1 == ~t1_pc~0; 27776#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27745#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27052#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27053#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 27591#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27592#L481 assume !(1 == ~t2_pc~0); 27371#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27370#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27499#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27462#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 27463#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27561#L500 assume 1 == ~t3_pc~0; 27797#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27798#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27015#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27016#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 27013#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27014#L519 assume 1 == ~t4_pc~0; 27317#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27318#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27115#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27116#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 27414#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27177#L538 assume !(1 == ~t5_pc~0); 27178#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 27075#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27076#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27357#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27358#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27944#L557 assume 1 == ~t6_pc~0; 27714#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27393#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27481#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27415#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 27416#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28162#L576 assume !(1 == ~t7_pc~0); 27381#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 27382#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27713#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28182#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 28004#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27500#L595 assume 1 == ~t8_pc~0; 27501#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28019#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27947#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27841#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 27842#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27307#L614 assume !(1 == ~t9_pc~0); 27308#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 27203#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27204#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27534#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 27465#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27466#L1025 assume !(1 == ~M_E~0); 27734#L1025-2 assume !(1 == ~T1_E~0); 27796#L1030-1 assume !(1 == ~T2_E~0); 27935#L1035-1 assume !(1 == ~T3_E~0); 28360#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28050#L1045-1 assume !(1 == ~T5_E~0); 27367#L1050-1 assume !(1 == ~T6_E~0); 27368#L1055-1 assume !(1 == ~T7_E~0); 27188#L1060-1 assume !(1 == ~T8_E~0); 27189#L1065-1 assume !(1 == ~T9_E~0); 27254#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 28166#L1075-1 assume !(1 == ~E_2~0); 28350#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 28284#L1085-1 assume !(1 == ~E_4~0); 28262#L1090-1 assume !(1 == ~E_5~0); 28260#L1095-1 assume !(1 == ~E_6~0); 28258#L1100-1 assume !(1 == ~E_7~0); 28256#L1105-1 assume !(1 == ~E_8~0); 28246#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 28237#L1115-1 assume { :end_inline_reset_delta_events } true; 28230#L1396-2 [2023-11-19 08:04:35,102 INFO L750 eck$LassoCheckResult]: Loop: 28230#L1396-2 assume !false; 28224#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28220#L897-1 assume !false; 28219#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 28218#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 28208#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 28207#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28205#L766 assume !(0 != eval_~tmp~0#1); 28204#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28203#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28202#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28201#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28200#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27526#L932-3 assume !(0 == ~T3_E~0); 27527#L937-3 assume !(0 == ~T4_E~0); 27151#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27152#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27528#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27529#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28104#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 27981#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27982#L972-3 assume !(0 == ~E_2~0); 27886#L977-3 assume !(0 == ~E_3~0); 27887#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28191#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 27479#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 27480#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27477#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27478#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27190#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27191#L443-30 assume 1 == ~m_pc~0; 30699#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 30697#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30695#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30693#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30692#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27619#L462-30 assume 1 == ~t1_pc~0; 27447#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27448#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27746#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27747#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28062#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27604#L481-30 assume 1 == ~t2_pc~0; 27314#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27315#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27408#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27286#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 27287#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27564#L500-30 assume 1 == ~t3_pc~0; 27322#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27323#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27659#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27718#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27547#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27548#L519-30 assume 1 == ~t4_pc~0; 27927#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27719#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27720#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27731#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 27732#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29313#L538-30 assume 1 == ~t5_pc~0; 29310#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29307#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29305#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29303#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29302#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29300#L557-30 assume !(1 == ~t6_pc~0); 29296#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 29294#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29291#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29289#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29163#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29161#L576-30 assume 1 == ~t7_pc~0; 29158#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29155#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29153#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29151#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29149#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29147#L595-30 assume !(1 == ~t8_pc~0); 29143#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 29053#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29050#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29048#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28966#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28963#L614-30 assume 1 == ~t9_pc~0; 28960#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28854#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28735#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28732#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28730#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28624#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28621#L1025-5 assume !(1 == ~T1_E~0); 28619#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27801#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28616#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28183#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28541#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28539#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28537#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28535#L1065-3 assume !(1 == ~T9_E~0); 28534#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28465#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28418#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28415#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28413#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28412#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28410#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28408#L1105-3 assume !(1 == ~E_8~0); 28406#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28361#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 28310#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 28299#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 28297#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 28289#L1415 assume !(0 == start_simulation_~tmp~3#1); 28287#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 28270#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 28263#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 28261#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 28259#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28257#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28247#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 28238#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 28230#L1396-2 [2023-11-19 08:04:35,103 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:35,104 INFO L85 PathProgramCache]: Analyzing trace with hash -1455005537, now seen corresponding path program 1 times [2023-11-19 08:04:35,104 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:35,104 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [306683407] [2023-11-19 08:04:35,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:35,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:35,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:35,188 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:35,189 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:35,189 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [306683407] [2023-11-19 08:04:35,189 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [306683407] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:35,189 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:35,190 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:35,190 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1275850802] [2023-11-19 08:04:35,190 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:35,190 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:04:35,191 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:35,191 INFO L85 PathProgramCache]: Analyzing trace with hash 2085337713, now seen corresponding path program 1 times [2023-11-19 08:04:35,191 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:35,191 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1818901157] [2023-11-19 08:04:35,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:35,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:35,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:35,264 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:35,264 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:35,264 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1818901157] [2023-11-19 08:04:35,265 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1818901157] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:35,265 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:35,265 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:35,265 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1290974620] [2023-11-19 08:04:35,265 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:35,266 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:04:35,266 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:04:35,267 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 08:04:35,267 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 08:04:35,267 INFO L87 Difference]: Start difference. First operand 3936 states and 5804 transitions. cyclomatic complexity: 1872 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:35,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:04:35,617 INFO L93 Difference]: Finished difference Result 11024 states and 16038 transitions. [2023-11-19 08:04:35,617 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11024 states and 16038 transitions. [2023-11-19 08:04:35,699 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10546 [2023-11-19 08:04:35,865 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11024 states to 11024 states and 16038 transitions. [2023-11-19 08:04:35,865 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11024 [2023-11-19 08:04:35,876 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11024 [2023-11-19 08:04:35,877 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11024 states and 16038 transitions. [2023-11-19 08:04:35,893 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:04:35,894 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11024 states and 16038 transitions. [2023-11-19 08:04:35,907 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11024 states and 16038 transitions. [2023-11-19 08:04:36,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11024 to 10472. [2023-11-19 08:04:36,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10472 states, 10472 states have (on average 1.4589381207028267) internal successors, (15278), 10471 states have internal predecessors, (15278), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:36,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10472 states to 10472 states and 15278 transitions. [2023-11-19 08:04:36,180 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10472 states and 15278 transitions. [2023-11-19 08:04:36,181 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 08:04:36,181 INFO L428 stractBuchiCegarLoop]: Abstraction has 10472 states and 15278 transitions. [2023-11-19 08:04:36,181 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-19 08:04:36,182 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10472 states and 15278 transitions. [2023-11-19 08:04:36,242 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10290 [2023-11-19 08:04:36,242 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:04:36,243 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:04:36,245 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:36,245 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:36,245 INFO L748 eck$LassoCheckResult]: Stem: 42255#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 42256#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 43083#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43084#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43023#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 43024#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42999#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42799#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42800#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42593#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42594#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43117#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42989#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 42659#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 42413#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42414#L922 assume !(0 == ~M_E~0); 43191#L922-2 assume !(0 == ~T1_E~0); 43192#L927-1 assume !(0 == ~T2_E~0); 42864#L932-1 assume !(0 == ~T3_E~0); 42737#L937-1 assume !(0 == ~T4_E~0); 42738#L942-1 assume !(0 == ~T5_E~0); 42798#L947-1 assume !(0 == ~T6_E~0); 42868#L952-1 assume !(0 == ~T7_E~0); 42869#L957-1 assume !(0 == ~T8_E~0); 42934#L962-1 assume !(0 == ~T9_E~0); 42714#L967-1 assume !(0 == ~E_1~0); 42715#L972-1 assume !(0 == ~E_2~0); 43004#L977-1 assume !(0 == ~E_3~0); 43005#L982-1 assume !(0 == ~E_4~0); 42186#L987-1 assume !(0 == ~E_5~0); 42187#L992-1 assume !(0 == ~E_6~0); 42191#L997-1 assume !(0 == ~E_7~0); 42636#L1002-1 assume !(0 == ~E_8~0); 42622#L1007-1 assume !(0 == ~E_9~0); 41978#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41979#L443 assume !(1 == ~m_pc~0); 42883#L443-2 is_master_triggered_~__retres1~0#1 := 0; 42875#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42876#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 42349#L1140 assume !(0 != activate_threads_~tmp~1#1); 42083#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42084#L462 assume !(1 == ~t1_pc~0); 42730#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42731#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42022#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 42023#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 42568#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42569#L481 assume !(1 == ~t2_pc~0); 42343#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 42342#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42475#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 42439#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 42440#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42537#L500 assume 1 == ~t3_pc~0; 42781#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42782#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41985#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41986#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 41983#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41984#L519 assume 1 == ~t4_pc~0; 42288#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 42289#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42085#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42086#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 42387#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42147#L538 assume !(1 == ~t5_pc~0); 42148#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 42047#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42048#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 42329#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42330#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42918#L557 assume 1 == ~t6_pc~0; 42698#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42364#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42458#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42388#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 42389#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43153#L576 assume !(1 == ~t7_pc~0); 42353#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 42354#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42697#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43184#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 42978#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42478#L595 assume 1 == ~t8_pc~0; 42479#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42996#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42922#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42822#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 42823#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 42278#L614 assume !(1 == ~t9_pc~0); 42279#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 42173#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42174#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42512#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 42442#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42443#L1025 assume !(1 == ~M_E~0); 42720#L1025-2 assume !(1 == ~T1_E~0); 42780#L1030-1 assume !(1 == ~T2_E~0); 42910#L1035-1 assume !(1 == ~T3_E~0); 43045#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43029#L1045-1 assume !(1 == ~T5_E~0); 42339#L1050-1 assume !(1 == ~T6_E~0); 42340#L1055-1 assume !(1 == ~T7_E~0); 42158#L1060-1 assume !(1 == ~T8_E~0); 42159#L1065-1 assume !(1 == ~T9_E~0); 42225#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 43163#L1075-1 assume !(1 == ~E_2~0); 48475#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 42859#L1085-1 assume !(1 == ~E_4~0); 42860#L1090-1 assume !(1 == ~E_5~0); 43107#L1095-1 assume !(1 == ~E_6~0); 43166#L1100-1 assume !(1 == ~E_7~0); 50686#L1105-1 assume !(1 == ~E_8~0); 42129#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 42130#L1115-1 assume { :end_inline_reset_delta_events } true; 49738#L1396-2 [2023-11-19 08:04:36,246 INFO L750 eck$LassoCheckResult]: Loop: 49738#L1396-2 assume !false; 49739#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49719#L897-1 assume !false; 49720#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 43367#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 43358#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 43349#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 43350#L766 assume !(0 != eval_~tmp~0#1); 50575#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50573#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50571#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50569#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50566#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50567#L932-3 assume !(0 == ~T3_E~0); 51295#L937-3 assume !(0 == ~T4_E~0); 51294#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51293#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 51292#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 51291#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51290#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 51289#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 51288#L972-3 assume !(0 == ~E_2~0); 51287#L977-3 assume !(0 == ~E_3~0); 51286#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 51285#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51284#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51283#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 51282#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 51281#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 51280#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51279#L443-30 assume !(1 == ~m_pc~0); 51278#L443-32 is_master_triggered_~__retres1~0#1 := 0; 51277#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51276#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 51275#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51274#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51273#L462-30 assume !(1 == ~t1_pc~0); 51272#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 51271#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51270#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 51269#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 51268#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51267#L481-30 assume 1 == ~t2_pc~0; 51265#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51264#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51263#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 51262#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 51261#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51260#L500-30 assume 1 == ~t3_pc~0; 51258#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 51257#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51256#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 51255#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51254#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51253#L519-30 assume 1 == ~t4_pc~0; 51251#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51250#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51249#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 51248#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51247#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51246#L538-30 assume 1 == ~t5_pc~0; 51244#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 51243#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51242#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51241#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 51240#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 51239#L557-30 assume !(1 == ~t6_pc~0); 51237#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 51236#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 51235#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 51234#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 51233#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51232#L576-30 assume 1 == ~t7_pc~0; 51230#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 51229#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 51228#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51227#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 51226#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 51225#L595-30 assume !(1 == ~t8_pc~0); 51223#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 51222#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51221#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51220#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 51219#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51218#L614-30 assume 1 == ~t9_pc~0; 51216#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 51215#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51214#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51213#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51212#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51211#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 51210#L1025-5 assume !(1 == ~T1_E~0); 51209#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47105#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50389#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50387#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50388#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 51157#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 51156#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50381#L1065-3 assume !(1 == ~T9_E~0); 50382#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50377#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50378#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 47079#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50375#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50371#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50369#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50367#L1105-3 assume !(1 == ~E_8~0); 50365#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 50362#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 50363#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 50951#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 50950#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 50943#L1415 assume !(0 == start_simulation_~tmp~3#1); 50249#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 50250#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 50844#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 49803#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 49804#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49799#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49765#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 49766#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 49738#L1396-2 [2023-11-19 08:04:36,247 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:36,247 INFO L85 PathProgramCache]: Analyzing trace with hash 212114046, now seen corresponding path program 1 times [2023-11-19 08:04:36,247 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:36,250 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2063150720] [2023-11-19 08:04:36,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:36,250 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:36,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:36,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:36,335 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:36,336 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2063150720] [2023-11-19 08:04:36,336 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2063150720] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:36,336 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:36,336 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:36,337 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1008718005] [2023-11-19 08:04:36,337 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:36,337 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:04:36,338 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:36,338 INFO L85 PathProgramCache]: Analyzing trace with hash 1380728303, now seen corresponding path program 1 times [2023-11-19 08:04:36,338 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:36,338 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1488408635] [2023-11-19 08:04:36,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:36,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:36,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:36,393 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:36,393 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:36,393 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1488408635] [2023-11-19 08:04:36,394 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1488408635] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:36,394 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:36,394 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:36,394 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1439925834] [2023-11-19 08:04:36,394 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:36,395 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:04:36,395 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:04:36,395 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 08:04:36,396 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 08:04:36,396 INFO L87 Difference]: Start difference. First operand 10472 states and 15278 transitions. cyclomatic complexity: 4814 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:36,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:04:36,907 INFO L93 Difference]: Finished difference Result 29655 states and 42845 transitions. [2023-11-19 08:04:36,908 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29655 states and 42845 transitions. [2023-11-19 08:04:37,083 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28790 [2023-11-19 08:04:37,201 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29655 states to 29655 states and 42845 transitions. [2023-11-19 08:04:37,201 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29655 [2023-11-19 08:04:37,233 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29655 [2023-11-19 08:04:37,233 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29655 states and 42845 transitions. [2023-11-19 08:04:37,263 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:04:37,264 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29655 states and 42845 transitions. [2023-11-19 08:04:37,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29655 states and 42845 transitions. [2023-11-19 08:04:37,949 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29655 to 28411. [2023-11-19 08:04:38,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28411 states, 28411 states have (on average 1.4484882615888213) internal successors, (41153), 28410 states have internal predecessors, (41153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:38,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28411 states to 28411 states and 41153 transitions. [2023-11-19 08:04:38,125 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28411 states and 41153 transitions. [2023-11-19 08:04:38,126 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 08:04:38,127 INFO L428 stractBuchiCegarLoop]: Abstraction has 28411 states and 41153 transitions. [2023-11-19 08:04:38,127 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-19 08:04:38,127 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28411 states and 41153 transitions. [2023-11-19 08:04:38,387 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28190 [2023-11-19 08:04:38,387 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:04:38,388 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:04:38,390 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:38,390 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:38,391 INFO L748 eck$LassoCheckResult]: Stem: 82394#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 82395#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 83348#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 83349#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 83275#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 83276#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 83244#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 82987#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 82988#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 82748#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 82749#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 83408#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 83228#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 82825#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 82557#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 82558#L922 assume !(0 == ~M_E~0); 83526#L922-2 assume !(0 == ~T1_E~0); 83527#L927-1 assume !(0 == ~T2_E~0); 83066#L932-1 assume !(0 == ~T3_E~0); 82912#L937-1 assume !(0 == ~T4_E~0); 82913#L942-1 assume !(0 == ~T5_E~0); 82986#L947-1 assume !(0 == ~T6_E~0); 83070#L952-1 assume !(0 == ~T7_E~0); 83071#L957-1 assume !(0 == ~T8_E~0); 83156#L962-1 assume !(0 == ~T9_E~0); 82885#L967-1 assume !(0 == ~E_1~0); 82886#L972-1 assume !(0 == ~E_2~0); 83250#L977-1 assume !(0 == ~E_3~0); 83251#L982-1 assume !(0 == ~E_4~0); 82324#L987-1 assume !(0 == ~E_5~0); 82325#L992-1 assume !(0 == ~E_6~0); 82329#L997-1 assume !(0 == ~E_7~0); 82796#L1002-1 assume !(0 == ~E_8~0); 82781#L1007-1 assume !(0 == ~E_9~0); 82115#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82116#L443 assume !(1 == ~m_pc~0); 83093#L443-2 is_master_triggered_~__retres1~0#1 := 0; 83080#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 83081#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 82490#L1140 assume !(0 != activate_threads_~tmp~1#1); 82220#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 82221#L462 assume !(1 == ~t1_pc~0); 82902#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 82903#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82157#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 82158#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 82724#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82725#L481 assume !(1 == ~t2_pc~0); 82483#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 82482#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82624#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 82584#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 82585#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82694#L500 assume !(1 == ~t3_pc~0); 83334#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 83297#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82122#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 82123#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 82117#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82118#L519 assume 1 == ~t4_pc~0; 82427#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 82428#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82222#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 82223#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 82530#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 82285#L538 assume !(1 == ~t5_pc~0); 82286#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 82184#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82185#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 82468#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 82469#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 83136#L557 assume 1 == ~t6_pc~0; 82869#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 82505#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 82605#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 82531#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 82532#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 83471#L576 assume !(1 == ~t7_pc~0); 82494#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 82495#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 82868#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 83518#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 83213#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 82627#L595 assume 1 == ~t8_pc~0; 82628#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 83236#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 83143#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 83016#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 83017#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 82417#L614 assume !(1 == ~t9_pc~0); 82418#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 82311#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 82312#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 82665#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 82587#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82588#L1025 assume !(1 == ~M_E~0); 82893#L1025-2 assume !(1 == ~T1_E~0); 82963#L1030-1 assume !(1 == ~T2_E~0); 83126#L1035-1 assume !(1 == ~T3_E~0); 82579#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 82580#L1045-1 assume !(1 == ~T5_E~0); 105215#L1050-1 assume !(1 == ~T6_E~0); 105214#L1055-1 assume !(1 == ~T7_E~0); 105213#L1060-1 assume !(1 == ~T8_E~0); 105212#L1065-1 assume !(1 == ~T9_E~0); 105211#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 105210#L1075-1 assume !(1 == ~E_2~0); 105209#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 83061#L1085-1 assume !(1 == ~E_4~0); 83062#L1090-1 assume !(1 == ~E_5~0); 83392#L1095-1 assume !(1 == ~E_6~0); 83105#L1100-1 assume !(1 == ~E_7~0); 83106#L1105-1 assume !(1 == ~E_8~0); 82266#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 82267#L1115-1 assume { :end_inline_reset_delta_events } true; 82521#L1396-2 [2023-11-19 08:04:38,392 INFO L750 eck$LassoCheckResult]: Loop: 82521#L1396-2 assume !false; 82522#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 83468#L897-1 assume !false; 83469#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 83277#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 82140#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 82141#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 82651#L766 assume !(0 != eval_~tmp~0#1); 83376#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 107241#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 107238#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 107236#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 107233#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 107230#L932-3 assume !(0 == ~T3_E~0); 107227#L937-3 assume !(0 == ~T4_E~0); 107224#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 107220#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 107216#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 107213#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 107210#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 107207#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 107204#L972-3 assume !(0 == ~E_2~0); 107201#L977-3 assume !(0 == ~E_3~0); 107198#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 107195#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 107192#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 107189#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 107186#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 107182#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 107178#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 107175#L443-30 assume !(1 == ~m_pc~0); 107172#L443-32 is_master_triggered_~__retres1~0#1 := 0; 107169#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 107166#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 107162#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 107158#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 107155#L462-30 assume !(1 == ~t1_pc~0); 107152#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 107149#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 107146#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 107145#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 107144#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 107143#L481-30 assume 1 == ~t2_pc~0; 107141#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 107140#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 107139#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 82396#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 82397#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82697#L500-30 assume !(1 == ~t3_pc~0); 83088#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 82807#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82808#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 82874#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 82680#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82681#L519-30 assume !(1 == ~t4_pc~0); 82901#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 82875#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82876#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 82887#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 82888#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 83041#L538-30 assume 1 == ~t5_pc~0; 82307#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 82308#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82660#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 83022#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 82390#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 82391#L557-30 assume 1 == ~t6_pc~0; 82105#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 82107#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 82226#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 82227#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 82415#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 82416#L576-30 assume 1 == ~t7_pc~0; 83026#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 82176#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 82840#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 83102#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 82578#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 82537#L595-30 assume 1 == ~t8_pc~0; 82539#L596-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 82470#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 82471#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 83390#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 83391#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 83477#L614-30 assume 1 == ~t9_pc~0; 82474#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 82475#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 82144#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 82145#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 82300#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83008#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 82726#L1025-5 assume !(1 == ~T1_E~0); 82727#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 82965#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 83411#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 83519#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 83400#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 83235#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 82190#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 82191#L1065-3 assume !(1 == ~T9_E~0); 83259#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 83044#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 83045#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 83412#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 83245#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 83246#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 83281#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 83282#L1105-3 assume !(1 == ~E_8~0); 82347#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 82348#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 83325#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 82356#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 82357#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 83254#L1415 assume !(0 == start_simulation_~tmp~3#1); 82971#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 83498#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 82254#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 82155#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 82156#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 83552#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 83553#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 109153#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 82521#L1396-2 [2023-11-19 08:04:38,393 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:38,393 INFO L85 PathProgramCache]: Analyzing trace with hash 2031839965, now seen corresponding path program 1 times [2023-11-19 08:04:38,394 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:38,394 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [276458422] [2023-11-19 08:04:38,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:38,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:38,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:38,476 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:38,476 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:38,476 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [276458422] [2023-11-19 08:04:38,476 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [276458422] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:38,477 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:38,477 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 08:04:38,478 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [260192594] [2023-11-19 08:04:38,478 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:38,478 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:04:38,479 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:38,479 INFO L85 PathProgramCache]: Analyzing trace with hash 1858045743, now seen corresponding path program 1 times [2023-11-19 08:04:38,479 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:38,480 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [501138948] [2023-11-19 08:04:38,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:38,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:38,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:38,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:38,545 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:38,545 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [501138948] [2023-11-19 08:04:38,545 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [501138948] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:38,546 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:38,546 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:38,546 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1502955709] [2023-11-19 08:04:38,546 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:38,547 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:04:38,547 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:04:38,548 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:04:38,548 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:04:38,549 INFO L87 Difference]: Start difference. First operand 28411 states and 41153 transitions. cyclomatic complexity: 12758 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:39,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:04:39,122 INFO L93 Difference]: Finished difference Result 53826 states and 77683 transitions. [2023-11-19 08:04:39,122 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53826 states and 77683 transitions. [2023-11-19 08:04:39,576 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 53474 [2023-11-19 08:04:39,801 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53826 states to 53826 states and 77683 transitions. [2023-11-19 08:04:39,801 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53826 [2023-11-19 08:04:39,858 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53826 [2023-11-19 08:04:39,858 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53826 states and 77683 transitions. [2023-11-19 08:04:40,003 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:04:40,003 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53826 states and 77683 transitions. [2023-11-19 08:04:40,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53826 states and 77683 transitions. [2023-11-19 08:04:41,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53826 to 53754. [2023-11-19 08:04:41,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53754 states, 53754 states have (on average 1.4438181344644119) internal successors, (77611), 53753 states have internal predecessors, (77611), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:41,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53754 states to 53754 states and 77611 transitions. [2023-11-19 08:04:41,545 INFO L240 hiAutomatonCegarLoop]: Abstraction has 53754 states and 77611 transitions. [2023-11-19 08:04:41,545 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:04:41,547 INFO L428 stractBuchiCegarLoop]: Abstraction has 53754 states and 77611 transitions. [2023-11-19 08:04:41,547 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-19 08:04:41,547 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53754 states and 77611 transitions. [2023-11-19 08:04:41,913 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 53402 [2023-11-19 08:04:41,914 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:04:41,914 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:04:41,916 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:41,916 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:41,917 INFO L748 eck$LassoCheckResult]: Stem: 164633#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 164634#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 165515#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 165516#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 165451#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 165452#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 165425#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 165190#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 165191#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 164969#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 164970#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 165554#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 165413#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 165039#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 164788#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 164789#L922 assume !(0 == ~M_E~0); 165629#L922-2 assume !(0 == ~T1_E~0); 165630#L927-1 assume !(0 == ~T2_E~0); 165270#L932-1 assume !(0 == ~T3_E~0); 165123#L937-1 assume !(0 == ~T4_E~0); 165124#L942-1 assume !(0 == ~T5_E~0); 165189#L947-1 assume !(0 == ~T6_E~0); 165275#L952-1 assume !(0 == ~T7_E~0); 165276#L957-1 assume !(0 == ~T8_E~0); 165351#L962-1 assume !(0 == ~T9_E~0); 165098#L967-1 assume !(0 == ~E_1~0); 165099#L972-1 assume !(0 == ~E_2~0); 165434#L977-1 assume !(0 == ~E_3~0); 165435#L982-1 assume !(0 == ~E_4~0); 164567#L987-1 assume !(0 == ~E_5~0); 164568#L992-1 assume !(0 == ~E_6~0); 164572#L997-1 assume !(0 == ~E_7~0); 165015#L1002-1 assume !(0 == ~E_8~0); 165002#L1007-1 assume !(0 == ~E_9~0); 164359#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 164360#L443 assume !(1 == ~m_pc~0); 165296#L443-2 is_master_triggered_~__retres1~0#1 := 0; 165282#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 165283#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 164723#L1140 assume !(0 != activate_threads_~tmp~1#1); 164464#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 164465#L462 assume !(1 == ~t1_pc~0); 165113#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 165114#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 164403#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 164404#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 164946#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 164947#L481 assume !(1 == ~t2_pc~0); 164717#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 164716#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 164850#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 164812#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 164813#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 164917#L500 assume !(1 == ~t3_pc~0); 165503#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 165469#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 164366#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 164367#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 164364#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 164365#L519 assume !(1 == ~t4_pc~0); 165178#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 164914#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 164466#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 164467#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 164761#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 164528#L538 assume !(1 == ~t5_pc~0); 164529#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 164428#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 164429#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 164703#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 164704#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 165334#L557 assume 1 == ~t6_pc~0; 165081#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 164738#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 164833#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 164762#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 164763#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 165594#L576 assume !(1 == ~t7_pc~0); 164727#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 164728#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 165080#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 165624#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 165401#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 164853#L595 assume 1 == ~t8_pc~0; 164854#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 165420#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 165338#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 165218#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 165219#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 164656#L614 assume !(1 == ~t9_pc~0); 164657#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 164554#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 164555#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 164889#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 164815#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 164816#L1025 assume !(1 == ~M_E~0); 165106#L1025-2 assume !(1 == ~T1_E~0); 165168#L1030-1 assume !(1 == ~T2_E~0); 165324#L1035-1 assume !(1 == ~T3_E~0); 165473#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 177241#L1045-1 assume !(1 == ~T5_E~0); 177253#L1050-1 assume !(1 == ~T6_E~0); 177252#L1055-1 assume !(1 == ~T7_E~0); 177251#L1060-1 assume !(1 == ~T8_E~0); 177250#L1065-1 assume !(1 == ~T9_E~0); 177249#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 177248#L1075-1 assume !(1 == ~E_2~0); 177223#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 177221#L1085-1 assume !(1 == ~E_4~0); 177219#L1090-1 assume !(1 == ~E_5~0); 177217#L1095-1 assume !(1 == ~E_6~0); 177215#L1100-1 assume !(1 == ~E_7~0); 177213#L1105-1 assume !(1 == ~E_8~0); 177211#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 175470#L1115-1 assume { :end_inline_reset_delta_events } true; 175468#L1396-2 [2023-11-19 08:04:41,917 INFO L750 eck$LassoCheckResult]: Loop: 175468#L1396-2 assume !false; 175466#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 175461#L897-1 assume !false; 175460#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 175455#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 175444#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 175443#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 175440#L766 assume !(0 != eval_~tmp~0#1); 175441#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 165046#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 164996#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 164997#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 164695#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 164696#L932-3 assume !(0 == ~T3_E~0); 217519#L937-3 assume !(0 == ~T4_E~0); 217518#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 217517#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 217516#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 217515#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 217513#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 217511#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 217509#L972-3 assume !(0 == ~E_2~0); 217507#L977-3 assume !(0 == ~E_3~0); 217505#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 217503#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 217501#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 217499#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 217497#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 217495#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 217493#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 164873#L443-30 assume !(1 == ~m_pc~0); 164874#L443-32 is_master_triggered_~__retres1~0#1 := 0; 217542#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 217540#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 217538#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 217536#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 214622#L462-30 assume !(1 == ~t1_pc~0); 214621#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 214620#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 214619#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 214618#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 214617#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 214616#L481-30 assume !(1 == ~t2_pc~0); 214615#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 214613#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 214612#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 214611#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 214610#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 214609#L500-30 assume !(1 == ~t3_pc~0); 214608#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 214607#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 214606#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 214605#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 214604#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 214603#L519-30 assume !(1 == ~t4_pc~0); 214602#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 214601#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 214600#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 214599#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 214598#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 214597#L538-30 assume !(1 == ~t5_pc~0); 214595#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 214593#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 214592#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 214591#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 214590#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 214589#L557-30 assume !(1 == ~t6_pc~0); 177146#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 177144#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 177142#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 177140#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 177138#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 177136#L576-30 assume 1 == ~t7_pc~0; 177132#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 177130#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 177128#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 177126#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 177124#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 177122#L595-30 assume !(1 == ~t8_pc~0); 177118#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 177116#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 177114#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 177112#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 177110#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 177108#L614-30 assume 1 == ~t9_pc~0; 177104#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 177102#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 177100#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 177098#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 177096#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 177094#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 177092#L1025-5 assume !(1 == ~T1_E~0); 177091#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 175758#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 177087#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 177086#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 177084#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 177082#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 177080#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 177078#L1065-3 assume !(1 == ~T9_E~0); 177076#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 177074#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 177073#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 177070#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 177069#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 177068#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 177066#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 177067#L1105-3 assume !(1 == ~E_8~0); 177062#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 177063#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 177058#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 177049#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 177042#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 177043#L1415 assume !(0 == start_simulation_~tmp~3#1); 175505#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 175506#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 175484#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 175481#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 175482#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 175476#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 175473#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 175471#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 175468#L1396-2 [2023-11-19 08:04:41,918 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:41,919 INFO L85 PathProgramCache]: Analyzing trace with hash 2039590524, now seen corresponding path program 1 times [2023-11-19 08:04:41,919 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:41,919 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [341399206] [2023-11-19 08:04:41,919 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:41,920 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:41,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:42,034 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:42,035 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:42,036 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [341399206] [2023-11-19 08:04:42,036 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [341399206] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:42,036 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:42,037 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 08:04:42,037 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1152348287] [2023-11-19 08:04:42,037 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:42,040 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:04:42,041 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:42,041 INFO L85 PathProgramCache]: Analyzing trace with hash -867619861, now seen corresponding path program 1 times [2023-11-19 08:04:42,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:42,041 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1321542114] [2023-11-19 08:04:42,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:42,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:42,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:42,101 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:42,102 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:42,102 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1321542114] [2023-11-19 08:04:42,102 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1321542114] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:42,102 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:42,103 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:42,103 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2020939161] [2023-11-19 08:04:42,104 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:42,104 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:04:42,104 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:04:42,105 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 08:04:42,105 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 08:04:42,106 INFO L87 Difference]: Start difference. First operand 53754 states and 77611 transitions. cyclomatic complexity: 23889 Second operand has 5 states, 5 states have (on average 23.0) internal successors, (115), 5 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:43,158 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:04:43,158 INFO L93 Difference]: Finished difference Result 122652 states and 175606 transitions. [2023-11-19 08:04:43,158 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122652 states and 175606 transitions. [2023-11-19 08:04:44,156 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 121988 [2023-11-19 08:04:44,906 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122652 states to 122652 states and 175606 transitions. [2023-11-19 08:04:44,907 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 122652 [2023-11-19 08:04:45,029 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 122652 [2023-11-19 08:04:45,029 INFO L73 IsDeterministic]: Start isDeterministic. Operand 122652 states and 175606 transitions. [2023-11-19 08:04:45,128 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:04:45,129 INFO L218 hiAutomatonCegarLoop]: Abstraction has 122652 states and 175606 transitions. [2023-11-19 08:04:45,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122652 states and 175606 transitions. [2023-11-19 08:04:46,456 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122652 to 55509. [2023-11-19 08:04:46,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55509 states, 55509 states have (on average 1.4297861608027527) internal successors, (79366), 55508 states have internal predecessors, (79366), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:46,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55509 states to 55509 states and 79366 transitions. [2023-11-19 08:04:46,704 INFO L240 hiAutomatonCegarLoop]: Abstraction has 55509 states and 79366 transitions. [2023-11-19 08:04:46,705 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-19 08:04:46,706 INFO L428 stractBuchiCegarLoop]: Abstraction has 55509 states and 79366 transitions. [2023-11-19 08:04:46,706 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-19 08:04:46,706 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55509 states and 79366 transitions. [2023-11-19 08:04:46,927 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 55154 [2023-11-19 08:04:46,928 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:04:46,928 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:04:46,932 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:46,932 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:46,933 INFO L748 eck$LassoCheckResult]: Stem: 341057#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 341058#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 341911#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 341912#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 341851#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 341852#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 341825#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 341604#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 341605#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 341396#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 341397#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 341942#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 341811#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 341462#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 341215#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 341216#L922 assume !(0 == ~M_E~0); 342018#L922-2 assume !(0 == ~T1_E~0); 342019#L927-1 assume !(0 == ~T2_E~0); 341672#L932-1 assume !(0 == ~T3_E~0); 341538#L937-1 assume !(0 == ~T4_E~0); 341539#L942-1 assume !(0 == ~T5_E~0); 341603#L947-1 assume !(0 == ~T6_E~0); 341676#L952-1 assume !(0 == ~T7_E~0); 341677#L957-1 assume !(0 == ~T8_E~0); 341760#L962-1 assume !(0 == ~T9_E~0); 341517#L967-1 assume !(0 == ~E_1~0); 341518#L972-1 assume !(0 == ~E_2~0); 341832#L977-1 assume !(0 == ~E_3~0); 341833#L982-1 assume !(0 == ~E_4~0); 340988#L987-1 assume !(0 == ~E_5~0); 340989#L992-1 assume !(0 == ~E_6~0); 340993#L997-1 assume !(0 == ~E_7~0); 341439#L1002-1 assume !(0 == ~E_8~0); 341424#L1007-1 assume !(0 == ~E_9~0); 340778#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 340779#L443 assume !(1 == ~m_pc~0); 341702#L443-2 is_master_triggered_~__retres1~0#1 := 0; 341687#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 341688#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 341150#L1140 assume !(0 != activate_threads_~tmp~1#1); 340885#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 340886#L462 assume !(1 == ~t1_pc~0); 341530#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 341531#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 340822#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 340823#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 341375#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 341376#L481 assume !(1 == ~t2_pc~0); 341144#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 341143#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 341278#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 341238#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 341239#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 341344#L500 assume !(1 == ~t3_pc~0); 341900#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 341871#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 340785#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 340786#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 340783#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 340784#L519 assume !(1 == ~t4_pc~0); 341591#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 341341#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 340887#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 340888#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 341188#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 340949#L538 assume !(1 == ~t5_pc~0); 340950#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 340847#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 340848#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 341129#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 341130#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 341742#L557 assume 1 == ~t6_pc~0; 341502#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 341165#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 341259#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 341189#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 341190#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 341991#L576 assume !(1 == ~t7_pc~0); 341154#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 341155#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 341501#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 342013#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 341802#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 341281#L595 assume 1 == ~t8_pc~0; 341282#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 341819#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 341746#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 341628#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 341629#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 341080#L614 assume !(1 == ~t9_pc~0); 341081#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 340975#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 340976#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 341318#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 341241#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 341242#L1025 assume !(1 == ~M_E~0); 341523#L1025-2 assume !(1 == ~T1_E~0); 341584#L1030-1 assume !(1 == ~T2_E~0); 341731#L1035-1 assume !(1 == ~T3_E~0); 341875#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 367608#L1045-1 assume !(1 == ~T5_E~0); 367604#L1050-1 assume !(1 == ~T6_E~0); 367599#L1055-1 assume !(1 == ~T7_E~0); 367595#L1060-1 assume !(1 == ~T8_E~0); 367588#L1065-1 assume !(1 == ~T9_E~0); 367584#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 367580#L1075-1 assume !(1 == ~E_2~0); 367576#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 341667#L1085-1 assume !(1 == ~E_4~0); 341668#L1090-1 assume !(1 == ~E_5~0); 341997#L1095-1 assume !(1 == ~E_6~0); 341998#L1100-1 assume !(1 == ~E_7~0); 341718#L1105-1 assume !(1 == ~E_8~0); 341719#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 341289#L1115-1 assume { :end_inline_reset_delta_events } true; 341290#L1396-2 [2023-11-19 08:04:46,934 INFO L750 eck$LassoCheckResult]: Loop: 341290#L1396-2 assume !false; 376902#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 376895#L897-1 assume !false; 376890#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 376739#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 376706#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 376702#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 376697#L766 assume !(0 != eval_~tmp~0#1); 376698#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 377934#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 377933#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 377932#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 377931#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 377930#L932-3 assume !(0 == ~T3_E~0); 377929#L937-3 assume !(0 == ~T4_E~0); 377928#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 377927#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 377926#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 377925#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 377924#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 377923#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 377922#L972-3 assume !(0 == ~E_2~0); 377921#L977-3 assume !(0 == ~E_3~0); 377920#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 377919#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 377918#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 377917#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 377916#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 377915#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 377914#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 377913#L443-30 assume !(1 == ~m_pc~0); 377912#L443-32 is_master_triggered_~__retres1~0#1 := 0; 377911#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 377910#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 377909#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 377908#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 377907#L462-30 assume !(1 == ~t1_pc~0); 377906#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 377905#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 377904#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 377903#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 377902#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 377901#L481-30 assume !(1 == ~t2_pc~0); 377900#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 377898#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 377897#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 377896#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 377895#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 377894#L500-30 assume !(1 == ~t3_pc~0); 377893#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 377892#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 377891#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 377890#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 377889#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 377888#L519-30 assume !(1 == ~t4_pc~0); 377887#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 377886#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 377885#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 377884#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 377883#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 377882#L538-30 assume !(1 == ~t5_pc~0); 377881#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 377879#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 377877#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 377875#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 377867#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 377866#L557-30 assume 1 == ~t6_pc~0; 377776#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 377717#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 377623#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 377621#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 377619#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 377616#L576-30 assume 1 == ~t7_pc~0; 377613#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 377611#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 377609#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 377607#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 377605#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 377602#L595-30 assume 1 == ~t8_pc~0; 377600#L596-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 377597#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 377595#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 377593#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 377591#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 377588#L614-30 assume 1 == ~t9_pc~0; 377585#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 377566#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 377558#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 377550#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 377293#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 377292#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 377290#L1025-5 assume !(1 == ~T1_E~0); 377288#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 367639#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 377285#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 370316#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 377282#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 377280#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 377279#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 377277#L1065-3 assume !(1 == ~T9_E~0); 377275#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 377273#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 377271#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 367611#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 377268#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 377267#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 377265#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 377263#L1105-3 assume !(1 == ~E_8~0); 377226#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 377223#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 377171#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 377160#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 377158#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 377120#L1415 assume !(0 == start_simulation_~tmp~3#1); 377100#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 376970#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 376962#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 376960#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 376956#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 376954#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 376952#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 376950#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 341290#L1396-2 [2023-11-19 08:04:46,934 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:46,934 INFO L85 PathProgramCache]: Analyzing trace with hash -327104070, now seen corresponding path program 1 times [2023-11-19 08:04:46,935 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:46,935 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1554081873] [2023-11-19 08:04:46,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:46,935 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:46,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:47,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:47,041 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:47,041 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1554081873] [2023-11-19 08:04:47,041 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1554081873] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:47,041 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:47,042 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:47,042 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [181018888] [2023-11-19 08:04:47,042 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:47,043 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:04:47,043 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:47,044 INFO L85 PathProgramCache]: Analyzing trace with hash 833461355, now seen corresponding path program 1 times [2023-11-19 08:04:47,044 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:47,044 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [647585560] [2023-11-19 08:04:47,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:47,045 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:47,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:47,106 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:47,106 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:47,106 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [647585560] [2023-11-19 08:04:47,107 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [647585560] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:47,107 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:47,107 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:47,107 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [953876056] [2023-11-19 08:04:47,107 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:47,108 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:04:47,108 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:04:47,109 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 08:04:47,109 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 08:04:47,109 INFO L87 Difference]: Start difference. First operand 55509 states and 79366 transitions. cyclomatic complexity: 23889 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:48,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:04:48,662 INFO L93 Difference]: Finished difference Result 156232 states and 221963 transitions. [2023-11-19 08:04:48,663 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 156232 states and 221963 transitions. [2023-11-19 08:04:49,254 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 152758 [2023-11-19 08:04:50,380 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 156232 states to 156232 states and 221963 transitions. [2023-11-19 08:04:50,381 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 156232 [2023-11-19 08:04:50,485 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 156232 [2023-11-19 08:04:50,485 INFO L73 IsDeterministic]: Start isDeterministic. Operand 156232 states and 221963 transitions. [2023-11-19 08:04:50,678 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:04:50,679 INFO L218 hiAutomatonCegarLoop]: Abstraction has 156232 states and 221963 transitions. [2023-11-19 08:04:50,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156232 states and 221963 transitions. [2023-11-19 08:04:52,586 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156232 to 151328. [2023-11-19 08:04:52,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 151328 states, 151328 states have (on average 1.4239466589130894) internal successors, (215483), 151327 states have internal predecessors, (215483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:53,799 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151328 states to 151328 states and 215483 transitions. [2023-11-19 08:04:53,799 INFO L240 hiAutomatonCegarLoop]: Abstraction has 151328 states and 215483 transitions. [2023-11-19 08:04:53,800 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 08:04:53,800 INFO L428 stractBuchiCegarLoop]: Abstraction has 151328 states and 215483 transitions. [2023-11-19 08:04:53,800 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-19 08:04:53,801 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 151328 states and 215483 transitions. [2023-11-19 08:04:54,196 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 150670 [2023-11-19 08:04:54,196 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:04:54,197 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:04:54,199 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:54,199 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:04:54,199 INFO L748 eck$LassoCheckResult]: Stem: 552805#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 552806#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 553737#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 553738#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 553660#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 553661#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 553630#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 553384#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 553385#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 553153#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 553154#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 553772#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 553618#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 553224#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 552969#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 552970#L922 assume !(0 == ~M_E~0); 553853#L922-2 assume !(0 == ~T1_E~0); 553854#L927-1 assume !(0 == ~T2_E~0); 553460#L932-1 assume !(0 == ~T3_E~0); 553305#L937-1 assume !(0 == ~T4_E~0); 553306#L942-1 assume !(0 == ~T5_E~0); 553383#L947-1 assume !(0 == ~T6_E~0); 553465#L952-1 assume !(0 == ~T7_E~0); 553466#L957-1 assume !(0 == ~T8_E~0); 553552#L962-1 assume !(0 == ~T9_E~0); 553278#L967-1 assume !(0 == ~E_1~0); 553279#L972-1 assume !(0 == ~E_2~0); 553639#L977-1 assume !(0 == ~E_3~0); 553640#L982-1 assume !(0 == ~E_4~0); 552735#L987-1 assume !(0 == ~E_5~0); 552736#L992-1 assume !(0 == ~E_6~0); 552742#L997-1 assume !(0 == ~E_7~0); 553197#L1002-1 assume !(0 == ~E_8~0); 553186#L1007-1 assume !(0 == ~E_9~0); 552529#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 552530#L443 assume !(1 == ~m_pc~0); 553487#L443-2 is_master_triggered_~__retres1~0#1 := 0; 553473#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 553474#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 552902#L1140 assume !(0 != activate_threads_~tmp~1#1); 552635#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 552636#L462 assume !(1 == ~t1_pc~0); 553295#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 553296#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 552573#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 552574#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 553129#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 553130#L481 assume !(1 == ~t2_pc~0); 552895#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 552894#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 553033#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 552993#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 552994#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 553097#L500 assume !(1 == ~t3_pc~0); 553724#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 553684#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 552536#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 552537#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 552534#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 552535#L519 assume !(1 == ~t4_pc~0); 553367#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 553096#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 552637#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 552638#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 552940#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 552699#L538 assume !(1 == ~t5_pc~0); 552700#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 552596#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 552597#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 552880#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 552881#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 553533#L557 assume !(1 == ~t6_pc~0); 552917#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 552918#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 553014#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 552941#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 552942#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 553815#L576 assume !(1 == ~t7_pc~0); 552906#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 552907#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 553265#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 553850#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 553609#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 553034#L595 assume 1 == ~t8_pc~0; 553035#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 553626#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 553538#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 553413#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 553414#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 552831#L614 assume !(1 == ~t9_pc~0); 552832#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 552725#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 552726#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 553072#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 552996#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 552997#L1025 assume !(1 == ~M_E~0); 553286#L1025-2 assume !(1 == ~T1_E~0); 553355#L1030-1 assume !(1 == ~T2_E~0); 553519#L1035-1 assume !(1 == ~T3_E~0); 553692#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 553666#L1045-1 assume !(1 == ~T5_E~0); 553667#L1050-1 assume !(1 == ~T6_E~0); 553087#L1055-1 assume !(1 == ~T7_E~0); 553088#L1060-1 assume !(1 == ~T8_E~0); 552774#L1065-1 assume !(1 == ~T9_E~0); 552775#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 553468#L1075-1 assume !(1 == ~E_2~0); 553469#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 553455#L1085-1 assume !(1 == ~E_4~0); 553456#L1090-1 assume !(1 == ~E_5~0); 553765#L1095-1 assume !(1 == ~E_6~0); 553499#L1100-1 assume !(1 == ~E_7~0); 553500#L1105-1 assume !(1 == ~E_8~0); 552681#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 552682#L1115-1 assume { :end_inline_reset_delta_events } true; 553045#L1396-2 [2023-11-19 08:04:54,200 INFO L750 eck$LassoCheckResult]: Loop: 553045#L1396-2 assume !false; 553825#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 553771#L897-1 assume !false; 553813#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 553662#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 552552#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 552553#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 553059#L766 assume !(0 != eval_~tmp~0#1); 553753#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 688115#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 688113#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 688111#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 688109#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 688106#L932-3 assume !(0 == ~T3_E~0); 688104#L937-3 assume !(0 == ~T4_E~0); 688103#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 688102#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 688101#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 688100#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 688099#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 688098#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 688097#L972-3 assume !(0 == ~E_2~0); 688096#L977-3 assume !(0 == ~E_3~0); 688094#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 688092#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 688090#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 688088#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 688086#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 688084#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 688082#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 688081#L443-30 assume !(1 == ~m_pc~0); 688079#L443-32 is_master_triggered_~__retres1~0#1 := 0; 688077#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 688075#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 688073#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 688071#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 688068#L462-30 assume !(1 == ~t1_pc~0); 688066#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 688064#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 688062#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 688060#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 688058#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 688056#L481-30 assume !(1 == ~t2_pc~0); 688054#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 688051#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 688049#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 688047#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 688045#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 688043#L500-30 assume !(1 == ~t3_pc~0); 688041#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 688039#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 688037#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 688035#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 688033#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 688030#L519-30 assume !(1 == ~t4_pc~0); 688027#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 688024#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 688021#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 688019#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 553437#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 553438#L538-30 assume 1 == ~t5_pc~0; 552721#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 552722#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 553067#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 553419#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 552801#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 552802#L557-30 assume !(1 == ~t6_pc~0); 552814#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 553212#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 552641#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 552642#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 552829#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 552830#L576-30 assume 1 == ~t7_pc~0; 553423#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 552595#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 553241#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 553495#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 552990#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 552949#L595-30 assume !(1 == ~t8_pc~0); 552950#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 552882#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 552883#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 553762#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 553763#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 553818#L614-30 assume 1 == ~t9_pc~0; 552888#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 552889#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 552561#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 552562#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 552714#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 553403#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 553131#L1025-5 assume !(1 == ~T1_E~0); 553132#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 553358#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 553775#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 553851#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 553769#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 553624#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 552604#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 552605#L1065-3 assume !(1 == ~T9_E~0); 553647#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 553441#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 553442#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 553776#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 553632#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 553633#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 553664#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 553665#L1105-3 assume !(1 == ~E_8~0); 552760#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 552761#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 553695#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 552615#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 552769#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 552971#L1415 assume !(0 == start_simulation_~tmp~3#1); 553642#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 691986#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 691978#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 691976#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 691974#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 691972#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 691971#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 691970#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 553045#L1396-2 [2023-11-19 08:04:54,201 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:54,201 INFO L85 PathProgramCache]: Analyzing trace with hash -1602206759, now seen corresponding path program 1 times [2023-11-19 08:04:54,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:54,201 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1785341010] [2023-11-19 08:04:54,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:54,202 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:54,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:54,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:54,275 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:54,275 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1785341010] [2023-11-19 08:04:54,276 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1785341010] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:54,276 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:54,276 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 08:04:54,276 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1479847920] [2023-11-19 08:04:54,277 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:54,277 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:04:54,277 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:04:54,278 INFO L85 PathProgramCache]: Analyzing trace with hash 1607621516, now seen corresponding path program 1 times [2023-11-19 08:04:54,278 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:04:54,278 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [847369439] [2023-11-19 08:04:54,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:04:54,278 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:04:54,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:04:54,343 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:04:54,343 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:04:54,343 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [847369439] [2023-11-19 08:04:54,344 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [847369439] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:04:54,344 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:04:54,344 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:04:54,344 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1326454468] [2023-11-19 08:04:54,344 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:04:54,345 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:04:54,345 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:04:54,345 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 08:04:54,346 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 08:04:54,346 INFO L87 Difference]: Start difference. First operand 151328 states and 215483 transitions. cyclomatic complexity: 64219 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:04:56,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:04:56,005 INFO L93 Difference]: Finished difference Result 285409 states and 405592 transitions. [2023-11-19 08:04:56,005 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 285409 states and 405592 transitions. [2023-11-19 08:04:57,720 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 283824 [2023-11-19 08:04:58,365 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 285409 states to 285409 states and 405592 transitions. [2023-11-19 08:04:58,365 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 285409 [2023-11-19 08:04:58,507 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 285409 [2023-11-19 08:04:58,507 INFO L73 IsDeterministic]: Start isDeterministic. Operand 285409 states and 405592 transitions. [2023-11-19 08:04:58,621 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:04:58,621 INFO L218 hiAutomatonCegarLoop]: Abstraction has 285409 states and 405592 transitions. [2023-11-19 08:04:58,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 285409 states and 405592 transitions. [2023-11-19 08:05:02,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 285409 to 284977. [2023-11-19 08:05:02,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 284977 states, 284977 states have (on average 1.4217287710938076) internal successors, (405160), 284976 states have internal predecessors, (405160), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:05:04,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 284977 states to 284977 states and 405160 transitions. [2023-11-19 08:05:04,025 INFO L240 hiAutomatonCegarLoop]: Abstraction has 284977 states and 405160 transitions. [2023-11-19 08:05:04,026 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 08:05:04,026 INFO L428 stractBuchiCegarLoop]: Abstraction has 284977 states and 405160 transitions. [2023-11-19 08:05:04,026 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-19 08:05:04,027 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 284977 states and 405160 transitions. [2023-11-19 08:05:04,689 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 283392 [2023-11-19 08:05:04,689 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 08:05:04,689 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 08:05:04,695 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:05:04,695 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 08:05:04,695 INFO L748 eck$LassoCheckResult]: Stem: 989548#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 989549#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 990478#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 990479#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 990403#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 990404#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 990377#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 990137#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 990138#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 989897#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 989898#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 990514#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 990363#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 989976#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 989712#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 989713#L922 assume !(0 == ~M_E~0); 990609#L922-2 assume !(0 == ~T1_E~0); 990610#L927-1 assume !(0 == ~T2_E~0); 990210#L932-1 assume !(0 == ~T3_E~0); 990062#L937-1 assume !(0 == ~T4_E~0); 990063#L942-1 assume !(0 == ~T5_E~0); 990136#L947-1 assume !(0 == ~T6_E~0); 990214#L952-1 assume !(0 == ~T7_E~0); 990215#L957-1 assume !(0 == ~T8_E~0); 990299#L962-1 assume !(0 == ~T9_E~0); 990032#L967-1 assume !(0 == ~E_1~0); 990033#L972-1 assume !(0 == ~E_2~0); 990382#L977-1 assume !(0 == ~E_3~0); 990383#L982-1 assume !(0 == ~E_4~0); 989480#L987-1 assume !(0 == ~E_5~0); 989481#L992-1 assume !(0 == ~E_6~0); 989487#L997-1 assume !(0 == ~E_7~0); 989947#L1002-1 assume !(0 == ~E_8~0); 989930#L1007-1 assume !(0 == ~E_9~0); 989273#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 989274#L443 assume !(1 == ~m_pc~0); 990234#L443-2 is_master_triggered_~__retres1~0#1 := 0; 990222#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 990223#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 989647#L1140 assume !(0 != activate_threads_~tmp~1#1); 989380#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 989381#L462 assume !(1 == ~t1_pc~0); 990051#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 990052#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 989315#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 989316#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 989873#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 989874#L481 assume !(1 == ~t2_pc~0); 989640#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 989639#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 989777#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 989736#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 989737#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 989842#L500 assume !(1 == ~t3_pc~0); 990465#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 990423#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 989280#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 989281#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 989275#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 989276#L519 assume !(1 == ~t4_pc~0); 990120#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 989841#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 989382#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 989383#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 989683#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 989444#L538 assume !(1 == ~t5_pc~0); 989445#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 989340#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 989341#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 989625#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 989626#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 990275#L557 assume !(1 == ~t6_pc~0); 989661#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 989662#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 989756#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 989684#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 989685#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 990569#L576 assume !(1 == ~t7_pc~0); 989651#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 989652#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 990018#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 990601#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 990352#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 989781#L595 assume !(1 == ~t8_pc~0); 989782#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 990372#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 990282#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 990162#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 990163#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 989575#L614 assume !(1 == ~t9_pc~0); 989576#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 989469#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 989470#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 989818#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 989740#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 989741#L1025 assume !(1 == ~M_E~0); 990041#L1025-2 assume !(1 == ~T1_E~0); 990112#L1030-1 assume !(1 == ~T2_E~0); 990269#L1035-1 assume !(1 == ~T3_E~0); 1073404#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1073405#L1045-1 assume !(1 == ~T5_E~0); 1094593#L1050-1 assume !(1 == ~T6_E~0); 1094591#L1055-1 assume !(1 == ~T7_E~0); 1094589#L1060-1 assume !(1 == ~T8_E~0); 1094586#L1065-1 assume !(1 == ~T9_E~0); 1094584#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1094582#L1075-1 assume !(1 == ~E_2~0); 1094580#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 990205#L1085-1 assume !(1 == ~E_4~0); 990206#L1090-1 assume !(1 == ~E_5~0); 990505#L1095-1 assume !(1 == ~E_6~0); 990250#L1100-1 assume !(1 == ~E_7~0); 990251#L1105-1 assume !(1 == ~E_8~0); 989426#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 989427#L1115-1 assume { :end_inline_reset_delta_events } true; 989790#L1396-2 [2023-11-19 08:05:04,696 INFO L750 eck$LassoCheckResult]: Loop: 989790#L1396-2 assume !false; 1099543#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1099538#L897-1 assume !false; 1099536#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1099533#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1099522#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1099520#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1099517#L766 assume !(0 != eval_~tmp~0#1); 1099518#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1102203#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1102201#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1102199#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1102197#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1102195#L932-3 assume !(0 == ~T3_E~0); 1102193#L937-3 assume !(0 == ~T4_E~0); 1102191#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1102189#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1102187#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1102185#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1102183#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1102181#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1102179#L972-3 assume !(0 == ~E_2~0); 1102177#L977-3 assume !(0 == ~E_3~0); 1102175#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1102173#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1102171#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1102169#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1102167#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1102165#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1102163#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1102161#L443-30 assume !(1 == ~m_pc~0); 1102159#L443-32 is_master_triggered_~__retres1~0#1 := 0; 1102157#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1102155#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1102153#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1102151#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1102149#L462-30 assume !(1 == ~t1_pc~0); 1102147#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1102145#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1102143#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1102141#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1102139#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1102137#L481-30 assume 1 == ~t2_pc~0; 1102133#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1102131#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1102129#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1102127#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 1102125#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1102123#L500-30 assume !(1 == ~t3_pc~0); 1102122#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1102120#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1102118#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1102116#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1102114#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1102112#L519-30 assume !(1 == ~t4_pc~0); 1102110#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1102108#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1102106#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1102104#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1102102#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1102098#L538-30 assume 1 == ~t5_pc~0; 1102096#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1102097#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1102206#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1102086#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1102084#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1102082#L557-30 assume !(1 == ~t6_pc~0); 1102080#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1102078#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1102076#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1102074#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1102072#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1102070#L576-30 assume 1 == ~t7_pc~0; 1102066#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1102064#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1102062#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1102060#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1102058#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1102056#L595-30 assume !(1 == ~t8_pc~0); 1102054#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1102052#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1102050#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1102048#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1102046#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1102044#L614-30 assume 1 == ~t9_pc~0; 1102040#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1102038#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1102036#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1102034#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1102032#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1102030#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1102028#L1025-5 assume !(1 == ~T1_E~0); 1102027#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1071059#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1102023#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1071053#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1102021#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1102019#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1102017#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1102015#L1065-3 assume !(1 == ~T9_E~0); 1102013#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1102011#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1102010#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1094387#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1102006#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1102005#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1102004#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1102003#L1105-3 assume !(1 == ~E_8~0); 1102002#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1102001#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1101998#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1101988#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1101986#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1099577#L1415 assume !(0 == start_simulation_~tmp~3#1); 1099575#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1099563#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1099555#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1099553#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1099551#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1099549#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1099547#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1099546#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 989790#L1396-2 [2023-11-19 08:05:04,697 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:05:04,697 INFO L85 PathProgramCache]: Analyzing trace with hash -683232136, now seen corresponding path program 1 times [2023-11-19 08:05:04,697 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:05:04,697 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [979859872] [2023-11-19 08:05:04,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:05:04,698 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:05:04,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:05:04,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:05:04,772 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:05:04,772 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [979859872] [2023-11-19 08:05:04,773 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [979859872] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:05:04,773 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:05:04,773 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:05:04,773 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1238749737] [2023-11-19 08:05:04,773 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:05:04,774 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 08:05:04,774 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 08:05:04,774 INFO L85 PathProgramCache]: Analyzing trace with hash 590693613, now seen corresponding path program 1 times [2023-11-19 08:05:04,774 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 08:05:04,775 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1723004287] [2023-11-19 08:05:04,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 08:05:04,775 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 08:05:04,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 08:05:04,824 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 08:05:04,824 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 08:05:04,825 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1723004287] [2023-11-19 08:05:04,825 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1723004287] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 08:05:04,825 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 08:05:04,825 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 08:05:04,825 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1689510721] [2023-11-19 08:05:04,825 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 08:05:04,826 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 08:05:04,826 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 08:05:04,826 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 08:05:04,827 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 08:05:04,827 INFO L87 Difference]: Start difference. First operand 284977 states and 405160 transitions. cyclomatic complexity: 120311 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 08:05:06,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 08:05:06,177 INFO L93 Difference]: Finished difference Result 142537 states and 201724 transitions. [2023-11-19 08:05:06,178 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 142537 states and 201724 transitions. [2023-11-19 08:05:06,650 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 141696 [2023-11-19 08:05:06,948 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 142537 states to 142537 states and 201724 transitions. [2023-11-19 08:05:06,948 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 142537 [2023-11-19 08:05:07,016 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 142537 [2023-11-19 08:05:07,016 INFO L73 IsDeterministic]: Start isDeterministic. Operand 142537 states and 201724 transitions. [2023-11-19 08:05:07,070 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 08:05:07,070 INFO L218 hiAutomatonCegarLoop]: Abstraction has 142537 states and 201724 transitions. [2023-11-19 08:05:07,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142537 states and 201724 transitions.