./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.10.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 9bd2c7ff Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5ad66b1b-29e3-4a70-ba84-c9e27d3f06e0/bin/uautomizer-verify-uCwYo4JHxu/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5ad66b1b-29e3-4a70-ba84-c9e27d3f06e0/bin/uautomizer-verify-uCwYo4JHxu/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5ad66b1b-29e3-4a70-ba84-c9e27d3f06e0/bin/uautomizer-verify-uCwYo4JHxu/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5ad66b1b-29e3-4a70-ba84-c9e27d3f06e0/bin/uautomizer-verify-uCwYo4JHxu/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.10.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5ad66b1b-29e3-4a70-ba84-c9e27d3f06e0/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5ad66b1b-29e3-4a70-ba84-c9e27d3f06e0/bin/uautomizer-verify-uCwYo4JHxu --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c68befe0cb772d649d152823cc17c89d77797d55cc04257d4beaaad2b518a7a0 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-9bd2c7f [2023-11-19 07:43:43,837 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-19 07:43:43,983 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5ad66b1b-29e3-4a70-ba84-c9e27d3f06e0/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-19 07:43:43,991 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-19 07:43:43,992 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-19 07:43:44,048 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-19 07:43:44,050 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-19 07:43:44,051 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-19 07:43:44,052 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-19 07:43:44,059 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-19 07:43:44,061 INFO L153 SettingsManager]: * Use SBE=true [2023-11-19 07:43:44,062 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-19 07:43:44,062 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-19 07:43:44,064 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-19 07:43:44,065 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-19 07:43:44,066 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-19 07:43:44,066 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-19 07:43:44,067 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-19 07:43:44,068 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-19 07:43:44,068 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-19 07:43:44,069 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-19 07:43:44,070 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-19 07:43:44,070 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-19 07:43:44,071 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-19 07:43:44,071 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-19 07:43:44,072 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-19 07:43:44,073 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-19 07:43:44,073 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-19 07:43:44,074 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-19 07:43:44,074 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-19 07:43:44,076 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-19 07:43:44,076 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-19 07:43:44,077 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-19 07:43:44,077 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-19 07:43:44,077 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-19 07:43:44,078 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-19 07:43:44,079 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5ad66b1b-29e3-4a70-ba84-c9e27d3f06e0/bin/uautomizer-verify-uCwYo4JHxu/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5ad66b1b-29e3-4a70-ba84-c9e27d3f06e0/bin/uautomizer-verify-uCwYo4JHxu Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c68befe0cb772d649d152823cc17c89d77797d55cc04257d4beaaad2b518a7a0 [2023-11-19 07:43:44,464 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-19 07:43:44,508 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-19 07:43:44,511 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-19 07:43:44,514 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-19 07:43:44,514 INFO L274 PluginConnector]: CDTParser initialized [2023-11-19 07:43:44,516 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5ad66b1b-29e3-4a70-ba84-c9e27d3f06e0/bin/uautomizer-verify-uCwYo4JHxu/../../sv-benchmarks/c/systemc/transmitter.10.cil.c [2023-11-19 07:43:48,263 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-19 07:43:48,547 INFO L384 CDTParser]: Found 1 translation units. [2023-11-19 07:43:48,548 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5ad66b1b-29e3-4a70-ba84-c9e27d3f06e0/sv-benchmarks/c/systemc/transmitter.10.cil.c [2023-11-19 07:43:48,570 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5ad66b1b-29e3-4a70-ba84-c9e27d3f06e0/bin/uautomizer-verify-uCwYo4JHxu/data/b6effc164/69dd897fa5a641e6bdd210108aa36dc8/FLAG83b37421e [2023-11-19 07:43:48,600 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5ad66b1b-29e3-4a70-ba84-c9e27d3f06e0/bin/uautomizer-verify-uCwYo4JHxu/data/b6effc164/69dd897fa5a641e6bdd210108aa36dc8 [2023-11-19 07:43:48,606 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-19 07:43:48,608 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-19 07:43:48,610 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-19 07:43:48,611 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-19 07:43:48,620 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-19 07:43:48,621 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:43:48" (1/1) ... [2023-11-19 07:43:48,622 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@68db485a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:48, skipping insertion in model container [2023-11-19 07:43:48,622 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:43:48" (1/1) ... [2023-11-19 07:43:48,695 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-19 07:43:49,108 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:43:49,139 INFO L202 MainTranslator]: Completed pre-run [2023-11-19 07:43:49,228 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:43:49,268 INFO L206 MainTranslator]: Completed translation [2023-11-19 07:43:49,269 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:49 WrapperNode [2023-11-19 07:43:49,269 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-19 07:43:49,271 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-19 07:43:49,271 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-19 07:43:49,271 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-19 07:43:49,281 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:49" (1/1) ... [2023-11-19 07:43:49,302 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:49" (1/1) ... [2023-11-19 07:43:49,430 INFO L138 Inliner]: procedures = 48, calls = 61, calls flagged for inlining = 56, calls inlined = 197, statements flattened = 3016 [2023-11-19 07:43:49,431 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-19 07:43:49,432 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-19 07:43:49,432 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-19 07:43:49,432 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-19 07:43:49,445 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:49" (1/1) ... [2023-11-19 07:43:49,445 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:49" (1/1) ... [2023-11-19 07:43:49,464 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:49" (1/1) ... [2023-11-19 07:43:49,466 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:49" (1/1) ... [2023-11-19 07:43:49,528 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:49" (1/1) ... [2023-11-19 07:43:49,597 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:49" (1/1) ... [2023-11-19 07:43:49,615 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:49" (1/1) ... [2023-11-19 07:43:49,648 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:49" (1/1) ... [2023-11-19 07:43:49,669 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-19 07:43:49,671 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-19 07:43:49,671 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-19 07:43:49,671 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-19 07:43:49,672 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:49" (1/1) ... [2023-11-19 07:43:49,680 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 07:43:49,696 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5ad66b1b-29e3-4a70-ba84-c9e27d3f06e0/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:43:49,717 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5ad66b1b-29e3-4a70-ba84-c9e27d3f06e0/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 07:43:49,748 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5ad66b1b-29e3-4a70-ba84-c9e27d3f06e0/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-19 07:43:49,783 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-19 07:43:49,783 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-19 07:43:49,783 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-19 07:43:49,783 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-19 07:43:49,991 INFO L236 CfgBuilder]: Building ICFG [2023-11-19 07:43:49,994 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-19 07:43:52,381 INFO L277 CfgBuilder]: Performing block encoding [2023-11-19 07:43:52,422 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-19 07:43:52,423 INFO L302 CfgBuilder]: Removed 14 assume(true) statements. [2023-11-19 07:43:52,441 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:43:52 BoogieIcfgContainer [2023-11-19 07:43:52,441 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-19 07:43:52,443 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-19 07:43:52,445 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-19 07:43:52,449 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-19 07:43:52,450 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:43:52,451 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 07:43:48" (1/3) ... [2023-11-19 07:43:52,452 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@20c67c35 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:43:52, skipping insertion in model container [2023-11-19 07:43:52,452 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:43:52,452 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:43:49" (2/3) ... [2023-11-19 07:43:52,454 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@20c67c35 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:43:52, skipping insertion in model container [2023-11-19 07:43:52,455 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:43:52,455 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:43:52" (3/3) ... [2023-11-19 07:43:52,456 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.10.cil.c [2023-11-19 07:43:52,579 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-19 07:43:52,580 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-19 07:43:52,580 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-19 07:43:52,580 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-19 07:43:52,580 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-19 07:43:52,581 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-19 07:43:52,581 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-19 07:43:52,581 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-19 07:43:52,596 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1297 states, 1296 states have (on average 1.5046296296296295) internal successors, (1950), 1296 states have internal predecessors, (1950), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:52,701 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1156 [2023-11-19 07:43:52,702 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:52,702 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:52,721 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:52,722 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:52,722 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-19 07:43:52,726 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1297 states, 1296 states have (on average 1.5046296296296295) internal successors, (1950), 1296 states have internal predecessors, (1950), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:52,748 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1156 [2023-11-19 07:43:52,748 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:52,749 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:52,755 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:52,755 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:52,769 INFO L748 eck$LassoCheckResult]: Stem: 182#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 1179#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 951#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1175#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1282#L701true assume !(1 == ~m_i~0);~m_st~0 := 2; 1156#L701-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1178#L706-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 269#L711-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 136#L716-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1200#L721-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 891#L726-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1085#L731-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 861#L736-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 936#L741-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1236#L746-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 161#L751-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 798#L1006true assume !(0 == ~M_E~0); 84#L1006-2true assume !(0 == ~T1_E~0); 994#L1011-1true assume !(0 == ~T2_E~0); 1036#L1016-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1182#L1021-1true assume !(0 == ~T4_E~0); 24#L1026-1true assume !(0 == ~T5_E~0); 1250#L1031-1true assume !(0 == ~T6_E~0); 566#L1036-1true assume !(0 == ~T7_E~0); 564#L1041-1true assume !(0 == ~T8_E~0); 908#L1046-1true assume !(0 == ~T9_E~0); 177#L1051-1true assume !(0 == ~T10_E~0); 706#L1056-1true assume 0 == ~E_1~0;~E_1~0 := 1; 754#L1061-1true assume !(0 == ~E_2~0); 138#L1066-1true assume !(0 == ~E_3~0); 1077#L1071-1true assume !(0 == ~E_4~0); 682#L1076-1true assume !(0 == ~E_5~0); 88#L1081-1true assume !(0 == ~E_6~0); 257#L1086-1true assume !(0 == ~E_7~0); 1091#L1091-1true assume !(0 == ~E_8~0); 967#L1096-1true assume 0 == ~E_9~0;~E_9~0 := 1; 1183#L1101-1true assume !(0 == ~E_10~0); 298#L1106-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1108#L484true assume !(1 == ~m_pc~0); 365#L484-2true is_master_triggered_~__retres1~0#1 := 0; 495#L495true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 807#is_master_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 801#L1245true assume !(0 != activate_threads_~tmp~1#1); 1221#L1245-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 558#L503true assume 1 == ~t1_pc~0; 571#L504true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 738#L514true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 381#L1253true assume !(0 != activate_threads_~tmp___0~0#1); 42#L1253-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 912#L522true assume !(1 == ~t2_pc~0); 526#L522-2true is_transmit2_triggered_~__retres1~2#1 := 0; 144#L533true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 294#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 892#L1261true assume !(0 != activate_threads_~tmp___1~0#1); 1213#L1261-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1059#L541true assume 1 == ~t3_pc~0; 483#L542true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 836#L552true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 593#L1269true assume !(0 != activate_threads_~tmp___2~0#1); 531#L1269-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 982#L560true assume !(1 == ~t4_pc~0); 1083#L560-2true is_transmit4_triggered_~__retres1~4#1 := 0; 459#L571true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23#L1277true assume !(0 != activate_threads_~tmp___3~0#1); 898#L1277-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 166#L579true assume 1 == ~t5_pc~0; 2#L580true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 55#L590true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 811#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1034#L1285true assume !(0 != activate_threads_~tmp___4~0#1); 1111#L1285-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1276#L598true assume 1 == ~t6_pc~0; 212#L599true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 402#L609true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 281#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 844#L1293true assume !(0 != activate_threads_~tmp___5~0#1); 600#L1293-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 552#L617true assume !(1 == ~t7_pc~0); 455#L617-2true is_transmit7_triggered_~__retres1~7#1 := 0; 1193#L628true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1203#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 914#L1301true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 314#L1301-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 597#L636true assume 1 == ~t8_pc~0; 440#L637true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 789#L647true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 739#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 609#L1309true assume !(0 != activate_threads_~tmp___7~0#1); 408#L1309-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 687#L655true assume !(1 == ~t9_pc~0); 770#L655-2true is_transmit9_triggered_~__retres1~9#1 := 0; 1138#L666true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 340#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1041#L1317true assume !(0 != activate_threads_~tmp___8~0#1); 621#L1317-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 979#L674true assume 1 == ~t10_pc~0; 78#L675true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1065#L685true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 432#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1296#L1325true assume !(0 != activate_threads_~tmp___9~0#1); 400#L1325-2true havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 901#L1119true assume !(1 == ~M_E~0); 127#L1119-2true assume !(1 == ~T1_E~0); 349#L1124-1true assume !(1 == ~T2_E~0); 37#L1129-1true assume !(1 == ~T3_E~0); 538#L1134-1true assume !(1 == ~T4_E~0); 192#L1139-1true assume !(1 == ~T5_E~0); 312#L1144-1true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1256#L1149-1true assume !(1 == ~T7_E~0); 124#L1154-1true assume !(1 == ~T8_E~0); 168#L1159-1true assume !(1 == ~T9_E~0); 1227#L1164-1true assume !(1 == ~T10_E~0); 419#L1169-1true assume !(1 == ~E_1~0); 343#L1174-1true assume !(1 == ~E_2~0); 219#L1179-1true assume !(1 == ~E_3~0); 163#L1184-1true assume 1 == ~E_4~0;~E_4~0 := 2; 190#L1189-1true assume !(1 == ~E_5~0); 247#L1194-1true assume !(1 == ~E_6~0); 1271#L1199-1true assume !(1 == ~E_7~0); 226#L1204-1true assume !(1 == ~E_8~0); 1134#L1209-1true assume !(1 == ~E_9~0); 619#L1214-1true assume !(1 == ~E_10~0); 1226#L1219-1true assume { :end_inline_reset_delta_events } true; 17#L1520-2true [2023-11-19 07:43:52,774 INFO L750 eck$LassoCheckResult]: Loop: 17#L1520-2true assume !false; 1279#L1521true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 683#L981-1true assume !true; 749#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 450#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 309#L1006-3true assume !(0 == ~M_E~0); 976#L1006-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 735#L1011-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 986#L1016-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 784#L1021-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 460#L1026-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1152#L1031-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 701#L1036-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1222#L1041-3true assume !(0 == ~T8_E~0); 777#L1046-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1107#L1051-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 702#L1056-3true assume 0 == ~E_1~0;~E_1~0 := 1; 175#L1061-3true assume 0 == ~E_2~0;~E_2~0 := 1; 176#L1066-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1239#L1071-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1008#L1076-3true assume 0 == ~E_5~0;~E_5~0 := 1; 69#L1081-3true assume !(0 == ~E_6~0); 1153#L1086-3true assume 0 == ~E_7~0;~E_7~0 := 1; 90#L1091-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1068#L1096-3true assume 0 == ~E_9~0;~E_9~0 := 1; 940#L1101-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1001#L1106-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 480#L484-33true assume 1 == ~m_pc~0; 1190#L485-11true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 412#L495-11true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 766#is_master_triggered_returnLabel#12true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20#L1245-33true assume !(0 != activate_threads_~tmp~1#1); 636#L1245-35true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 251#L503-33true assume 1 == ~t1_pc~0; 1191#L504-11true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 603#L514-11true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1161#is_transmit1_triggered_returnLabel#12true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 209#L1253-33true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 647#L1253-35true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 506#L522-33true assume !(1 == ~t2_pc~0); 1169#L522-35true is_transmit2_triggered_~__retres1~2#1 := 0; 86#L533-11true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 716#is_transmit2_triggered_returnLabel#12true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 813#L1261-33true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 524#L1261-35true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 887#L541-33true assume 1 == ~t3_pc~0; 96#L542-11true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19#L552-11true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 101#is_transmit3_triggered_returnLabel#12true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 500#L1269-33true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 944#L1269-35true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 698#L560-33true assume 1 == ~t4_pc~0; 414#L561-11true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 58#L571-11true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1013#is_transmit4_triggered_returnLabel#12true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1090#L1277-33true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 673#L1277-35true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14#L579-33true assume 1 == ~t5_pc~0; 456#L580-11true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1053#L590-11true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1100#is_transmit5_triggered_returnLabel#12true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 553#L1285-33true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 575#L1285-35true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1055#L598-33true assume !(1 == ~t6_pc~0); 386#L598-35true is_transmit6_triggered_~__retres1~6#1 := 0; 263#L609-11true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 376#is_transmit6_triggered_returnLabel#12true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 189#L1293-33true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 913#L1293-35true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1166#L617-33true assume 1 == ~t7_pc~0; 932#L618-11true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 782#L628-11true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 823#is_transmit7_triggered_returnLabel#12true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1140#L1301-33true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1010#L1301-35true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52#L636-33true assume !(1 == ~t8_pc~0); 1029#L636-35true is_transmit8_triggered_~__retres1~8#1 := 0; 666#L647-11true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 525#is_transmit8_triggered_returnLabel#12true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1071#L1309-33true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 654#L1309-35true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1269#L655-33true assume !(1 == ~t9_pc~0); 1198#L655-35true is_transmit9_triggered_~__retres1~9#1 := 0; 238#L666-11true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 720#is_transmit9_triggered_returnLabel#12true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 756#L1317-33true assume !(0 != activate_threads_~tmp___8~0#1); 1019#L1317-35true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 342#L674-33true assume !(1 == ~t10_pc~0); 1049#L674-35true is_transmit10_triggered_~__retres1~10#1 := 0; 1082#L685-11true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 835#is_transmit10_triggered_returnLabel#12true activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 513#L1325-33true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1076#L1325-35true havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1114#L1119-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1120#L1119-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1274#L1124-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1162#L1129-3true assume !(1 == ~T3_E~0); 207#L1134-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 497#L1139-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 335#L1144-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 445#L1149-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1260#L1154-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 710#L1159-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1243#L1164-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1024#L1169-3true assume !(1 == ~E_1~0); 262#L1174-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1104#L1179-3true assume 1 == ~E_3~0;~E_3~0 := 2; 846#L1184-3true assume 1 == ~E_4~0;~E_4~0 := 2; 81#L1189-3true assume 1 == ~E_5~0;~E_5~0 := 2; 851#L1194-3true assume 1 == ~E_6~0;~E_6~0 := 2; 235#L1199-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1278#L1204-3true assume 1 == ~E_8~0;~E_8~0 := 2; 433#L1209-3true assume !(1 == ~E_9~0); 27#L1214-3true assume 1 == ~E_10~0;~E_10~0 := 2; 948#L1219-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 611#L764-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 959#L821-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 256#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 296#L1539true assume !(0 == start_simulation_~tmp~3#1); 501#L1539-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 420#L764-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 876#L821-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 41#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 240#L1494true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 745#L1501true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 470#stop_simulation_returnLabel#1true start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 297#L1552true assume !(0 != start_simulation_~tmp___0~1#1); 17#L1520-2true [2023-11-19 07:43:52,783 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:52,784 INFO L85 PathProgramCache]: Analyzing trace with hash 1310232617, now seen corresponding path program 1 times [2023-11-19 07:43:52,796 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:52,796 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1910340257] [2023-11-19 07:43:52,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:52,798 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:52,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:53,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:53,312 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:53,312 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1910340257] [2023-11-19 07:43:53,313 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1910340257] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:53,313 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:53,314 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:53,316 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1578876473] [2023-11-19 07:43:53,317 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:53,323 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:53,324 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:53,324 INFO L85 PathProgramCache]: Analyzing trace with hash 939086972, now seen corresponding path program 1 times [2023-11-19 07:43:53,324 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:53,325 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1980615251] [2023-11-19 07:43:53,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:53,325 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:53,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:53,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:53,408 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:53,408 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1980615251] [2023-11-19 07:43:53,408 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1980615251] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:53,409 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:53,409 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:43:53,409 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [608146999] [2023-11-19 07:43:53,409 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:53,456 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:53,458 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:53,499 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:43:53,500 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:43:53,506 INFO L87 Difference]: Start difference. First operand has 1297 states, 1296 states have (on average 1.5046296296296295) internal successors, (1950), 1296 states have internal predecessors, (1950), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:53,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:53,614 INFO L93 Difference]: Finished difference Result 1295 states and 1918 transitions. [2023-11-19 07:43:53,616 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1295 states and 1918 transitions. [2023-11-19 07:43:53,635 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-19 07:43:53,657 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1295 states to 1289 states and 1912 transitions. [2023-11-19 07:43:53,658 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-19 07:43:53,661 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-19 07:43:53,662 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1912 transitions. [2023-11-19 07:43:53,670 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:53,670 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1912 transitions. [2023-11-19 07:43:53,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1912 transitions. [2023-11-19 07:43:53,801 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-19 07:43:53,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.4833204034134988) internal successors, (1912), 1288 states have internal predecessors, (1912), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:53,814 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1912 transitions. [2023-11-19 07:43:53,817 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1912 transitions. [2023-11-19 07:43:53,818 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:43:53,823 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1912 transitions. [2023-11-19 07:43:53,823 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-19 07:43:53,823 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1912 transitions. [2023-11-19 07:43:53,836 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-19 07:43:53,836 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:53,837 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:53,842 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:53,842 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:53,843 INFO L748 eck$LassoCheckResult]: Stem: 2961#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 2962#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3814#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3815#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3882#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 3876#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3877#L706-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3130#L711-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2873#L716-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2874#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3783#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3784#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3765#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3766#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3806#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 2924#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2925#L1006 assume !(0 == ~M_E~0); 2776#L1006-2 assume !(0 == ~T1_E~0); 2777#L1011-1 assume !(0 == ~T2_E~0); 3831#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3848#L1021-1 assume !(0 == ~T4_E~0); 2654#L1026-1 assume !(0 == ~T5_E~0); 2655#L1031-1 assume !(0 == ~T6_E~0); 3542#L1036-1 assume !(0 == ~T7_E~0); 3539#L1041-1 assume !(0 == ~T8_E~0); 3540#L1046-1 assume !(0 == ~T9_E~0); 2952#L1051-1 assume !(0 == ~T10_E~0); 2953#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 3669#L1061-1 assume !(0 == ~E_2~0); 2877#L1066-1 assume !(0 == ~E_3~0); 2878#L1071-1 assume !(0 == ~E_4~0); 3644#L1076-1 assume !(0 == ~E_5~0); 2784#L1081-1 assume !(0 == ~E_6~0); 2785#L1086-1 assume !(0 == ~E_7~0); 3104#L1091-1 assume !(0 == ~E_8~0); 3823#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 3824#L1101-1 assume !(0 == ~E_10~0); 3173#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3174#L484 assume !(1 == ~m_pc~0); 2834#L484-2 is_master_triggered_~__retres1~0#1 := 0; 2833#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3456#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3737#L1245 assume !(0 != activate_threads_~tmp~1#1); 3738#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3529#L503 assume 1 == ~t1_pc~0; 3530#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3549#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2695#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2696#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 2689#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2690#L522 assume !(1 == ~t2_pc~0); 3495#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2888#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2889#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3168#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 3785#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3856#L541 assume 1 == ~t3_pc~0; 3438#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3240#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2636#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2637#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 3501#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3502#L560 assume !(1 == ~t4_pc~0); 2770#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2769#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2800#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2650#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 2651#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2933#L579 assume 1 == ~t5_pc~0; 2601#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2602#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2715#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3742#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 3847#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3866#L598 assume 1 == ~t6_pc~0; 3017#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3018#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3145#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3146#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 3575#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3520#L617 assume !(1 == ~t7_pc~0); 2993#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2992#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3886#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3797#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3207#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3208#L636 assume 1 == ~t8_pc~0; 3391#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3392#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3698#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3584#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 3340#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3341#L655 assume !(1 == ~t9_pc~0); 3368#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3369#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3254#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3255#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 3595#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3596#L674 assume 1 == ~t10_pc~0; 2761#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 2762#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3382#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3383#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 3329#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3330#L1119 assume !(1 == ~M_E~0); 2860#L1119-2 assume !(1 == ~T1_E~0); 2861#L1124-1 assume !(1 == ~T2_E~0); 2679#L1129-1 assume !(1 == ~T3_E~0); 2680#L1134-1 assume !(1 == ~T4_E~0); 2978#L1139-1 assume !(1 == ~T5_E~0); 2979#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3203#L1149-1 assume !(1 == ~T7_E~0); 2854#L1154-1 assume !(1 == ~T8_E~0); 2855#L1159-1 assume !(1 == ~T9_E~0); 2936#L1164-1 assume !(1 == ~T10_E~0); 3357#L1169-1 assume !(1 == ~E_1~0); 3256#L1174-1 assume !(1 == ~E_2~0); 3030#L1179-1 assume !(1 == ~E_3~0); 2926#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2927#L1189-1 assume !(1 == ~E_5~0); 2976#L1194-1 assume !(1 == ~E_6~0); 3082#L1199-1 assume !(1 == ~E_7~0); 3042#L1204-1 assume !(1 == ~E_8~0); 3043#L1209-1 assume !(1 == ~E_9~0); 3593#L1214-1 assume !(1 == ~E_10~0); 3594#L1219-1 assume { :end_inline_reset_delta_events } true; 2638#L1520-2 [2023-11-19 07:43:53,844 INFO L750 eck$LassoCheckResult]: Loop: 2638#L1520-2 assume !false; 2639#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3430#L981-1 assume !false; 3615#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3616#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2622#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3223#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3224#L836 assume !(0 != eval_~tmp~0#1); 3707#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3399#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3195#L1006-3 assume !(0 == ~M_E~0); 3196#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3693#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3694#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3731#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3410#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3411#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3661#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3662#L1041-3 assume !(0 == ~T8_E~0); 3725#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3726#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3663#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2949#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2950#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2951#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3834#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2743#L1081-3 assume !(0 == ~E_6~0); 2744#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2791#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2792#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3807#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3808#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3432#L484-33 assume !(1 == ~m_pc~0); 3433#L484-35 is_master_triggered_~__retres1~0#1 := 0; 3343#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3344#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2644#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 2645#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3090#L503-33 assume 1 == ~t1_pc~0; 3091#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3578#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3579#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3011#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3012#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3470#L522-33 assume 1 == ~t2_pc~0; 3472#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2781#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2782#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3679#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3493#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3494#L541-33 assume 1 == ~t3_pc~0; 2801#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2642#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2643#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2813#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3462#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3659#L560-33 assume 1 == ~t4_pc~0; 3347#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2719#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2720#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3836#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3638#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2628#L579-33 assume 1 == ~t5_pc~0; 2629#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2881#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3852#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3521#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3522#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3548#L598-33 assume !(1 == ~t6_pc~0); 3304#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 3114#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3115#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2973#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2974#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3796#L617-33 assume !(1 == ~t7_pc~0); 2774#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 2775#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3730#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3749#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3835#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2709#L636-33 assume 1 == ~t8_pc~0; 2710#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3631#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3491#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3492#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3620#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3621#L655-33 assume 1 == ~t9_pc~0; 3883#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3059#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3060#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3682#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 3711#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3253#L674-33 assume 1 == ~t10_pc~0; 3109#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3110#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3755#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3479#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3480#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3857#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3867#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3869#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3879#L1129-3 assume !(1 == ~T3_E~0); 3004#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3005#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3242#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3243#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3397#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3674#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3675#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3842#L1169-3 assume !(1 == ~E_1~0); 3112#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3113#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3760#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2766#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2767#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3057#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3058#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3381#L1209-3 assume !(1 == ~E_9~0); 2656#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2657#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3583#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2746#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3100#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 3101#L1539 assume !(0 == start_simulation_~tmp~3#1); 3171#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3358#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3153#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2685#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 2686#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3065#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3419#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3172#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 2638#L1520-2 [2023-11-19 07:43:53,845 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:53,845 INFO L85 PathProgramCache]: Analyzing trace with hash -934325781, now seen corresponding path program 1 times [2023-11-19 07:43:53,845 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:53,846 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1897360025] [2023-11-19 07:43:53,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:53,846 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:53,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:54,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:54,055 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:54,056 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1897360025] [2023-11-19 07:43:54,056 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1897360025] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:54,057 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:54,057 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:54,057 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [522911150] [2023-11-19 07:43:54,058 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:54,058 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:54,073 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:54,073 INFO L85 PathProgramCache]: Analyzing trace with hash 867756010, now seen corresponding path program 1 times [2023-11-19 07:43:54,073 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:54,074 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1387411961] [2023-11-19 07:43:54,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:54,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:54,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:54,294 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:54,298 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:54,299 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1387411961] [2023-11-19 07:43:54,300 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1387411961] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:54,300 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:54,301 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:54,301 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1097291499] [2023-11-19 07:43:54,301 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:54,303 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:54,305 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:54,306 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:43:54,307 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:43:54,308 INFO L87 Difference]: Start difference. First operand 1289 states and 1912 transitions. cyclomatic complexity: 624 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:54,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:54,352 INFO L93 Difference]: Finished difference Result 1289 states and 1911 transitions. [2023-11-19 07:43:54,353 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1289 states and 1911 transitions. [2023-11-19 07:43:54,369 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-19 07:43:54,383 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1289 states to 1289 states and 1911 transitions. [2023-11-19 07:43:54,383 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-19 07:43:54,385 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-19 07:43:54,386 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1911 transitions. [2023-11-19 07:43:54,390 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:54,390 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1911 transitions. [2023-11-19 07:43:54,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1911 transitions. [2023-11-19 07:43:54,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-19 07:43:54,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.482544608223429) internal successors, (1911), 1288 states have internal predecessors, (1911), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:54,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1911 transitions. [2023-11-19 07:43:54,434 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1911 transitions. [2023-11-19 07:43:54,436 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:43:54,438 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1911 transitions. [2023-11-19 07:43:54,438 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-19 07:43:54,438 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1911 transitions. [2023-11-19 07:43:54,449 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-19 07:43:54,451 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:54,451 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:54,462 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:54,468 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:54,469 INFO L748 eck$LassoCheckResult]: Stem: 5546#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 5547#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 6399#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6400#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6467#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 6461#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6462#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5715#L711-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5460#L716-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5461#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6368#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6369#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6350#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6351#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6391#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5509#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5510#L1006 assume !(0 == ~M_E~0); 5364#L1006-2 assume !(0 == ~T1_E~0); 5365#L1011-1 assume !(0 == ~T2_E~0); 6416#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6433#L1021-1 assume !(0 == ~T4_E~0); 5239#L1026-1 assume !(0 == ~T5_E~0); 5240#L1031-1 assume !(0 == ~T6_E~0); 6129#L1036-1 assume !(0 == ~T7_E~0); 6124#L1041-1 assume !(0 == ~T8_E~0); 6125#L1046-1 assume !(0 == ~T9_E~0); 5537#L1051-1 assume !(0 == ~T10_E~0); 5538#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 6254#L1061-1 assume !(0 == ~E_2~0); 5462#L1066-1 assume !(0 == ~E_3~0); 5463#L1071-1 assume !(0 == ~E_4~0); 6229#L1076-1 assume !(0 == ~E_5~0); 5369#L1081-1 assume !(0 == ~E_6~0); 5370#L1086-1 assume !(0 == ~E_7~0); 5689#L1091-1 assume !(0 == ~E_8~0); 6408#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 6409#L1101-1 assume !(0 == ~E_10~0); 5758#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5759#L484 assume !(1 == ~m_pc~0); 5421#L484-2 is_master_triggered_~__retres1~0#1 := 0; 5420#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6041#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6322#L1245 assume !(0 != activate_threads_~tmp~1#1); 6323#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6114#L503 assume 1 == ~t1_pc~0; 6115#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6136#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5280#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5281#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 5276#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5277#L522 assume !(1 == ~t2_pc~0); 6080#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5474#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5475#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5754#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 6370#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6441#L541 assume 1 == ~t3_pc~0; 6025#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5825#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5221#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5222#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 6090#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6091#L560 assume !(1 == ~t4_pc~0); 5355#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5354#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5385#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5235#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 5236#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5520#L579 assume 1 == ~t5_pc~0; 5186#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5187#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5300#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6327#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 6432#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6451#L598 assume 1 == ~t6_pc~0; 5602#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5603#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5731#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5732#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 6160#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6105#L617 assume !(1 == ~t7_pc~0); 5578#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5577#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6471#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6382#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5795#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5796#L636 assume 1 == ~t8_pc~0; 5976#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5977#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6287#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6170#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 5925#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5926#L655 assume !(1 == ~t9_pc~0); 5955#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 5956#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5839#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5840#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 6180#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6181#L674 assume 1 == ~t10_pc~0; 5346#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5347#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5967#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5968#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 5914#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5915#L1119 assume !(1 == ~M_E~0); 5445#L1119-2 assume !(1 == ~T1_E~0); 5446#L1124-1 assume !(1 == ~T2_E~0); 5264#L1129-1 assume !(1 == ~T3_E~0); 5265#L1134-1 assume !(1 == ~T4_E~0); 5563#L1139-1 assume !(1 == ~T5_E~0); 5564#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5791#L1149-1 assume !(1 == ~T7_E~0); 5439#L1154-1 assume !(1 == ~T8_E~0); 5440#L1159-1 assume !(1 == ~T9_E~0); 5521#L1164-1 assume !(1 == ~T10_E~0); 5942#L1169-1 assume !(1 == ~E_1~0); 5842#L1174-1 assume !(1 == ~E_2~0); 5617#L1179-1 assume !(1 == ~E_3~0); 5511#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5512#L1189-1 assume !(1 == ~E_5~0); 5561#L1194-1 assume !(1 == ~E_6~0); 5667#L1199-1 assume !(1 == ~E_7~0); 5627#L1204-1 assume !(1 == ~E_8~0); 5628#L1209-1 assume !(1 == ~E_9~0); 6178#L1214-1 assume !(1 == ~E_10~0); 6179#L1219-1 assume { :end_inline_reset_delta_events } true; 5223#L1520-2 [2023-11-19 07:43:54,472 INFO L750 eck$LassoCheckResult]: Loop: 5223#L1520-2 assume !false; 5224#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6015#L981-1 assume !false; 6200#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6201#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5207#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5808#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5809#L836 assume !(0 != eval_~tmp~0#1); 6292#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5984#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5780#L1006-3 assume !(0 == ~M_E~0); 5781#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6278#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6279#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6316#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5993#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5994#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6246#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6247#L1041-3 assume !(0 == ~T8_E~0); 6308#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6309#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6248#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5534#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5535#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5536#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6419#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5328#L1081-3 assume !(0 == ~E_6~0); 5329#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5374#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5375#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6392#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6393#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6017#L484-33 assume !(1 == ~m_pc~0); 6018#L484-35 is_master_triggered_~__retres1~0#1 := 0; 5928#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5929#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5229#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 5230#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5674#L503-33 assume 1 == ~t1_pc~0; 5675#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6163#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6164#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5594#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5595#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6055#L522-33 assume !(1 == ~t2_pc~0); 6056#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 5366#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5367#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6264#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6076#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6077#L541-33 assume 1 == ~t3_pc~0; 5386#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5227#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5228#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5395#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6047#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6244#L560-33 assume 1 == ~t4_pc~0; 5932#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5304#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5305#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6421#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6223#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5216#L579-33 assume 1 == ~t5_pc~0; 5217#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5467#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6437#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6106#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6107#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6135#L598-33 assume !(1 == ~t6_pc~0); 5892#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 5699#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5700#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5558#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5559#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6381#L617-33 assume 1 == ~t7_pc~0; 6389#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5360#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6315#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6334#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6420#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5294#L636-33 assume !(1 == ~t8_pc~0); 5296#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 6216#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6078#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6079#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6207#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6208#L655-33 assume 1 == ~t9_pc~0; 6468#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5647#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5648#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6267#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 6296#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5838#L674-33 assume !(1 == ~t10_pc~0); 5696#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 5695#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6340#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6064#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6065#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6442#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6452#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6454#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6464#L1129-3 assume !(1 == ~T3_E~0); 5592#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5593#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5827#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5828#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5982#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6259#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6260#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6428#L1169-3 assume !(1 == ~E_1~0); 5697#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5698#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6345#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5351#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5352#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5642#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5643#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5966#L1209-3 assume !(1 == ~E_9~0); 5243#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5244#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6169#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5331#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5685#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 5686#L1539 assume !(0 == start_simulation_~tmp~3#1); 5756#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5943#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5738#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5272#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 5273#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5650#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6004#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 5757#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 5223#L1520-2 [2023-11-19 07:43:54,473 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:54,479 INFO L85 PathProgramCache]: Analyzing trace with hash 158309421, now seen corresponding path program 1 times [2023-11-19 07:43:54,479 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:54,480 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1758140078] [2023-11-19 07:43:54,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:54,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:54,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:54,598 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:54,598 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:54,599 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1758140078] [2023-11-19 07:43:54,599 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1758140078] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:54,599 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:54,599 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:54,600 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [503463453] [2023-11-19 07:43:54,600 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:54,601 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:54,601 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:54,601 INFO L85 PathProgramCache]: Analyzing trace with hash -1384946584, now seen corresponding path program 1 times [2023-11-19 07:43:54,602 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:54,603 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1600318563] [2023-11-19 07:43:54,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:54,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:54,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:54,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:54,715 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:54,716 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1600318563] [2023-11-19 07:43:54,716 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1600318563] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:54,717 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:54,717 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:54,717 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1982544345] [2023-11-19 07:43:54,717 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:54,718 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:54,718 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:54,719 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:43:54,719 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:43:54,719 INFO L87 Difference]: Start difference. First operand 1289 states and 1911 transitions. cyclomatic complexity: 623 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:54,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:54,786 INFO L93 Difference]: Finished difference Result 1289 states and 1910 transitions. [2023-11-19 07:43:54,786 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1289 states and 1910 transitions. [2023-11-19 07:43:54,799 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-19 07:43:54,810 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1289 states to 1289 states and 1910 transitions. [2023-11-19 07:43:54,810 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-19 07:43:54,811 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-19 07:43:54,812 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1910 transitions. [2023-11-19 07:43:54,814 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:54,814 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1910 transitions. [2023-11-19 07:43:54,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1910 transitions. [2023-11-19 07:43:54,836 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-19 07:43:54,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.4817688130333593) internal successors, (1910), 1288 states have internal predecessors, (1910), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:54,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1910 transitions. [2023-11-19 07:43:54,846 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1910 transitions. [2023-11-19 07:43:54,847 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:43:54,849 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1910 transitions. [2023-11-19 07:43:54,849 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-19 07:43:54,849 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1910 transitions. [2023-11-19 07:43:54,859 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-19 07:43:54,859 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:54,860 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:54,862 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:54,863 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:54,864 INFO L748 eck$LassoCheckResult]: Stem: 8131#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 8132#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 8983#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8984#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9052#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 9046#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9047#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8298#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8043#L716-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8044#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8953#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8954#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8935#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8936#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8976#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8092#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8093#L1006 assume !(0 == ~M_E~0); 7946#L1006-2 assume !(0 == ~T1_E~0); 7947#L1011-1 assume !(0 == ~T2_E~0); 9001#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9018#L1021-1 assume !(0 == ~T4_E~0); 7822#L1026-1 assume !(0 == ~T5_E~0); 7823#L1031-1 assume !(0 == ~T6_E~0); 8712#L1036-1 assume !(0 == ~T7_E~0); 8709#L1041-1 assume !(0 == ~T8_E~0); 8710#L1046-1 assume !(0 == ~T9_E~0); 8122#L1051-1 assume !(0 == ~T10_E~0); 8123#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 8839#L1061-1 assume !(0 == ~E_2~0); 8047#L1066-1 assume !(0 == ~E_3~0); 8048#L1071-1 assume !(0 == ~E_4~0); 8814#L1076-1 assume !(0 == ~E_5~0); 7954#L1081-1 assume !(0 == ~E_6~0); 7955#L1086-1 assume !(0 == ~E_7~0); 8272#L1091-1 assume !(0 == ~E_8~0); 8991#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 8992#L1101-1 assume !(0 == ~E_10~0); 8343#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8344#L484 assume !(1 == ~m_pc~0); 8004#L484-2 is_master_triggered_~__retres1~0#1 := 0; 8003#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8626#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8907#L1245 assume !(0 != activate_threads_~tmp~1#1); 8908#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8699#L503 assume 1 == ~t1_pc~0; 8700#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8718#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7863#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7864#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 7859#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7860#L522 assume !(1 == ~t2_pc~0); 8665#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8058#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8059#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8338#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 8955#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9026#L541 assume 1 == ~t3_pc~0; 8608#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8410#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7806#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7807#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 8671#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8672#L560 assume !(1 == ~t4_pc~0); 7938#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7937#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7970#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7820#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 7821#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8103#L579 assume 1 == ~t5_pc~0; 7771#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7772#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7885#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8912#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 9016#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9036#L598 assume 1 == ~t6_pc~0; 8187#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8188#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8313#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8314#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 8745#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8690#L617 assume !(1 == ~t7_pc~0); 8163#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8162#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9056#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8967#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8377#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8378#L636 assume 1 == ~t8_pc~0; 8561#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8562#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8867#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8753#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 8508#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8509#L655 assume !(1 == ~t9_pc~0); 8536#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 8537#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8420#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8421#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 8765#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8766#L674 assume 1 == ~t10_pc~0; 7931#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7932#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8551#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8552#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 8499#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8500#L1119 assume !(1 == ~M_E~0); 8030#L1119-2 assume !(1 == ~T1_E~0); 8031#L1124-1 assume !(1 == ~T2_E~0); 7849#L1129-1 assume !(1 == ~T3_E~0); 7850#L1134-1 assume !(1 == ~T4_E~0); 8147#L1139-1 assume !(1 == ~T5_E~0); 8148#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8373#L1149-1 assume !(1 == ~T7_E~0); 8024#L1154-1 assume !(1 == ~T8_E~0); 8025#L1159-1 assume !(1 == ~T9_E~0); 8106#L1164-1 assume !(1 == ~T10_E~0); 8527#L1169-1 assume !(1 == ~E_1~0); 8426#L1174-1 assume !(1 == ~E_2~0); 8200#L1179-1 assume !(1 == ~E_3~0); 8096#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8097#L1189-1 assume !(1 == ~E_5~0); 8145#L1194-1 assume !(1 == ~E_6~0); 8251#L1199-1 assume !(1 == ~E_7~0); 8212#L1204-1 assume !(1 == ~E_8~0); 8213#L1209-1 assume !(1 == ~E_9~0); 8763#L1214-1 assume !(1 == ~E_10~0); 8764#L1219-1 assume { :end_inline_reset_delta_events } true; 7808#L1520-2 [2023-11-19 07:43:54,864 INFO L750 eck$LassoCheckResult]: Loop: 7808#L1520-2 assume !false; 7809#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8600#L981-1 assume !false; 8785#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8786#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 7792#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8390#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8391#L836 assume !(0 != eval_~tmp~0#1); 8877#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8569#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8365#L1006-3 assume !(0 == ~M_E~0); 8366#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8863#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8864#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8901#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8578#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8579#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8831#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8832#L1041-3 assume !(0 == ~T8_E~0); 8893#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8894#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8833#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8119#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8120#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8121#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9004#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7913#L1081-3 assume !(0 == ~E_6~0); 7914#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7959#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7960#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8977#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8978#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8602#L484-33 assume !(1 == ~m_pc~0); 8603#L484-35 is_master_triggered_~__retres1~0#1 := 0; 8513#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8514#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7814#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 7815#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8259#L503-33 assume 1 == ~t1_pc~0; 8260#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8748#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8749#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8181#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8182#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8640#L522-33 assume !(1 == ~t2_pc~0); 8641#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 7951#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7952#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8849#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8661#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8662#L541-33 assume 1 == ~t3_pc~0; 7971#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7812#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7813#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7980#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8632#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8829#L560-33 assume 1 == ~t4_pc~0; 8517#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7889#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7890#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9006#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8808#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7801#L579-33 assume 1 == ~t5_pc~0; 7802#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8052#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9022#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8691#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8692#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8723#L598-33 assume 1 == ~t6_pc~0; 9024#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8284#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8285#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8143#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8144#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8966#L617-33 assume !(1 == ~t7_pc~0); 7944#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 7945#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8900#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8919#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9005#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7879#L636-33 assume 1 == ~t8_pc~0; 7880#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8801#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8663#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8664#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8792#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8793#L655-33 assume 1 == ~t9_pc~0; 9053#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8232#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8233#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8852#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 8881#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8425#L674-33 assume 1 == ~t10_pc~0; 8279#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8280#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8925#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8649#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8650#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9027#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9037#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9039#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9049#L1129-3 assume !(1 == ~T3_E~0); 8177#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8178#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8412#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8413#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8567#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8844#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8845#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9013#L1169-3 assume !(1 == ~E_1~0); 8282#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8283#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8930#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7939#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7940#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8227#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8228#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8553#L1209-3 assume !(1 == ~E_9~0); 7828#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7829#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8755#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 7916#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8270#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 8271#L1539 assume !(0 == start_simulation_~tmp~3#1); 8341#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8528#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8323#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 7857#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 7858#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8235#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8589#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 8342#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 7808#L1520-2 [2023-11-19 07:43:54,867 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:54,867 INFO L85 PathProgramCache]: Analyzing trace with hash 1440481707, now seen corresponding path program 1 times [2023-11-19 07:43:54,867 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:54,868 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1802638328] [2023-11-19 07:43:54,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:54,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:54,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:54,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:54,935 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:54,936 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1802638328] [2023-11-19 07:43:54,936 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1802638328] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:54,937 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:54,937 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:54,937 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1293483895] [2023-11-19 07:43:54,937 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:54,938 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:54,938 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:54,939 INFO L85 PathProgramCache]: Analyzing trace with hash 1365031658, now seen corresponding path program 1 times [2023-11-19 07:43:54,939 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:54,943 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1245339930] [2023-11-19 07:43:54,944 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:54,944 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:54,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:55,044 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:55,046 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:55,046 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1245339930] [2023-11-19 07:43:55,046 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1245339930] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:55,047 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:55,047 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:55,047 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [285005329] [2023-11-19 07:43:55,047 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:55,048 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:55,048 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:55,048 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:43:55,048 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:43:55,049 INFO L87 Difference]: Start difference. First operand 1289 states and 1910 transitions. cyclomatic complexity: 622 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:55,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:55,083 INFO L93 Difference]: Finished difference Result 1289 states and 1909 transitions. [2023-11-19 07:43:55,083 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1289 states and 1909 transitions. [2023-11-19 07:43:55,095 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-19 07:43:55,107 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1289 states to 1289 states and 1909 transitions. [2023-11-19 07:43:55,107 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-19 07:43:55,109 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-19 07:43:55,109 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1909 transitions. [2023-11-19 07:43:55,111 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:55,111 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1909 transitions. [2023-11-19 07:43:55,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1909 transitions. [2023-11-19 07:43:55,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-19 07:43:55,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.4809930178432893) internal successors, (1909), 1288 states have internal predecessors, (1909), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:55,144 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1909 transitions. [2023-11-19 07:43:55,145 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1909 transitions. [2023-11-19 07:43:55,145 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:43:55,148 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1909 transitions. [2023-11-19 07:43:55,152 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-19 07:43:55,153 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1909 transitions. [2023-11-19 07:43:55,162 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-19 07:43:55,163 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:55,163 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:55,165 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:55,166 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:55,166 INFO L748 eck$LassoCheckResult]: Stem: 10716#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 10717#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 11569#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11570#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11637#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 11631#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11632#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10883#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10628#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10629#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11538#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11539#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11520#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11521#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11561#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10677#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10678#L1006 assume !(0 == ~M_E~0); 10531#L1006-2 assume !(0 == ~T1_E~0); 10532#L1011-1 assume !(0 == ~T2_E~0); 11586#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11603#L1021-1 assume !(0 == ~T4_E~0); 10407#L1026-1 assume !(0 == ~T5_E~0); 10408#L1031-1 assume !(0 == ~T6_E~0); 11297#L1036-1 assume !(0 == ~T7_E~0); 11294#L1041-1 assume !(0 == ~T8_E~0); 11295#L1046-1 assume !(0 == ~T9_E~0); 10707#L1051-1 assume !(0 == ~T10_E~0); 10708#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 11424#L1061-1 assume !(0 == ~E_2~0); 10632#L1066-1 assume !(0 == ~E_3~0); 10633#L1071-1 assume !(0 == ~E_4~0); 11399#L1076-1 assume !(0 == ~E_5~0); 10539#L1081-1 assume !(0 == ~E_6~0); 10540#L1086-1 assume !(0 == ~E_7~0); 10857#L1091-1 assume !(0 == ~E_8~0); 11576#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 11577#L1101-1 assume !(0 == ~E_10~0); 10928#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10929#L484 assume !(1 == ~m_pc~0); 10589#L484-2 is_master_triggered_~__retres1~0#1 := 0; 10588#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11211#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11492#L1245 assume !(0 != activate_threads_~tmp~1#1); 11493#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11284#L503 assume 1 == ~t1_pc~0; 11285#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11303#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10448#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10449#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 10444#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10445#L522 assume !(1 == ~t2_pc~0); 11250#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10643#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10644#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10923#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 11540#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11611#L541 assume 1 == ~t3_pc~0; 11193#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10995#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10391#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10392#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 11256#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11257#L560 assume !(1 == ~t4_pc~0); 10523#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10522#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10555#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10405#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 10406#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10688#L579 assume 1 == ~t5_pc~0; 10356#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10357#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10470#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11497#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 11601#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11621#L598 assume 1 == ~t6_pc~0; 10772#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10773#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10898#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10899#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 11330#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11275#L617 assume !(1 == ~t7_pc~0); 10748#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10747#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11641#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11552#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10962#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10963#L636 assume 1 == ~t8_pc~0; 11146#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11147#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11452#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11338#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 11093#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11094#L655 assume !(1 == ~t9_pc~0); 11123#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 11124#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11005#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11006#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 11350#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11351#L674 assume 1 == ~t10_pc~0; 10516#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10517#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11136#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11137#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 11084#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11085#L1119 assume !(1 == ~M_E~0); 10615#L1119-2 assume !(1 == ~T1_E~0); 10616#L1124-1 assume !(1 == ~T2_E~0); 10434#L1129-1 assume !(1 == ~T3_E~0); 10435#L1134-1 assume !(1 == ~T4_E~0); 10733#L1139-1 assume !(1 == ~T5_E~0); 10734#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10958#L1149-1 assume !(1 == ~T7_E~0); 10609#L1154-1 assume !(1 == ~T8_E~0); 10610#L1159-1 assume !(1 == ~T9_E~0); 10691#L1164-1 assume !(1 == ~T10_E~0); 11112#L1169-1 assume !(1 == ~E_1~0); 11011#L1174-1 assume !(1 == ~E_2~0); 10785#L1179-1 assume !(1 == ~E_3~0); 10681#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10682#L1189-1 assume !(1 == ~E_5~0); 10730#L1194-1 assume !(1 == ~E_6~0); 10836#L1199-1 assume !(1 == ~E_7~0); 10797#L1204-1 assume !(1 == ~E_8~0); 10798#L1209-1 assume !(1 == ~E_9~0); 11348#L1214-1 assume !(1 == ~E_10~0); 11349#L1219-1 assume { :end_inline_reset_delta_events } true; 10393#L1520-2 [2023-11-19 07:43:55,167 INFO L750 eck$LassoCheckResult]: Loop: 10393#L1520-2 assume !false; 10394#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11185#L981-1 assume !false; 11370#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11371#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10377#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 10978#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10979#L836 assume !(0 != eval_~tmp~0#1); 11462#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11154#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10950#L1006-3 assume !(0 == ~M_E~0); 10951#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11448#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11449#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11486#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11163#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11164#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11416#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11417#L1041-3 assume !(0 == ~T8_E~0); 11478#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11479#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 11418#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10704#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10705#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10706#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11589#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10498#L1081-3 assume !(0 == ~E_6~0); 10499#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10544#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10545#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11562#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 11563#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11187#L484-33 assume !(1 == ~m_pc~0); 11188#L484-35 is_master_triggered_~__retres1~0#1 := 0; 11098#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11099#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10399#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 10400#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10844#L503-33 assume 1 == ~t1_pc~0; 10845#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11333#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11334#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10766#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10767#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11225#L522-33 assume !(1 == ~t2_pc~0); 11226#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 10536#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10537#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11434#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11246#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11247#L541-33 assume 1 == ~t3_pc~0; 10556#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10397#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10398#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10565#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11217#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11414#L560-33 assume 1 == ~t4_pc~0; 11102#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10474#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10475#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11591#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11393#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10386#L579-33 assume 1 == ~t5_pc~0; 10387#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10637#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11607#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11276#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11277#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11308#L598-33 assume !(1 == ~t6_pc~0); 11063#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 10869#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10870#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10728#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10729#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11551#L617-33 assume !(1 == ~t7_pc~0); 10529#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 10530#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11485#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11504#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11590#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10464#L636-33 assume 1 == ~t8_pc~0; 10465#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11386#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11248#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11249#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11379#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11380#L655-33 assume 1 == ~t9_pc~0; 11638#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10817#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10818#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11437#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 11466#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11010#L674-33 assume 1 == ~t10_pc~0; 10864#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10865#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11510#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11234#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11235#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11612#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11622#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11624#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11634#L1129-3 assume !(1 == ~T3_E~0); 10762#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10763#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10997#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10998#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11152#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11429#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11430#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11598#L1169-3 assume !(1 == ~E_1~0); 10867#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10868#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11515#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10524#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10525#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10812#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10813#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11138#L1209-3 assume !(1 == ~E_9~0); 10413#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10414#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11340#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10501#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 10855#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 10856#L1539 assume !(0 == start_simulation_~tmp~3#1); 10927#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11113#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10908#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 10440#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 10441#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10820#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11174#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 10925#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 10393#L1520-2 [2023-11-19 07:43:55,168 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:55,170 INFO L85 PathProgramCache]: Analyzing trace with hash -1012009875, now seen corresponding path program 1 times [2023-11-19 07:43:55,170 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:55,170 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [353001893] [2023-11-19 07:43:55,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:55,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:55,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:55,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:55,232 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:55,232 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [353001893] [2023-11-19 07:43:55,233 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [353001893] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:55,233 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:55,233 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:55,233 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1844000146] [2023-11-19 07:43:55,234 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:55,234 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:55,234 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:55,235 INFO L85 PathProgramCache]: Analyzing trace with hash 2069950345, now seen corresponding path program 1 times [2023-11-19 07:43:55,235 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:55,235 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1218886279] [2023-11-19 07:43:55,235 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:55,236 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:55,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:55,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:55,313 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:55,313 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1218886279] [2023-11-19 07:43:55,314 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1218886279] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:55,314 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:55,314 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:55,314 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [332278881] [2023-11-19 07:43:55,314 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:55,315 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:55,315 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:55,316 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:43:55,316 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:43:55,316 INFO L87 Difference]: Start difference. First operand 1289 states and 1909 transitions. cyclomatic complexity: 621 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:55,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:55,353 INFO L93 Difference]: Finished difference Result 1289 states and 1908 transitions. [2023-11-19 07:43:55,353 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1289 states and 1908 transitions. [2023-11-19 07:43:55,366 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-19 07:43:55,377 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1289 states to 1289 states and 1908 transitions. [2023-11-19 07:43:55,378 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-19 07:43:55,379 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-19 07:43:55,379 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1908 transitions. [2023-11-19 07:43:55,383 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:55,383 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1908 transitions. [2023-11-19 07:43:55,386 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1908 transitions. [2023-11-19 07:43:55,406 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-19 07:43:55,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.4802172226532195) internal successors, (1908), 1288 states have internal predecessors, (1908), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:55,463 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1908 transitions. [2023-11-19 07:43:55,463 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1908 transitions. [2023-11-19 07:43:55,466 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:43:55,467 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1908 transitions. [2023-11-19 07:43:55,467 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-19 07:43:55,467 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1908 transitions. [2023-11-19 07:43:55,477 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-19 07:43:55,477 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:55,477 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:55,480 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:55,480 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:55,481 INFO L748 eck$LassoCheckResult]: Stem: 13301#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 13302#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 14154#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14155#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14222#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 14216#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14217#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13470#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13213#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13214#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14123#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14124#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14105#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14106#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14146#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13264#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13265#L1006 assume !(0 == ~M_E~0); 13116#L1006-2 assume !(0 == ~T1_E~0); 13117#L1011-1 assume !(0 == ~T2_E~0); 14171#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14188#L1021-1 assume !(0 == ~T4_E~0); 12994#L1026-1 assume !(0 == ~T5_E~0); 12995#L1031-1 assume !(0 == ~T6_E~0); 13883#L1036-1 assume !(0 == ~T7_E~0); 13879#L1041-1 assume !(0 == ~T8_E~0); 13880#L1046-1 assume !(0 == ~T9_E~0); 13292#L1051-1 assume !(0 == ~T10_E~0); 13293#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 14009#L1061-1 assume !(0 == ~E_2~0); 13217#L1066-1 assume !(0 == ~E_3~0); 13218#L1071-1 assume !(0 == ~E_4~0); 13984#L1076-1 assume !(0 == ~E_5~0); 13124#L1081-1 assume !(0 == ~E_6~0); 13125#L1086-1 assume !(0 == ~E_7~0); 13444#L1091-1 assume !(0 == ~E_8~0); 14163#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 14164#L1101-1 assume !(0 == ~E_10~0); 13513#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13514#L484 assume !(1 == ~m_pc~0); 13174#L484-2 is_master_triggered_~__retres1~0#1 := 0; 13173#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13796#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14077#L1245 assume !(0 != activate_threads_~tmp~1#1); 14078#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13869#L503 assume 1 == ~t1_pc~0; 13870#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13889#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13035#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13036#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 13029#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13030#L522 assume !(1 == ~t2_pc~0); 13835#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13228#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13229#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13508#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 14125#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14196#L541 assume 1 == ~t3_pc~0; 13778#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13580#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12976#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12977#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 13841#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13842#L560 assume !(1 == ~t4_pc~0); 13110#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 13109#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13140#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12990#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 12991#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13275#L579 assume 1 == ~t5_pc~0; 12941#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12942#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13055#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14082#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 14187#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14206#L598 assume 1 == ~t6_pc~0; 13357#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13358#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13486#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13487#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 13915#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13860#L617 assume !(1 == ~t7_pc~0); 13333#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13332#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14226#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14137#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13548#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13549#L636 assume 1 == ~t8_pc~0; 13731#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13732#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14038#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13924#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 13680#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13681#L655 assume !(1 == ~t9_pc~0); 13708#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 13709#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13594#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13595#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 13935#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13936#L674 assume 1 == ~t10_pc~0; 13101#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13102#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13722#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13723#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 13669#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13670#L1119 assume !(1 == ~M_E~0); 13200#L1119-2 assume !(1 == ~T1_E~0); 13201#L1124-1 assume !(1 == ~T2_E~0); 13019#L1129-1 assume !(1 == ~T3_E~0); 13020#L1134-1 assume !(1 == ~T4_E~0); 13318#L1139-1 assume !(1 == ~T5_E~0); 13319#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13543#L1149-1 assume !(1 == ~T7_E~0); 13194#L1154-1 assume !(1 == ~T8_E~0); 13195#L1159-1 assume !(1 == ~T9_E~0); 13276#L1164-1 assume !(1 == ~T10_E~0); 13697#L1169-1 assume !(1 == ~E_1~0); 13596#L1174-1 assume !(1 == ~E_2~0); 13370#L1179-1 assume !(1 == ~E_3~0); 13266#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 13267#L1189-1 assume !(1 == ~E_5~0); 13316#L1194-1 assume !(1 == ~E_6~0); 13422#L1199-1 assume !(1 == ~E_7~0); 13382#L1204-1 assume !(1 == ~E_8~0); 13383#L1209-1 assume !(1 == ~E_9~0); 13933#L1214-1 assume !(1 == ~E_10~0); 13934#L1219-1 assume { :end_inline_reset_delta_events } true; 12978#L1520-2 [2023-11-19 07:43:55,481 INFO L750 eck$LassoCheckResult]: Loop: 12978#L1520-2 assume !false; 12979#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13770#L981-1 assume !false; 13955#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 13956#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 12962#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13563#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13564#L836 assume !(0 != eval_~tmp~0#1); 14047#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13739#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13535#L1006-3 assume !(0 == ~M_E~0); 13536#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14033#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14034#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14071#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13750#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13751#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14001#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14002#L1041-3 assume !(0 == ~T8_E~0); 14065#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14066#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 14003#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13289#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13290#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13291#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14174#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13083#L1081-3 assume !(0 == ~E_6~0); 13084#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13131#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13132#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 14147#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14148#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13772#L484-33 assume !(1 == ~m_pc~0); 13773#L484-35 is_master_triggered_~__retres1~0#1 := 0; 13683#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13684#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12984#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 12985#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13430#L503-33 assume 1 == ~t1_pc~0; 13431#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13918#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13919#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13351#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13352#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13810#L522-33 assume !(1 == ~t2_pc~0); 13811#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 13121#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13122#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14019#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13831#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13832#L541-33 assume 1 == ~t3_pc~0; 13141#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12982#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12983#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13150#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13802#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13999#L560-33 assume 1 == ~t4_pc~0; 13687#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13059#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13060#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14176#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13978#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12968#L579-33 assume 1 == ~t5_pc~0; 12969#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13222#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14192#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13861#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13862#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13888#L598-33 assume 1 == ~t6_pc~0; 14194#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13454#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13455#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13313#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13314#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14136#L617-33 assume 1 == ~t7_pc~0; 14144#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13115#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14070#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14089#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14175#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13049#L636-33 assume 1 == ~t8_pc~0; 13050#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13971#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13833#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13834#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13962#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13963#L655-33 assume !(1 == ~t9_pc~0); 14224#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 13400#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13401#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14022#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 14051#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13593#L674-33 assume 1 == ~t10_pc~0; 13449#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13450#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14095#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13819#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13820#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14197#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14207#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14209#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14219#L1129-3 assume !(1 == ~T3_E~0); 13344#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13345#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13582#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13583#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13737#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14014#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14015#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14182#L1169-3 assume !(1 == ~E_1~0); 13452#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13453#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14100#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13106#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13107#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13397#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13398#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13721#L1209-3 assume !(1 == ~E_9~0); 12996#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12997#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 13923#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13086#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13440#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 13441#L1539 assume !(0 == start_simulation_~tmp~3#1); 13511#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 13698#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13493#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13025#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 13026#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13405#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13759#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 13512#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 12978#L1520-2 [2023-11-19 07:43:55,483 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:55,483 INFO L85 PathProgramCache]: Analyzing trace with hash 709992811, now seen corresponding path program 1 times [2023-11-19 07:43:55,483 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:55,483 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1218736589] [2023-11-19 07:43:55,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:55,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:55,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:55,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:55,538 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:55,539 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1218736589] [2023-11-19 07:43:55,539 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1218736589] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:55,539 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:55,539 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:55,539 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1250822082] [2023-11-19 07:43:55,540 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:55,540 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:55,541 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:55,541 INFO L85 PathProgramCache]: Analyzing trace with hash 1198674282, now seen corresponding path program 1 times [2023-11-19 07:43:55,546 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:55,546 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1335693704] [2023-11-19 07:43:55,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:55,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:55,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:55,623 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:55,623 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:55,624 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1335693704] [2023-11-19 07:43:55,624 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1335693704] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:55,624 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:55,624 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:55,624 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [40611680] [2023-11-19 07:43:55,625 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:55,625 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:55,626 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:55,626 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:43:55,626 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:43:55,627 INFO L87 Difference]: Start difference. First operand 1289 states and 1908 transitions. cyclomatic complexity: 620 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:55,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:55,661 INFO L93 Difference]: Finished difference Result 1289 states and 1907 transitions. [2023-11-19 07:43:55,662 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1289 states and 1907 transitions. [2023-11-19 07:43:55,673 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-19 07:43:55,684 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1289 states to 1289 states and 1907 transitions. [2023-11-19 07:43:55,684 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-19 07:43:55,686 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-19 07:43:55,686 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1907 transitions. [2023-11-19 07:43:55,688 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:55,689 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1907 transitions. [2023-11-19 07:43:55,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1907 transitions. [2023-11-19 07:43:55,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-19 07:43:55,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.4794414274631498) internal successors, (1907), 1288 states have internal predecessors, (1907), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:55,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1907 transitions. [2023-11-19 07:43:55,722 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1907 transitions. [2023-11-19 07:43:55,722 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:43:55,724 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1907 transitions. [2023-11-19 07:43:55,724 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-19 07:43:55,725 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1907 transitions. [2023-11-19 07:43:55,733 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-19 07:43:55,734 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:55,734 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:55,736 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:55,737 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:55,737 INFO L748 eck$LassoCheckResult]: Stem: 15886#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 15887#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 16739#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16740#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16807#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 16801#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16802#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16055#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15800#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15801#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16708#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16709#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16690#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16691#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16731#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15849#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15850#L1006 assume !(0 == ~M_E~0); 15704#L1006-2 assume !(0 == ~T1_E~0); 15705#L1011-1 assume !(0 == ~T2_E~0); 16756#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16773#L1021-1 assume !(0 == ~T4_E~0); 15579#L1026-1 assume !(0 == ~T5_E~0); 15580#L1031-1 assume !(0 == ~T6_E~0); 16469#L1036-1 assume !(0 == ~T7_E~0); 16464#L1041-1 assume !(0 == ~T8_E~0); 16465#L1046-1 assume !(0 == ~T9_E~0); 15877#L1051-1 assume !(0 == ~T10_E~0); 15878#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 16594#L1061-1 assume !(0 == ~E_2~0); 15802#L1066-1 assume !(0 == ~E_3~0); 15803#L1071-1 assume !(0 == ~E_4~0); 16569#L1076-1 assume !(0 == ~E_5~0); 15709#L1081-1 assume !(0 == ~E_6~0); 15710#L1086-1 assume !(0 == ~E_7~0); 16029#L1091-1 assume !(0 == ~E_8~0); 16748#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 16749#L1101-1 assume !(0 == ~E_10~0); 16098#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16099#L484 assume !(1 == ~m_pc~0); 15761#L484-2 is_master_triggered_~__retres1~0#1 := 0; 15760#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16381#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16662#L1245 assume !(0 != activate_threads_~tmp~1#1); 16663#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16454#L503 assume 1 == ~t1_pc~0; 16455#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16478#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15620#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15621#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 15616#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15617#L522 assume !(1 == ~t2_pc~0); 16420#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15817#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15818#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16094#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 16710#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16781#L541 assume 1 == ~t3_pc~0; 16365#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16165#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15563#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15564#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 16430#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16431#L560 assume !(1 == ~t4_pc~0); 15695#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15694#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15725#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15575#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 15576#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15860#L579 assume 1 == ~t5_pc~0; 15526#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15527#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15640#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16667#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 16772#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16791#L598 assume 1 == ~t6_pc~0; 15942#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15943#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16071#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16072#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 16500#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16445#L617 assume !(1 == ~t7_pc~0); 15918#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 15917#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16811#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16722#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16135#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16136#L636 assume 1 == ~t8_pc~0; 16316#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16317#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16627#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16508#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 16263#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16264#L655 assume !(1 == ~t9_pc~0); 16291#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 16292#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16175#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16176#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 16520#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16521#L674 assume 1 == ~t10_pc~0; 15686#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15687#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16306#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16307#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 16254#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16255#L1119 assume !(1 == ~M_E~0); 15785#L1119-2 assume !(1 == ~T1_E~0); 15786#L1124-1 assume !(1 == ~T2_E~0); 15604#L1129-1 assume !(1 == ~T3_E~0); 15605#L1134-1 assume !(1 == ~T4_E~0); 15902#L1139-1 assume !(1 == ~T5_E~0); 15903#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16128#L1149-1 assume !(1 == ~T7_E~0); 15779#L1154-1 assume !(1 == ~T8_E~0); 15780#L1159-1 assume !(1 == ~T9_E~0); 15861#L1164-1 assume !(1 == ~T10_E~0); 16282#L1169-1 assume !(1 == ~E_1~0); 16181#L1174-1 assume !(1 == ~E_2~0); 15955#L1179-1 assume !(1 == ~E_3~0); 15851#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15852#L1189-1 assume !(1 == ~E_5~0); 15900#L1194-1 assume !(1 == ~E_6~0); 16006#L1199-1 assume !(1 == ~E_7~0); 15967#L1204-1 assume !(1 == ~E_8~0); 15968#L1209-1 assume !(1 == ~E_9~0); 16518#L1214-1 assume !(1 == ~E_10~0); 16519#L1219-1 assume { :end_inline_reset_delta_events } true; 15561#L1520-2 [2023-11-19 07:43:55,738 INFO L750 eck$LassoCheckResult]: Loop: 15561#L1520-2 assume !false; 15562#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16355#L981-1 assume !false; 16540#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16541#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 15547#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16145#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16146#L836 assume !(0 != eval_~tmp~0#1); 16632#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16324#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16120#L1006-3 assume !(0 == ~M_E~0); 16121#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16618#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16619#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16656#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16333#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16334#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16586#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16587#L1041-3 assume !(0 == ~T8_E~0); 16648#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16649#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16588#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15874#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15875#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15876#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16759#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15668#L1081-3 assume !(0 == ~E_6~0); 15669#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15714#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15715#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16732#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16733#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16357#L484-33 assume !(1 == ~m_pc~0); 16358#L484-35 is_master_triggered_~__retres1~0#1 := 0; 16268#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16269#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15569#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 15570#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16014#L503-33 assume !(1 == ~t1_pc~0); 16016#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 16503#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16504#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15936#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15937#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16395#L522-33 assume !(1 == ~t2_pc~0); 16396#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 15706#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15707#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16604#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16416#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16417#L541-33 assume 1 == ~t3_pc~0; 15726#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15567#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15568#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15735#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16387#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16584#L560-33 assume 1 == ~t4_pc~0; 16272#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15644#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15645#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16761#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16563#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15556#L579-33 assume 1 == ~t5_pc~0; 15557#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15807#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16777#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16446#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16447#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16477#L598-33 assume !(1 == ~t6_pc~0); 16232#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 16039#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16040#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15898#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15899#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16721#L617-33 assume !(1 == ~t7_pc~0); 15699#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 15700#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16655#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16674#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16760#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15634#L636-33 assume 1 == ~t8_pc~0; 15635#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16556#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16418#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16419#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16547#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16548#L655-33 assume 1 == ~t9_pc~0; 16808#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15987#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15988#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16607#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 16636#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16180#L674-33 assume 1 == ~t10_pc~0; 16034#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16035#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16680#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16404#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16405#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16782#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16792#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16794#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16804#L1129-3 assume !(1 == ~T3_E~0); 15932#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15933#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16167#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16168#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16322#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16599#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16600#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16768#L1169-3 assume !(1 == ~E_1~0); 16037#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16038#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16685#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15691#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15692#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15982#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15983#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16308#L1209-3 assume !(1 == ~E_9~0); 15583#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15584#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16510#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 15671#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16025#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 16026#L1539 assume !(0 == start_simulation_~tmp~3#1); 16096#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16283#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16078#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 15612#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 15613#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15990#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16344#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 16097#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 15561#L1520-2 [2023-11-19 07:43:55,739 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:55,739 INFO L85 PathProgramCache]: Analyzing trace with hash 1042635949, now seen corresponding path program 1 times [2023-11-19 07:43:55,740 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:55,740 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1040720318] [2023-11-19 07:43:55,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:55,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:55,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:55,806 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:55,806 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:55,807 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1040720318] [2023-11-19 07:43:55,807 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1040720318] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:55,807 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:55,807 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:55,807 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1390737095] [2023-11-19 07:43:55,808 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:55,808 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:55,808 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:55,809 INFO L85 PathProgramCache]: Analyzing trace with hash -1952021528, now seen corresponding path program 1 times [2023-11-19 07:43:55,809 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:55,809 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1190682477] [2023-11-19 07:43:55,809 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:55,810 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:55,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:55,879 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:55,879 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:55,879 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1190682477] [2023-11-19 07:43:55,880 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1190682477] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:55,880 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:55,880 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:55,880 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1592122014] [2023-11-19 07:43:55,881 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:55,881 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:55,881 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:55,882 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:43:55,882 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:43:55,882 INFO L87 Difference]: Start difference. First operand 1289 states and 1907 transitions. cyclomatic complexity: 619 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:55,919 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:55,919 INFO L93 Difference]: Finished difference Result 1289 states and 1906 transitions. [2023-11-19 07:43:55,920 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1289 states and 1906 transitions. [2023-11-19 07:43:55,932 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-19 07:43:55,945 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1289 states to 1289 states and 1906 transitions. [2023-11-19 07:43:55,945 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-19 07:43:55,947 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-19 07:43:55,947 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1906 transitions. [2023-11-19 07:43:55,949 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:55,949 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1906 transitions. [2023-11-19 07:43:55,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1906 transitions. [2023-11-19 07:43:55,974 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-19 07:43:55,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.47866563227308) internal successors, (1906), 1288 states have internal predecessors, (1906), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:55,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1906 transitions. [2023-11-19 07:43:55,984 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1906 transitions. [2023-11-19 07:43:55,985 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:43:55,987 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1906 transitions. [2023-11-19 07:43:55,988 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-19 07:43:55,988 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1906 transitions. [2023-11-19 07:43:55,995 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-19 07:43:55,995 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:55,995 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:55,998 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:55,998 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:55,999 INFO L748 eck$LassoCheckResult]: Stem: 18471#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 18472#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 19323#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19324#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19392#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 19386#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19387#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18638#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18383#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18384#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19293#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19294#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19275#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19276#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19316#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18432#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18433#L1006 assume !(0 == ~M_E~0); 18286#L1006-2 assume !(0 == ~T1_E~0); 18287#L1011-1 assume !(0 == ~T2_E~0); 19341#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19358#L1021-1 assume !(0 == ~T4_E~0); 18162#L1026-1 assume !(0 == ~T5_E~0); 18163#L1031-1 assume !(0 == ~T6_E~0); 19052#L1036-1 assume !(0 == ~T7_E~0); 19049#L1041-1 assume !(0 == ~T8_E~0); 19050#L1046-1 assume !(0 == ~T9_E~0); 18462#L1051-1 assume !(0 == ~T10_E~0); 18463#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 19179#L1061-1 assume !(0 == ~E_2~0); 18387#L1066-1 assume !(0 == ~E_3~0); 18388#L1071-1 assume !(0 == ~E_4~0); 19154#L1076-1 assume !(0 == ~E_5~0); 18294#L1081-1 assume !(0 == ~E_6~0); 18295#L1086-1 assume !(0 == ~E_7~0); 18612#L1091-1 assume !(0 == ~E_8~0); 19331#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 19332#L1101-1 assume !(0 == ~E_10~0); 18683#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18684#L484 assume !(1 == ~m_pc~0); 18344#L484-2 is_master_triggered_~__retres1~0#1 := 0; 18343#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18966#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19247#L1245 assume !(0 != activate_threads_~tmp~1#1); 19248#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19039#L503 assume 1 == ~t1_pc~0; 19040#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19058#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18203#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18204#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 18199#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18200#L522 assume !(1 == ~t2_pc~0); 19005#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18398#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18399#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18678#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 19295#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19366#L541 assume 1 == ~t3_pc~0; 18948#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18750#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18146#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18147#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 19011#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19012#L560 assume !(1 == ~t4_pc~0); 18278#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18277#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18310#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18160#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 18161#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18443#L579 assume 1 == ~t5_pc~0; 18111#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18112#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18225#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19252#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 19356#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19376#L598 assume 1 == ~t6_pc~0; 18527#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18528#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18653#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18654#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 19085#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19030#L617 assume !(1 == ~t7_pc~0); 18503#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18502#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19396#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19307#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18717#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18718#L636 assume 1 == ~t8_pc~0; 18901#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18902#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19207#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19093#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 18848#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18849#L655 assume !(1 == ~t9_pc~0); 18876#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 18877#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18760#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18761#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 19105#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19106#L674 assume 1 == ~t10_pc~0; 18271#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 18272#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18891#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18892#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 18839#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18840#L1119 assume !(1 == ~M_E~0); 18370#L1119-2 assume !(1 == ~T1_E~0); 18371#L1124-1 assume !(1 == ~T2_E~0); 18189#L1129-1 assume !(1 == ~T3_E~0); 18190#L1134-1 assume !(1 == ~T4_E~0); 18487#L1139-1 assume !(1 == ~T5_E~0); 18488#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18713#L1149-1 assume !(1 == ~T7_E~0); 18364#L1154-1 assume !(1 == ~T8_E~0); 18365#L1159-1 assume !(1 == ~T9_E~0); 18446#L1164-1 assume !(1 == ~T10_E~0); 18867#L1169-1 assume !(1 == ~E_1~0); 18766#L1174-1 assume !(1 == ~E_2~0); 18540#L1179-1 assume !(1 == ~E_3~0); 18436#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 18437#L1189-1 assume !(1 == ~E_5~0); 18485#L1194-1 assume !(1 == ~E_6~0); 18591#L1199-1 assume !(1 == ~E_7~0); 18552#L1204-1 assume !(1 == ~E_8~0); 18553#L1209-1 assume !(1 == ~E_9~0); 19103#L1214-1 assume !(1 == ~E_10~0); 19104#L1219-1 assume { :end_inline_reset_delta_events } true; 18148#L1520-2 [2023-11-19 07:43:56,000 INFO L750 eck$LassoCheckResult]: Loop: 18148#L1520-2 assume !false; 18149#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18940#L981-1 assume !false; 19125#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19126#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 18132#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 18730#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18731#L836 assume !(0 != eval_~tmp~0#1); 19217#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18909#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18705#L1006-3 assume !(0 == ~M_E~0); 18706#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19203#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19204#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19241#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18918#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18919#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19171#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19172#L1041-3 assume !(0 == ~T8_E~0); 19233#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19234#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19173#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18459#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18460#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18461#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19344#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18253#L1081-3 assume !(0 == ~E_6~0); 18254#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18299#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18300#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19317#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19318#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18942#L484-33 assume 1 == ~m_pc~0; 18944#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 18853#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18854#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18154#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 18155#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18599#L503-33 assume 1 == ~t1_pc~0; 18600#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19088#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19089#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18521#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18522#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18980#L522-33 assume !(1 == ~t2_pc~0); 18981#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 18291#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18292#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19189#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19001#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19002#L541-33 assume 1 == ~t3_pc~0; 18311#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18152#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18153#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18320#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18972#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19169#L560-33 assume 1 == ~t4_pc~0; 18857#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18229#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18230#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19346#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19148#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18141#L579-33 assume 1 == ~t5_pc~0; 18142#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18392#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19362#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19031#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19032#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19063#L598-33 assume !(1 == ~t6_pc~0); 18817#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 18624#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18625#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18483#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18484#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19306#L617-33 assume 1 == ~t7_pc~0; 19314#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18285#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19240#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19259#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19345#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18219#L636-33 assume 1 == ~t8_pc~0; 18220#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19141#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19003#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19004#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19132#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19133#L655-33 assume 1 == ~t9_pc~0; 19393#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18572#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18573#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19192#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 19221#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18765#L674-33 assume 1 == ~t10_pc~0; 18619#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 18620#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19265#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18989#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 18990#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19367#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19377#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19379#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19389#L1129-3 assume !(1 == ~T3_E~0); 18517#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18518#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18752#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18753#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18907#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19184#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19185#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19353#L1169-3 assume !(1 == ~E_1~0); 18622#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18623#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19270#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18279#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18280#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18567#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18568#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18893#L1209-3 assume !(1 == ~E_9~0); 18168#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 18169#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19095#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 18256#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 18610#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 18611#L1539 assume !(0 == start_simulation_~tmp~3#1); 18681#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 18868#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 18663#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 18197#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 18198#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18575#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18929#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 18682#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 18148#L1520-2 [2023-11-19 07:43:56,001 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:56,001 INFO L85 PathProgramCache]: Analyzing trace with hash -886296277, now seen corresponding path program 1 times [2023-11-19 07:43:56,001 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:56,001 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1424622595] [2023-11-19 07:43:56,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:56,002 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:56,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:56,105 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:56,105 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:56,105 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1424622595] [2023-11-19 07:43:56,106 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1424622595] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:56,106 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:56,106 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:56,106 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [670539932] [2023-11-19 07:43:56,106 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:56,107 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:56,107 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:56,107 INFO L85 PathProgramCache]: Analyzing trace with hash -80312693, now seen corresponding path program 1 times [2023-11-19 07:43:56,107 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:56,108 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [245011837] [2023-11-19 07:43:56,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:56,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:56,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:56,191 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:56,192 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:56,192 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [245011837] [2023-11-19 07:43:56,195 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [245011837] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:56,195 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:56,195 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:56,195 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [496743605] [2023-11-19 07:43:56,196 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:56,196 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:56,196 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:56,197 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:43:56,197 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:43:56,198 INFO L87 Difference]: Start difference. First operand 1289 states and 1906 transitions. cyclomatic complexity: 618 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:56,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:56,247 INFO L93 Difference]: Finished difference Result 1289 states and 1905 transitions. [2023-11-19 07:43:56,248 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1289 states and 1905 transitions. [2023-11-19 07:43:56,258 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-19 07:43:56,269 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1289 states to 1289 states and 1905 transitions. [2023-11-19 07:43:56,269 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-19 07:43:56,270 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-19 07:43:56,271 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1905 transitions. [2023-11-19 07:43:56,273 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:56,273 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1905 transitions. [2023-11-19 07:43:56,277 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1905 transitions. [2023-11-19 07:43:56,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-19 07:43:56,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.47788983708301) internal successors, (1905), 1288 states have internal predecessors, (1905), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:56,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1905 transitions. [2023-11-19 07:43:56,311 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1905 transitions. [2023-11-19 07:43:56,311 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:43:56,314 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1905 transitions. [2023-11-19 07:43:56,315 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-19 07:43:56,315 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1905 transitions. [2023-11-19 07:43:56,325 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-19 07:43:56,325 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:56,326 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:56,328 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:56,329 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:56,329 INFO L748 eck$LassoCheckResult]: Stem: 21056#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 21057#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 21909#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21910#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21977#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 21971#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21972#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21223#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20968#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20969#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21878#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 21879#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 21860#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 21861#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21901#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21019#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21020#L1006 assume !(0 == ~M_E~0); 20871#L1006-2 assume !(0 == ~T1_E~0); 20872#L1011-1 assume !(0 == ~T2_E~0); 21926#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21943#L1021-1 assume !(0 == ~T4_E~0); 20749#L1026-1 assume !(0 == ~T5_E~0); 20750#L1031-1 assume !(0 == ~T6_E~0); 21637#L1036-1 assume !(0 == ~T7_E~0); 21634#L1041-1 assume !(0 == ~T8_E~0); 21635#L1046-1 assume !(0 == ~T9_E~0); 21047#L1051-1 assume !(0 == ~T10_E~0); 21048#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 21764#L1061-1 assume !(0 == ~E_2~0); 20972#L1066-1 assume !(0 == ~E_3~0); 20973#L1071-1 assume !(0 == ~E_4~0); 21739#L1076-1 assume !(0 == ~E_5~0); 20879#L1081-1 assume !(0 == ~E_6~0); 20880#L1086-1 assume !(0 == ~E_7~0); 21197#L1091-1 assume !(0 == ~E_8~0); 21916#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 21917#L1101-1 assume !(0 == ~E_10~0); 21268#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21269#L484 assume !(1 == ~m_pc~0); 20929#L484-2 is_master_triggered_~__retres1~0#1 := 0; 20928#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21551#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21832#L1245 assume !(0 != activate_threads_~tmp~1#1); 21833#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21624#L503 assume 1 == ~t1_pc~0; 21625#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21643#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20788#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20789#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 20784#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20785#L522 assume !(1 == ~t2_pc~0); 21590#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20983#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20984#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21263#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 21880#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21951#L541 assume 1 == ~t3_pc~0; 21533#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21335#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20731#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20732#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 21596#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21597#L560 assume !(1 == ~t4_pc~0); 20865#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20864#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20895#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20745#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 20746#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21028#L579 assume 1 == ~t5_pc~0; 20696#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20697#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20810#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21837#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 21941#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21961#L598 assume 1 == ~t6_pc~0; 21112#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21113#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21238#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21239#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 21670#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21615#L617 assume !(1 == ~t7_pc~0); 21088#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 21087#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21981#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21892#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21302#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21303#L636 assume 1 == ~t8_pc~0; 21486#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21487#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21792#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21679#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 21433#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21434#L655 assume !(1 == ~t9_pc~0); 21463#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 21464#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21346#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21347#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 21690#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21691#L674 assume 1 == ~t10_pc~0; 20856#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20857#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21477#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21478#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 21424#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21425#L1119 assume !(1 == ~M_E~0); 20955#L1119-2 assume !(1 == ~T1_E~0); 20956#L1124-1 assume !(1 == ~T2_E~0); 20774#L1129-1 assume !(1 == ~T3_E~0); 20775#L1134-1 assume !(1 == ~T4_E~0); 21073#L1139-1 assume !(1 == ~T5_E~0); 21074#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21298#L1149-1 assume !(1 == ~T7_E~0); 20949#L1154-1 assume !(1 == ~T8_E~0); 20950#L1159-1 assume !(1 == ~T9_E~0); 21031#L1164-1 assume !(1 == ~T10_E~0); 21452#L1169-1 assume !(1 == ~E_1~0); 21351#L1174-1 assume !(1 == ~E_2~0); 21125#L1179-1 assume !(1 == ~E_3~0); 21021#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 21022#L1189-1 assume !(1 == ~E_5~0); 21070#L1194-1 assume !(1 == ~E_6~0); 21176#L1199-1 assume !(1 == ~E_7~0); 21137#L1204-1 assume !(1 == ~E_8~0); 21138#L1209-1 assume !(1 == ~E_9~0); 21688#L1214-1 assume !(1 == ~E_10~0); 21689#L1219-1 assume { :end_inline_reset_delta_events } true; 20733#L1520-2 [2023-11-19 07:43:56,330 INFO L750 eck$LassoCheckResult]: Loop: 20733#L1520-2 assume !false; 20734#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21525#L981-1 assume !false; 21710#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 21711#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 20717#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 21318#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21319#L836 assume !(0 != eval_~tmp~0#1); 21802#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21494#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21290#L1006-3 assume !(0 == ~M_E~0); 21291#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21788#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21789#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21826#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21503#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21504#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21756#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21757#L1041-3 assume !(0 == ~T8_E~0); 21818#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21819#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21758#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21044#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21045#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21046#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21929#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20838#L1081-3 assume !(0 == ~E_6~0); 20839#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20884#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20885#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21902#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21903#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21527#L484-33 assume !(1 == ~m_pc~0); 21528#L484-35 is_master_triggered_~__retres1~0#1 := 0; 21438#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21439#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20739#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 20740#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21184#L503-33 assume 1 == ~t1_pc~0; 21185#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21673#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21674#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21106#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21107#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21565#L522-33 assume !(1 == ~t2_pc~0); 21566#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 20876#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20877#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21774#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21588#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21589#L541-33 assume 1 == ~t3_pc~0; 20896#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20737#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20738#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20905#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21557#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21754#L560-33 assume 1 == ~t4_pc~0; 21442#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20814#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20815#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21931#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21733#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20726#L579-33 assume 1 == ~t5_pc~0; 20727#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20977#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21947#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21616#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21617#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21648#L598-33 assume !(1 == ~t6_pc~0); 21403#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 21209#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21210#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21068#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21069#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21891#L617-33 assume !(1 == ~t7_pc~0); 20869#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 20870#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21825#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21844#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21930#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20801#L636-33 assume 1 == ~t8_pc~0; 20802#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21726#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21586#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21587#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21715#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21716#L655-33 assume 1 == ~t9_pc~0; 21978#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21154#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21155#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21777#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 21805#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21345#L674-33 assume 1 == ~t10_pc~0; 21204#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21205#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21849#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21574#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21575#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21952#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21962#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21964#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21974#L1129-3 assume !(1 == ~T3_E~0); 21099#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21100#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21337#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21338#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21492#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21769#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21770#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21937#L1169-3 assume !(1 == ~E_1~0); 21207#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21208#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21855#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20861#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20862#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21152#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21153#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21476#L1209-3 assume !(1 == ~E_9~0); 20751#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20752#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 21678#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 20841#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 21195#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 21196#L1539 assume !(0 == start_simulation_~tmp~3#1); 21266#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 21453#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 21248#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 20780#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 20781#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21160#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21514#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 21267#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 20733#L1520-2 [2023-11-19 07:43:56,332 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:56,332 INFO L85 PathProgramCache]: Analyzing trace with hash 1406784749, now seen corresponding path program 1 times [2023-11-19 07:43:56,333 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:56,333 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1161466806] [2023-11-19 07:43:56,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:56,333 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:56,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:56,392 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:56,393 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:56,393 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1161466806] [2023-11-19 07:43:56,393 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1161466806] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:56,394 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:56,394 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:56,394 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1610057195] [2023-11-19 07:43:56,394 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:56,395 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:56,396 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:56,396 INFO L85 PathProgramCache]: Analyzing trace with hash 2069950345, now seen corresponding path program 2 times [2023-11-19 07:43:56,396 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:56,396 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [900174524] [2023-11-19 07:43:56,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:56,397 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:56,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:56,480 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:56,480 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:56,481 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [900174524] [2023-11-19 07:43:56,481 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [900174524] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:56,481 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:56,481 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:56,482 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [205759698] [2023-11-19 07:43:56,482 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:56,482 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:56,483 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:56,483 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:43:56,483 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:43:56,484 INFO L87 Difference]: Start difference. First operand 1289 states and 1905 transitions. cyclomatic complexity: 617 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:56,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:56,530 INFO L93 Difference]: Finished difference Result 1289 states and 1904 transitions. [2023-11-19 07:43:56,530 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1289 states and 1904 transitions. [2023-11-19 07:43:56,542 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-19 07:43:56,554 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1289 states to 1289 states and 1904 transitions. [2023-11-19 07:43:56,554 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-19 07:43:56,559 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-19 07:43:56,559 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1904 transitions. [2023-11-19 07:43:56,562 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:56,562 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1904 transitions. [2023-11-19 07:43:56,565 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1904 transitions. [2023-11-19 07:43:56,589 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-19 07:43:56,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.4771140418929403) internal successors, (1904), 1288 states have internal predecessors, (1904), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:56,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1904 transitions. [2023-11-19 07:43:56,599 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1904 transitions. [2023-11-19 07:43:56,600 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:43:56,602 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1904 transitions. [2023-11-19 07:43:56,602 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-19 07:43:56,602 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1904 transitions. [2023-11-19 07:43:56,609 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-19 07:43:56,609 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:56,610 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:56,612 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:56,612 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:56,613 INFO L748 eck$LassoCheckResult]: Stem: 23641#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 23642#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 24494#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24495#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24562#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 24556#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24557#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23810#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23553#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23554#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24463#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24464#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24445#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24446#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24486#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 23604#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23605#L1006 assume !(0 == ~M_E~0); 23456#L1006-2 assume !(0 == ~T1_E~0); 23457#L1011-1 assume !(0 == ~T2_E~0); 24511#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24528#L1021-1 assume !(0 == ~T4_E~0); 23334#L1026-1 assume !(0 == ~T5_E~0); 23335#L1031-1 assume !(0 == ~T6_E~0); 24223#L1036-1 assume !(0 == ~T7_E~0); 24219#L1041-1 assume !(0 == ~T8_E~0); 24220#L1046-1 assume !(0 == ~T9_E~0); 23632#L1051-1 assume !(0 == ~T10_E~0); 23633#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 24349#L1061-1 assume !(0 == ~E_2~0); 23557#L1066-1 assume !(0 == ~E_3~0); 23558#L1071-1 assume !(0 == ~E_4~0); 24324#L1076-1 assume !(0 == ~E_5~0); 23464#L1081-1 assume !(0 == ~E_6~0); 23465#L1086-1 assume !(0 == ~E_7~0); 23784#L1091-1 assume !(0 == ~E_8~0); 24503#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 24504#L1101-1 assume !(0 == ~E_10~0); 23853#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23854#L484 assume !(1 == ~m_pc~0); 23516#L484-2 is_master_triggered_~__retres1~0#1 := 0; 23515#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24136#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24417#L1245 assume !(0 != activate_threads_~tmp~1#1); 24418#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24209#L503 assume 1 == ~t1_pc~0; 24210#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24229#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23375#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23376#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 23369#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23370#L522 assume !(1 == ~t2_pc~0); 24175#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23569#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23570#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23849#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 24465#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24536#L541 assume 1 == ~t3_pc~0; 24118#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23920#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23316#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23317#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 24181#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24182#L560 assume !(1 == ~t4_pc~0); 23450#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 23449#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23480#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23330#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 23331#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23615#L579 assume 1 == ~t5_pc~0; 23281#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23282#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23395#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24422#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 24527#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24546#L598 assume 1 == ~t6_pc~0; 23697#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23698#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23826#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23827#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 24255#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24200#L617 assume !(1 == ~t7_pc~0); 23673#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 23672#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24566#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24477#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 23888#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23889#L636 assume 1 == ~t8_pc~0; 24071#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24072#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24378#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24264#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 24020#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24021#L655 assume !(1 == ~t9_pc~0); 24049#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 24050#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23934#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23935#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 24275#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24276#L674 assume 1 == ~t10_pc~0; 23441#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23442#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24062#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24063#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 24009#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24010#L1119 assume !(1 == ~M_E~0); 23540#L1119-2 assume !(1 == ~T1_E~0); 23541#L1124-1 assume !(1 == ~T2_E~0); 23359#L1129-1 assume !(1 == ~T3_E~0); 23360#L1134-1 assume !(1 == ~T4_E~0); 23658#L1139-1 assume !(1 == ~T5_E~0); 23659#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23883#L1149-1 assume !(1 == ~T7_E~0); 23534#L1154-1 assume !(1 == ~T8_E~0); 23535#L1159-1 assume !(1 == ~T9_E~0); 23616#L1164-1 assume !(1 == ~T10_E~0); 24037#L1169-1 assume !(1 == ~E_1~0); 23936#L1174-1 assume !(1 == ~E_2~0); 23710#L1179-1 assume !(1 == ~E_3~0); 23606#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 23607#L1189-1 assume !(1 == ~E_5~0); 23656#L1194-1 assume !(1 == ~E_6~0); 23762#L1199-1 assume !(1 == ~E_7~0); 23722#L1204-1 assume !(1 == ~E_8~0); 23723#L1209-1 assume !(1 == ~E_9~0); 24273#L1214-1 assume !(1 == ~E_10~0); 24274#L1219-1 assume { :end_inline_reset_delta_events } true; 23318#L1520-2 [2023-11-19 07:43:56,614 INFO L750 eck$LassoCheckResult]: Loop: 23318#L1520-2 assume !false; 23319#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24110#L981-1 assume !false; 24295#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24296#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 23302#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 23903#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23904#L836 assume !(0 != eval_~tmp~0#1); 24387#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24079#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23875#L1006-3 assume !(0 == ~M_E~0); 23876#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24373#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24374#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24411#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24090#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24091#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24341#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24342#L1041-3 assume !(0 == ~T8_E~0); 24405#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 24406#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24343#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23629#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23630#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23631#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24514#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23423#L1081-3 assume !(0 == ~E_6~0); 23424#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23473#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23474#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 24487#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24488#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24113#L484-33 assume !(1 == ~m_pc~0); 24114#L484-35 is_master_triggered_~__retres1~0#1 := 0; 24023#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24024#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23324#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 23325#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23766#L503-33 assume 1 == ~t1_pc~0; 23767#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24258#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24259#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23689#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23690#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24147#L522-33 assume !(1 == ~t2_pc~0); 24148#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 23461#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23462#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24359#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24171#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24172#L541-33 assume 1 == ~t3_pc~0; 23481#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23322#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23323#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23490#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24142#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24339#L560-33 assume 1 == ~t4_pc~0; 24027#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23399#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23400#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24516#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24318#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23311#L579-33 assume 1 == ~t5_pc~0; 23312#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23562#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24532#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24201#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24202#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24228#L598-33 assume !(1 == ~t6_pc~0); 23986#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 23794#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23795#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23653#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23654#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24476#L617-33 assume 1 == ~t7_pc~0; 24484#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23455#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24410#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24429#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24515#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23389#L636-33 assume 1 == ~t8_pc~0; 23390#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24311#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24173#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24174#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24302#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24303#L655-33 assume 1 == ~t9_pc~0; 24563#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23740#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23741#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24362#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 24391#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23933#L674-33 assume 1 == ~t10_pc~0; 23789#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23790#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24435#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24159#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24160#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24537#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24547#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24549#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24559#L1129-3 assume !(1 == ~T3_E~0); 23684#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23685#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23922#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23923#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24077#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24354#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24355#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24522#L1169-3 assume !(1 == ~E_1~0); 23792#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23793#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 24440#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23446#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23447#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23737#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 23738#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24061#L1209-3 assume !(1 == ~E_9~0); 23336#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 23337#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24263#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 23426#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 23780#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 23781#L1539 assume !(0 == start_simulation_~tmp~3#1); 23851#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24038#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 23833#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 23367#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 23368#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23745#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24099#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 23852#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 23318#L1520-2 [2023-11-19 07:43:56,615 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:56,615 INFO L85 PathProgramCache]: Analyzing trace with hash 935428399, now seen corresponding path program 1 times [2023-11-19 07:43:56,615 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:56,616 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1121740015] [2023-11-19 07:43:56,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:56,616 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:56,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:56,723 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:56,723 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:56,723 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1121740015] [2023-11-19 07:43:56,723 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1121740015] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:56,724 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:56,724 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:56,724 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [720039396] [2023-11-19 07:43:56,724 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:56,725 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:56,725 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:56,725 INFO L85 PathProgramCache]: Analyzing trace with hash -1083369558, now seen corresponding path program 1 times [2023-11-19 07:43:56,726 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:56,726 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1305165153] [2023-11-19 07:43:56,726 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:56,726 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:56,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:56,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:56,791 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:56,791 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1305165153] [2023-11-19 07:43:56,792 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1305165153] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:56,792 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:56,792 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:56,792 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [228571122] [2023-11-19 07:43:56,792 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:56,793 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:56,793 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:56,793 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:43:56,794 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:43:56,794 INFO L87 Difference]: Start difference. First operand 1289 states and 1904 transitions. cyclomatic complexity: 616 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:56,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:56,962 INFO L93 Difference]: Finished difference Result 2460 states and 3626 transitions. [2023-11-19 07:43:56,962 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2460 states and 3626 transitions. [2023-11-19 07:43:56,982 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2304 [2023-11-19 07:43:57,004 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2460 states to 2460 states and 3626 transitions. [2023-11-19 07:43:57,004 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2460 [2023-11-19 07:43:57,007 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2460 [2023-11-19 07:43:57,008 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2460 states and 3626 transitions. [2023-11-19 07:43:57,012 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:57,012 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2460 states and 3626 transitions. [2023-11-19 07:43:57,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2460 states and 3626 transitions. [2023-11-19 07:43:57,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2460 to 2460. [2023-11-19 07:43:57,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2460 states, 2460 states have (on average 1.4739837398373983) internal successors, (3626), 2459 states have internal predecessors, (3626), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:57,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2460 states to 2460 states and 3626 transitions. [2023-11-19 07:43:57,081 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2460 states and 3626 transitions. [2023-11-19 07:43:57,081 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:43:57,082 INFO L428 stractBuchiCegarLoop]: Abstraction has 2460 states and 3626 transitions. [2023-11-19 07:43:57,082 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-19 07:43:57,082 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2460 states and 3626 transitions. [2023-11-19 07:43:57,096 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2304 [2023-11-19 07:43:57,096 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:57,096 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:57,099 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:57,099 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:57,100 INFO L748 eck$LassoCheckResult]: Stem: 27404#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 27405#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 28273#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28274#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28369#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 28359#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28360#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27571#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27315#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27316#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28241#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 28242#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 28223#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 28224#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28265#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 27365#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27366#L1006 assume !(0 == ~M_E~0); 27217#L1006-2 assume !(0 == ~T1_E~0); 27218#L1011-1 assume !(0 == ~T2_E~0); 28296#L1016-1 assume !(0 == ~T3_E~0); 28318#L1021-1 assume !(0 == ~T4_E~0); 27091#L1026-1 assume !(0 == ~T5_E~0); 27092#L1031-1 assume !(0 == ~T6_E~0); 27991#L1036-1 assume !(0 == ~T7_E~0); 27988#L1041-1 assume !(0 == ~T8_E~0); 27989#L1046-1 assume !(0 == ~T9_E~0); 27395#L1051-1 assume !(0 == ~T10_E~0); 27396#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 28125#L1061-1 assume !(0 == ~E_2~0); 27319#L1066-1 assume !(0 == ~E_3~0); 27320#L1071-1 assume !(0 == ~E_4~0); 28100#L1076-1 assume !(0 == ~E_5~0); 27225#L1081-1 assume !(0 == ~E_6~0); 27226#L1086-1 assume !(0 == ~E_7~0); 27545#L1091-1 assume !(0 == ~E_8~0); 28284#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 28285#L1101-1 assume !(0 == ~E_10~0); 27617#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27618#L484 assume !(1 == ~m_pc~0); 27276#L484-2 is_master_triggered_~__retres1~0#1 := 0; 27275#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27901#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28195#L1245 assume !(0 != activate_threads_~tmp~1#1); 28196#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27978#L503 assume 1 == ~t1_pc~0; 27979#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27997#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27133#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27134#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 27129#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27130#L522 assume !(1 == ~t2_pc~0); 27941#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27330#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27331#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27612#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 28243#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28330#L541 assume 1 == ~t3_pc~0; 27883#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27684#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27075#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27076#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 27948#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27949#L560 assume !(1 == ~t4_pc~0); 27209#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27208#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27241#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27089#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 27090#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27376#L579 assume 1 == ~t5_pc~0; 27040#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27041#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27155#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28200#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 28316#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28347#L598 assume 1 == ~t6_pc~0; 27460#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27461#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27586#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27587#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 28026#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27969#L617 assume !(1 == ~t7_pc~0); 27436#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 27435#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28373#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28256#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27651#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27652#L636 assume 1 == ~t8_pc~0; 27836#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27837#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28153#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28034#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 27783#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27784#L655 assume !(1 == ~t9_pc~0); 27811#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 27812#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27694#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27695#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 28047#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28048#L674 assume 1 == ~t10_pc~0; 27202#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 27203#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 27826#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27827#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 27774#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27775#L1119 assume !(1 == ~M_E~0); 27302#L1119-2 assume !(1 == ~T1_E~0); 27303#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27705#L1129-1 assume !(1 == ~T3_E~0); 27119#L1134-1 assume !(1 == ~T4_E~0); 28729#L1139-1 assume !(1 == ~T5_E~0); 28725#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28462#L1149-1 assume !(1 == ~T7_E~0); 28461#L1154-1 assume !(1 == ~T8_E~0); 28459#L1159-1 assume !(1 == ~T9_E~0); 28457#L1164-1 assume !(1 == ~T10_E~0); 28456#L1169-1 assume !(1 == ~E_1~0); 28452#L1174-1 assume !(1 == ~E_2~0); 28450#L1179-1 assume !(1 == ~E_3~0); 28448#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 28447#L1189-1 assume !(1 == ~E_5~0); 28435#L1194-1 assume !(1 == ~E_6~0); 28433#L1199-1 assume !(1 == ~E_7~0); 28431#L1204-1 assume !(1 == ~E_8~0); 28429#L1209-1 assume !(1 == ~E_9~0); 28427#L1214-1 assume !(1 == ~E_10~0); 28414#L1219-1 assume { :end_inline_reset_delta_events } true; 28410#L1520-2 [2023-11-19 07:43:57,101 INFO L750 eck$LassoCheckResult]: Loop: 28410#L1520-2 assume !false; 28406#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28404#L981-1 assume !false; 28403#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 28394#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28391#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 28390#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28389#L836 assume !(0 != eval_~tmp~0#1); 28388#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28387#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28386#L1006-3 assume !(0 == ~M_E~0); 28385#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28384#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28293#L1016-3 assume !(0 == ~T3_E~0); 28188#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27853#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27854#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28117#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28118#L1041-3 assume !(0 == ~T8_E~0); 28180#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28181#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28119#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27392#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27393#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27394#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28300#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 27184#L1081-3 assume !(0 == ~E_6~0); 27185#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29088#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29086#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29084#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29082#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29081#L484-33 assume 1 == ~m_pc~0; 29079#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 29076#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29074#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 29072#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 29070#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29068#L503-33 assume 1 == ~t1_pc~0; 29065#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29064#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29063#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29062#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29059#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29057#L522-33 assume 1 == ~t2_pc~0; 29054#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29052#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29050#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29048#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29045#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29043#L541-33 assume !(1 == ~t3_pc~0); 29040#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 29037#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29035#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29032#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29030#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29028#L560-33 assume !(1 == ~t4_pc~0); 29025#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 29023#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29021#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29018#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29016#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29014#L579-33 assume 1 == ~t5_pc~0; 29011#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28324#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28325#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27970#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27971#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28002#L598-33 assume !(1 == ~t6_pc~0); 28994#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 28992#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28990#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28988#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 28986#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28983#L617-33 assume 1 == ~t7_pc~0; 28980#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28978#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28976#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28974#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28972#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28969#L636-33 assume !(1 == ~t8_pc~0); 28966#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 28964#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28962#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28960#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28958#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28956#L655-33 assume 1 == ~t9_pc~0; 28953#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28952#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28951#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28949#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 28947#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28945#L674-33 assume 1 == ~t10_pc~0; 28942#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28940#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28938#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28936#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28934#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28932#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28930#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28928#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28382#L1129-3 assume !(1 == ~T3_E~0); 28364#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28925#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28924#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28923#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28922#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28921#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28920#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28919#L1169-3 assume !(1 == ~E_1~0); 28917#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28343#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28218#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27210#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27211#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27500#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27501#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27828#L1209-3 assume !(1 == ~E_9~0); 27097#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 27098#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 28036#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 27187#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 28277#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 28723#L1539 assume !(0 == start_simulation_~tmp~3#1); 28719#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 28446#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28434#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 28432#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 28430#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28428#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28426#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 28413#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 28410#L1520-2 [2023-11-19 07:43:57,102 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:57,102 INFO L85 PathProgramCache]: Analyzing trace with hash -388783629, now seen corresponding path program 1 times [2023-11-19 07:43:57,102 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:57,103 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2024644620] [2023-11-19 07:43:57,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:57,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:57,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:57,216 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:57,216 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:57,216 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2024644620] [2023-11-19 07:43:57,216 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2024644620] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:57,216 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:57,217 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:57,217 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1654842177] [2023-11-19 07:43:57,217 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:57,217 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:57,218 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:57,218 INFO L85 PathProgramCache]: Analyzing trace with hash -876991093, now seen corresponding path program 1 times [2023-11-19 07:43:57,218 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:57,218 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [134315408] [2023-11-19 07:43:57,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:57,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:57,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:57,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:57,286 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:57,286 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [134315408] [2023-11-19 07:43:57,287 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [134315408] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:57,287 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:57,287 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:57,287 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [601082183] [2023-11-19 07:43:57,287 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:57,288 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:57,288 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:57,289 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:43:57,289 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:43:57,289 INFO L87 Difference]: Start difference. First operand 2460 states and 3626 transitions. cyclomatic complexity: 1168 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:57,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:57,511 INFO L93 Difference]: Finished difference Result 4636 states and 6829 transitions. [2023-11-19 07:43:57,511 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4636 states and 6829 transitions. [2023-11-19 07:43:57,543 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4448 [2023-11-19 07:43:57,581 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4636 states to 4636 states and 6829 transitions. [2023-11-19 07:43:57,581 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4636 [2023-11-19 07:43:57,587 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4636 [2023-11-19 07:43:57,587 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4636 states and 6829 transitions. [2023-11-19 07:43:57,594 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:57,594 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4636 states and 6829 transitions. [2023-11-19 07:43:57,601 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4636 states and 6829 transitions. [2023-11-19 07:43:57,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4636 to 4632. [2023-11-19 07:43:57,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4632 states, 4632 states have (on average 1.4734455958549222) internal successors, (6825), 4631 states have internal predecessors, (6825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:57,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4632 states to 4632 states and 6825 transitions. [2023-11-19 07:43:57,714 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4632 states and 6825 transitions. [2023-11-19 07:43:57,715 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:43:57,715 INFO L428 stractBuchiCegarLoop]: Abstraction has 4632 states and 6825 transitions. [2023-11-19 07:43:57,716 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-19 07:43:57,716 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4632 states and 6825 transitions. [2023-11-19 07:43:57,742 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4448 [2023-11-19 07:43:57,743 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:57,743 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:57,746 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:57,746 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:57,746 INFO L748 eck$LassoCheckResult]: Stem: 34509#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 34510#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 35379#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35380#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35455#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 35448#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 35449#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34676#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34420#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34421#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35347#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35348#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35329#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35330#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35371#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 34472#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34473#L1006 assume !(0 == ~M_E~0); 34322#L1006-2 assume !(0 == ~T1_E~0); 34323#L1011-1 assume !(0 == ~T2_E~0); 35396#L1016-1 assume !(0 == ~T3_E~0); 35415#L1021-1 assume !(0 == ~T4_E~0); 34199#L1026-1 assume !(0 == ~T5_E~0); 34200#L1031-1 assume !(0 == ~T6_E~0); 35097#L1036-1 assume !(0 == ~T7_E~0); 35094#L1041-1 assume !(0 == ~T8_E~0); 35095#L1046-1 assume !(0 == ~T9_E~0); 34500#L1051-1 assume !(0 == ~T10_E~0); 34501#L1056-1 assume !(0 == ~E_1~0); 35229#L1061-1 assume !(0 == ~E_2~0); 34424#L1066-1 assume !(0 == ~E_3~0); 34425#L1071-1 assume !(0 == ~E_4~0); 35203#L1076-1 assume !(0 == ~E_5~0); 34330#L1081-1 assume !(0 == ~E_6~0); 34331#L1086-1 assume !(0 == ~E_7~0); 34650#L1091-1 assume !(0 == ~E_8~0); 35388#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 35389#L1101-1 assume !(0 == ~E_10~0); 34721#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34722#L484 assume !(1 == ~m_pc~0); 34381#L484-2 is_master_triggered_~__retres1~0#1 := 0; 34380#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35008#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 35297#L1245 assume !(0 != activate_threads_~tmp~1#1); 35298#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35084#L503 assume 1 == ~t1_pc~0; 35085#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35103#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34240#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 34241#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 34234#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34235#L522 assume !(1 == ~t2_pc~0); 35047#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34435#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34436#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34716#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 35349#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35424#L541 assume 1 == ~t3_pc~0; 34990#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34789#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34181#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34182#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 35053#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35054#L560 assume !(1 == ~t4_pc~0); 34316#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 34315#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34346#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34195#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 34196#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34481#L579 assume 1 == ~t5_pc~0; 34146#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34147#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34260#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35302#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 35413#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35438#L598 assume 1 == ~t6_pc~0; 34565#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34566#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34691#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34692#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 35132#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35075#L617 assume !(1 == ~t7_pc~0); 34541#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 34540#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35459#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35361#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 34756#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34757#L636 assume 1 == ~t8_pc~0; 34943#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34944#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35257#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35142#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 34888#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34889#L655 assume !(1 == ~t9_pc~0); 34919#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 34920#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34803#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34804#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 35153#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35154#L674 assume 1 == ~t10_pc~0; 34307#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 34308#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 34934#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34935#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 34879#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34880#L1119 assume !(1 == ~M_E~0); 34407#L1119-2 assume !(1 == ~T1_E~0); 34408#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34224#L1129-1 assume !(1 == ~T3_E~0); 34225#L1134-1 assume !(1 == ~T4_E~0); 35064#L1139-1 assume !(1 == ~T5_E~0); 34751#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34752#L1149-1 assume !(1 == ~T7_E~0); 34401#L1154-1 assume !(1 == ~T8_E~0); 34402#L1159-1 assume !(1 == ~T9_E~0); 34484#L1164-1 assume !(1 == ~T10_E~0); 35563#L1169-1 assume !(1 == ~E_1~0); 35559#L1174-1 assume !(1 == ~E_2~0); 35558#L1179-1 assume !(1 == ~E_3~0); 35556#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 35554#L1189-1 assume !(1 == ~E_5~0); 35552#L1194-1 assume !(1 == ~E_6~0); 35551#L1199-1 assume !(1 == ~E_7~0); 35533#L1204-1 assume !(1 == ~E_8~0); 35521#L1209-1 assume !(1 == ~E_9~0); 35512#L1214-1 assume !(1 == ~E_10~0); 35504#L1219-1 assume { :end_inline_reset_delta_events } true; 35498#L1520-2 [2023-11-19 07:43:57,747 INFO L750 eck$LassoCheckResult]: Loop: 35498#L1520-2 assume !false; 35493#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35491#L981-1 assume !false; 35490#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 35481#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 35478#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 35477#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 35475#L836 assume !(0 != eval_~tmp~0#1); 35474#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35473#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35472#L1006-3 assume !(0 == ~M_E~0); 35471#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35469#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35470#L1016-3 assume !(0 == ~T3_E~0); 36980#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36943#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36851#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36849#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36847#L1041-3 assume !(0 == ~T8_E~0); 36845#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36843#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36841#L1056-3 assume !(0 == ~E_1~0); 36839#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36837#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36832#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36826#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36820#L1081-3 assume !(0 == ~E_6~0); 36815#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36810#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 36805#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36799#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36793#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36787#L484-33 assume 1 == ~m_pc~0; 36781#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 36776#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36772#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36767#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 36761#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36757#L503-33 assume 1 == ~t1_pc~0; 36752#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36748#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36743#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36736#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36729#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36724#L522-33 assume 1 == ~t2_pc~0; 36718#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36713#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36708#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36701#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36694#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36689#L541-33 assume 1 == ~t3_pc~0; 36683#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36678#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36673#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36666#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36659#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36654#L560-33 assume !(1 == ~t4_pc~0); 36648#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 36644#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36640#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36634#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36269#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36266#L579-33 assume 1 == ~t5_pc~0; 36263#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36261#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36259#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36257#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 36255#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36252#L598-33 assume !(1 == ~t6_pc~0); 36249#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 36247#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36245#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36243#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 36241#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36238#L617-33 assume 1 == ~t7_pc~0; 36208#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36206#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36203#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36201#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36198#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36196#L636-33 assume !(1 == ~t8_pc~0); 36193#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 36191#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36190#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35938#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35936#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35933#L655-33 assume 1 == ~t9_pc~0; 35929#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35927#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35925#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35923#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 35920#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35918#L674-33 assume 1 == ~t10_pc~0; 35913#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35911#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35908#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35684#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35681#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35677#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35673#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35669#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35467#L1129-3 assume !(1 == ~T3_E~0); 35662#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35659#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35656#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 35653#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 35650#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 35647#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 35643#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 35639#L1169-3 assume !(1 == ~E_1~0); 35637#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35635#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 35633#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35631#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35628#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35626#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35625#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35623#L1209-3 assume !(1 == ~E_9~0); 35621#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35619#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 35617#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 35605#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 35603#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 35600#L1539 assume !(0 == start_simulation_~tmp~3#1); 35598#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 35597#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 35584#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 35550#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 35532#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35520#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35511#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 35503#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 35498#L1520-2 [2023-11-19 07:43:57,749 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:57,749 INFO L85 PathProgramCache]: Analyzing trace with hash 642257269, now seen corresponding path program 1 times [2023-11-19 07:43:57,749 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:57,749 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2127681966] [2023-11-19 07:43:57,750 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:57,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:57,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:57,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:57,840 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:57,841 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2127681966] [2023-11-19 07:43:57,841 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2127681966] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:57,841 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:57,841 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:57,842 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1425032628] [2023-11-19 07:43:57,842 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:57,842 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:57,843 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:57,843 INFO L85 PathProgramCache]: Analyzing trace with hash -539525330, now seen corresponding path program 1 times [2023-11-19 07:43:57,843 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:57,844 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [895006399] [2023-11-19 07:43:57,844 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:57,844 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:57,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:57,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:57,910 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:57,910 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [895006399] [2023-11-19 07:43:57,910 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [895006399] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:57,911 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:57,911 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:57,911 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1511712038] [2023-11-19 07:43:57,911 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:57,912 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:57,912 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:57,913 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:43:57,913 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:43:57,913 INFO L87 Difference]: Start difference. First operand 4632 states and 6825 transitions. cyclomatic complexity: 2197 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:58,192 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:58,192 INFO L93 Difference]: Finished difference Result 8784 states and 12922 transitions. [2023-11-19 07:43:58,192 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8784 states and 12922 transitions. [2023-11-19 07:43:58,333 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8580 [2023-11-19 07:43:58,412 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8784 states to 8784 states and 12922 transitions. [2023-11-19 07:43:58,412 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8784 [2023-11-19 07:43:58,424 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8784 [2023-11-19 07:43:58,424 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8784 states and 12922 transitions. [2023-11-19 07:43:58,439 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:58,439 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8784 states and 12922 transitions. [2023-11-19 07:43:58,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8784 states and 12922 transitions. [2023-11-19 07:43:58,615 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8784 to 8780. [2023-11-19 07:43:58,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8780 states, 8780 states have (on average 1.4712984054669704) internal successors, (12918), 8779 states have internal predecessors, (12918), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:58,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8780 states to 8780 states and 12918 transitions. [2023-11-19 07:43:58,695 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8780 states and 12918 transitions. [2023-11-19 07:43:58,695 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:43:58,696 INFO L428 stractBuchiCegarLoop]: Abstraction has 8780 states and 12918 transitions. [2023-11-19 07:43:58,696 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-19 07:43:58,696 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8780 states and 12918 transitions. [2023-11-19 07:43:58,750 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8580 [2023-11-19 07:43:58,750 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:43:58,750 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:43:58,753 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:58,754 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:43:58,754 INFO L748 eck$LassoCheckResult]: Stem: 47932#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 47933#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 48803#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48804#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48883#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 48875#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48876#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48100#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47844#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47845#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48771#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48772#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48753#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 48754#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 48795#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47893#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47894#L1006 assume !(0 == ~M_E~0); 47747#L1006-2 assume !(0 == ~T1_E~0); 47748#L1011-1 assume !(0 == ~T2_E~0); 48822#L1016-1 assume !(0 == ~T3_E~0); 48841#L1021-1 assume !(0 == ~T4_E~0); 47623#L1026-1 assume !(0 == ~T5_E~0); 47624#L1031-1 assume !(0 == ~T6_E~0); 48524#L1036-1 assume !(0 == ~T7_E~0); 48521#L1041-1 assume !(0 == ~T8_E~0); 48522#L1046-1 assume !(0 == ~T9_E~0); 47923#L1051-1 assume !(0 == ~T10_E~0); 47924#L1056-1 assume !(0 == ~E_1~0); 48653#L1061-1 assume !(0 == ~E_2~0); 47848#L1066-1 assume !(0 == ~E_3~0); 47849#L1071-1 assume !(0 == ~E_4~0); 48628#L1076-1 assume !(0 == ~E_5~0); 47755#L1081-1 assume !(0 == ~E_6~0); 47756#L1086-1 assume !(0 == ~E_7~0); 48074#L1091-1 assume !(0 == ~E_8~0); 48811#L1096-1 assume !(0 == ~E_9~0); 48812#L1101-1 assume !(0 == ~E_10~0); 48146#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48147#L484 assume !(1 == ~m_pc~0); 47805#L484-2 is_master_triggered_~__retres1~0#1 := 0; 47804#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48434#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 48725#L1245 assume !(0 != activate_threads_~tmp~1#1); 48726#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48511#L503 assume 1 == ~t1_pc~0; 48512#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 48530#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47664#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47665#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 47660#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47661#L522 assume !(1 == ~t2_pc~0); 48474#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 47859#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47860#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 48140#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 48773#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48850#L541 assume 1 == ~t3_pc~0; 48416#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 48213#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47607#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47608#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 48480#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48481#L560 assume !(1 == ~t4_pc~0); 47739#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 47738#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47771#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47621#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 47622#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47904#L579 assume 1 == ~t5_pc~0; 47572#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47573#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47686#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48730#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 48839#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48860#L598 assume 1 == ~t6_pc~0; 47989#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47990#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48115#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48116#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 48558#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48502#L617 assume !(1 == ~t7_pc~0); 47965#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 47964#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48887#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48786#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 48180#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48181#L636 assume 1 == ~t8_pc~0; 48368#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 48369#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48685#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48567#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 48312#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48313#L655 assume !(1 == ~t9_pc~0); 48341#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 48342#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48223#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48224#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 48579#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48580#L674 assume 1 == ~t10_pc~0; 47732#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 47733#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48356#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48357#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 48303#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48304#L1119 assume !(1 == ~M_E~0); 47831#L1119-2 assume !(1 == ~T1_E~0); 47832#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47650#L1129-1 assume !(1 == ~T3_E~0); 47651#L1134-1 assume !(1 == ~T4_E~0); 47948#L1139-1 assume !(1 == ~T5_E~0); 47949#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48176#L1149-1 assume !(1 == ~T7_E~0); 47825#L1154-1 assume !(1 == ~T8_E~0); 47826#L1159-1 assume !(1 == ~T9_E~0); 47907#L1164-1 assume !(1 == ~T10_E~0); 48889#L1169-1 assume !(1 == ~E_1~0); 49018#L1174-1 assume !(1 == ~E_2~0); 48972#L1179-1 assume !(1 == ~E_3~0); 48970#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 48968#L1189-1 assume !(1 == ~E_5~0); 48967#L1194-1 assume !(1 == ~E_6~0); 48965#L1199-1 assume !(1 == ~E_7~0); 48963#L1204-1 assume !(1 == ~E_8~0); 48949#L1209-1 assume !(1 == ~E_9~0); 48938#L1214-1 assume !(1 == ~E_10~0); 48930#L1219-1 assume { :end_inline_reset_delta_events } true; 48924#L1520-2 [2023-11-19 07:43:58,755 INFO L750 eck$LassoCheckResult]: Loop: 48924#L1520-2 assume !false; 48919#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48917#L981-1 assume !false; 48916#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 48907#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 48904#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 48903#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 48901#L836 assume !(0 != eval_~tmp~0#1); 48900#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 48899#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 48898#L1006-3 assume !(0 == ~M_E~0); 48897#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 48895#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 48896#L1016-3 assume !(0 == ~T3_E~0); 49813#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49804#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49797#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49790#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49781#L1041-3 assume !(0 == ~T8_E~0); 49774#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 49766#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 49758#L1056-3 assume !(0 == ~E_1~0); 49751#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49744#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 49734#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 49727#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 49719#L1081-3 assume !(0 == ~E_6~0); 49710#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 49703#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49696#L1096-3 assume !(0 == ~E_9~0); 49686#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 49679#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49671#L484-33 assume 1 == ~m_pc~0; 49661#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 49654#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49647#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 49637#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 49630#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49622#L503-33 assume 1 == ~t1_pc~0; 49612#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49605#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49598#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49588#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49581#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49573#L522-33 assume 1 == ~t2_pc~0; 49563#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 49556#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49549#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49539#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49532#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49524#L541-33 assume 1 == ~t3_pc~0; 49514#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49507#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49501#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49456#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49454#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49452#L560-33 assume !(1 == ~t4_pc~0); 49449#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 49447#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49444#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49442#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49440#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49438#L579-33 assume 1 == ~t5_pc~0; 49433#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49431#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49429#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49427#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49425#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49422#L598-33 assume !(1 == ~t6_pc~0); 49419#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 49417#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49415#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49413#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49411#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49410#L617-33 assume 1 == ~t7_pc~0; 49406#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49404#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49402#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49400#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 49398#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49396#L636-33 assume !(1 == ~t8_pc~0); 49394#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 49391#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49389#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49387#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49385#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49383#L655-33 assume 1 == ~t9_pc~0; 49379#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49377#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49375#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49373#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 49371#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49368#L674-33 assume 1 == ~t10_pc~0; 49342#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49335#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49328#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49321#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49314#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49307#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49300#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49293#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48893#L1129-3 assume !(1 == ~T3_E~0); 49282#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49278#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49273#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49267#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49262#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49257#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49252#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 49246#L1169-3 assume !(1 == ~E_1~0); 49243#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49239#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 49236#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49233#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49230#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49227#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49224#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49219#L1209-3 assume !(1 == ~E_9~0); 49217#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49215#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 49211#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 49198#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 49196#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 49194#L1539 assume !(0 == start_simulation_~tmp~3#1); 49191#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 48991#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 48977#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 48975#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 48961#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48946#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48937#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 48929#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 48924#L1520-2 [2023-11-19 07:43:58,756 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:58,757 INFO L85 PathProgramCache]: Analyzing trace with hash -1298324745, now seen corresponding path program 1 times [2023-11-19 07:43:58,757 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:58,757 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [854928637] [2023-11-19 07:43:58,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:58,758 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:58,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:58,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:58,856 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:58,857 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [854928637] [2023-11-19 07:43:58,857 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [854928637] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:58,857 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:58,857 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:58,858 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2062650208] [2023-11-19 07:43:58,858 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:58,858 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:43:58,859 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:43:58,859 INFO L85 PathProgramCache]: Analyzing trace with hash 1722047920, now seen corresponding path program 1 times [2023-11-19 07:43:58,859 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:43:58,860 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [307542636] [2023-11-19 07:43:58,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:43:58,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:43:58,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:43:58,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:43:58,931 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:43:58,931 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [307542636] [2023-11-19 07:43:58,932 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [307542636] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:43:58,932 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:43:58,932 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:43:58,932 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1491415118] [2023-11-19 07:43:58,933 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:43:58,933 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:43:58,933 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:43:58,934 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:43:58,934 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:43:58,935 INFO L87 Difference]: Start difference. First operand 8780 states and 12918 transitions. cyclomatic complexity: 4146 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:43:59,524 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:43:59,524 INFO L93 Difference]: Finished difference Result 24954 states and 36298 transitions. [2023-11-19 07:43:59,524 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24954 states and 36298 transitions. [2023-11-19 07:43:59,706 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24388 [2023-11-19 07:43:59,822 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24954 states to 24954 states and 36298 transitions. [2023-11-19 07:43:59,823 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24954 [2023-11-19 07:43:59,858 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24954 [2023-11-19 07:43:59,859 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24954 states and 36298 transitions. [2023-11-19 07:43:59,890 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:43:59,890 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24954 states and 36298 transitions. [2023-11-19 07:43:59,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24954 states and 36298 transitions. [2023-11-19 07:44:00,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24954 to 24038. [2023-11-19 07:44:00,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24038 states, 24038 states have (on average 1.4572759796988102) internal successors, (35030), 24037 states have internal predecessors, (35030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:44:00,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24038 states to 24038 states and 35030 transitions. [2023-11-19 07:44:00,949 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24038 states and 35030 transitions. [2023-11-19 07:44:00,949 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:44:00,950 INFO L428 stractBuchiCegarLoop]: Abstraction has 24038 states and 35030 transitions. [2023-11-19 07:44:00,950 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-19 07:44:00,950 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24038 states and 35030 transitions. [2023-11-19 07:44:01,195 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 23820 [2023-11-19 07:44:01,196 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:44:01,196 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:44:01,199 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:44:01,199 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:44:01,200 INFO L748 eck$LassoCheckResult]: Stem: 81677#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 81678#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 82610#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 82611#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 82716#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 82706#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82707#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 81848#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81587#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 81588#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 82571#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 82572#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 82550#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 82551#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 82599#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 81639#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 81640#L1006 assume !(0 == ~M_E~0); 81496#L1006-2 assume !(0 == ~T1_E~0); 81497#L1011-1 assume !(0 == ~T2_E~0); 82636#L1016-1 assume !(0 == ~T3_E~0); 82658#L1021-1 assume !(0 == ~T4_E~0); 81369#L1026-1 assume !(0 == ~T5_E~0); 81370#L1031-1 assume !(0 == ~T6_E~0); 82278#L1036-1 assume !(0 == ~T7_E~0); 82274#L1041-1 assume !(0 == ~T8_E~0); 82275#L1046-1 assume !(0 == ~T9_E~0); 81667#L1051-1 assume !(0 == ~T10_E~0); 81668#L1056-1 assume !(0 == ~E_1~0); 82421#L1061-1 assume !(0 == ~E_2~0); 81591#L1066-1 assume !(0 == ~E_3~0); 81592#L1071-1 assume !(0 == ~E_4~0); 82394#L1076-1 assume !(0 == ~E_5~0); 81501#L1081-1 assume !(0 == ~E_6~0); 81502#L1086-1 assume !(0 == ~E_7~0); 81822#L1091-1 assume !(0 == ~E_8~0); 82621#L1096-1 assume !(0 == ~E_9~0); 82622#L1101-1 assume !(0 == ~E_10~0); 81892#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81893#L484 assume !(1 == ~m_pc~0); 82004#L484-2 is_master_triggered_~__retres1~0#1 := 0; 82005#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82186#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 82514#L1245 assume !(0 != activate_threads_~tmp~1#1); 82515#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 82265#L503 assume !(1 == ~t1_pc~0); 82266#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 82461#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81411#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 81412#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 81405#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81406#L522 assume !(1 == ~t2_pc~0); 82226#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 81604#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81605#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 81887#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 82573#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82668#L541 assume 1 == ~t3_pc~0; 82167#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 81959#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81353#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 81354#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 82233#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82234#L560 assume !(1 == ~t4_pc~0); 81488#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 81487#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81517#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 81365#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 81366#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 81650#L579 assume 1 == ~t5_pc~0; 81316#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 81317#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 81431#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 82519#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 82657#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 82689#L598 assume 1 == ~t6_pc~0; 81733#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 81734#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 81865#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 81866#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 82312#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 82256#L617 assume !(1 == ~t7_pc~0); 81709#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 81708#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 82726#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 82590#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 81928#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 81929#L636 assume 1 == ~t8_pc~0; 82118#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 82119#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 82462#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 82322#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 82064#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 82065#L655 assume !(1 == ~t9_pc~0); 82094#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 82095#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 81973#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 81974#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 82332#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 82333#L674 assume 1 == ~t10_pc~0; 81479#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 81480#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 82109#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 82110#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 82053#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82054#L1119 assume !(1 == ~M_E~0); 81574#L1119-2 assume !(1 == ~T1_E~0); 81575#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 81982#L1129-1 assume !(1 == ~T3_E~0); 93003#L1134-1 assume !(1 == ~T4_E~0); 93002#L1139-1 assume !(1 == ~T5_E~0); 93001#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 93000#L1149-1 assume !(1 == ~T7_E~0); 92999#L1154-1 assume !(1 == ~T8_E~0); 92998#L1159-1 assume !(1 == ~T9_E~0); 92997#L1164-1 assume !(1 == ~T10_E~0); 92995#L1169-1 assume !(1 == ~E_1~0); 92994#L1174-1 assume !(1 == ~E_2~0); 92993#L1179-1 assume !(1 == ~E_3~0); 92989#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 92987#L1189-1 assume !(1 == ~E_5~0); 92985#L1194-1 assume !(1 == ~E_6~0); 92984#L1199-1 assume !(1 == ~E_7~0); 92981#L1204-1 assume !(1 == ~E_8~0); 92977#L1209-1 assume !(1 == ~E_9~0); 92972#L1214-1 assume !(1 == ~E_10~0); 92968#L1219-1 assume { :end_inline_reset_delta_events } true; 92963#L1520-2 [2023-11-19 07:44:01,201 INFO L750 eck$LassoCheckResult]: Loop: 92963#L1520-2 assume !false; 92957#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 92955#L981-1 assume !false; 92954#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 92945#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 92942#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 92941#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 92929#L836 assume !(0 != eval_~tmp~0#1); 82470#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 82126#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 81914#L1006-3 assume !(0 == ~M_E~0); 81915#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 82454#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 82455#L1016-3 assume !(0 == ~T3_E~0); 82502#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 82137#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 82138#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 82413#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 82414#L1041-3 assume !(0 == ~T8_E~0); 82496#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 82497#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 82415#L1056-3 assume !(0 == ~E_1~0); 81664#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 81665#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 81666#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 82640#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 81460#L1081-3 assume !(0 == ~E_6~0); 81461#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 81510#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 81511#L1096-3 assume !(0 == ~E_9~0); 82601#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 82602#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82162#L484-33 assume !(1 == ~m_pc~0); 82163#L484-35 is_master_triggered_~__retres1~0#1 := 0; 82067#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82068#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 81359#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 81360#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81805#L503-33 assume !(1 == ~t1_pc~0); 81806#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 82315#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82316#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 81725#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 81726#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82198#L522-33 assume !(1 == ~t2_pc~0); 82199#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 81498#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81499#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 82435#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 82222#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82223#L541-33 assume !(1 == ~t3_pc~0); 81519#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 81357#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81358#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 81530#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 82192#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82411#L560-33 assume 1 == ~t4_pc~0; 82071#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 81436#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81437#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 82643#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 82677#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 103271#L579-33 assume 1 == ~t5_pc~0; 103265#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 103263#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 103262#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 102563#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 102562#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 102561#L598-33 assume !(1 == ~t6_pc~0); 102555#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 102556#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 102870#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 102868#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 102549#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 82713#L617-33 assume 1 == ~t7_pc~0; 82597#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 81493#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 82501#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 82529#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 82641#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 81422#L636-33 assume !(1 == ~t8_pc~0); 81424#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 82381#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 82224#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 82225#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 82366#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 82367#L655-33 assume 1 == ~t9_pc~0; 82717#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 81779#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 81780#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 82439#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 82475#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 81969#L674-33 assume 1 == ~t10_pc~0; 81827#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 81828#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 82535#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 82210#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 82211#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82673#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 82690#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 82692#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 82739#L1129-3 assume !(1 == ~T3_E~0); 97765#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 97762#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 97760#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 97758#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 97756#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 97754#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 97752#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 97749#L1169-3 assume !(1 == ~E_1~0); 95148#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 97746#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 97744#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 97742#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 97740#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 97737#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 97735#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 93699#L1209-3 assume !(1 == ~E_9~0); 93697#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 93695#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 93693#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 93679#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 93677#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 93675#L1539 assume !(0 == start_simulation_~tmp~3#1); 93673#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 93672#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 93658#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 93656#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 93654#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 93653#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 93650#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 92967#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 92963#L1520-2 [2023-11-19 07:44:01,202 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:44:01,203 INFO L85 PathProgramCache]: Analyzing trace with hash 1011813846, now seen corresponding path program 1 times [2023-11-19 07:44:01,203 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:44:01,203 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1429069113] [2023-11-19 07:44:01,203 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:44:01,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:44:01,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:44:01,304 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:44:01,304 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:44:01,305 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1429069113] [2023-11-19 07:44:01,305 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1429069113] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:44:01,305 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:44:01,305 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:44:01,305 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1699307930] [2023-11-19 07:44:01,306 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:44:01,308 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:44:01,309 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:44:01,309 INFO L85 PathProgramCache]: Analyzing trace with hash 130234253, now seen corresponding path program 1 times [2023-11-19 07:44:01,309 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:44:01,309 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1427773256] [2023-11-19 07:44:01,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:44:01,310 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:44:01,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:44:01,371 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:44:01,371 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:44:01,372 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1427773256] [2023-11-19 07:44:01,372 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1427773256] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:44:01,372 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:44:01,372 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:44:01,373 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [49151088] [2023-11-19 07:44:01,373 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:44:01,374 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:44:01,374 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:44:01,375 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:44:01,375 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:44:01,375 INFO L87 Difference]: Start difference. First operand 24038 states and 35030 transitions. cyclomatic complexity: 11008 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:44:02,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:44:02,242 INFO L93 Difference]: Finished difference Result 68621 states and 99137 transitions. [2023-11-19 07:44:02,242 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 68621 states and 99137 transitions. [2023-11-19 07:44:02,756 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 67600 [2023-11-19 07:44:03,110 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 68621 states to 68621 states and 99137 transitions. [2023-11-19 07:44:03,110 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 68621 [2023-11-19 07:44:03,178 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 68621 [2023-11-19 07:44:03,178 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68621 states and 99137 transitions. [2023-11-19 07:44:03,243 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:44:03,243 INFO L218 hiAutomatonCegarLoop]: Abstraction has 68621 states and 99137 transitions. [2023-11-19 07:44:03,311 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68621 states and 99137 transitions. [2023-11-19 07:44:04,497 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68621 to 66489. [2023-11-19 07:44:04,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66489 states, 66489 states have (on average 1.4470513919595722) internal successors, (96213), 66488 states have internal predecessors, (96213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:44:05,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66489 states to 66489 states and 96213 transitions. [2023-11-19 07:44:05,040 INFO L240 hiAutomatonCegarLoop]: Abstraction has 66489 states and 96213 transitions. [2023-11-19 07:44:05,040 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:44:05,041 INFO L428 stractBuchiCegarLoop]: Abstraction has 66489 states and 96213 transitions. [2023-11-19 07:44:05,042 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-19 07:44:05,042 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66489 states and 96213 transitions. [2023-11-19 07:44:05,374 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 66232 [2023-11-19 07:44:05,375 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:44:05,375 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:44:05,379 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:44:05,380 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:44:05,380 INFO L748 eck$LassoCheckResult]: Stem: 174342#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 174343#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 175320#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 175321#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 175445#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 175436#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 175437#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 174515#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 174253#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 174254#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 175274#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 175275#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 175242#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 175243#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 175305#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 174305#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 174306#L1006 assume !(0 == ~M_E~0); 174160#L1006-2 assume !(0 == ~T1_E~0); 174161#L1011-1 assume !(0 == ~T2_E~0); 175352#L1016-1 assume !(0 == ~T3_E~0); 175372#L1021-1 assume !(0 == ~T4_E~0); 174038#L1026-1 assume !(0 == ~T5_E~0); 174039#L1031-1 assume !(0 == ~T6_E~0); 174961#L1036-1 assume !(0 == ~T7_E~0); 174955#L1041-1 assume !(0 == ~T8_E~0); 174956#L1046-1 assume !(0 == ~T9_E~0); 174333#L1051-1 assume !(0 == ~T10_E~0); 174334#L1056-1 assume !(0 == ~E_1~0); 175106#L1061-1 assume !(0 == ~E_2~0); 174255#L1066-1 assume !(0 == ~E_3~0); 174256#L1071-1 assume !(0 == ~E_4~0); 175079#L1076-1 assume !(0 == ~E_5~0); 174165#L1081-1 assume !(0 == ~E_6~0); 174166#L1086-1 assume !(0 == ~E_7~0); 174487#L1091-1 assume !(0 == ~E_8~0); 175337#L1096-1 assume !(0 == ~E_9~0); 175338#L1101-1 assume !(0 == ~E_10~0); 174561#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 174562#L484 assume !(1 == ~m_pc~0); 174678#L484-2 is_master_triggered_~__retres1~0#1 := 0; 174679#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 174864#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 175198#L1245 assume !(0 != activate_threads_~tmp~1#1); 175199#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 174946#L503 assume !(1 == ~t1_pc~0); 174947#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 175147#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 174079#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 174080#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 174073#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 174074#L522 assume !(1 == ~t2_pc~0); 174907#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 174272#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 174273#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 174556#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 175276#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 175383#L541 assume !(1 == ~t3_pc~0); 174630#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 174631#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 174022#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 174023#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 174918#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 174919#L560 assume !(1 == ~t4_pc~0); 174152#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 174151#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 174180#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 174034#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 174035#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 174314#L579 assume 1 == ~t5_pc~0; 173985#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 173986#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 174099#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 175208#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 175371#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 175411#L598 assume 1 == ~t6_pc~0; 174399#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 174400#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 174532#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 174533#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 174994#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 174937#L617 assume !(1 == ~t7_pc~0); 174375#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 174374#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 175455#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 175295#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 174600#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 174601#L636 assume 1 == ~t8_pc~0; 174794#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 174795#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 175148#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 175006#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 174739#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 174740#L655 assume !(1 == ~t9_pc~0); 174771#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 174772#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 174647#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 174648#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 175015#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 175016#L674 assume 1 == ~t10_pc~0; 174143#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 174144#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 174784#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 174785#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 174728#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 174729#L1119 assume !(1 == ~M_E~0); 174238#L1119-2 assume !(1 == ~T1_E~0); 174239#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 174063#L1129-1 assume !(1 == ~T3_E~0); 174064#L1134-1 assume !(1 == ~T4_E~0); 174924#L1139-1 assume !(1 == ~T5_E~0); 174595#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 174596#L1149-1 assume !(1 == ~T7_E~0); 174232#L1154-1 assume !(1 == ~T8_E~0); 174233#L1159-1 assume !(1 == ~T9_E~0); 175468#L1164-1 assume !(1 == ~T10_E~0); 175469#L1169-1 assume !(1 == ~E_1~0); 188038#L1174-1 assume !(1 == ~E_2~0); 188036#L1179-1 assume !(1 == ~E_3~0); 188034#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 188032#L1189-1 assume !(1 == ~E_5~0); 188030#L1194-1 assume !(1 == ~E_6~0); 188029#L1199-1 assume !(1 == ~E_7~0); 187847#L1204-1 assume !(1 == ~E_8~0); 187845#L1209-1 assume !(1 == ~E_9~0); 187841#L1214-1 assume !(1 == ~E_10~0); 187838#L1219-1 assume { :end_inline_reset_delta_events } true; 187839#L1520-2 [2023-11-19 07:44:05,381 INFO L750 eck$LassoCheckResult]: Loop: 187839#L1520-2 assume !false; 200118#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 200117#L981-1 assume !false; 200116#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 184582#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 184577#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 184576#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 184563#L836 assume !(0 != eval_~tmp~0#1); 184565#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 206519#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 206518#L1006-3 assume !(0 == ~M_E~0); 206517#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 206516#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 206515#L1016-3 assume !(0 == ~T3_E~0); 206514#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 206513#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 206512#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 206511#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 206510#L1041-3 assume !(0 == ~T8_E~0); 206509#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 206508#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 206507#L1056-3 assume !(0 == ~E_1~0); 206506#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 206505#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 206504#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 206503#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 206502#L1081-3 assume !(0 == ~E_6~0); 206501#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 206500#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 206499#L1096-3 assume !(0 == ~E_9~0); 206498#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 206497#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 206496#L484-33 assume !(1 == ~m_pc~0); 206495#L484-35 is_master_triggered_~__retres1~0#1 := 0; 206494#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 206493#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 206492#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 206491#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 206490#L503-33 assume !(1 == ~t1_pc~0); 206489#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 206488#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 206487#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 206486#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 206485#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 206484#L522-33 assume !(1 == ~t2_pc~0); 206483#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 206481#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 206480#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 206479#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 206478#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 206477#L541-33 assume !(1 == ~t3_pc~0); 206476#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 206475#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 206474#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 206473#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 206472#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 206471#L560-33 assume 1 == ~t4_pc~0; 206470#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 206468#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 206467#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 206466#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 206465#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 206464#L579-33 assume !(1 == ~t5_pc~0); 206463#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 206461#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 206460#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 206459#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 206458#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 206457#L598-33 assume !(1 == ~t6_pc~0); 206455#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 206454#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 206453#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 206452#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 206451#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 206450#L617-33 assume !(1 == ~t7_pc~0); 206449#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 206447#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 206446#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 206445#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 206444#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 206443#L636-33 assume 1 == ~t8_pc~0; 206442#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 206440#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 206439#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 206438#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 206437#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 206436#L655-33 assume !(1 == ~t9_pc~0); 206435#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 206433#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 206432#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 206431#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 206430#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 206429#L674-33 assume 1 == ~t10_pc~0; 206427#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 206426#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 206425#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 206424#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 206423#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 206422#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 206421#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 206420#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 200176#L1129-3 assume !(1 == ~T3_E~0); 205552#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 205551#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 205550#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 205549#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 205548#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 205547#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 205546#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 203805#L1169-3 assume !(1 == ~E_1~0); 203804#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 203803#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 203802#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 203801#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 203800#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 203799#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 203798#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 200153#L1209-3 assume !(1 == ~E_9~0); 200152#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 200151#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 200150#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 200139#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 200138#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 200137#L1539 assume !(0 == start_simulation_~tmp~3#1); 200136#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 200135#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 200124#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 200123#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 200122#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 200121#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 200120#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 200119#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 187839#L1520-2 [2023-11-19 07:44:05,382 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:44:05,382 INFO L85 PathProgramCache]: Analyzing trace with hash 1918570293, now seen corresponding path program 1 times [2023-11-19 07:44:05,382 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:44:05,382 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [504118680] [2023-11-19 07:44:05,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:44:05,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:44:05,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:44:05,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:44:05,498 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:44:05,499 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [504118680] [2023-11-19 07:44:05,499 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [504118680] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:44:05,499 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:44:05,499 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:44:05,499 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [742595211] [2023-11-19 07:44:05,500 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:44:05,500 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:44:05,501 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:44:05,501 INFO L85 PathProgramCache]: Analyzing trace with hash -711093237, now seen corresponding path program 1 times [2023-11-19 07:44:05,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:44:05,501 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [951499650] [2023-11-19 07:44:05,502 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:44:05,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:44:05,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:44:05,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:44:05,610 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:44:05,610 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [951499650] [2023-11-19 07:44:05,610 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [951499650] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:44:05,610 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:44:05,610 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:44:05,611 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [902767866] [2023-11-19 07:44:05,611 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:44:05,611 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:44:05,612 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:44:05,612 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:44:05,612 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:44:05,613 INFO L87 Difference]: Start difference. First operand 66489 states and 96213 transitions. cyclomatic complexity: 29756 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 2 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:44:06,586 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:44:06,587 INFO L93 Difference]: Finished difference Result 126552 states and 182491 transitions. [2023-11-19 07:44:06,587 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 126552 states and 182491 transitions. [2023-11-19 07:44:07,596 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 126092 [2023-11-19 07:44:08,344 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 126552 states to 126552 states and 182491 transitions. [2023-11-19 07:44:08,345 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 126552 [2023-11-19 07:44:08,401 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 126552 [2023-11-19 07:44:08,401 INFO L73 IsDeterministic]: Start isDeterministic. Operand 126552 states and 182491 transitions. [2023-11-19 07:44:08,532 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:44:08,532 INFO L218 hiAutomatonCegarLoop]: Abstraction has 126552 states and 182491 transitions. [2023-11-19 07:44:08,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126552 states and 182491 transitions. [2023-11-19 07:44:10,209 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126552 to 126408. [2023-11-19 07:44:10,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 126408 states, 126408 states have (on average 1.4425273716853364) internal successors, (182347), 126407 states have internal predecessors, (182347), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:44:10,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126408 states to 126408 states and 182347 transitions. [2023-11-19 07:44:10,850 INFO L240 hiAutomatonCegarLoop]: Abstraction has 126408 states and 182347 transitions. [2023-11-19 07:44:10,851 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:44:10,851 INFO L428 stractBuchiCegarLoop]: Abstraction has 126408 states and 182347 transitions. [2023-11-19 07:44:10,852 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-19 07:44:10,852 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 126408 states and 182347 transitions. [2023-11-19 07:44:11,824 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 125948 [2023-11-19 07:44:11,824 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:44:11,824 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:44:11,827 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:44:11,827 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:44:11,827 INFO L748 eck$LassoCheckResult]: Stem: 367390#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 367391#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 368394#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 368395#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 368510#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 368502#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 368503#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 367565#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 367303#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 367304#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 368345#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 368346#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 368313#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 368314#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 368381#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 367351#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 367352#L1006 assume !(0 == ~M_E~0); 367208#L1006-2 assume !(0 == ~T1_E~0); 367209#L1011-1 assume !(0 == ~T2_E~0); 368423#L1016-1 assume !(0 == ~T3_E~0); 368446#L1021-1 assume !(0 == ~T4_E~0); 367085#L1026-1 assume !(0 == ~T5_E~0); 367086#L1031-1 assume !(0 == ~T6_E~0); 368014#L1036-1 assume !(0 == ~T7_E~0); 368008#L1041-1 assume !(0 == ~T8_E~0); 368009#L1046-1 assume !(0 == ~T9_E~0); 367380#L1051-1 assume !(0 == ~T10_E~0); 367381#L1056-1 assume !(0 == ~E_1~0); 368172#L1061-1 assume !(0 == ~E_2~0); 367305#L1066-1 assume !(0 == ~E_3~0); 367306#L1071-1 assume !(0 == ~E_4~0); 368141#L1076-1 assume !(0 == ~E_5~0); 367213#L1081-1 assume !(0 == ~E_6~0); 367214#L1086-1 assume !(0 == ~E_7~0); 367539#L1091-1 assume !(0 == ~E_8~0); 368405#L1096-1 assume !(0 == ~E_9~0); 368406#L1101-1 assume !(0 == ~E_10~0); 367611#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 367612#L484 assume !(1 == ~m_pc~0); 367727#L484-2 is_master_triggered_~__retres1~0#1 := 0; 367728#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 367912#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 368265#L1245 assume !(0 != activate_threads_~tmp~1#1); 368266#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 367997#L503 assume !(1 == ~t1_pc~0); 367998#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 368218#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 367126#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 367127#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 367122#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 367123#L522 assume !(1 == ~t2_pc~0); 367955#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 367319#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 367320#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 367607#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 368347#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 368459#L541 assume !(1 == ~t3_pc~0); 367681#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 367682#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 367069#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 367070#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 367967#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 367968#L560 assume !(1 == ~t4_pc~0); 367200#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 367199#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 367228#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 367081#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 367082#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 367362#L579 assume !(1 == ~t5_pc~0); 367363#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 367147#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 367148#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 368271#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 368445#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 368479#L598 assume 1 == ~t6_pc~0; 367447#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 367448#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 367582#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 367583#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 368050#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 367988#L617 assume !(1 == ~t7_pc~0); 367424#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 367423#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 368521#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 368364#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 367649#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 367650#L636 assume 1 == ~t8_pc~0; 367839#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 367840#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 368219#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 368060#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 367786#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 367787#L655 assume !(1 == ~t9_pc~0); 367817#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 367818#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 367696#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 367697#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 368071#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 368072#L674 assume 1 == ~t10_pc~0; 367191#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 367192#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 367830#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 367831#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 367775#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 367776#L1119 assume !(1 == ~M_E~0); 367287#L1119-2 assume !(1 == ~T1_E~0); 367288#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 367110#L1129-1 assume !(1 == ~T3_E~0); 367111#L1134-1 assume !(1 == ~T4_E~0); 367409#L1139-1 assume !(1 == ~T5_E~0); 367410#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 368543#L1149-1 assume !(1 == ~T7_E~0); 368544#L1154-1 assume !(1 == ~T8_E~0); 367364#L1159-1 assume !(1 == ~T9_E~0); 367365#L1164-1 assume !(1 == ~T10_E~0); 367803#L1169-1 assume !(1 == ~E_1~0); 367699#L1174-1 assume !(1 == ~E_2~0); 367700#L1179-1 assume !(1 == ~E_3~0); 367353#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 367354#L1189-1 assume !(1 == ~E_5~0); 367517#L1194-1 assume !(1 == ~E_6~0); 367518#L1199-1 assume !(1 == ~E_7~0); 367474#L1204-1 assume !(1 == ~E_8~0); 367475#L1209-1 assume !(1 == ~E_9~0); 380534#L1214-1 assume !(1 == ~E_10~0); 382203#L1219-1 assume { :end_inline_reset_delta_events } true; 382204#L1520-2 [2023-11-19 07:44:11,828 INFO L750 eck$LassoCheckResult]: Loop: 382204#L1520-2 assume !false; 422570#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 422568#L981-1 assume !false; 422567#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 417488#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 417484#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 417482#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 417479#L836 assume !(0 != eval_~tmp~0#1); 417480#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 425628#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 425627#L1006-3 assume !(0 == ~M_E~0); 425626#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 425625#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 425624#L1016-3 assume !(0 == ~T3_E~0); 425623#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 425622#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 425621#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 425620#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 425619#L1041-3 assume !(0 == ~T8_E~0); 425618#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 425617#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 425616#L1056-3 assume !(0 == ~E_1~0); 425615#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 425614#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 425613#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 425612#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 425611#L1081-3 assume !(0 == ~E_6~0); 425610#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 425609#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 425608#L1096-3 assume !(0 == ~E_9~0); 425607#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 425606#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 425605#L484-33 assume !(1 == ~m_pc~0); 425604#L484-35 is_master_triggered_~__retres1~0#1 := 0; 425603#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 425602#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 425601#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 425600#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 425599#L503-33 assume !(1 == ~t1_pc~0); 425598#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 425597#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 425596#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 425595#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 425594#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 425593#L522-33 assume 1 == ~t2_pc~0; 425591#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 425590#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 425589#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 425588#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 425587#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 425586#L541-33 assume !(1 == ~t3_pc~0); 425585#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 425584#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 425583#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 425582#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 425581#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 425580#L560-33 assume !(1 == ~t4_pc~0); 425578#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 425577#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 425576#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 425575#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 425574#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 425573#L579-33 assume !(1 == ~t5_pc~0); 425572#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 425571#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 425570#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 425569#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 425568#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 425567#L598-33 assume 1 == ~t6_pc~0; 425566#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 425564#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 425563#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 425562#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 425561#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 425560#L617-33 assume 1 == ~t7_pc~0; 425558#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 425557#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 425556#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 425555#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 425554#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 425553#L636-33 assume 1 == ~t8_pc~0; 425552#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 425550#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 425549#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 425548#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 425547#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 425546#L655-33 assume 1 == ~t9_pc~0; 425544#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 425543#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 425542#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 425541#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 425540#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 425539#L674-33 assume !(1 == ~t10_pc~0); 425538#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 425536#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 425535#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 425534#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 425533#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 382930#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 382931#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 382913#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 379084#L1129-3 assume !(1 == ~T3_E~0); 382896#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 382897#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 382789#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 382790#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 382708#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 382709#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 382690#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 382681#L1169-3 assume !(1 == ~E_1~0); 382673#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 382674#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 382659#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 382651#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 382652#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 382636#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 382628#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 382629#L1209-3 assume !(1 == ~E_9~0); 381614#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 382609#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 382610#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 425233#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 425232#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 425231#L1539 assume !(0 == start_simulation_~tmp~3#1); 425229#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 425228#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 425217#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 425216#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 425215#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 425214#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 425213#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 425212#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 382204#L1520-2 [2023-11-19 07:44:11,829 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:44:11,829 INFO L85 PathProgramCache]: Analyzing trace with hash 776922900, now seen corresponding path program 1 times [2023-11-19 07:44:11,829 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:44:11,829 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1132444971] [2023-11-19 07:44:11,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:44:11,830 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:44:11,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:44:11,914 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:44:11,915 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:44:11,915 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1132444971] [2023-11-19 07:44:11,915 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1132444971] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:44:11,915 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:44:11,916 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:44:11,916 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1205534967] [2023-11-19 07:44:11,916 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:44:11,916 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:44:11,917 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:44:11,917 INFO L85 PathProgramCache]: Analyzing trace with hash 310554957, now seen corresponding path program 1 times [2023-11-19 07:44:11,917 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:44:11,917 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [34918545] [2023-11-19 07:44:11,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:44:11,918 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:44:11,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:44:11,965 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:44:11,965 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:44:11,965 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [34918545] [2023-11-19 07:44:11,965 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [34918545] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:44:11,966 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:44:11,966 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:44:11,966 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [552156304] [2023-11-19 07:44:11,966 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:44:11,966 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:44:11,967 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:44:11,967 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:44:11,967 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:44:11,967 INFO L87 Difference]: Start difference. First operand 126408 states and 182347 transitions. cyclomatic complexity: 56003 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:44:13,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:44:13,924 INFO L93 Difference]: Finished difference Result 358431 states and 513764 transitions. [2023-11-19 07:44:13,924 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 358431 states and 513764 transitions. [2023-11-19 07:44:15,792 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 354228 [2023-11-19 07:44:17,336 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 358431 states to 358431 states and 513764 transitions. [2023-11-19 07:44:17,336 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 358431 [2023-11-19 07:44:17,478 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 358431 [2023-11-19 07:44:17,478 INFO L73 IsDeterministic]: Start isDeterministic. Operand 358431 states and 513764 transitions. [2023-11-19 07:44:17,736 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:44:17,737 INFO L218 hiAutomatonCegarLoop]: Abstraction has 358431 states and 513764 transitions. [2023-11-19 07:44:17,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 358431 states and 513764 transitions. [2023-11-19 07:44:21,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 358431 to 349951. [2023-11-19 07:44:21,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 349951 states, 349951 states have (on average 1.4355038276787322) internal successors, (502356), 349950 states have internal predecessors, (502356), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:44:22,828 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 349951 states to 349951 states and 502356 transitions. [2023-11-19 07:44:22,828 INFO L240 hiAutomatonCegarLoop]: Abstraction has 349951 states and 502356 transitions. [2023-11-19 07:44:22,829 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:44:22,830 INFO L428 stractBuchiCegarLoop]: Abstraction has 349951 states and 502356 transitions. [2023-11-19 07:44:22,830 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-19 07:44:22,830 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 349951 states and 502356 transitions. [2023-11-19 07:44:24,968 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 349044 [2023-11-19 07:44:24,968 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:44:24,974 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:44:24,978 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:44:24,978 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:44:24,978 INFO L748 eck$LassoCheckResult]: Stem: 852241#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 852242#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 853262#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 853263#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 853400#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 853389#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 853390#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 852407#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 852155#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 852156#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 853217#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 853218#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 853186#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 853187#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 853247#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 852203#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 852204#L1006 assume !(0 == ~M_E~0); 852061#L1006-2 assume !(0 == ~T1_E~0); 852062#L1011-1 assume !(0 == ~T2_E~0); 853302#L1016-1 assume !(0 == ~T3_E~0); 853330#L1021-1 assume !(0 == ~T4_E~0); 851934#L1026-1 assume !(0 == ~T5_E~0); 851935#L1031-1 assume !(0 == ~T6_E~0); 852869#L1036-1 assume !(0 == ~T7_E~0); 852863#L1041-1 assume !(0 == ~T8_E~0); 852864#L1046-1 assume !(0 == ~T9_E~0); 852232#L1051-1 assume !(0 == ~T10_E~0); 852233#L1056-1 assume !(0 == ~E_1~0); 853033#L1061-1 assume !(0 == ~E_2~0); 852157#L1066-1 assume !(0 == ~E_3~0); 852158#L1071-1 assume !(0 == ~E_4~0); 852998#L1076-1 assume !(0 == ~E_5~0); 852066#L1081-1 assume !(0 == ~E_6~0); 852067#L1086-1 assume !(0 == ~E_7~0); 852381#L1091-1 assume !(0 == ~E_8~0); 853279#L1096-1 assume !(0 == ~E_9~0); 853280#L1101-1 assume !(0 == ~E_10~0); 852455#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 852456#L484 assume !(1 == ~m_pc~0); 852573#L484-2 is_master_triggered_~__retres1~0#1 := 0; 852574#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 852771#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 853133#L1245 assume !(0 != activate_threads_~tmp~1#1); 853134#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 852854#L503 assume !(1 == ~t1_pc~0); 852855#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 853080#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 851976#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 851977#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 851972#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 851973#L522 assume !(1 == ~t2_pc~0); 852812#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 852171#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 852172#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 852451#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 853219#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 853343#L541 assume !(1 == ~t3_pc~0); 852526#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 852527#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 851918#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 851919#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 852825#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 852826#L560 assume !(1 == ~t4_pc~0); 852053#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 852052#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 852081#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 851930#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 851931#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 852214#L579 assume !(1 == ~t5_pc~0); 852215#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 851997#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 851998#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 853140#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 853329#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 853369#L598 assume !(1 == ~t6_pc~0); 853050#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 852628#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 852424#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 852425#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 852903#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 852845#L617 assume !(1 == ~t7_pc~0); 852273#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 852272#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 853411#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 853233#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 852494#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 852495#L636 assume 1 == ~t8_pc~0; 852688#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 852689#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 853081#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 852915#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 852634#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 852635#L655 assume !(1 == ~t9_pc~0); 852665#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 852666#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 852541#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 852542#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 852926#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 852927#L674 assume 1 == ~t10_pc~0; 852044#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 852045#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 852678#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 852679#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 852622#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 852623#L1119 assume !(1 == ~M_E~0); 852139#L1119-2 assume !(1 == ~T1_E~0); 852140#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 852551#L1129-1 assume !(1 == ~T3_E~0); 1041799#L1134-1 assume !(1 == ~T4_E~0); 852258#L1139-1 assume !(1 == ~T5_E~0); 852259#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1105449#L1149-1 assume !(1 == ~T7_E~0); 1105446#L1154-1 assume !(1 == ~T8_E~0); 852216#L1159-1 assume !(1 == ~T9_E~0); 852217#L1164-1 assume !(1 == ~T10_E~0); 852651#L1169-1 assume !(1 == ~E_1~0); 852545#L1174-1 assume !(1 == ~E_2~0); 852309#L1179-1 assume !(1 == ~E_3~0); 852205#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 852206#L1189-1 assume !(1 == ~E_5~0); 852256#L1194-1 assume !(1 == ~E_6~0); 852360#L1199-1 assume !(1 == ~E_7~0); 852318#L1204-1 assume !(1 == ~E_8~0); 852319#L1209-1 assume !(1 == ~E_9~0); 852924#L1214-1 assume !(1 == ~E_10~0); 852925#L1219-1 assume { :end_inline_reset_delta_events } true; 853421#L1520-2 [2023-11-19 07:44:24,979 INFO L750 eck$LassoCheckResult]: Loop: 853421#L1520-2 assume !false; 1175515#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1175512#L981-1 assume !false; 1175510#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1175455#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1175446#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1175437#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1175431#L836 assume !(0 != eval_~tmp~0#1); 1175432#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1176803#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1176801#L1006-3 assume !(0 == ~M_E~0); 1176799#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1176797#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1176795#L1016-3 assume !(0 == ~T3_E~0); 1176793#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1176790#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1176788#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1176786#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1176784#L1041-3 assume !(0 == ~T8_E~0); 1176782#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1176780#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1176778#L1056-3 assume !(0 == ~E_1~0); 1176776#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1176774#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1176772#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1176770#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1176768#L1081-3 assume !(0 == ~E_6~0); 1176765#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1176763#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1176761#L1096-3 assume !(0 == ~E_9~0); 1176759#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1176757#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1176755#L484-33 assume !(1 == ~m_pc~0); 1176754#L484-35 is_master_triggered_~__retres1~0#1 := 0; 1176751#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1176749#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1176747#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 1176745#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1176743#L503-33 assume !(1 == ~t1_pc~0); 1176741#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1176739#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1176737#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1176735#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1176733#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1176731#L522-33 assume !(1 == ~t2_pc~0); 1176729#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1176725#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1176723#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1176721#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1176719#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1176717#L541-33 assume !(1 == ~t3_pc~0); 1176715#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1176712#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1176710#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1176708#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1176706#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1176704#L560-33 assume !(1 == ~t4_pc~0); 1176701#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 1176698#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1176696#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1176694#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1176692#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1176690#L579-33 assume !(1 == ~t5_pc~0); 1176688#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1176685#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1176683#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1176681#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1176679#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1176578#L598-33 assume !(1 == ~t6_pc~0); 1176577#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 1176567#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1176559#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1176552#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1176544#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1176531#L617-33 assume 1 == ~t7_pc~0; 1176521#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1176516#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1176499#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1176425#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1176420#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1176415#L636-33 assume !(1 == ~t8_pc~0); 1176407#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 1176371#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1176370#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1176369#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1176368#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1176366#L655-33 assume 1 == ~t9_pc~0; 1176363#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1176361#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1176359#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1176357#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 1176355#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1176353#L674-33 assume !(1 == ~t10_pc~0); 1176351#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 1176348#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1176346#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1176344#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1176342#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1176340#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1176338#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1176336#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1044946#L1129-3 assume !(1 == ~T3_E~0); 1087026#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1176329#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1176326#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1176323#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1176320#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1176317#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1176314#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1176311#L1169-3 assume !(1 == ~E_1~0); 1151835#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1176303#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1176299#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1176295#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1176290#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1176287#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1176284#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1176281#L1209-3 assume !(1 == ~E_9~0); 1113604#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1176277#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1176037#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1176019#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1176009#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1176000#L1539 assume !(0 == start_simulation_~tmp~3#1); 1175991#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1175557#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1175546#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1175545#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 1175544#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1175542#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1175540#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1175538#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 853421#L1520-2 [2023-11-19 07:44:24,980 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:44:24,980 INFO L85 PathProgramCache]: Analyzing trace with hash 75354675, now seen corresponding path program 1 times [2023-11-19 07:44:24,980 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:44:24,981 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [819751372] [2023-11-19 07:44:24,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:44:24,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:44:25,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:44:25,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:44:25,082 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:44:25,082 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [819751372] [2023-11-19 07:44:25,082 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [819751372] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:44:25,082 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:44:25,083 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:44:25,083 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2050160000] [2023-11-19 07:44:25,083 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:44:25,084 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:44:25,084 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:44:25,084 INFO L85 PathProgramCache]: Analyzing trace with hash 1516099754, now seen corresponding path program 1 times [2023-11-19 07:44:25,084 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:44:25,085 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1175731713] [2023-11-19 07:44:25,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:44:25,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:44:25,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:44:25,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:44:25,141 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:44:25,141 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1175731713] [2023-11-19 07:44:25,142 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1175731713] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:44:25,142 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:44:25,142 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:44:25,142 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [150980352] [2023-11-19 07:44:25,142 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:44:25,143 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:44:25,143 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:44:25,143 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 07:44:25,144 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 07:44:25,144 INFO L87 Difference]: Start difference. First operand 349951 states and 502356 transitions. cyclomatic complexity: 152533 Second operand has 5 states, 5 states have (on average 25.2) internal successors, (126), 5 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:44:28,902 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:44:28,903 INFO L93 Difference]: Finished difference Result 766719 states and 1092625 transitions. [2023-11-19 07:44:28,903 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 766719 states and 1092625 transitions.