./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.11.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 9bd2c7ff Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e986a08e-2fc2-4ace-8abd-dc5ce627b1bc/bin/uautomizer-verify-uCwYo4JHxu/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e986a08e-2fc2-4ace-8abd-dc5ce627b1bc/bin/uautomizer-verify-uCwYo4JHxu/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e986a08e-2fc2-4ace-8abd-dc5ce627b1bc/bin/uautomizer-verify-uCwYo4JHxu/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e986a08e-2fc2-4ace-8abd-dc5ce627b1bc/bin/uautomizer-verify-uCwYo4JHxu/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.11.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e986a08e-2fc2-4ace-8abd-dc5ce627b1bc/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e986a08e-2fc2-4ace-8abd-dc5ce627b1bc/bin/uautomizer-verify-uCwYo4JHxu --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 940a677bfde7dbbc79e036121bd0ec6fd3518c0f58a02d336e5d42fafb098792 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-9bd2c7f [2023-11-19 07:37:45,365 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-19 07:37:45,479 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e986a08e-2fc2-4ace-8abd-dc5ce627b1bc/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-19 07:37:45,488 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-19 07:37:45,491 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-19 07:37:45,528 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-19 07:37:45,530 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-19 07:37:45,531 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-19 07:37:45,532 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-19 07:37:45,532 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-19 07:37:45,533 INFO L153 SettingsManager]: * Use SBE=true [2023-11-19 07:37:45,534 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-19 07:37:45,534 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-19 07:37:45,535 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-19 07:37:45,535 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-19 07:37:45,536 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-19 07:37:45,536 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-19 07:37:45,537 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-19 07:37:45,537 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-19 07:37:45,537 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-19 07:37:45,538 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-19 07:37:45,540 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-19 07:37:45,540 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-19 07:37:45,541 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-19 07:37:45,541 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-19 07:37:45,541 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-19 07:37:45,542 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-19 07:37:45,542 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-19 07:37:45,543 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-19 07:37:45,543 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-19 07:37:45,544 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-19 07:37:45,545 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-19 07:37:45,545 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-19 07:37:45,545 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-19 07:37:45,545 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-19 07:37:45,546 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-19 07:37:45,546 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e986a08e-2fc2-4ace-8abd-dc5ce627b1bc/bin/uautomizer-verify-uCwYo4JHxu/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e986a08e-2fc2-4ace-8abd-dc5ce627b1bc/bin/uautomizer-verify-uCwYo4JHxu Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 940a677bfde7dbbc79e036121bd0ec6fd3518c0f58a02d336e5d42fafb098792 [2023-11-19 07:37:45,813 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-19 07:37:45,845 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-19 07:37:45,849 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-19 07:37:45,851 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-19 07:37:45,852 INFO L274 PluginConnector]: CDTParser initialized [2023-11-19 07:37:45,854 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e986a08e-2fc2-4ace-8abd-dc5ce627b1bc/bin/uautomizer-verify-uCwYo4JHxu/../../sv-benchmarks/c/systemc/transmitter.11.cil.c [2023-11-19 07:37:48,855 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-19 07:37:49,133 INFO L384 CDTParser]: Found 1 translation units. [2023-11-19 07:37:49,134 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e986a08e-2fc2-4ace-8abd-dc5ce627b1bc/sv-benchmarks/c/systemc/transmitter.11.cil.c [2023-11-19 07:37:49,150 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e986a08e-2fc2-4ace-8abd-dc5ce627b1bc/bin/uautomizer-verify-uCwYo4JHxu/data/cb117110e/45d6b916f0e3490194e274904efe752a/FLAG4310cafb8 [2023-11-19 07:37:49,172 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e986a08e-2fc2-4ace-8abd-dc5ce627b1bc/bin/uautomizer-verify-uCwYo4JHxu/data/cb117110e/45d6b916f0e3490194e274904efe752a [2023-11-19 07:37:49,175 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-19 07:37:49,177 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-19 07:37:49,178 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-19 07:37:49,178 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-19 07:37:49,183 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-19 07:37:49,184 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:37:49" (1/1) ... [2023-11-19 07:37:49,185 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3f54e3b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:49, skipping insertion in model container [2023-11-19 07:37:49,185 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:37:49" (1/1) ... [2023-11-19 07:37:49,247 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-19 07:37:49,549 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:37:49,579 INFO L202 MainTranslator]: Completed pre-run [2023-11-19 07:37:49,650 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:37:49,673 INFO L206 MainTranslator]: Completed translation [2023-11-19 07:37:49,673 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:49 WrapperNode [2023-11-19 07:37:49,673 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-19 07:37:49,674 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-19 07:37:49,675 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-19 07:37:49,675 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-19 07:37:49,682 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:49" (1/1) ... [2023-11-19 07:37:49,697 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:49" (1/1) ... [2023-11-19 07:37:49,803 INFO L138 Inliner]: procedures = 50, calls = 64, calls flagged for inlining = 59, calls inlined = 225, statements flattened = 3461 [2023-11-19 07:37:49,804 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-19 07:37:49,804 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-19 07:37:49,805 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-19 07:37:49,805 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-19 07:37:49,815 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:49" (1/1) ... [2023-11-19 07:37:49,815 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:49" (1/1) ... [2023-11-19 07:37:49,838 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:49" (1/1) ... [2023-11-19 07:37:49,845 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:49" (1/1) ... [2023-11-19 07:37:49,915 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:49" (1/1) ... [2023-11-19 07:37:49,962 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:49" (1/1) ... [2023-11-19 07:37:49,971 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:49" (1/1) ... [2023-11-19 07:37:49,984 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:49" (1/1) ... [2023-11-19 07:37:50,026 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-19 07:37:50,030 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-19 07:37:50,030 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-19 07:37:50,030 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-19 07:37:50,031 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:49" (1/1) ... [2023-11-19 07:37:50,037 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 07:37:50,050 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e986a08e-2fc2-4ace-8abd-dc5ce627b1bc/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:37:50,066 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e986a08e-2fc2-4ace-8abd-dc5ce627b1bc/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 07:37:50,090 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e986a08e-2fc2-4ace-8abd-dc5ce627b1bc/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-19 07:37:50,111 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-19 07:37:50,112 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-19 07:37:50,112 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-19 07:37:50,112 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-19 07:37:50,252 INFO L236 CfgBuilder]: Building ICFG [2023-11-19 07:37:50,254 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-19 07:37:52,370 INFO L277 CfgBuilder]: Performing block encoding [2023-11-19 07:37:52,392 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-19 07:37:52,393 INFO L302 CfgBuilder]: Removed 15 assume(true) statements. [2023-11-19 07:37:52,408 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:37:52 BoogieIcfgContainer [2023-11-19 07:37:52,408 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-19 07:37:52,409 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-19 07:37:52,409 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-19 07:37:52,413 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-19 07:37:52,414 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:37:52,415 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 07:37:49" (1/3) ... [2023-11-19 07:37:52,416 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3892a91c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:37:52, skipping insertion in model container [2023-11-19 07:37:52,416 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:37:52,416 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:37:49" (2/3) ... [2023-11-19 07:37:52,417 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3892a91c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:37:52, skipping insertion in model container [2023-11-19 07:37:52,417 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:37:52,417 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:37:52" (3/3) ... [2023-11-19 07:37:52,419 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.11.cil.c [2023-11-19 07:37:52,510 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-19 07:37:52,511 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-19 07:37:52,511 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-19 07:37:52,511 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-19 07:37:52,511 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-19 07:37:52,512 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-19 07:37:52,512 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-19 07:37:52,512 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-19 07:37:52,523 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1496 states, 1495 states have (on average 1.5010033444816053) internal successors, (2244), 1495 states have internal predecessors, (2244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:52,608 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1343 [2023-11-19 07:37:52,616 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:52,616 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:52,637 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:52,638 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:52,638 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-19 07:37:52,642 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1496 states, 1495 states have (on average 1.5010033444816053) internal successors, (2244), 1495 states have internal predecessors, (2244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:52,665 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1343 [2023-11-19 07:37:52,666 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:52,666 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:52,673 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:52,674 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:52,686 INFO L748 eck$LassoCheckResult]: Stem: 227#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1380#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1124#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1376#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 510#L761true assume !(1 == ~m_i~0);~m_st~0 := 2; 528#L761-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 424#L766-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 355#L771-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 197#L776-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 18#L781-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1480#L786-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 39#L791-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 657#L796-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 621#L801-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 665#L806-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1359#L811-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 255#L816-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1175#L1090true assume !(0 == ~M_E~0); 280#L1090-2true assume !(0 == ~T1_E~0); 1333#L1095-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 801#L1100-1true assume !(0 == ~T3_E~0); 828#L1105-1true assume !(0 == ~T4_E~0); 151#L1110-1true assume !(0 == ~T5_E~0); 375#L1115-1true assume !(0 == ~T6_E~0); 601#L1120-1true assume !(0 == ~T7_E~0); 1368#L1125-1true assume !(0 == ~T8_E~0); 1360#L1130-1true assume !(0 == ~T9_E~0); 826#L1135-1true assume 0 == ~T10_E~0;~T10_E~0 := 1; 258#L1140-1true assume !(0 == ~T11_E~0); 757#L1145-1true assume !(0 == ~E_1~0); 796#L1150-1true assume !(0 == ~E_2~0); 364#L1155-1true assume !(0 == ~E_3~0); 1344#L1160-1true assume !(0 == ~E_4~0); 429#L1165-1true assume !(0 == ~E_5~0); 1097#L1170-1true assume !(0 == ~E_6~0); 1285#L1175-1true assume 0 == ~E_7~0;~E_7~0 := 1; 481#L1180-1true assume !(0 == ~E_8~0); 914#L1185-1true assume !(0 == ~E_9~0); 256#L1190-1true assume !(0 == ~E_10~0); 491#L1195-1true assume !(0 == ~E_11~0); 1041#L1200-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 371#L525true assume !(1 == ~m_pc~0); 60#L525-2true is_master_triggered_~__retres1~0#1 := 0; 1035#L536true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 925#is_master_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 894#L1350true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 248#L1350-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 532#L544true assume 1 == ~t1_pc~0; 410#L545true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 754#L555true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 163#L1358true assume !(0 != activate_threads_~tmp___0~0#1); 578#L1358-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1030#L563true assume !(1 == ~t2_pc~0); 744#L563-2true is_transmit2_triggered_~__retres1~2#1 := 0; 69#L574true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 362#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 295#L1366true assume !(0 != activate_threads_~tmp___1~0#1); 643#L1366-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 755#L582true assume 1 == ~t3_pc~0; 136#L583true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1246#L593true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1108#L1374true assume !(0 != activate_threads_~tmp___2~0#1); 103#L1374-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1404#L601true assume !(1 == ~t4_pc~0); 847#L601-2true is_transmit4_triggered_~__retres1~4#1 := 0; 376#L612true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 108#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 765#L1382true assume !(0 != activate_threads_~tmp___3~0#1); 1411#L1382-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1218#L620true assume 1 == ~t5_pc~0; 83#L621true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 662#L631true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 932#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1479#L1390true assume !(0 != activate_threads_~tmp___4~0#1); 1274#L1390-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1372#L639true assume !(1 == ~t6_pc~0); 599#L639-2true is_transmit6_triggered_~__retres1~6#1 := 0; 315#L650true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 347#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1269#L1398true assume !(0 != activate_threads_~tmp___5~0#1); 379#L1398-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 961#L658true assume 1 == ~t7_pc~0; 600#L659true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1293#L669true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1396#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 704#L1406true assume !(0 != activate_threads_~tmp___6~0#1); 251#L1406-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 383#L677true assume 1 == ~t8_pc~0; 883#L678true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 143#L688true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 849#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 292#L1414true assume !(0 != activate_threads_~tmp___7~0#1); 884#L1414-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 996#L696true assume !(1 == ~t9_pc~0); 588#L696-2true is_transmit9_triggered_~__retres1~9#1 := 0; 672#L707true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 416#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 605#L1422true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 805#L1422-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1152#L715true assume 1 == ~t10_pc~0; 814#L716true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 690#L726true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 520#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 781#L1430true assume !(0 != activate_threads_~tmp___9~0#1); 477#L1430-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 141#L734true assume !(1 == ~t11_pc~0); 430#L734-2true is_transmit11_triggered_~__retres1~11#1 := 0; 483#L745true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 711#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12#L1438true assume !(0 != activate_threads_~tmp___10~0#1); 663#L1438-2true havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1214#L1213true assume !(1 == ~M_E~0); 475#L1213-2true assume !(1 == ~T1_E~0); 981#L1218-1true assume !(1 == ~T2_E~0); 29#L1223-1true assume !(1 == ~T3_E~0); 459#L1228-1true assume !(1 == ~T4_E~0); 1275#L1233-1true assume !(1 == ~T5_E~0); 1460#L1238-1true assume !(1 == ~T6_E~0); 764#L1243-1true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1418#L1248-1true assume !(1 == ~T8_E~0); 811#L1253-1true assume !(1 == ~T9_E~0); 1112#L1258-1true assume !(1 == ~T10_E~0); 789#L1263-1true assume !(1 == ~T11_E~0); 1160#L1268-1true assume !(1 == ~E_1~0); 617#L1273-1true assume !(1 == ~E_2~0); 1256#L1278-1true assume !(1 == ~E_3~0); 314#L1283-1true assume 1 == ~E_4~0;~E_4~0 := 2; 1306#L1288-1true assume !(1 == ~E_5~0); 939#L1293-1true assume !(1 == ~E_6~0); 890#L1298-1true assume !(1 == ~E_7~0); 647#L1303-1true assume !(1 == ~E_8~0); 321#L1308-1true assume !(1 == ~E_9~0); 260#L1313-1true assume !(1 == ~E_10~0); 1385#L1318-1true assume !(1 == ~E_11~0); 265#L1323-1true assume { :end_inline_reset_delta_events } true; 1165#L1644-2true [2023-11-19 07:37:52,690 INFO L750 eck$LassoCheckResult]: Loop: 1165#L1644-2true assume !false; 702#L1645true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 208#L1065-1true assume !true; 857#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 543#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 966#L1090-3true assume !(0 == ~M_E~0); 1054#L1090-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1388#L1095-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 999#L1100-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1267#L1105-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 193#L1110-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1102#L1115-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 356#L1120-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 762#L1125-3true assume !(0 == ~T8_E~0); 1140#L1130-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1305#L1135-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 308#L1140-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 43#L1145-3true assume 0 == ~E_1~0;~E_1~0 := 1; 497#L1150-3true assume 0 == ~E_2~0;~E_2~0 := 1; 104#L1155-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1440#L1160-3true assume 0 == ~E_4~0;~E_4~0 := 1; 299#L1165-3true assume !(0 == ~E_5~0); 1494#L1170-3true assume 0 == ~E_6~0;~E_6~0 := 1; 573#L1175-3true assume 0 == ~E_7~0;~E_7~0 := 1; 250#L1180-3true assume 0 == ~E_8~0;~E_8~0 := 1; 117#L1185-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1308#L1190-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1117#L1195-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1492#L1200-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 446#L525-36true assume 1 == ~m_pc~0; 1121#L526-12true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 168#L536-12true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1127#is_master_triggered_returnLabel#13true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 329#L1350-36true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 572#L1350-38true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 282#L544-36true assume !(1 == ~t1_pc~0); 936#L544-38true is_transmit1_triggered_~__retres1~1#1 := 0; 679#L555-12true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1125#is_transmit1_triggered_returnLabel#13true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1286#L1358-36true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1093#L1358-38true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 927#L563-36true assume !(1 == ~t2_pc~0); 974#L563-38true is_transmit2_triggered_~__retres1~2#1 := 0; 41#L574-12true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 904#is_transmit2_triggered_returnLabel#13true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1284#L1366-36true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 457#L1366-38true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1387#L582-36true assume 1 == ~t3_pc~0; 350#L583-12true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 509#L593-12true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 411#is_transmit3_triggered_returnLabel#13true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 670#L1374-36true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 482#L1374-38true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 443#L601-36true assume 1 == ~t4_pc~0; 368#L602-12true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1475#L612-12true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 557#is_transmit4_triggered_returnLabel#13true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1064#L1382-36true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1208#L1382-38true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 911#L620-36true assume !(1 == ~t5_pc~0); 1472#L620-38true is_transmit5_triggered_~__retres1~5#1 := 0; 747#L631-12true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1075#is_transmit5_triggered_returnLabel#13true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 382#L1390-36true assume !(0 != activate_threads_~tmp___4~0#1); 174#L1390-38true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65#L639-36true assume !(1 == ~t6_pc~0); 1429#L639-38true is_transmit6_triggered_~__retres1~6#1 := 0; 85#L650-12true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 387#is_transmit6_triggered_returnLabel#13true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 203#L1398-36true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 603#L1398-38true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1207#L658-36true assume 1 == ~t7_pc~0; 123#L659-12true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1032#L669-12true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1038#is_transmit7_triggered_returnLabel#13true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 61#L1406-36true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 733#L1406-38true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 950#L677-36true assume 1 == ~t8_pc~0; 1110#L678-12true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 644#L688-12true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 645#is_transmit8_triggered_returnLabel#13true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1205#L1414-36true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 558#L1414-38true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1114#L696-36true assume !(1 == ~t9_pc~0); 1330#L696-38true is_transmit9_triggered_~__retres1~9#1 := 0; 846#L707-12true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 436#is_transmit9_triggered_returnLabel#13true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1033#L1422-36true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 574#L1422-38true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1281#L715-36true assume !(1 == ~t10_pc~0); 545#L715-38true is_transmit10_triggered_~__retres1~10#1 := 0; 13#L726-12true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 320#is_transmit10_triggered_returnLabel#13true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2#L1430-36true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1079#L1430-38true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 200#L734-36true assume !(1 == ~t11_pc~0); 49#L734-38true is_transmit11_triggered_~__retres1~11#1 := 0; 209#L745-12true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1331#is_transmit11_triggered_returnLabel#13true activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9#L1438-36true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 625#L1438-38true havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1119#L1213-3true assume 1 == ~M_E~0;~M_E~0 := 2; 361#L1213-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 730#L1218-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 225#L1223-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 770#L1228-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 332#L1233-3true assume !(1 == ~T5_E~0); 1295#L1238-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 507#L1243-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1063#L1248-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1423#L1253-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1070#L1258-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 216#L1263-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1015#L1268-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1040#L1273-3true assume !(1 == ~E_2~0); 1473#L1278-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1043#L1283-3true assume 1 == ~E_4~0;~E_4~0 := 2; 428#L1288-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1316#L1293-3true assume 1 == ~E_6~0;~E_6~0 := 2; 328#L1298-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1167#L1303-3true assume 1 == ~E_8~0;~E_8~0 := 2; 699#L1308-3true assume 1 == ~E_9~0;~E_9~0 := 2; 326#L1313-3true assume !(1 == ~E_10~0); 1066#L1318-3true assume 1 == ~E_11~0;~E_11~0 := 2; 217#L1323-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1450#L829-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 439#L891-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 316#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1451#L1663true assume !(0 == start_simulation_~tmp~3#1); 1355#L1663-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 602#L829-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 526#L891-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 46#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 76#L1618true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 254#L1625true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 560#stop_simulation_returnLabel#1true start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1194#L1676true assume !(0 != start_simulation_~tmp___0~1#1); 1165#L1644-2true [2023-11-19 07:37:52,696 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:52,697 INFO L85 PathProgramCache]: Analyzing trace with hash -92888918, now seen corresponding path program 1 times [2023-11-19 07:37:52,707 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:52,707 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2029979589] [2023-11-19 07:37:52,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:52,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:52,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:53,099 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:53,100 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:53,100 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2029979589] [2023-11-19 07:37:53,101 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2029979589] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:53,101 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:53,101 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:53,103 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1364080649] [2023-11-19 07:37:53,104 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:53,109 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:37:53,110 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:53,110 INFO L85 PathProgramCache]: Analyzing trace with hash -1163004199, now seen corresponding path program 1 times [2023-11-19 07:37:53,110 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:53,111 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1776090369] [2023-11-19 07:37:53,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:53,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:53,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:53,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:53,190 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:53,190 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1776090369] [2023-11-19 07:37:53,190 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1776090369] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:53,191 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:53,191 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:37:53,191 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1411725463] [2023-11-19 07:37:53,191 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:53,193 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:37:53,194 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:53,226 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2023-11-19 07:37:53,227 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2023-11-19 07:37:53,232 INFO L87 Difference]: Start difference. First operand has 1496 states, 1495 states have (on average 1.5010033444816053) internal successors, (2244), 1495 states have internal predecessors, (2244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 68.5) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:53,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:53,326 INFO L93 Difference]: Finished difference Result 1494 states and 2211 transitions. [2023-11-19 07:37:53,328 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1494 states and 2211 transitions. [2023-11-19 07:37:53,345 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:53,363 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1494 states to 1488 states and 2205 transitions. [2023-11-19 07:37:53,364 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-19 07:37:53,367 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-19 07:37:53,368 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2205 transitions. [2023-11-19 07:37:53,378 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:53,378 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2205 transitions. [2023-11-19 07:37:53,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2205 transitions. [2023-11-19 07:37:53,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-19 07:37:53,473 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4818548387096775) internal successors, (2205), 1487 states have internal predecessors, (2205), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:53,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2205 transitions. [2023-11-19 07:37:53,486 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2205 transitions. [2023-11-19 07:37:53,487 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2023-11-19 07:37:53,491 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2205 transitions. [2023-11-19 07:37:53,492 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-19 07:37:53,492 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2205 transitions. [2023-11-19 07:37:53,502 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:53,502 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:53,503 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:53,507 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:53,507 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:53,508 INFO L748 eck$LassoCheckResult]: Stem: 3441#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 3442#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4424#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4425#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3891#L761 assume !(1 == ~m_i~0);~m_st~0 := 2; 3892#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3763#L766-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3656#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3385#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3033#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3034#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3078#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3079#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4023#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4024#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4066#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 3482#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3483#L1090 assume !(0 == ~M_E~0); 3528#L1090-2 assume !(0 == ~T1_E~0); 3529#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4214#L1100-1 assume !(0 == ~T3_E~0); 4215#L1105-1 assume !(0 == ~T4_E~0); 3306#L1110-1 assume !(0 == ~T5_E~0); 3307#L1115-1 assume !(0 == ~T6_E~0); 3692#L1120-1 assume !(0 == ~T7_E~0); 4000#L1125-1 assume !(0 == ~T8_E~0); 4472#L1130-1 assume !(0 == ~T9_E~0); 4235#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3487#L1140-1 assume !(0 == ~T11_E~0); 3488#L1145-1 assume !(0 == ~E_1~0); 4169#L1150-1 assume !(0 == ~E_2~0); 3669#L1155-1 assume !(0 == ~E_3~0); 3670#L1160-1 assume !(0 == ~E_4~0); 3768#L1165-1 assume !(0 == ~E_5~0); 3769#L1170-1 assume !(0 == ~E_6~0); 4407#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 3849#L1180-1 assume !(0 == ~E_8~0); 3850#L1185-1 assume !(0 == ~E_9~0); 3484#L1190-1 assume !(0 == ~E_10~0); 3485#L1195-1 assume !(0 == ~E_11~0); 3865#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3689#L525 assume !(1 == ~m_pc~0); 3123#L525-2 is_master_triggered_~__retres1~0#1 := 0; 3124#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4309#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4284#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3474#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3475#L544 assume 1 == ~t1_pc~0; 3744#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3691#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3102#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3103#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 3329#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3969#L563 assume !(1 == ~t2_pc~0); 4155#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3142#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3143#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3556#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 3557#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4047#L582 assume 1 == ~t3_pc~0; 3275#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3276#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3025#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3026#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 3211#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3212#L601 assume !(1 == ~t4_pc~0); 4181#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3693#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3225#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3226#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 4176#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4448#L620 assume 1 == ~t5_pc~0; 3174#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3175#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4063#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4315#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 4457#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4458#L639 assume !(1 == ~t6_pc~0); 3998#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3593#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3594#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3642#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 3699#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3700#L658 assume 1 == ~t7_pc~0; 3999#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3916#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4463#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4116#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 3477#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3478#L677 assume 1 == ~t8_pc~0; 3707#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3288#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3289#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3549#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 3550#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4276#L696 assume !(1 == ~t9_pc~0); 3983#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3984#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3754#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3755#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4005#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4218#L715 assume 1 == ~t10_pc~0; 4225#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4097#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3903#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3904#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 3843#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3282#L734 assume !(1 == ~t11_pc~0); 3283#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 3770#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3854#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3023#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 3024#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4064#L1213 assume !(1 == ~M_E~0); 3841#L1213-2 assume !(1 == ~T1_E~0); 3842#L1218-1 assume !(1 == ~T2_E~0); 3056#L1223-1 assume !(1 == ~T3_E~0); 3057#L1228-1 assume !(1 == ~T4_E~0); 3816#L1233-1 assume !(1 == ~T5_E~0); 4459#L1238-1 assume !(1 == ~T6_E~0); 4174#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4175#L1248-1 assume !(1 == ~T8_E~0); 4221#L1253-1 assume !(1 == ~T9_E~0); 4222#L1258-1 assume !(1 == ~T10_E~0); 4197#L1263-1 assume !(1 == ~T11_E~0); 4198#L1268-1 assume !(1 == ~E_1~0); 4018#L1273-1 assume !(1 == ~E_2~0); 4019#L1278-1 assume !(1 == ~E_3~0); 3589#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3590#L1288-1 assume !(1 == ~E_5~0); 4320#L1293-1 assume !(1 == ~E_6~0); 4280#L1298-1 assume !(1 == ~E_7~0); 4051#L1303-1 assume !(1 == ~E_8~0); 3599#L1308-1 assume !(1 == ~E_9~0); 3491#L1313-1 assume !(1 == ~E_10~0); 3492#L1318-1 assume !(1 == ~E_11~0); 3502#L1323-1 assume { :end_inline_reset_delta_events } true; 3503#L1644-2 [2023-11-19 07:37:53,509 INFO L750 eck$LassoCheckResult]: Loop: 3503#L1644-2 assume !false; 4113#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3407#L1065-1 assume !false; 3408#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4455#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3138#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3715#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3604#L906 assume !(0 != eval_~tmp~0#1); 3606#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3926#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3927#L1090-3 assume !(0 == ~M_E~0); 4335#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4392#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4357#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4358#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3380#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3381#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3657#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3658#L1125-3 assume !(0 == ~T8_E~0); 4173#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4430#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3581#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3090#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3091#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3214#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3215#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3562#L1165-3 assume !(0 == ~E_5~0); 3563#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3962#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3476#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3240#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3241#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4418#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4419#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3797#L525-36 assume !(1 == ~m_pc~0); 3798#L525-38 is_master_triggered_~__retres1~0#1 := 0; 3338#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3339#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3614#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3615#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3525#L544-36 assume 1 == ~t1_pc~0; 3526#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4085#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4086#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4423#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4405#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4310#L563-36 assume !(1 == ~t2_pc~0); 3328#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 3086#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3087#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4291#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3813#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3814#L582-36 assume !(1 == ~t3_pc~0); 3648#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3647#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3745#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3746#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3851#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3791#L601-36 assume 1 == ~t4_pc~0; 3677#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3678#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3943#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3944#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4396#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4297#L620-36 assume 1 == ~t5_pc~0; 3728#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3729#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4158#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3704#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 3347#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3134#L639-36 assume !(1 == ~t6_pc~0); 3136#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 3172#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3173#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3397#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3398#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4003#L658-36 assume !(1 == ~t7_pc~0); 3147#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 3148#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4382#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3125#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3126#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4147#L677-36 assume 1 == ~t8_pc~0; 4324#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3919#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4048#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4049#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3945#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3946#L696-36 assume 1 == ~t9_pc~0; 3837#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3838#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3779#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3780#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3963#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3964#L715-36 assume !(1 == ~t10_pc~0); 3925#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3021#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3022#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2999#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3000#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3390#L734-36 assume !(1 == ~t11_pc~0); 3100#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 3101#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3406#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3015#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3016#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4027#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3663#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3664#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3438#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3439#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3618#L1233-3 assume !(1 == ~T5_E~0); 3619#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3888#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3889#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4395#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4397#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3420#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3421#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4370#L1273-3 assume !(1 == ~E_2~0); 4385#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4387#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3766#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3767#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3612#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3613#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4109#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3609#L1313-3 assume !(1 == ~E_10~0); 3610#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 3422#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3423#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3365#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3591#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3592#L1663 assume !(0 == start_simulation_~tmp~3#1); 3263#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4001#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3209#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3092#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 3093#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3158#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3481#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3947#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 3503#L1644-2 [2023-11-19 07:37:53,510 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:53,511 INFO L85 PathProgramCache]: Analyzing trace with hash -92888918, now seen corresponding path program 2 times [2023-11-19 07:37:53,511 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:53,511 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [40712094] [2023-11-19 07:37:53,511 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:53,512 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:53,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:53,633 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:53,634 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:53,634 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [40712094] [2023-11-19 07:37:53,634 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [40712094] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:53,634 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:53,635 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:53,635 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [970695954] [2023-11-19 07:37:53,635 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:53,636 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:37:53,636 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:53,637 INFO L85 PathProgramCache]: Analyzing trace with hash -825746646, now seen corresponding path program 1 times [2023-11-19 07:37:53,637 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:53,637 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1753999692] [2023-11-19 07:37:53,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:53,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:53,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:53,841 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:53,842 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:53,842 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1753999692] [2023-11-19 07:37:53,842 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1753999692] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:53,846 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:53,847 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:53,847 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1762046016] [2023-11-19 07:37:53,847 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:53,848 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:37:53,848 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:53,849 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:37:53,849 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:37:53,849 INFO L87 Difference]: Start difference. First operand 1488 states and 2205 transitions. cyclomatic complexity: 718 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:53,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:53,908 INFO L93 Difference]: Finished difference Result 1488 states and 2204 transitions. [2023-11-19 07:37:53,908 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2204 transitions. [2023-11-19 07:37:53,921 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:53,934 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2204 transitions. [2023-11-19 07:37:53,934 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-19 07:37:53,937 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-19 07:37:53,937 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2204 transitions. [2023-11-19 07:37:53,939 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:53,940 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2204 transitions. [2023-11-19 07:37:53,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2204 transitions. [2023-11-19 07:37:53,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-19 07:37:53,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4811827956989247) internal successors, (2204), 1487 states have internal predecessors, (2204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:53,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2204 transitions. [2023-11-19 07:37:53,978 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2204 transitions. [2023-11-19 07:37:53,980 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:37:53,981 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2204 transitions. [2023-11-19 07:37:53,981 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-19 07:37:53,981 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2204 transitions. [2023-11-19 07:37:53,990 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:53,991 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:53,991 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:54,001 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:54,007 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:54,008 INFO L748 eck$LassoCheckResult]: Stem: 6424#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 6425#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 7406#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7407#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6874#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 6875#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6746#L766-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 6639#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6368#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6016#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6017#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6061#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6062#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7004#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7005#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7049#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 6465#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6466#L1090 assume !(0 == ~M_E~0); 6508#L1090-2 assume !(0 == ~T1_E~0); 6509#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7196#L1100-1 assume !(0 == ~T3_E~0); 7197#L1105-1 assume !(0 == ~T4_E~0); 6288#L1110-1 assume !(0 == ~T5_E~0); 6289#L1115-1 assume !(0 == ~T6_E~0); 6675#L1120-1 assume !(0 == ~T7_E~0); 6983#L1125-1 assume !(0 == ~T8_E~0); 7455#L1130-1 assume !(0 == ~T9_E~0); 7218#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6470#L1140-1 assume !(0 == ~T11_E~0); 6471#L1145-1 assume !(0 == ~E_1~0); 7152#L1150-1 assume !(0 == ~E_2~0); 6652#L1155-1 assume !(0 == ~E_3~0); 6653#L1160-1 assume !(0 == ~E_4~0); 6751#L1165-1 assume !(0 == ~E_5~0); 6752#L1170-1 assume !(0 == ~E_6~0); 7390#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 6832#L1180-1 assume !(0 == ~E_8~0); 6833#L1185-1 assume !(0 == ~E_9~0); 6467#L1190-1 assume !(0 == ~E_10~0); 6468#L1195-1 assume !(0 == ~E_11~0); 6848#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6667#L525 assume !(1 == ~m_pc~0); 6106#L525-2 is_master_triggered_~__retres1~0#1 := 0; 6107#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7292#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7265#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6457#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6458#L544 assume 1 == ~t1_pc~0; 6727#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6674#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6080#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6081#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 6312#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6952#L563 assume !(1 == ~t2_pc~0); 7138#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6125#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6126#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6536#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 6537#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7030#L582 assume 1 == ~t3_pc~0; 6256#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6257#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6008#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6009#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 6194#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6195#L601 assume !(1 == ~t4_pc~0); 7164#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6676#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6204#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6205#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 7159#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7431#L620 assume 1 == ~t5_pc~0; 6153#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6154#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7046#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7297#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 7440#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7441#L639 assume !(1 == ~t6_pc~0); 6981#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6574#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6575#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6625#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 6682#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6683#L658 assume 1 == ~t7_pc~0; 6982#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6898#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7446#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7098#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 6460#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6461#L677 assume 1 == ~t8_pc~0; 6688#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6271#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6272#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6532#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 6533#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7259#L696 assume !(1 == ~t9_pc~0); 6964#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 6965#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6737#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6738#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6988#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7201#L715 assume 1 == ~t10_pc~0; 7208#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7080#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6886#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6887#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 6826#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6265#L734 assume !(1 == ~t11_pc~0); 6266#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 6753#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6835#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6004#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 6005#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7047#L1213 assume !(1 == ~M_E~0); 6823#L1213-2 assume !(1 == ~T1_E~0); 6824#L1218-1 assume !(1 == ~T2_E~0); 6039#L1223-1 assume !(1 == ~T3_E~0); 6040#L1228-1 assume !(1 == ~T4_E~0); 6799#L1233-1 assume !(1 == ~T5_E~0); 7442#L1238-1 assume !(1 == ~T6_E~0); 7157#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7158#L1248-1 assume !(1 == ~T8_E~0); 7204#L1253-1 assume !(1 == ~T9_E~0); 7205#L1258-1 assume !(1 == ~T10_E~0); 7180#L1263-1 assume !(1 == ~T11_E~0); 7181#L1268-1 assume !(1 == ~E_1~0); 7001#L1273-1 assume !(1 == ~E_2~0); 7002#L1278-1 assume !(1 == ~E_3~0); 6572#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6573#L1288-1 assume !(1 == ~E_5~0); 7303#L1293-1 assume !(1 == ~E_6~0); 7263#L1298-1 assume !(1 == ~E_7~0); 7034#L1303-1 assume !(1 == ~E_8~0); 6582#L1308-1 assume !(1 == ~E_9~0); 6474#L1313-1 assume !(1 == ~E_10~0); 6475#L1318-1 assume !(1 == ~E_11~0); 6482#L1323-1 assume { :end_inline_reset_delta_events } true; 6483#L1644-2 [2023-11-19 07:37:54,010 INFO L750 eck$LassoCheckResult]: Loop: 6483#L1644-2 assume !false; 7096#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6389#L1065-1 assume !false; 6390#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7438#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6121#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6698#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6587#L906 assume !(0 != eval_~tmp~0#1); 6589#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6908#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6909#L1090-3 assume !(0 == ~M_E~0); 7318#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7375#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7340#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7341#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6363#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6364#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6640#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6641#L1125-3 assume !(0 == ~T8_E~0); 7156#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7413#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6562#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 6071#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6072#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6196#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6197#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6545#L1165-3 assume !(0 == ~E_5~0); 6546#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6945#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6459#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6220#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6221#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 7401#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7402#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6780#L525-36 assume !(1 == ~m_pc~0); 6781#L525-38 is_master_triggered_~__retres1~0#1 := 0; 6321#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6322#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6597#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6598#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6511#L544-36 assume 1 == ~t1_pc~0; 6512#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7068#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7069#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7408#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7388#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7293#L563-36 assume 1 == ~t2_pc~0; 6310#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6069#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6070#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7274#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6796#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6797#L582-36 assume 1 == ~t3_pc~0; 6629#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6630#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6728#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6729#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6834#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6774#L601-36 assume 1 == ~t4_pc~0; 6660#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6661#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6926#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6927#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7379#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7280#L620-36 assume 1 == ~t5_pc~0; 6713#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6714#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7141#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6687#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 6330#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6117#L639-36 assume 1 == ~t6_pc~0; 6118#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6158#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6159#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6380#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6381#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6986#L658-36 assume !(1 == ~t7_pc~0); 6130#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 6131#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7365#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6108#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6109#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7130#L677-36 assume !(1 == ~t8_pc~0); 6901#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 6902#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7031#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7032#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6928#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6929#L696-36 assume 1 == ~t9_pc~0; 6820#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6821#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6762#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6763#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6946#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6947#L715-36 assume 1 == ~t10_pc~0; 7091#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 6006#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6007#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5982#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5983#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6373#L734-36 assume !(1 == ~t11_pc~0); 6085#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 6086#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6391#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5998#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 5999#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7010#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6648#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6649#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6421#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6422#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6601#L1233-3 assume !(1 == ~T5_E~0); 6602#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6871#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6872#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7378#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7380#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6404#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 6405#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7353#L1273-3 assume !(1 == ~E_2~0); 7368#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7370#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6749#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6750#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6595#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6596#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7092#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6592#L1313-3 assume !(1 == ~E_10~0); 6593#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 6406#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6407#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6348#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6576#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 6577#L1663 assume !(0 == start_simulation_~tmp~3#1); 6246#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6984#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6192#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6078#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 6079#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6141#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6464#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 6930#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 6483#L1644-2 [2023-11-19 07:37:54,011 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:54,015 INFO L85 PathProgramCache]: Analyzing trace with hash -456355416, now seen corresponding path program 1 times [2023-11-19 07:37:54,016 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:54,016 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1207018550] [2023-11-19 07:37:54,016 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:54,016 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:54,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:54,107 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:54,110 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:54,111 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1207018550] [2023-11-19 07:37:54,111 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1207018550] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:54,112 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:54,112 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:54,112 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1001831231] [2023-11-19 07:37:54,112 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:54,113 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:37:54,113 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:54,114 INFO L85 PathProgramCache]: Analyzing trace with hash 297167501, now seen corresponding path program 1 times [2023-11-19 07:37:54,115 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:54,115 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1515242210] [2023-11-19 07:37:54,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:54,116 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:54,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:54,242 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:54,242 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:54,243 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1515242210] [2023-11-19 07:37:54,243 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1515242210] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:54,244 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:54,244 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:54,244 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [37166498] [2023-11-19 07:37:54,244 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:54,245 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:37:54,245 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:54,245 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:37:54,245 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:37:54,246 INFO L87 Difference]: Start difference. First operand 1488 states and 2204 transitions. cyclomatic complexity: 717 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:54,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:54,282 INFO L93 Difference]: Finished difference Result 1488 states and 2203 transitions. [2023-11-19 07:37:54,282 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2203 transitions. [2023-11-19 07:37:54,293 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:54,304 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2203 transitions. [2023-11-19 07:37:54,305 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-19 07:37:54,307 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-19 07:37:54,308 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2203 transitions. [2023-11-19 07:37:54,310 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:54,310 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2203 transitions. [2023-11-19 07:37:54,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2203 transitions. [2023-11-19 07:37:54,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-19 07:37:54,340 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.480510752688172) internal successors, (2203), 1487 states have internal predecessors, (2203), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:54,346 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2203 transitions. [2023-11-19 07:37:54,346 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2203 transitions. [2023-11-19 07:37:54,347 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:37:54,348 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2203 transitions. [2023-11-19 07:37:54,349 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-19 07:37:54,349 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2203 transitions. [2023-11-19 07:37:54,358 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:54,358 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:54,358 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:54,361 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:54,362 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:54,362 INFO L748 eck$LassoCheckResult]: Stem: 9407#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 9408#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 10389#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10390#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9857#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 9858#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9729#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9622#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9351#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8999#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9000#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9044#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9045#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9987#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9988#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10032#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9448#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9449#L1090 assume !(0 == ~M_E~0); 9491#L1090-2 assume !(0 == ~T1_E~0); 9492#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10180#L1100-1 assume !(0 == ~T3_E~0); 10181#L1105-1 assume !(0 == ~T4_E~0); 9272#L1110-1 assume !(0 == ~T5_E~0); 9273#L1115-1 assume !(0 == ~T6_E~0); 9658#L1120-1 assume !(0 == ~T7_E~0); 9966#L1125-1 assume !(0 == ~T8_E~0); 10438#L1130-1 assume !(0 == ~T9_E~0); 10201#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9453#L1140-1 assume !(0 == ~T11_E~0); 9454#L1145-1 assume !(0 == ~E_1~0); 10135#L1150-1 assume !(0 == ~E_2~0); 9635#L1155-1 assume !(0 == ~E_3~0); 9636#L1160-1 assume !(0 == ~E_4~0); 9734#L1165-1 assume !(0 == ~E_5~0); 9735#L1170-1 assume !(0 == ~E_6~0); 10373#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 9815#L1180-1 assume !(0 == ~E_8~0); 9816#L1185-1 assume !(0 == ~E_9~0); 9450#L1190-1 assume !(0 == ~E_10~0); 9451#L1195-1 assume !(0 == ~E_11~0); 9831#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9655#L525 assume !(1 == ~m_pc~0); 9089#L525-2 is_master_triggered_~__retres1~0#1 := 0; 9090#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10275#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10250#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9440#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9441#L544 assume 1 == ~t1_pc~0; 9710#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9657#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9068#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9069#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 9295#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9935#L563 assume !(1 == ~t2_pc~0); 10121#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9108#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9109#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9519#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 9520#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10013#L582 assume 1 == ~t3_pc~0; 9241#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9242#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8991#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8992#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 9177#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9178#L601 assume !(1 == ~t4_pc~0); 10147#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9659#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9191#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9192#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 10142#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10414#L620 assume 1 == ~t5_pc~0; 9140#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9141#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10029#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10281#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 10423#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10424#L639 assume !(1 == ~t6_pc~0); 9964#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9559#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9560#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9608#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 9665#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9666#L658 assume 1 == ~t7_pc~0; 9965#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9882#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10429#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10082#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 9443#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9444#L677 assume 1 == ~t8_pc~0; 9673#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9254#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9255#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9515#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 9516#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10242#L696 assume !(1 == ~t9_pc~0); 9949#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 9950#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9720#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9721#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9971#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10184#L715 assume 1 == ~t10_pc~0; 10191#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10063#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9869#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9870#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 9809#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9248#L734 assume !(1 == ~t11_pc~0); 9249#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 9736#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9818#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8989#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 8990#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10030#L1213 assume !(1 == ~M_E~0); 9807#L1213-2 assume !(1 == ~T1_E~0); 9808#L1218-1 assume !(1 == ~T2_E~0); 9022#L1223-1 assume !(1 == ~T3_E~0); 9023#L1228-1 assume !(1 == ~T4_E~0); 9782#L1233-1 assume !(1 == ~T5_E~0); 10425#L1238-1 assume !(1 == ~T6_E~0); 10140#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10141#L1248-1 assume !(1 == ~T8_E~0); 10187#L1253-1 assume !(1 == ~T9_E~0); 10188#L1258-1 assume !(1 == ~T10_E~0); 10163#L1263-1 assume !(1 == ~T11_E~0); 10164#L1268-1 assume !(1 == ~E_1~0); 9984#L1273-1 assume !(1 == ~E_2~0); 9985#L1278-1 assume !(1 == ~E_3~0); 9555#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 9556#L1288-1 assume !(1 == ~E_5~0); 10286#L1293-1 assume !(1 == ~E_6~0); 10246#L1298-1 assume !(1 == ~E_7~0); 10017#L1303-1 assume !(1 == ~E_8~0); 9565#L1308-1 assume !(1 == ~E_9~0); 9457#L1313-1 assume !(1 == ~E_10~0); 9458#L1318-1 assume !(1 == ~E_11~0); 9468#L1323-1 assume { :end_inline_reset_delta_events } true; 9469#L1644-2 [2023-11-19 07:37:54,363 INFO L750 eck$LassoCheckResult]: Loop: 9469#L1644-2 assume !false; 10079#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9373#L1065-1 assume !false; 9374#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10421#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9104#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9681#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9570#L906 assume !(0 != eval_~tmp~0#1); 9572#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9892#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9893#L1090-3 assume !(0 == ~M_E~0); 10301#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10358#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10323#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10324#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9346#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9347#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9623#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9624#L1125-3 assume !(0 == ~T8_E~0); 10139#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10396#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9547#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9056#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9057#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9180#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9181#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9528#L1165-3 assume !(0 == ~E_5~0); 9529#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9928#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9442#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9204#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9205#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 10384#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10385#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9763#L525-36 assume !(1 == ~m_pc~0); 9764#L525-38 is_master_triggered_~__retres1~0#1 := 0; 9309#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9310#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9580#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9581#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9494#L544-36 assume 1 == ~t1_pc~0; 9495#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10051#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10052#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10391#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10372#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10276#L563-36 assume 1 == ~t2_pc~0; 9293#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9049#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9050#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10257#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9779#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9780#L582-36 assume 1 == ~t3_pc~0; 9612#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9613#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9711#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9712#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9817#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9754#L601-36 assume 1 == ~t4_pc~0; 9643#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9644#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9909#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9910#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10362#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10263#L620-36 assume !(1 == ~t5_pc~0); 9696#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 9695#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10124#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9670#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 9313#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9100#L639-36 assume 1 == ~t6_pc~0; 9101#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9138#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9139#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9363#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9364#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9969#L658-36 assume !(1 == ~t7_pc~0); 9113#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 9114#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10348#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9091#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9092#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10113#L677-36 assume 1 == ~t8_pc~0; 10290#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9885#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10014#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10015#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9911#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9912#L696-36 assume 1 == ~t9_pc~0; 9803#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9804#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9745#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9746#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9929#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9930#L715-36 assume !(1 == ~t10_pc~0); 9891#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 8987#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8988#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8965#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8966#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9356#L734-36 assume !(1 == ~t11_pc~0); 9066#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 9067#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9372#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8981#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8982#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9993#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9629#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9630#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9404#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9405#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9584#L1233-3 assume !(1 == ~T5_E~0); 9585#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9854#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9855#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10361#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10363#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9386#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9387#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10336#L1273-3 assume !(1 == ~E_2~0); 10351#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10353#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9732#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9733#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9578#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9579#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10075#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9575#L1313-3 assume !(1 == ~E_10~0); 9576#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 9388#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9389#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9331#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9557#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 9558#L1663 assume !(0 == start_simulation_~tmp~3#1); 9224#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9967#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9175#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9058#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 9059#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9124#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9447#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 9913#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 9469#L1644-2 [2023-11-19 07:37:54,365 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:54,365 INFO L85 PathProgramCache]: Analyzing trace with hash 88517158, now seen corresponding path program 1 times [2023-11-19 07:37:54,366 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:54,366 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1850562969] [2023-11-19 07:37:54,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:54,366 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:54,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:54,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:54,442 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:54,442 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1850562969] [2023-11-19 07:37:54,443 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1850562969] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:54,443 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:54,443 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:54,443 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1062428156] [2023-11-19 07:37:54,443 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:54,444 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:37:54,444 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:54,445 INFO L85 PathProgramCache]: Analyzing trace with hash -1935633556, now seen corresponding path program 1 times [2023-11-19 07:37:54,445 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:54,445 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1990738585] [2023-11-19 07:37:54,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:54,446 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:54,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:54,520 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:54,520 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:54,520 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1990738585] [2023-11-19 07:37:54,521 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1990738585] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:54,521 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:54,521 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:54,521 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2105300648] [2023-11-19 07:37:54,521 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:54,522 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:37:54,522 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:54,522 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:37:54,523 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:37:54,523 INFO L87 Difference]: Start difference. First operand 1488 states and 2203 transitions. cyclomatic complexity: 716 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:54,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:54,559 INFO L93 Difference]: Finished difference Result 1488 states and 2202 transitions. [2023-11-19 07:37:54,560 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2202 transitions. [2023-11-19 07:37:54,570 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:54,581 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2202 transitions. [2023-11-19 07:37:54,582 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-19 07:37:54,583 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-19 07:37:54,583 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2202 transitions. [2023-11-19 07:37:54,586 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:54,586 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2202 transitions. [2023-11-19 07:37:54,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2202 transitions. [2023-11-19 07:37:54,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-19 07:37:54,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4798387096774193) internal successors, (2202), 1487 states have internal predecessors, (2202), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:54,621 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2202 transitions. [2023-11-19 07:37:54,621 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2202 transitions. [2023-11-19 07:37:54,622 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:37:54,623 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2202 transitions. [2023-11-19 07:37:54,623 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-19 07:37:54,623 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2202 transitions. [2023-11-19 07:37:54,631 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:54,632 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:54,632 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:54,666 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:54,666 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:54,667 INFO L748 eck$LassoCheckResult]: Stem: 12390#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 12391#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 13372#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13373#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12840#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 12841#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12712#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12605#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12334#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 11982#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11983#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12027#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12028#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12970#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12971#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13015#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12431#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12432#L1090 assume !(0 == ~M_E~0); 12474#L1090-2 assume !(0 == ~T1_E~0); 12475#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13162#L1100-1 assume !(0 == ~T3_E~0); 13163#L1105-1 assume !(0 == ~T4_E~0); 12254#L1110-1 assume !(0 == ~T5_E~0); 12255#L1115-1 assume !(0 == ~T6_E~0); 12641#L1120-1 assume !(0 == ~T7_E~0); 12949#L1125-1 assume !(0 == ~T8_E~0); 13421#L1130-1 assume !(0 == ~T9_E~0); 13184#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12436#L1140-1 assume !(0 == ~T11_E~0); 12437#L1145-1 assume !(0 == ~E_1~0); 13118#L1150-1 assume !(0 == ~E_2~0); 12618#L1155-1 assume !(0 == ~E_3~0); 12619#L1160-1 assume !(0 == ~E_4~0); 12717#L1165-1 assume !(0 == ~E_5~0); 12718#L1170-1 assume !(0 == ~E_6~0); 13356#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 12798#L1180-1 assume !(0 == ~E_8~0); 12799#L1185-1 assume !(0 == ~E_9~0); 12433#L1190-1 assume !(0 == ~E_10~0); 12434#L1195-1 assume !(0 == ~E_11~0); 12814#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12633#L525 assume !(1 == ~m_pc~0); 12072#L525-2 is_master_triggered_~__retres1~0#1 := 0; 12073#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13258#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13231#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12423#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12424#L544 assume 1 == ~t1_pc~0; 12693#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12640#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12046#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12047#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 12278#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12918#L563 assume !(1 == ~t2_pc~0); 13104#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12091#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12092#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12502#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 12503#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12996#L582 assume 1 == ~t3_pc~0; 12222#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12223#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11974#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11975#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 12160#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12161#L601 assume !(1 == ~t4_pc~0); 13130#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12642#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12170#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12171#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 13125#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13397#L620 assume 1 == ~t5_pc~0; 12119#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12120#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13012#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13263#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 13406#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13407#L639 assume !(1 == ~t6_pc~0); 12947#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12540#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12541#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12591#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 12648#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12649#L658 assume 1 == ~t7_pc~0; 12948#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12864#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13412#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13064#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 12426#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12427#L677 assume 1 == ~t8_pc~0; 12654#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12237#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12238#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12498#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 12499#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13225#L696 assume !(1 == ~t9_pc~0); 12930#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 12931#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12703#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12704#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12954#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13167#L715 assume 1 == ~t10_pc~0; 13174#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13046#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12852#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12853#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 12792#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12231#L734 assume !(1 == ~t11_pc~0); 12232#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 12719#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12801#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11970#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 11971#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13013#L1213 assume !(1 == ~M_E~0); 12789#L1213-2 assume !(1 == ~T1_E~0); 12790#L1218-1 assume !(1 == ~T2_E~0); 12005#L1223-1 assume !(1 == ~T3_E~0); 12006#L1228-1 assume !(1 == ~T4_E~0); 12765#L1233-1 assume !(1 == ~T5_E~0); 13408#L1238-1 assume !(1 == ~T6_E~0); 13123#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13124#L1248-1 assume !(1 == ~T8_E~0); 13170#L1253-1 assume !(1 == ~T9_E~0); 13171#L1258-1 assume !(1 == ~T10_E~0); 13146#L1263-1 assume !(1 == ~T11_E~0); 13147#L1268-1 assume !(1 == ~E_1~0); 12967#L1273-1 assume !(1 == ~E_2~0); 12968#L1278-1 assume !(1 == ~E_3~0); 12538#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 12539#L1288-1 assume !(1 == ~E_5~0); 13269#L1293-1 assume !(1 == ~E_6~0); 13229#L1298-1 assume !(1 == ~E_7~0); 13000#L1303-1 assume !(1 == ~E_8~0); 12548#L1308-1 assume !(1 == ~E_9~0); 12440#L1313-1 assume !(1 == ~E_10~0); 12441#L1318-1 assume !(1 == ~E_11~0); 12448#L1323-1 assume { :end_inline_reset_delta_events } true; 12449#L1644-2 [2023-11-19 07:37:54,667 INFO L750 eck$LassoCheckResult]: Loop: 12449#L1644-2 assume !false; 13062#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12355#L1065-1 assume !false; 12356#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13404#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12087#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12664#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12553#L906 assume !(0 != eval_~tmp~0#1); 12555#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12874#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12875#L1090-3 assume !(0 == ~M_E~0); 13284#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13341#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13306#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13307#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12329#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12330#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12606#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12607#L1125-3 assume !(0 == ~T8_E~0); 13122#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13379#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12528#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12037#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12038#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12162#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12163#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12511#L1165-3 assume !(0 == ~E_5~0); 12512#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12911#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12425#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12186#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12187#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 13367#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 13368#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12746#L525-36 assume !(1 == ~m_pc~0); 12747#L525-38 is_master_triggered_~__retres1~0#1 := 0; 12287#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12288#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12563#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12564#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12477#L544-36 assume 1 == ~t1_pc~0; 12478#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13034#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13035#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13374#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13354#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13259#L563-36 assume 1 == ~t2_pc~0; 12276#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12035#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12036#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13240#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12762#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12763#L582-36 assume 1 == ~t3_pc~0; 12595#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12596#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12694#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12695#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12800#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12740#L601-36 assume 1 == ~t4_pc~0; 12626#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12627#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12892#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12893#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13345#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13246#L620-36 assume 1 == ~t5_pc~0; 12679#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12680#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13107#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12653#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 12296#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12083#L639-36 assume 1 == ~t6_pc~0; 12084#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12124#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12125#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12346#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12347#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12952#L658-36 assume !(1 == ~t7_pc~0); 12096#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 12097#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13331#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12074#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12075#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13096#L677-36 assume !(1 == ~t8_pc~0); 12867#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 12868#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12997#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12998#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12894#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12895#L696-36 assume 1 == ~t9_pc~0; 12786#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12787#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12728#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12729#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12912#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12913#L715-36 assume 1 == ~t10_pc~0; 13057#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11972#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11973#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11948#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11949#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12339#L734-36 assume !(1 == ~t11_pc~0); 12051#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 12052#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12357#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11964#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11965#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12976#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12614#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12615#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12387#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12388#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12567#L1233-3 assume !(1 == ~T5_E~0); 12568#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12837#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12838#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13344#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13346#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12370#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12371#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13319#L1273-3 assume !(1 == ~E_2~0); 13334#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13336#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12715#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12716#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12561#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12562#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13058#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12558#L1313-3 assume !(1 == ~E_10~0); 12559#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12372#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12373#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12314#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12542#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 12543#L1663 assume !(0 == start_simulation_~tmp~3#1); 12212#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12950#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12158#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12044#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 12045#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12107#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12430#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 12896#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 12449#L1644-2 [2023-11-19 07:37:54,672 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:54,672 INFO L85 PathProgramCache]: Analyzing trace with hash -586642968, now seen corresponding path program 1 times [2023-11-19 07:37:54,672 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:54,673 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [573478753] [2023-11-19 07:37:54,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:54,673 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:54,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:54,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:54,746 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:54,747 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [573478753] [2023-11-19 07:37:54,747 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [573478753] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:54,747 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:54,747 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:54,748 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1778434264] [2023-11-19 07:37:54,748 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:54,748 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:37:54,749 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:54,749 INFO L85 PathProgramCache]: Analyzing trace with hash 297167501, now seen corresponding path program 2 times [2023-11-19 07:37:54,750 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:54,750 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [664974089] [2023-11-19 07:37:54,750 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:54,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:54,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:54,827 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:54,827 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:54,828 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [664974089] [2023-11-19 07:37:54,828 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [664974089] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:54,828 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:54,828 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:54,829 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1654601872] [2023-11-19 07:37:54,829 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:54,829 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:37:54,829 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:54,830 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:37:54,830 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:37:54,830 INFO L87 Difference]: Start difference. First operand 1488 states and 2202 transitions. cyclomatic complexity: 715 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:54,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:54,872 INFO L93 Difference]: Finished difference Result 1488 states and 2201 transitions. [2023-11-19 07:37:54,872 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2201 transitions. [2023-11-19 07:37:54,883 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:54,895 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2201 transitions. [2023-11-19 07:37:54,895 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-19 07:37:54,897 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-19 07:37:54,897 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2201 transitions. [2023-11-19 07:37:54,900 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:54,900 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2201 transitions. [2023-11-19 07:37:54,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2201 transitions. [2023-11-19 07:37:54,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-19 07:37:54,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4791666666666667) internal successors, (2201), 1487 states have internal predecessors, (2201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:54,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2201 transitions. [2023-11-19 07:37:54,936 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2201 transitions. [2023-11-19 07:37:54,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:37:54,939 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2201 transitions. [2023-11-19 07:37:54,939 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-19 07:37:54,939 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2201 transitions. [2023-11-19 07:37:54,948 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:54,948 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:54,948 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:54,951 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:54,951 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:54,951 INFO L748 eck$LassoCheckResult]: Stem: 15373#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 15374#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 16355#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16356#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15823#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 15824#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15695#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15588#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15317#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14965#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 14966#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 15010#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15011#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15953#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15954#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15998#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 15414#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15415#L1090 assume !(0 == ~M_E~0); 15457#L1090-2 assume !(0 == ~T1_E~0); 15458#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16146#L1100-1 assume !(0 == ~T3_E~0); 16147#L1105-1 assume !(0 == ~T4_E~0); 15238#L1110-1 assume !(0 == ~T5_E~0); 15239#L1115-1 assume !(0 == ~T6_E~0); 15624#L1120-1 assume !(0 == ~T7_E~0); 15932#L1125-1 assume !(0 == ~T8_E~0); 16404#L1130-1 assume !(0 == ~T9_E~0); 16167#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15419#L1140-1 assume !(0 == ~T11_E~0); 15420#L1145-1 assume !(0 == ~E_1~0); 16101#L1150-1 assume !(0 == ~E_2~0); 15601#L1155-1 assume !(0 == ~E_3~0); 15602#L1160-1 assume !(0 == ~E_4~0); 15700#L1165-1 assume !(0 == ~E_5~0); 15701#L1170-1 assume !(0 == ~E_6~0); 16339#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 15781#L1180-1 assume !(0 == ~E_8~0); 15782#L1185-1 assume !(0 == ~E_9~0); 15416#L1190-1 assume !(0 == ~E_10~0); 15417#L1195-1 assume !(0 == ~E_11~0); 15797#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15621#L525 assume !(1 == ~m_pc~0); 15055#L525-2 is_master_triggered_~__retres1~0#1 := 0; 15056#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16241#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16216#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15406#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15407#L544 assume 1 == ~t1_pc~0; 15676#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15623#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15034#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15035#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 15261#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15901#L563 assume !(1 == ~t2_pc~0); 16087#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15074#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15075#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15485#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 15486#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15979#L582 assume 1 == ~t3_pc~0; 15207#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15208#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14957#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14958#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 15143#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15144#L601 assume !(1 == ~t4_pc~0); 16113#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15625#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15157#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15158#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 16108#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16380#L620 assume 1 == ~t5_pc~0; 15104#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15105#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15995#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16247#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 16389#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16390#L639 assume !(1 == ~t6_pc~0); 15930#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 15525#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15526#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15574#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 15631#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15632#L658 assume 1 == ~t7_pc~0; 15931#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15848#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16395#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16047#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 15409#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15410#L677 assume 1 == ~t8_pc~0; 15639#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15220#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15221#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15481#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 15482#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16208#L696 assume !(1 == ~t9_pc~0); 15915#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 15916#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15686#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15687#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15937#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16150#L715 assume 1 == ~t10_pc~0; 16157#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16029#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15835#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15836#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 15775#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15214#L734 assume !(1 == ~t11_pc~0); 15215#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 15702#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15784#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14955#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 14956#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15996#L1213 assume !(1 == ~M_E~0); 15773#L1213-2 assume !(1 == ~T1_E~0); 15774#L1218-1 assume !(1 == ~T2_E~0); 14988#L1223-1 assume !(1 == ~T3_E~0); 14989#L1228-1 assume !(1 == ~T4_E~0); 15748#L1233-1 assume !(1 == ~T5_E~0); 16391#L1238-1 assume !(1 == ~T6_E~0); 16106#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16107#L1248-1 assume !(1 == ~T8_E~0); 16153#L1253-1 assume !(1 == ~T9_E~0); 16154#L1258-1 assume !(1 == ~T10_E~0); 16129#L1263-1 assume !(1 == ~T11_E~0); 16130#L1268-1 assume !(1 == ~E_1~0); 15950#L1273-1 assume !(1 == ~E_2~0); 15951#L1278-1 assume !(1 == ~E_3~0); 15521#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15522#L1288-1 assume !(1 == ~E_5~0); 16252#L1293-1 assume !(1 == ~E_6~0); 16212#L1298-1 assume !(1 == ~E_7~0); 15983#L1303-1 assume !(1 == ~E_8~0); 15531#L1308-1 assume !(1 == ~E_9~0); 15423#L1313-1 assume !(1 == ~E_10~0); 15424#L1318-1 assume !(1 == ~E_11~0); 15434#L1323-1 assume { :end_inline_reset_delta_events } true; 15435#L1644-2 [2023-11-19 07:37:54,952 INFO L750 eck$LassoCheckResult]: Loop: 15435#L1644-2 assume !false; 16045#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15339#L1065-1 assume !false; 15340#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16387#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15070#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15647#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15536#L906 assume !(0 != eval_~tmp~0#1); 15538#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15858#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15859#L1090-3 assume !(0 == ~M_E~0); 16267#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16324#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16289#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16290#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15312#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15313#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15589#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15590#L1125-3 assume !(0 == ~T8_E~0); 16105#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16362#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15513#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 15022#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15023#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15146#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15147#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15494#L1165-3 assume !(0 == ~E_5~0); 15495#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15894#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15408#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15170#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15171#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16350#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16351#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15729#L525-36 assume !(1 == ~m_pc~0); 15730#L525-38 is_master_triggered_~__retres1~0#1 := 0; 15275#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15276#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15546#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15547#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15460#L544-36 assume 1 == ~t1_pc~0; 15461#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16017#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16018#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16357#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16338#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16242#L563-36 assume 1 == ~t2_pc~0; 15259#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15018#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15019#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16223#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15745#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15746#L582-36 assume 1 == ~t3_pc~0; 15578#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15579#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15677#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15678#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15783#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15723#L601-36 assume 1 == ~t4_pc~0; 15609#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15610#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15875#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15876#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16328#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16227#L620-36 assume 1 == ~t5_pc~0; 15660#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15661#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16090#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15636#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 15279#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15063#L639-36 assume 1 == ~t6_pc~0; 15064#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15102#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15103#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15329#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15330#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15935#L658-36 assume !(1 == ~t7_pc~0); 15079#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 15080#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16314#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15057#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15058#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16079#L677-36 assume 1 == ~t8_pc~0; 16256#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15851#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15980#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15981#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15877#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15878#L696-36 assume 1 == ~t9_pc~0; 15769#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15770#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15711#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15712#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15895#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15896#L715-36 assume !(1 == ~t10_pc~0); 15857#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 14953#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14954#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14931#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14932#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15322#L734-36 assume !(1 == ~t11_pc~0); 15032#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 15033#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15338#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14947#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14948#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15959#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15595#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15596#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15370#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15371#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15550#L1233-3 assume !(1 == ~T5_E~0); 15551#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15820#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15821#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16327#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16329#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15352#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15353#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16302#L1273-3 assume !(1 == ~E_2~0); 16317#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16319#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15698#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15699#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15544#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15545#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16041#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15541#L1313-3 assume !(1 == ~E_10~0); 15542#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 15354#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15355#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15297#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15523#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 15524#L1663 assume !(0 == start_simulation_~tmp~3#1); 15190#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15933#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15141#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15024#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 15025#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15087#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15413#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 15879#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 15435#L1644-2 [2023-11-19 07:37:54,953 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:54,953 INFO L85 PathProgramCache]: Analyzing trace with hash 361408998, now seen corresponding path program 1 times [2023-11-19 07:37:54,953 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:54,954 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1781428880] [2023-11-19 07:37:54,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:54,954 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:54,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:55,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:55,010 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:55,010 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1781428880] [2023-11-19 07:37:55,010 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1781428880] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:55,010 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:55,011 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:55,011 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [668999036] [2023-11-19 07:37:55,011 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:55,011 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:37:55,012 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:55,012 INFO L85 PathProgramCache]: Analyzing trace with hash -658480883, now seen corresponding path program 1 times [2023-11-19 07:37:55,013 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:55,016 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1412410012] [2023-11-19 07:37:55,017 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:55,017 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:55,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:55,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:55,109 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:55,109 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1412410012] [2023-11-19 07:37:55,109 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1412410012] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:55,110 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:55,110 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:55,110 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [495538529] [2023-11-19 07:37:55,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:55,111 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:37:55,111 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:55,111 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:37:55,112 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:37:55,112 INFO L87 Difference]: Start difference. First operand 1488 states and 2201 transitions. cyclomatic complexity: 714 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:55,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:55,147 INFO L93 Difference]: Finished difference Result 1488 states and 2200 transitions. [2023-11-19 07:37:55,147 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2200 transitions. [2023-11-19 07:37:55,157 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:55,168 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2200 transitions. [2023-11-19 07:37:55,168 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-19 07:37:55,170 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-19 07:37:55,170 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2200 transitions. [2023-11-19 07:37:55,172 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:55,173 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2200 transitions. [2023-11-19 07:37:55,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2200 transitions. [2023-11-19 07:37:55,242 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-19 07:37:55,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.478494623655914) internal successors, (2200), 1487 states have internal predecessors, (2200), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:55,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2200 transitions. [2023-11-19 07:37:55,254 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2200 transitions. [2023-11-19 07:37:55,255 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:37:55,256 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2200 transitions. [2023-11-19 07:37:55,256 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-19 07:37:55,256 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2200 transitions. [2023-11-19 07:37:55,263 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:55,263 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:55,264 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:55,267 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:55,267 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:55,268 INFO L748 eck$LassoCheckResult]: Stem: 18356#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 18357#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 19338#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19339#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18806#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 18807#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18678#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18571#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18300#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17948#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17949#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17993#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17994#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 18936#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18937#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18981#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 18397#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18398#L1090 assume !(0 == ~M_E~0); 18440#L1090-2 assume !(0 == ~T1_E~0); 18441#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19128#L1100-1 assume !(0 == ~T3_E~0); 19129#L1105-1 assume !(0 == ~T4_E~0); 18220#L1110-1 assume !(0 == ~T5_E~0); 18221#L1115-1 assume !(0 == ~T6_E~0); 18607#L1120-1 assume !(0 == ~T7_E~0); 18915#L1125-1 assume !(0 == ~T8_E~0); 19387#L1130-1 assume !(0 == ~T9_E~0); 19150#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18402#L1140-1 assume !(0 == ~T11_E~0); 18403#L1145-1 assume !(0 == ~E_1~0); 19084#L1150-1 assume !(0 == ~E_2~0); 18584#L1155-1 assume !(0 == ~E_3~0); 18585#L1160-1 assume !(0 == ~E_4~0); 18683#L1165-1 assume !(0 == ~E_5~0); 18684#L1170-1 assume !(0 == ~E_6~0); 19322#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 18764#L1180-1 assume !(0 == ~E_8~0); 18765#L1185-1 assume !(0 == ~E_9~0); 18399#L1190-1 assume !(0 == ~E_10~0); 18400#L1195-1 assume !(0 == ~E_11~0); 18780#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18599#L525 assume !(1 == ~m_pc~0); 18038#L525-2 is_master_triggered_~__retres1~0#1 := 0; 18039#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19224#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19197#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18389#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18390#L544 assume 1 == ~t1_pc~0; 18659#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18606#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18012#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18013#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 18244#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18884#L563 assume !(1 == ~t2_pc~0); 19070#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18057#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18058#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18468#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 18469#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18962#L582 assume 1 == ~t3_pc~0; 18188#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18189#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17940#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17941#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 18126#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18127#L601 assume !(1 == ~t4_pc~0); 19096#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18608#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18136#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18137#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 19091#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19363#L620 assume 1 == ~t5_pc~0; 18085#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18086#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18978#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19229#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 19372#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19373#L639 assume !(1 == ~t6_pc~0); 18913#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 18506#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18507#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18557#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 18614#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18615#L658 assume 1 == ~t7_pc~0; 18914#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18830#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19378#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19030#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 18392#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18393#L677 assume 1 == ~t8_pc~0; 18620#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18203#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18204#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18464#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 18465#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19191#L696 assume !(1 == ~t9_pc~0); 18896#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 18897#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18669#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18670#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18920#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19133#L715 assume 1 == ~t10_pc~0; 19140#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19012#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18818#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18819#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 18758#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18197#L734 assume !(1 == ~t11_pc~0); 18198#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 18685#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18767#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17936#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 17937#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18979#L1213 assume !(1 == ~M_E~0); 18755#L1213-2 assume !(1 == ~T1_E~0); 18756#L1218-1 assume !(1 == ~T2_E~0); 17971#L1223-1 assume !(1 == ~T3_E~0); 17972#L1228-1 assume !(1 == ~T4_E~0); 18731#L1233-1 assume !(1 == ~T5_E~0); 19374#L1238-1 assume !(1 == ~T6_E~0); 19089#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19090#L1248-1 assume !(1 == ~T8_E~0); 19136#L1253-1 assume !(1 == ~T9_E~0); 19137#L1258-1 assume !(1 == ~T10_E~0); 19112#L1263-1 assume !(1 == ~T11_E~0); 19113#L1268-1 assume !(1 == ~E_1~0); 18933#L1273-1 assume !(1 == ~E_2~0); 18934#L1278-1 assume !(1 == ~E_3~0); 18504#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 18505#L1288-1 assume !(1 == ~E_5~0); 19235#L1293-1 assume !(1 == ~E_6~0); 19195#L1298-1 assume !(1 == ~E_7~0); 18966#L1303-1 assume !(1 == ~E_8~0); 18514#L1308-1 assume !(1 == ~E_9~0); 18406#L1313-1 assume !(1 == ~E_10~0); 18407#L1318-1 assume !(1 == ~E_11~0); 18414#L1323-1 assume { :end_inline_reset_delta_events } true; 18415#L1644-2 [2023-11-19 07:37:55,269 INFO L750 eck$LassoCheckResult]: Loop: 18415#L1644-2 assume !false; 19028#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18321#L1065-1 assume !false; 18322#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19370#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 18053#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 18630#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18519#L906 assume !(0 != eval_~tmp~0#1); 18521#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18840#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18841#L1090-3 assume !(0 == ~M_E~0); 19250#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19307#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19272#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19273#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18295#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18296#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18572#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18573#L1125-3 assume !(0 == ~T8_E~0); 19088#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19345#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18494#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 18003#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18004#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18128#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18129#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18477#L1165-3 assume !(0 == ~E_5~0); 18478#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18877#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18391#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18152#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18153#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19333#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 19334#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18712#L525-36 assume !(1 == ~m_pc~0); 18713#L525-38 is_master_triggered_~__retres1~0#1 := 0; 18253#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18254#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18529#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18530#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18443#L544-36 assume 1 == ~t1_pc~0; 18444#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19000#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19001#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19340#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19320#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19225#L563-36 assume 1 == ~t2_pc~0; 18242#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18001#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18002#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19206#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18728#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18729#L582-36 assume 1 == ~t3_pc~0; 18561#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18562#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18660#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18661#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18766#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18706#L601-36 assume 1 == ~t4_pc~0; 18592#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18593#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18858#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18859#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19311#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19212#L620-36 assume 1 == ~t5_pc~0; 18645#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18646#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19073#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18619#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 18262#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18049#L639-36 assume 1 == ~t6_pc~0; 18050#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18090#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18091#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18312#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18313#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18918#L658-36 assume 1 == ~t7_pc~0; 18162#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18063#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19297#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18040#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18041#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19062#L677-36 assume !(1 == ~t8_pc~0); 18833#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 18834#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18963#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18964#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18860#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18861#L696-36 assume 1 == ~t9_pc~0; 18752#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18753#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18694#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18695#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18878#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18879#L715-36 assume !(1 == ~t10_pc~0); 18842#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 17938#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17939#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17914#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17915#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18305#L734-36 assume !(1 == ~t11_pc~0); 18017#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 18018#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18323#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17930#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 17931#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18942#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18580#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18581#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18353#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18354#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18533#L1233-3 assume !(1 == ~T5_E~0); 18534#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18803#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18804#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19310#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19312#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18336#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18337#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19285#L1273-3 assume !(1 == ~E_2~0); 19300#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19302#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18681#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18682#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18527#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18528#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19024#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18524#L1313-3 assume !(1 == ~E_10~0); 18525#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 18338#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 18339#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 18280#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 18508#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 18509#L1663 assume !(0 == start_simulation_~tmp~3#1); 18178#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 18916#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 18124#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 18010#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 18011#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18073#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18396#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 18862#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 18415#L1644-2 [2023-11-19 07:37:55,269 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:55,270 INFO L85 PathProgramCache]: Analyzing trace with hash 946180648, now seen corresponding path program 1 times [2023-11-19 07:37:55,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:55,270 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [569739374] [2023-11-19 07:37:55,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:55,271 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:55,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:55,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:55,334 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:55,334 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [569739374] [2023-11-19 07:37:55,334 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [569739374] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:55,334 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:55,335 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:55,335 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1338065267] [2023-11-19 07:37:55,335 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:55,336 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:37:55,336 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:55,336 INFO L85 PathProgramCache]: Analyzing trace with hash -1386990515, now seen corresponding path program 1 times [2023-11-19 07:37:55,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:55,337 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1887886521] [2023-11-19 07:37:55,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:55,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:55,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:55,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:55,422 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:55,422 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1887886521] [2023-11-19 07:37:55,422 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1887886521] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:55,422 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:55,423 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:55,423 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1100090862] [2023-11-19 07:37:55,423 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:55,424 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:37:55,424 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:55,424 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:37:55,424 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:37:55,425 INFO L87 Difference]: Start difference. First operand 1488 states and 2200 transitions. cyclomatic complexity: 713 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:55,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:55,463 INFO L93 Difference]: Finished difference Result 1488 states and 2199 transitions. [2023-11-19 07:37:55,463 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2199 transitions. [2023-11-19 07:37:55,471 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:55,482 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2199 transitions. [2023-11-19 07:37:55,483 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-19 07:37:55,484 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-19 07:37:55,485 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2199 transitions. [2023-11-19 07:37:55,487 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:55,487 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2199 transitions. [2023-11-19 07:37:55,491 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2199 transitions. [2023-11-19 07:37:55,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-19 07:37:55,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4778225806451613) internal successors, (2199), 1487 states have internal predecessors, (2199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:55,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2199 transitions. [2023-11-19 07:37:55,523 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2199 transitions. [2023-11-19 07:37:55,523 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:37:55,524 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2199 transitions. [2023-11-19 07:37:55,524 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-19 07:37:55,524 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2199 transitions. [2023-11-19 07:37:55,530 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:55,530 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:55,531 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:55,533 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:55,533 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:55,534 INFO L748 eck$LassoCheckResult]: Stem: 21339#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 21340#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 22321#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22322#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21789#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 21790#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21661#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21554#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21283#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20931#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20932#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20976#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20977#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21919#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21920#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21964#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21380#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21381#L1090 assume !(0 == ~M_E~0); 21423#L1090-2 assume !(0 == ~T1_E~0); 21424#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22112#L1100-1 assume !(0 == ~T3_E~0); 22113#L1105-1 assume !(0 == ~T4_E~0); 21203#L1110-1 assume !(0 == ~T5_E~0); 21204#L1115-1 assume !(0 == ~T6_E~0); 21590#L1120-1 assume !(0 == ~T7_E~0); 21898#L1125-1 assume !(0 == ~T8_E~0); 22370#L1130-1 assume !(0 == ~T9_E~0); 22133#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21385#L1140-1 assume !(0 == ~T11_E~0); 21386#L1145-1 assume !(0 == ~E_1~0); 22067#L1150-1 assume !(0 == ~E_2~0); 21567#L1155-1 assume !(0 == ~E_3~0); 21568#L1160-1 assume !(0 == ~E_4~0); 21666#L1165-1 assume !(0 == ~E_5~0); 21667#L1170-1 assume !(0 == ~E_6~0); 22305#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 21747#L1180-1 assume !(0 == ~E_8~0); 21748#L1185-1 assume !(0 == ~E_9~0); 21382#L1190-1 assume !(0 == ~E_10~0); 21383#L1195-1 assume !(0 == ~E_11~0); 21763#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21587#L525 assume !(1 == ~m_pc~0); 21021#L525-2 is_master_triggered_~__retres1~0#1 := 0; 21022#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22207#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22180#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21372#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21373#L544 assume 1 == ~t1_pc~0; 21642#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21589#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21000#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21001#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 21227#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21867#L563 assume !(1 == ~t2_pc~0); 22053#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21040#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21041#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21451#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 21452#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21945#L582 assume 1 == ~t3_pc~0; 21173#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21174#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20923#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20924#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 21109#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21110#L601 assume !(1 == ~t4_pc~0); 22079#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 21591#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21123#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21124#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 22074#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22346#L620 assume 1 == ~t5_pc~0; 21068#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21069#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21961#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22212#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 22355#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22356#L639 assume !(1 == ~t6_pc~0); 21896#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21491#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21492#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21540#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 21597#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21598#L658 assume 1 == ~t7_pc~0; 21897#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21813#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22361#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22013#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 21375#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21376#L677 assume 1 == ~t8_pc~0; 21603#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21186#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21187#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21447#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 21448#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22174#L696 assume !(1 == ~t9_pc~0); 21881#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 21882#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21652#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21653#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21903#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22116#L715 assume 1 == ~t10_pc~0; 22123#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21995#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21801#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21802#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 21741#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21180#L734 assume !(1 == ~t11_pc~0); 21181#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 21668#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21750#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20921#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 20922#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21962#L1213 assume !(1 == ~M_E~0); 21739#L1213-2 assume !(1 == ~T1_E~0); 21740#L1218-1 assume !(1 == ~T2_E~0); 20954#L1223-1 assume !(1 == ~T3_E~0); 20955#L1228-1 assume !(1 == ~T4_E~0); 21714#L1233-1 assume !(1 == ~T5_E~0); 22357#L1238-1 assume !(1 == ~T6_E~0); 22072#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22073#L1248-1 assume !(1 == ~T8_E~0); 22119#L1253-1 assume !(1 == ~T9_E~0); 22120#L1258-1 assume !(1 == ~T10_E~0); 22095#L1263-1 assume !(1 == ~T11_E~0); 22096#L1268-1 assume !(1 == ~E_1~0); 21916#L1273-1 assume !(1 == ~E_2~0); 21917#L1278-1 assume !(1 == ~E_3~0); 21487#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 21488#L1288-1 assume !(1 == ~E_5~0); 22218#L1293-1 assume !(1 == ~E_6~0); 22178#L1298-1 assume !(1 == ~E_7~0); 21949#L1303-1 assume !(1 == ~E_8~0); 21497#L1308-1 assume !(1 == ~E_9~0); 21389#L1313-1 assume !(1 == ~E_10~0); 21390#L1318-1 assume !(1 == ~E_11~0); 21397#L1323-1 assume { :end_inline_reset_delta_events } true; 21398#L1644-2 [2023-11-19 07:37:55,535 INFO L750 eck$LassoCheckResult]: Loop: 21398#L1644-2 assume !false; 22011#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21305#L1065-1 assume !false; 21306#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22353#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 21036#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 21613#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21502#L906 assume !(0 != eval_~tmp~0#1); 21504#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21824#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21825#L1090-3 assume !(0 == ~M_E~0); 22233#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22290#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22255#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22256#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21278#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21279#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21555#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21556#L1125-3 assume !(0 == ~T8_E~0); 22071#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22328#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21477#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20988#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20989#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21112#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21113#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21460#L1165-3 assume !(0 == ~E_5~0); 21461#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21860#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21374#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 21136#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21137#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22316#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22317#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21695#L525-36 assume !(1 == ~m_pc~0); 21696#L525-38 is_master_triggered_~__retres1~0#1 := 0; 21241#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21242#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21512#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21513#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21426#L544-36 assume 1 == ~t1_pc~0; 21427#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21983#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21984#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22323#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22304#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22208#L563-36 assume 1 == ~t2_pc~0; 21225#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20984#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20985#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22189#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21711#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21712#L582-36 assume 1 == ~t3_pc~0; 21544#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21545#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21643#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21644#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21749#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21689#L601-36 assume 1 == ~t4_pc~0; 21575#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21576#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21841#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21842#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22294#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22195#L620-36 assume !(1 == ~t5_pc~0); 21632#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 21631#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22060#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21602#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 21245#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21032#L639-36 assume 1 == ~t6_pc~0; 21033#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21073#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21074#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21293#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21294#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21901#L658-36 assume !(1 == ~t7_pc~0); 21042#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 21043#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22280#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21023#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21024#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22045#L677-36 assume !(1 == ~t8_pc~0); 21815#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 21816#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21946#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21947#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21843#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21844#L696-36 assume 1 == ~t9_pc~0; 21735#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21736#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21677#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21678#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21861#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21862#L715-36 assume 1 == ~t10_pc~0; 22006#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20919#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20920#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20897#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20898#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21288#L734-36 assume !(1 == ~t11_pc~0); 20998#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 20999#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21304#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20913#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20914#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21925#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21561#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21562#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21336#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21337#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21516#L1233-3 assume !(1 == ~T5_E~0); 21517#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21786#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21787#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22293#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22295#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21318#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21319#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22268#L1273-3 assume !(1 == ~E_2~0); 22283#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22285#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21664#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21665#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21509#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21510#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22007#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21507#L1313-3 assume !(1 == ~E_10~0); 21508#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21320#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 21321#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 21263#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 21489#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 21490#L1663 assume !(0 == start_simulation_~tmp~3#1); 21154#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 21899#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 21107#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 20990#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 20991#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21053#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21379#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 21845#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 21398#L1644-2 [2023-11-19 07:37:55,535 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:55,535 INFO L85 PathProgramCache]: Analyzing trace with hash 1380686246, now seen corresponding path program 1 times [2023-11-19 07:37:55,536 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:55,536 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1430662595] [2023-11-19 07:37:55,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:55,536 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:55,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:55,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:55,587 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:55,587 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1430662595] [2023-11-19 07:37:55,588 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1430662595] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:55,588 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:55,588 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:55,588 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [573373520] [2023-11-19 07:37:55,589 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:55,589 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:37:55,589 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:55,590 INFO L85 PathProgramCache]: Analyzing trace with hash -979985172, now seen corresponding path program 1 times [2023-11-19 07:37:55,590 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:55,590 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1789398927] [2023-11-19 07:37:55,590 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:55,590 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:55,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:55,658 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:55,658 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:55,659 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1789398927] [2023-11-19 07:37:55,659 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1789398927] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:55,659 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:55,659 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:55,659 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [61665308] [2023-11-19 07:37:55,660 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:55,660 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:37:55,660 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:55,661 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:37:55,661 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:37:55,661 INFO L87 Difference]: Start difference. First operand 1488 states and 2199 transitions. cyclomatic complexity: 712 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:55,696 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:55,696 INFO L93 Difference]: Finished difference Result 1488 states and 2198 transitions. [2023-11-19 07:37:55,696 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2198 transitions. [2023-11-19 07:37:55,704 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:55,715 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2198 transitions. [2023-11-19 07:37:55,716 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-19 07:37:55,717 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-19 07:37:55,718 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2198 transitions. [2023-11-19 07:37:55,720 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:55,720 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2198 transitions. [2023-11-19 07:37:55,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2198 transitions. [2023-11-19 07:37:55,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-19 07:37:55,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4771505376344085) internal successors, (2198), 1487 states have internal predecessors, (2198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:55,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2198 transitions. [2023-11-19 07:37:55,756 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2198 transitions. [2023-11-19 07:37:55,756 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:37:55,757 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2198 transitions. [2023-11-19 07:37:55,757 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-19 07:37:55,757 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2198 transitions. [2023-11-19 07:37:55,763 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:55,763 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:55,763 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:55,766 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:55,766 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:55,767 INFO L748 eck$LassoCheckResult]: Stem: 24322#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 24323#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 25305#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25306#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24772#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 24773#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24644#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24537#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24266#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23914#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23915#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23959#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 23960#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24906#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24907#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24954#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24363#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24364#L1090 assume !(0 == ~M_E~0); 24410#L1090-2 assume !(0 == ~T1_E~0); 24411#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25095#L1100-1 assume !(0 == ~T3_E~0); 25096#L1105-1 assume !(0 == ~T4_E~0); 24187#L1110-1 assume !(0 == ~T5_E~0); 24188#L1115-1 assume !(0 == ~T6_E~0); 24576#L1120-1 assume !(0 == ~T7_E~0); 24881#L1125-1 assume !(0 == ~T8_E~0); 25353#L1130-1 assume !(0 == ~T9_E~0); 25116#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24368#L1140-1 assume !(0 == ~T11_E~0); 24369#L1145-1 assume !(0 == ~E_1~0); 25050#L1150-1 assume !(0 == ~E_2~0); 24550#L1155-1 assume !(0 == ~E_3~0); 24551#L1160-1 assume !(0 == ~E_4~0); 24649#L1165-1 assume !(0 == ~E_5~0); 24650#L1170-1 assume !(0 == ~E_6~0); 25288#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 24730#L1180-1 assume !(0 == ~E_8~0); 24731#L1185-1 assume !(0 == ~E_9~0); 24365#L1190-1 assume !(0 == ~E_10~0); 24366#L1195-1 assume !(0 == ~E_11~0); 24746#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24570#L525 assume !(1 == ~m_pc~0); 24004#L525-2 is_master_triggered_~__retres1~0#1 := 0; 24005#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25190#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25165#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24355#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24356#L544 assume 1 == ~t1_pc~0; 24625#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24572#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23983#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23984#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 24210#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24850#L563 assume !(1 == ~t2_pc~0); 25038#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24023#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24024#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24437#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 24438#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24928#L582 assume 1 == ~t3_pc~0; 24156#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24157#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23906#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23907#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 24092#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24093#L601 assume !(1 == ~t4_pc~0); 25062#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24577#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24106#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24107#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 25057#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25329#L620 assume 1 == ~t5_pc~0; 24055#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24056#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24944#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25196#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 25338#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25339#L639 assume !(1 == ~t6_pc~0); 24879#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24474#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24475#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24523#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 24582#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24583#L658 assume 1 == ~t7_pc~0; 24880#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24797#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25344#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24997#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 24358#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24359#L677 assume 1 == ~t8_pc~0; 24588#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24175#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24176#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24430#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 24431#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25157#L696 assume !(1 == ~t9_pc~0); 24865#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 24866#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24635#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24636#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24888#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25100#L715 assume 1 == ~t10_pc~0; 25106#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24978#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24784#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24785#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 24724#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24163#L734 assume !(1 == ~t11_pc~0); 24164#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 24652#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24735#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23904#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 23905#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24945#L1213 assume !(1 == ~M_E~0); 24722#L1213-2 assume !(1 == ~T1_E~0); 24723#L1218-1 assume !(1 == ~T2_E~0); 23937#L1223-1 assume !(1 == ~T3_E~0); 23938#L1228-1 assume !(1 == ~T4_E~0); 24697#L1233-1 assume !(1 == ~T5_E~0); 25340#L1238-1 assume !(1 == ~T6_E~0); 25055#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25056#L1248-1 assume !(1 == ~T8_E~0); 25102#L1253-1 assume !(1 == ~T9_E~0); 25103#L1258-1 assume !(1 == ~T10_E~0); 25078#L1263-1 assume !(1 == ~T11_E~0); 25079#L1268-1 assume !(1 == ~E_1~0); 24899#L1273-1 assume !(1 == ~E_2~0); 24900#L1278-1 assume !(1 == ~E_3~0); 24470#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 24471#L1288-1 assume !(1 == ~E_5~0); 25201#L1293-1 assume !(1 == ~E_6~0); 25161#L1298-1 assume !(1 == ~E_7~0); 24932#L1303-1 assume !(1 == ~E_8~0); 24480#L1308-1 assume !(1 == ~E_9~0); 24372#L1313-1 assume !(1 == ~E_10~0); 24373#L1318-1 assume !(1 == ~E_11~0); 24379#L1323-1 assume { :end_inline_reset_delta_events } true; 24380#L1644-2 [2023-11-19 07:37:55,767 INFO L750 eck$LassoCheckResult]: Loop: 24380#L1644-2 assume !false; 24994#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24287#L1065-1 assume !false; 24288#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 25336#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 24019#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 24596#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24485#L906 assume !(0 != eval_~tmp~0#1); 24487#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24806#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24807#L1090-3 assume !(0 == ~M_E~0); 25216#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25273#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25238#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25239#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24261#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24262#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24538#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24539#L1125-3 assume !(0 == ~T8_E~0); 25054#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25311#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24460#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 23969#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23970#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24094#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24095#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24443#L1165-3 assume !(0 == ~E_5~0); 24444#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24843#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24357#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24118#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 24119#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25299#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25300#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24678#L525-36 assume !(1 == ~m_pc~0); 24679#L525-38 is_master_triggered_~__retres1~0#1 := 0; 24219#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24220#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24495#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24496#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24407#L544-36 assume 1 == ~t1_pc~0; 24408#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24966#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24967#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25304#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25286#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25191#L563-36 assume 1 == ~t2_pc~0; 24208#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23967#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23968#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25172#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24694#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24695#L582-36 assume !(1 == ~t3_pc~0); 24529#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 24528#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24626#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24627#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24732#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24672#L601-36 assume !(1 == ~t4_pc~0); 24560#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 24559#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24824#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24825#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25277#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25178#L620-36 assume 1 == ~t5_pc~0; 24611#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24612#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25039#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24585#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 24228#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24015#L639-36 assume 1 == ~t6_pc~0; 24016#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24053#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24054#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24278#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24279#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24884#L658-36 assume 1 == ~t7_pc~0; 24128#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24029#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25263#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24006#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24007#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25028#L677-36 assume 1 == ~t8_pc~0; 25205#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24800#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24929#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24930#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24826#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24827#L696-36 assume !(1 == ~t9_pc~0); 24720#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 24719#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24660#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24661#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24844#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24845#L715-36 assume !(1 == ~t10_pc~0); 24808#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 23902#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23903#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23880#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23881#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24271#L734-36 assume 1 == ~t11_pc~0; 24272#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23982#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24289#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23896#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23897#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24908#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24546#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24547#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24319#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24320#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24499#L1233-3 assume !(1 == ~T5_E~0); 24500#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24769#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24770#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25276#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25278#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24302#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24303#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25251#L1273-3 assume !(1 == ~E_2~0); 25266#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25268#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24647#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24648#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24493#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24494#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24990#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24490#L1313-3 assume !(1 == ~E_10~0); 24491#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24304#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 24305#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 24246#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 24472#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 24473#L1663 assume !(0 == start_simulation_~tmp~3#1); 24144#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 24882#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 24090#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 23976#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 23977#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24039#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24362#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 24828#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 24380#L1644-2 [2023-11-19 07:37:55,768 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:55,768 INFO L85 PathProgramCache]: Analyzing trace with hash 1810344552, now seen corresponding path program 1 times [2023-11-19 07:37:55,768 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:55,769 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1119633510] [2023-11-19 07:37:55,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:55,769 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:55,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:55,858 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:55,859 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:55,859 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1119633510] [2023-11-19 07:37:55,859 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1119633510] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:55,859 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:55,859 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:55,860 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [615312621] [2023-11-19 07:37:55,860 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:55,860 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:37:55,861 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:55,861 INFO L85 PathProgramCache]: Analyzing trace with hash -2009510740, now seen corresponding path program 1 times [2023-11-19 07:37:55,861 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:55,861 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1453167646] [2023-11-19 07:37:55,861 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:55,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:55,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:55,929 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:55,929 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:55,929 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1453167646] [2023-11-19 07:37:55,930 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1453167646] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:55,930 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:55,930 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:55,930 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1521851594] [2023-11-19 07:37:55,930 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:55,931 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:37:55,931 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:55,931 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:37:55,932 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:37:55,932 INFO L87 Difference]: Start difference. First operand 1488 states and 2198 transitions. cyclomatic complexity: 711 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:55,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:55,967 INFO L93 Difference]: Finished difference Result 1488 states and 2197 transitions. [2023-11-19 07:37:55,967 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2197 transitions. [2023-11-19 07:37:55,975 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:55,986 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2197 transitions. [2023-11-19 07:37:55,986 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-19 07:37:55,988 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-19 07:37:55,988 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2197 transitions. [2023-11-19 07:37:55,991 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:55,991 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2197 transitions. [2023-11-19 07:37:55,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2197 transitions. [2023-11-19 07:37:56,016 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-19 07:37:56,020 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.476478494623656) internal successors, (2197), 1487 states have internal predecessors, (2197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:56,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2197 transitions. [2023-11-19 07:37:56,026 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2197 transitions. [2023-11-19 07:37:56,027 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:37:56,027 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2197 transitions. [2023-11-19 07:37:56,028 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-19 07:37:56,028 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2197 transitions. [2023-11-19 07:37:56,034 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:56,034 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:56,034 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:56,037 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:56,037 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:56,038 INFO L748 eck$LassoCheckResult]: Stem: 27305#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 27306#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 28287#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28288#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27755#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 27756#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27627#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27520#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27249#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26897#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26898#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26942#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26943#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27885#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27886#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 27930#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 27346#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27347#L1090 assume !(0 == ~M_E~0); 27389#L1090-2 assume !(0 == ~T1_E~0); 27390#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28077#L1100-1 assume !(0 == ~T3_E~0); 28078#L1105-1 assume !(0 == ~T4_E~0); 27169#L1110-1 assume !(0 == ~T5_E~0); 27170#L1115-1 assume !(0 == ~T6_E~0); 27556#L1120-1 assume !(0 == ~T7_E~0); 27864#L1125-1 assume !(0 == ~T8_E~0); 28336#L1130-1 assume !(0 == ~T9_E~0); 28099#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 27351#L1140-1 assume !(0 == ~T11_E~0); 27352#L1145-1 assume !(0 == ~E_1~0); 28033#L1150-1 assume !(0 == ~E_2~0); 27533#L1155-1 assume !(0 == ~E_3~0); 27534#L1160-1 assume !(0 == ~E_4~0); 27632#L1165-1 assume !(0 == ~E_5~0); 27633#L1170-1 assume !(0 == ~E_6~0); 28271#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 27713#L1180-1 assume !(0 == ~E_8~0); 27714#L1185-1 assume !(0 == ~E_9~0); 27348#L1190-1 assume !(0 == ~E_10~0); 27349#L1195-1 assume !(0 == ~E_11~0); 27729#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27548#L525 assume !(1 == ~m_pc~0); 26987#L525-2 is_master_triggered_~__retres1~0#1 := 0; 26988#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28173#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28146#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27338#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27339#L544 assume 1 == ~t1_pc~0; 27608#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27555#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26963#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26964#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 27193#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27833#L563 assume !(1 == ~t2_pc~0); 28019#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27006#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27007#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27417#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 27418#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27911#L582 assume 1 == ~t3_pc~0; 27137#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27138#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26889#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26890#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 27075#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27076#L601 assume !(1 == ~t4_pc~0); 28045#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27557#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27089#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27090#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 28040#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28312#L620 assume 1 == ~t5_pc~0; 27034#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27035#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27927#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28178#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 28321#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28322#L639 assume !(1 == ~t6_pc~0); 27862#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27457#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27458#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27506#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 27563#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27564#L658 assume 1 == ~t7_pc~0; 27863#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27779#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28327#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27979#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 27341#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27342#L677 assume 1 == ~t8_pc~0; 27569#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27152#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27153#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27413#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 27414#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28140#L696 assume !(1 == ~t9_pc~0); 27845#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 27846#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27618#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27619#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27869#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28082#L715 assume 1 == ~t10_pc~0; 28089#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 27961#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 27767#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27768#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 27707#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27146#L734 assume !(1 == ~t11_pc~0); 27147#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 27634#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27716#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26887#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 26888#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27928#L1213 assume !(1 == ~M_E~0); 27704#L1213-2 assume !(1 == ~T1_E~0); 27705#L1218-1 assume !(1 == ~T2_E~0); 26920#L1223-1 assume !(1 == ~T3_E~0); 26921#L1228-1 assume !(1 == ~T4_E~0); 27680#L1233-1 assume !(1 == ~T5_E~0); 28323#L1238-1 assume !(1 == ~T6_E~0); 28038#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28039#L1248-1 assume !(1 == ~T8_E~0); 28085#L1253-1 assume !(1 == ~T9_E~0); 28086#L1258-1 assume !(1 == ~T10_E~0); 28061#L1263-1 assume !(1 == ~T11_E~0); 28062#L1268-1 assume !(1 == ~E_1~0); 27882#L1273-1 assume !(1 == ~E_2~0); 27883#L1278-1 assume !(1 == ~E_3~0); 27453#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 27454#L1288-1 assume !(1 == ~E_5~0); 28184#L1293-1 assume !(1 == ~E_6~0); 28144#L1298-1 assume !(1 == ~E_7~0); 27915#L1303-1 assume !(1 == ~E_8~0); 27463#L1308-1 assume !(1 == ~E_9~0); 27355#L1313-1 assume !(1 == ~E_10~0); 27356#L1318-1 assume !(1 == ~E_11~0); 27363#L1323-1 assume { :end_inline_reset_delta_events } true; 27364#L1644-2 [2023-11-19 07:37:56,038 INFO L750 eck$LassoCheckResult]: Loop: 27364#L1644-2 assume !false; 27977#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27271#L1065-1 assume !false; 27272#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 28319#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 27002#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 27579#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27468#L906 assume !(0 != eval_~tmp~0#1); 27470#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27790#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27791#L1090-3 assume !(0 == ~M_E~0); 28199#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28256#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28221#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28222#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27244#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27245#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27521#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27522#L1125-3 assume !(0 == ~T8_E~0); 28037#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28294#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 27443#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26952#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26953#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27078#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27079#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27426#L1165-3 assume !(0 == ~E_5~0); 27427#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 27826#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27340#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27101#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27102#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28282#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28283#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27661#L525-36 assume !(1 == ~m_pc~0); 27662#L525-38 is_master_triggered_~__retres1~0#1 := 0; 27202#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27203#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27478#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27479#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27392#L544-36 assume 1 == ~t1_pc~0; 27393#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27949#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27950#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28289#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28270#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28174#L563-36 assume 1 == ~t2_pc~0; 27191#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26950#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26951#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28155#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27677#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27678#L582-36 assume 1 == ~t3_pc~0; 27510#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27511#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27609#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27610#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27715#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27655#L601-36 assume 1 == ~t4_pc~0; 27541#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27542#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27807#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27808#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28260#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28161#L620-36 assume 1 == ~t5_pc~0; 27596#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27597#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28024#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27568#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 27211#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26998#L639-36 assume 1 == ~t6_pc~0; 26999#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27039#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27040#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27261#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27262#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27867#L658-36 assume !(1 == ~t7_pc~0); 27011#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 27012#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28246#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26989#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26990#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28011#L677-36 assume !(1 == ~t8_pc~0); 27782#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 27783#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27912#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27913#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27809#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27810#L696-36 assume 1 == ~t9_pc~0; 27701#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27702#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27640#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27641#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27827#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27828#L715-36 assume 1 == ~t10_pc~0; 27972#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 26885#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26886#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26863#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26864#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27251#L734-36 assume !(1 == ~t11_pc~0); 26961#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 26962#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27270#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26879#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 26880#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27891#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27527#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27528#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27302#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27303#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27482#L1233-3 assume !(1 == ~T5_E~0); 27483#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27752#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27753#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28259#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28261#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 27284#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 27285#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28234#L1273-3 assume !(1 == ~E_2~0); 28249#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28250#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27630#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27631#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27475#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27476#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27973#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27473#L1313-3 assume !(1 == ~E_10~0); 27474#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 27286#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 27287#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 27229#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 27455#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 27456#L1663 assume !(0 == start_simulation_~tmp~3#1); 27120#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 27865#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 27073#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 26956#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 26957#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27019#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27345#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 27811#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 27364#L1644-2 [2023-11-19 07:37:56,039 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:56,039 INFO L85 PathProgramCache]: Analyzing trace with hash -1778026138, now seen corresponding path program 1 times [2023-11-19 07:37:56,040 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:56,040 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [178642312] [2023-11-19 07:37:56,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:56,040 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:56,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:56,099 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:56,100 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:56,100 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [178642312] [2023-11-19 07:37:56,100 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [178642312] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:56,100 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:56,101 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:56,101 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [149331874] [2023-11-19 07:37:56,101 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:56,101 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:37:56,102 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:56,102 INFO L85 PathProgramCache]: Analyzing trace with hash 297167501, now seen corresponding path program 3 times [2023-11-19 07:37:56,102 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:56,102 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [862061333] [2023-11-19 07:37:56,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:56,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:56,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:56,182 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:56,182 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:56,182 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [862061333] [2023-11-19 07:37:56,183 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [862061333] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:56,183 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:56,183 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:56,183 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1474506884] [2023-11-19 07:37:56,183 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:56,184 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:37:56,184 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:56,184 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:37:56,185 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:37:56,185 INFO L87 Difference]: Start difference. First operand 1488 states and 2197 transitions. cyclomatic complexity: 710 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:56,220 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:56,221 INFO L93 Difference]: Finished difference Result 1488 states and 2196 transitions. [2023-11-19 07:37:56,221 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2196 transitions. [2023-11-19 07:37:56,230 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:56,241 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2196 transitions. [2023-11-19 07:37:56,241 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-19 07:37:56,243 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-19 07:37:56,243 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2196 transitions. [2023-11-19 07:37:56,245 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:56,246 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2196 transitions. [2023-11-19 07:37:56,249 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2196 transitions. [2023-11-19 07:37:56,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-19 07:37:56,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4758064516129032) internal successors, (2196), 1487 states have internal predecessors, (2196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:56,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2196 transitions. [2023-11-19 07:37:56,280 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2196 transitions. [2023-11-19 07:37:56,280 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:37:56,281 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2196 transitions. [2023-11-19 07:37:56,281 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-19 07:37:56,281 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2196 transitions. [2023-11-19 07:37:56,287 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:56,287 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:56,288 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:56,290 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:56,290 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:56,291 INFO L748 eck$LassoCheckResult]: Stem: 30288#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 30289#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 31271#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31272#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30738#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 30739#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30610#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30503#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30232#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29880#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29881#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29925#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29926#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 30872#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 30873#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 30920#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 30329#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30330#L1090 assume !(0 == ~M_E~0); 30376#L1090-2 assume !(0 == ~T1_E~0); 30377#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31061#L1100-1 assume !(0 == ~T3_E~0); 31062#L1105-1 assume !(0 == ~T4_E~0); 30153#L1110-1 assume !(0 == ~T5_E~0); 30154#L1115-1 assume !(0 == ~T6_E~0); 30542#L1120-1 assume !(0 == ~T7_E~0); 30847#L1125-1 assume !(0 == ~T8_E~0); 31319#L1130-1 assume !(0 == ~T9_E~0); 31082#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30334#L1140-1 assume !(0 == ~T11_E~0); 30335#L1145-1 assume !(0 == ~E_1~0); 31016#L1150-1 assume !(0 == ~E_2~0); 30516#L1155-1 assume !(0 == ~E_3~0); 30517#L1160-1 assume !(0 == ~E_4~0); 30615#L1165-1 assume !(0 == ~E_5~0); 30616#L1170-1 assume !(0 == ~E_6~0); 31254#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 30696#L1180-1 assume !(0 == ~E_8~0); 30697#L1185-1 assume !(0 == ~E_9~0); 30331#L1190-1 assume !(0 == ~E_10~0); 30332#L1195-1 assume !(0 == ~E_11~0); 30712#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30536#L525 assume !(1 == ~m_pc~0); 29970#L525-2 is_master_triggered_~__retres1~0#1 := 0; 29971#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31156#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31131#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30321#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30322#L544 assume 1 == ~t1_pc~0; 30591#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30538#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29949#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29950#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 30176#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30816#L563 assume !(1 == ~t2_pc~0); 31004#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 29989#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29990#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30403#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 30404#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30894#L582 assume 1 == ~t3_pc~0; 30122#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30123#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29872#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29873#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 30058#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30059#L601 assume !(1 == ~t4_pc~0); 31028#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 30543#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30072#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30073#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 31023#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31295#L620 assume 1 == ~t5_pc~0; 30021#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30022#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30910#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31162#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 31304#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31305#L639 assume !(1 == ~t6_pc~0); 30845#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 30440#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30441#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30489#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 30548#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30549#L658 assume 1 == ~t7_pc~0; 30846#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30763#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31310#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30963#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 30324#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30325#L677 assume 1 == ~t8_pc~0; 30554#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30138#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30139#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30396#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 30397#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31123#L696 assume !(1 == ~t9_pc~0); 30831#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 30832#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30601#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30602#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30854#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31066#L715 assume 1 == ~t10_pc~0; 31072#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30944#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30750#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30751#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 30690#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30129#L734 assume !(1 == ~t11_pc~0); 30130#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 30617#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30701#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29870#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 29871#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30911#L1213 assume !(1 == ~M_E~0); 30688#L1213-2 assume !(1 == ~T1_E~0); 30689#L1218-1 assume !(1 == ~T2_E~0); 29903#L1223-1 assume !(1 == ~T3_E~0); 29904#L1228-1 assume !(1 == ~T4_E~0); 30663#L1233-1 assume !(1 == ~T5_E~0); 31306#L1238-1 assume !(1 == ~T6_E~0); 31021#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 31022#L1248-1 assume !(1 == ~T8_E~0); 31068#L1253-1 assume !(1 == ~T9_E~0); 31069#L1258-1 assume !(1 == ~T10_E~0); 31044#L1263-1 assume !(1 == ~T11_E~0); 31045#L1268-1 assume !(1 == ~E_1~0); 30865#L1273-1 assume !(1 == ~E_2~0); 30866#L1278-1 assume !(1 == ~E_3~0); 30436#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 30437#L1288-1 assume !(1 == ~E_5~0); 31167#L1293-1 assume !(1 == ~E_6~0); 31127#L1298-1 assume !(1 == ~E_7~0); 30898#L1303-1 assume !(1 == ~E_8~0); 30446#L1308-1 assume !(1 == ~E_9~0); 30338#L1313-1 assume !(1 == ~E_10~0); 30339#L1318-1 assume !(1 == ~E_11~0); 30349#L1323-1 assume { :end_inline_reset_delta_events } true; 30350#L1644-2 [2023-11-19 07:37:56,291 INFO L750 eck$LassoCheckResult]: Loop: 30350#L1644-2 assume !false; 30960#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30254#L1065-1 assume !false; 30255#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 31302#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 29985#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 30562#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30451#L906 assume !(0 != eval_~tmp~0#1); 30453#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30773#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30774#L1090-3 assume !(0 == ~M_E~0); 31182#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31239#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31204#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31205#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30227#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30228#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30504#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 30505#L1125-3 assume !(0 == ~T8_E~0); 31020#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 31277#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30426#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29935#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29936#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30060#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30061#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30409#L1165-3 assume !(0 == ~E_5~0); 30410#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30809#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30323#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30084#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 30085#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31265#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 31266#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30641#L525-36 assume !(1 == ~m_pc~0); 30642#L525-38 is_master_triggered_~__retres1~0#1 := 0; 30185#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30186#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30461#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30462#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30373#L544-36 assume 1 == ~t1_pc~0; 30374#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30932#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30933#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31270#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31252#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31157#L563-36 assume 1 == ~t2_pc~0; 30174#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29933#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29934#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31138#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30660#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30661#L582-36 assume 1 == ~t3_pc~0; 30493#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30494#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30592#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30593#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30698#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30638#L601-36 assume 1 == ~t4_pc~0; 30524#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30525#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30790#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30791#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31243#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31144#L620-36 assume 1 == ~t5_pc~0; 30577#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30578#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31005#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30551#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 30194#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29981#L639-36 assume 1 == ~t6_pc~0; 29982#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30019#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30020#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30244#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30245#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30850#L658-36 assume !(1 == ~t7_pc~0); 29994#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 29995#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31229#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29972#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29973#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30994#L677-36 assume 1 == ~t8_pc~0; 31171#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30766#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30895#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30896#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 30792#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30793#L696-36 assume 1 == ~t9_pc~0; 30684#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30685#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30626#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30627#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30810#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30811#L715-36 assume !(1 == ~t10_pc~0); 30772#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 29868#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29869#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29846#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29847#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30237#L734-36 assume !(1 == ~t11_pc~0); 29947#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 29948#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30253#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29862#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 29863#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30874#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30510#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30511#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30285#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30286#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30465#L1233-3 assume !(1 == ~T5_E~0); 30466#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30735#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30736#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 31242#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 31244#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30267#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 30268#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 31217#L1273-3 assume !(1 == ~E_2~0); 31232#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31234#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30613#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30614#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30459#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30460#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30956#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30456#L1313-3 assume !(1 == ~E_10~0); 30457#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 30269#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 30270#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 30212#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 30438#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 30439#L1663 assume !(0 == start_simulation_~tmp~3#1); 30110#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 30848#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 30056#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29939#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 29940#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30005#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30328#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 30794#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 30350#L1644-2 [2023-11-19 07:37:56,292 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:56,292 INFO L85 PathProgramCache]: Analyzing trace with hash 1655107556, now seen corresponding path program 1 times [2023-11-19 07:37:56,293 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:56,293 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1305948044] [2023-11-19 07:37:56,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:56,293 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:56,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:56,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:56,352 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:56,352 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1305948044] [2023-11-19 07:37:56,352 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1305948044] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:56,352 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:56,353 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:56,353 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1149647156] [2023-11-19 07:37:56,353 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:56,353 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:37:56,354 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:56,354 INFO L85 PathProgramCache]: Analyzing trace with hash -658480883, now seen corresponding path program 2 times [2023-11-19 07:37:56,354 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:56,354 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2140251645] [2023-11-19 07:37:56,355 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:56,355 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:56,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:56,461 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:56,462 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:56,462 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2140251645] [2023-11-19 07:37:56,462 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2140251645] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:56,462 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:56,462 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:56,463 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1588944901] [2023-11-19 07:37:56,463 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:56,463 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:37:56,463 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:56,464 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:37:56,464 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:37:56,464 INFO L87 Difference]: Start difference. First operand 1488 states and 2196 transitions. cyclomatic complexity: 709 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:56,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:56,496 INFO L93 Difference]: Finished difference Result 1488 states and 2195 transitions. [2023-11-19 07:37:56,496 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2195 transitions. [2023-11-19 07:37:56,503 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:56,512 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2195 transitions. [2023-11-19 07:37:56,513 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-19 07:37:56,514 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-19 07:37:56,514 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2195 transitions. [2023-11-19 07:37:56,517 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:56,517 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2195 transitions. [2023-11-19 07:37:56,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2195 transitions. [2023-11-19 07:37:56,540 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-19 07:37:56,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4751344086021505) internal successors, (2195), 1487 states have internal predecessors, (2195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:56,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2195 transitions. [2023-11-19 07:37:56,548 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2195 transitions. [2023-11-19 07:37:56,549 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:37:56,549 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2195 transitions. [2023-11-19 07:37:56,549 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-19 07:37:56,549 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2195 transitions. [2023-11-19 07:37:56,554 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:56,555 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:56,555 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:56,557 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:56,558 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:56,558 INFO L748 eck$LassoCheckResult]: Stem: 33271#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 33272#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 34253#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34254#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33721#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 33722#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33593#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33486#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33215#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32863#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32864#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32908#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32909#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33851#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33852#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 33896#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 33312#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33313#L1090 assume !(0 == ~M_E~0); 33355#L1090-2 assume !(0 == ~T1_E~0); 33356#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34043#L1100-1 assume !(0 == ~T3_E~0); 34044#L1105-1 assume !(0 == ~T4_E~0); 33135#L1110-1 assume !(0 == ~T5_E~0); 33136#L1115-1 assume !(0 == ~T6_E~0); 33522#L1120-1 assume !(0 == ~T7_E~0); 33830#L1125-1 assume !(0 == ~T8_E~0); 34302#L1130-1 assume !(0 == ~T9_E~0); 34065#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33317#L1140-1 assume !(0 == ~T11_E~0); 33318#L1145-1 assume !(0 == ~E_1~0); 33999#L1150-1 assume !(0 == ~E_2~0); 33499#L1155-1 assume !(0 == ~E_3~0); 33500#L1160-1 assume !(0 == ~E_4~0); 33598#L1165-1 assume !(0 == ~E_5~0); 33599#L1170-1 assume !(0 == ~E_6~0); 34237#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 33679#L1180-1 assume !(0 == ~E_8~0); 33680#L1185-1 assume !(0 == ~E_9~0); 33314#L1190-1 assume !(0 == ~E_10~0); 33315#L1195-1 assume !(0 == ~E_11~0); 33695#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33514#L525 assume !(1 == ~m_pc~0); 32953#L525-2 is_master_triggered_~__retres1~0#1 := 0; 32954#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34139#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 34112#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33304#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33305#L544 assume 1 == ~t1_pc~0; 33574#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33521#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32927#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32928#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 33159#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33799#L563 assume !(1 == ~t2_pc~0); 33985#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 32972#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32973#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33383#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 33384#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33877#L582 assume 1 == ~t3_pc~0; 33103#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33104#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32855#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32856#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 33041#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33042#L601 assume !(1 == ~t4_pc~0); 34011#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33523#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33053#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33054#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 34006#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34278#L620 assume 1 == ~t5_pc~0; 33000#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33001#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33893#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34144#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 34287#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34288#L639 assume !(1 == ~t6_pc~0); 33828#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 33421#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33422#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33472#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 33529#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33530#L658 assume 1 == ~t7_pc~0; 33829#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33745#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34293#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33945#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 33307#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33308#L677 assume 1 == ~t8_pc~0; 33535#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33118#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33119#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33379#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 33380#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34106#L696 assume !(1 == ~t9_pc~0); 33811#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 33812#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33584#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33585#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33835#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34048#L715 assume 1 == ~t10_pc~0; 34055#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33927#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33733#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33734#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 33673#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33112#L734 assume !(1 == ~t11_pc~0); 33113#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 33600#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33682#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32851#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 32852#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33894#L1213 assume !(1 == ~M_E~0); 33670#L1213-2 assume !(1 == ~T1_E~0); 33671#L1218-1 assume !(1 == ~T2_E~0); 32886#L1223-1 assume !(1 == ~T3_E~0); 32887#L1228-1 assume !(1 == ~T4_E~0); 33646#L1233-1 assume !(1 == ~T5_E~0); 34289#L1238-1 assume !(1 == ~T6_E~0); 34004#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34005#L1248-1 assume !(1 == ~T8_E~0); 34051#L1253-1 assume !(1 == ~T9_E~0); 34052#L1258-1 assume !(1 == ~T10_E~0); 34027#L1263-1 assume !(1 == ~T11_E~0); 34028#L1268-1 assume !(1 == ~E_1~0); 33848#L1273-1 assume !(1 == ~E_2~0); 33849#L1278-1 assume !(1 == ~E_3~0); 33419#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 33420#L1288-1 assume !(1 == ~E_5~0); 34150#L1293-1 assume !(1 == ~E_6~0); 34110#L1298-1 assume !(1 == ~E_7~0); 33881#L1303-1 assume !(1 == ~E_8~0); 33429#L1308-1 assume !(1 == ~E_9~0); 33321#L1313-1 assume !(1 == ~E_10~0); 33322#L1318-1 assume !(1 == ~E_11~0); 33329#L1323-1 assume { :end_inline_reset_delta_events } true; 33330#L1644-2 [2023-11-19 07:37:56,559 INFO L750 eck$LassoCheckResult]: Loop: 33330#L1644-2 assume !false; 33943#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33236#L1065-1 assume !false; 33237#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 34285#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 32968#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 33545#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 33434#L906 assume !(0 != eval_~tmp~0#1); 33436#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33755#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33756#L1090-3 assume !(0 == ~M_E~0); 34165#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34222#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34187#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34188#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33210#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33211#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33487#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33488#L1125-3 assume !(0 == ~T8_E~0); 34003#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 34260#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33409#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32918#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32919#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33043#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33044#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33392#L1165-3 assume !(0 == ~E_5~0); 33393#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33792#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33306#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33067#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33068#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34248#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 34249#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33627#L525-36 assume !(1 == ~m_pc~0); 33628#L525-38 is_master_triggered_~__retres1~0#1 := 0; 33168#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33169#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33444#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33445#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33358#L544-36 assume !(1 == ~t1_pc~0); 33360#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 33915#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33916#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34255#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34235#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34140#L563-36 assume 1 == ~t2_pc~0; 33157#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32916#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32917#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34121#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33643#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33644#L582-36 assume 1 == ~t3_pc~0; 33476#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33477#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33575#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33576#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33681#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33621#L601-36 assume 1 == ~t4_pc~0; 33507#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33508#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33773#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33774#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 34226#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34127#L620-36 assume 1 == ~t5_pc~0; 33560#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33561#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33988#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33534#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 33177#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32964#L639-36 assume 1 == ~t6_pc~0; 32965#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33005#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33006#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33227#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33228#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33833#L658-36 assume !(1 == ~t7_pc~0); 32977#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 32978#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34212#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32955#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32956#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33977#L677-36 assume !(1 == ~t8_pc~0); 33748#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 33749#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33878#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33879#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33775#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33776#L696-36 assume 1 == ~t9_pc~0; 33667#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33668#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33609#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33610#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33793#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33794#L715-36 assume 1 == ~t10_pc~0; 33938#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 32853#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32854#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32829#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32830#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33220#L734-36 assume !(1 == ~t11_pc~0); 32932#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 32933#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33238#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32845#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32846#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33857#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33495#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33496#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33268#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33269#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33448#L1233-3 assume !(1 == ~T5_E~0); 33449#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33718#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33719#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34225#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34227#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33251#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33252#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34200#L1273-3 assume !(1 == ~E_2~0); 34215#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34217#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33596#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33597#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33442#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33443#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33939#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33439#L1313-3 assume !(1 == ~E_10~0); 33440#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33253#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 33254#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 33195#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 33423#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 33424#L1663 assume !(0 == start_simulation_~tmp~3#1); 33086#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 33831#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 33039#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32925#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 32926#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32988#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33311#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 33777#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 33330#L1644-2 [2023-11-19 07:37:56,559 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:56,560 INFO L85 PathProgramCache]: Analyzing trace with hash -589450842, now seen corresponding path program 1 times [2023-11-19 07:37:56,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:56,560 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1796876746] [2023-11-19 07:37:56,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:56,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:56,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:56,654 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:56,654 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:56,654 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1796876746] [2023-11-19 07:37:56,655 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1796876746] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:56,655 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:56,655 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:37:56,655 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1051817832] [2023-11-19 07:37:56,655 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:56,656 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:37:56,656 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:56,656 INFO L85 PathProgramCache]: Analyzing trace with hash -1567805460, now seen corresponding path program 1 times [2023-11-19 07:37:56,657 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:56,657 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1065786378] [2023-11-19 07:37:56,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:56,657 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:56,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:56,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:56,734 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:56,734 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1065786378] [2023-11-19 07:37:56,735 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1065786378] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:56,735 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:56,735 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:56,735 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [34232949] [2023-11-19 07:37:56,735 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:56,736 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:37:56,736 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:56,736 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:37:56,736 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:37:56,737 INFO L87 Difference]: Start difference. First operand 1488 states and 2195 transitions. cyclomatic complexity: 708 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:56,788 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:56,788 INFO L93 Difference]: Finished difference Result 1488 states and 2190 transitions. [2023-11-19 07:37:56,788 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2190 transitions. [2023-11-19 07:37:56,795 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:56,808 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2190 transitions. [2023-11-19 07:37:56,808 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-19 07:37:56,810 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-19 07:37:56,810 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2190 transitions. [2023-11-19 07:37:56,813 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:56,813 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2190 transitions. [2023-11-19 07:37:56,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2190 transitions. [2023-11-19 07:37:56,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-19 07:37:56,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.471774193548387) internal successors, (2190), 1487 states have internal predecessors, (2190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:56,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2190 transitions. [2023-11-19 07:37:56,845 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2190 transitions. [2023-11-19 07:37:56,846 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:37:56,847 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2190 transitions. [2023-11-19 07:37:56,848 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-19 07:37:56,848 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2190 transitions. [2023-11-19 07:37:56,853 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:56,854 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:56,854 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:56,856 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:56,857 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:56,857 INFO L748 eck$LassoCheckResult]: Stem: 36254#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 36255#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 37237#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37238#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36704#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 36705#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36576#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36469#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36198#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35846#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35847#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35891#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35892#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36836#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36837#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36882#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 36295#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36296#L1090 assume !(0 == ~M_E~0); 36341#L1090-2 assume !(0 == ~T1_E~0); 36342#L1095-1 assume !(0 == ~T2_E~0); 37027#L1100-1 assume !(0 == ~T3_E~0); 37028#L1105-1 assume !(0 == ~T4_E~0); 36119#L1110-1 assume !(0 == ~T5_E~0); 36120#L1115-1 assume !(0 == ~T6_E~0); 36505#L1120-1 assume !(0 == ~T7_E~0); 36813#L1125-1 assume !(0 == ~T8_E~0); 37285#L1130-1 assume !(0 == ~T9_E~0); 37048#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36300#L1140-1 assume !(0 == ~T11_E~0); 36301#L1145-1 assume !(0 == ~E_1~0); 36982#L1150-1 assume !(0 == ~E_2~0); 36482#L1155-1 assume !(0 == ~E_3~0); 36483#L1160-1 assume !(0 == ~E_4~0); 36581#L1165-1 assume !(0 == ~E_5~0); 36582#L1170-1 assume !(0 == ~E_6~0); 37220#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 36662#L1180-1 assume !(0 == ~E_8~0); 36663#L1185-1 assume !(0 == ~E_9~0); 36297#L1190-1 assume !(0 == ~E_10~0); 36298#L1195-1 assume !(0 == ~E_11~0); 36678#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36502#L525 assume !(1 == ~m_pc~0); 35936#L525-2 is_master_triggered_~__retres1~0#1 := 0; 35937#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37122#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 37097#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36287#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36288#L544 assume 1 == ~t1_pc~0; 36557#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36504#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35915#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35916#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 36142#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36782#L563 assume !(1 == ~t2_pc~0); 36968#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 35955#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35956#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36369#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 36370#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36860#L582 assume 1 == ~t3_pc~0; 36088#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36089#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35838#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35839#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 36024#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36025#L601 assume !(1 == ~t4_pc~0); 36994#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 36506#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36038#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36039#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 36989#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37261#L620 assume 1 == ~t5_pc~0; 35987#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35988#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36876#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37128#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 37270#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37271#L639 assume !(1 == ~t6_pc~0); 36811#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36406#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36407#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36455#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 36512#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36513#L658 assume 1 == ~t7_pc~0; 36812#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36729#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37276#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36929#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 36290#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36291#L677 assume 1 == ~t8_pc~0; 36520#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36101#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36102#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36362#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 36363#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37089#L696 assume !(1 == ~t9_pc~0); 36796#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 36797#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36567#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36568#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36820#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37031#L715 assume 1 == ~t10_pc~0; 37038#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 36910#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36716#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36717#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 36656#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36095#L734 assume !(1 == ~t11_pc~0); 36096#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 36583#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36667#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35836#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 35837#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36877#L1213 assume !(1 == ~M_E~0); 36654#L1213-2 assume !(1 == ~T1_E~0); 36655#L1218-1 assume !(1 == ~T2_E~0); 35869#L1223-1 assume !(1 == ~T3_E~0); 35870#L1228-1 assume !(1 == ~T4_E~0); 36629#L1233-1 assume !(1 == ~T5_E~0); 37272#L1238-1 assume !(1 == ~T6_E~0); 36987#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36988#L1248-1 assume !(1 == ~T8_E~0); 37034#L1253-1 assume !(1 == ~T9_E~0); 37035#L1258-1 assume !(1 == ~T10_E~0); 37010#L1263-1 assume !(1 == ~T11_E~0); 37011#L1268-1 assume !(1 == ~E_1~0); 36831#L1273-1 assume !(1 == ~E_2~0); 36832#L1278-1 assume !(1 == ~E_3~0); 36402#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 36403#L1288-1 assume !(1 == ~E_5~0); 37133#L1293-1 assume !(1 == ~E_6~0); 37093#L1298-1 assume !(1 == ~E_7~0); 36864#L1303-1 assume !(1 == ~E_8~0); 36412#L1308-1 assume !(1 == ~E_9~0); 36304#L1313-1 assume !(1 == ~E_10~0); 36305#L1318-1 assume !(1 == ~E_11~0); 36315#L1323-1 assume { :end_inline_reset_delta_events } true; 36316#L1644-2 [2023-11-19 07:37:56,858 INFO L750 eck$LassoCheckResult]: Loop: 36316#L1644-2 assume !false; 36926#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36220#L1065-1 assume !false; 36221#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 37268#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 35951#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 36528#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 36417#L906 assume !(0 != eval_~tmp~0#1); 36419#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36739#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36740#L1090-3 assume !(0 == ~M_E~0); 37148#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37205#L1095-3 assume !(0 == ~T2_E~0); 37170#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37171#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36193#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36194#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36470#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36471#L1125-3 assume !(0 == ~T8_E~0); 36986#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37243#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36394#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 35903#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35904#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36027#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36028#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36375#L1165-3 assume !(0 == ~E_5~0); 36376#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36775#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36289#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 36053#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36054#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37231#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 37232#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36605#L525-36 assume !(1 == ~m_pc~0); 36606#L525-38 is_master_triggered_~__retres1~0#1 := 0; 36151#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36152#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36427#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36428#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36338#L544-36 assume 1 == ~t1_pc~0; 36339#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36898#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36899#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37236#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37218#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37123#L563-36 assume 1 == ~t2_pc~0; 36140#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35899#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35900#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37104#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36626#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36627#L582-36 assume 1 == ~t3_pc~0; 36459#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36460#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36558#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36559#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36664#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36604#L601-36 assume 1 == ~t4_pc~0; 36490#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36491#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36756#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36757#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37209#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37110#L620-36 assume 1 == ~t5_pc~0; 36541#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36542#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36971#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36517#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 36160#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35947#L639-36 assume 1 == ~t6_pc~0; 35948#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 35985#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35986#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36210#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 36211#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36816#L658-36 assume !(1 == ~t7_pc~0); 35960#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 35961#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37195#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35938#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35939#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36960#L677-36 assume 1 == ~t8_pc~0; 37137#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36732#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36861#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36862#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36758#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36759#L696-36 assume 1 == ~t9_pc~0; 36650#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36651#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36592#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36593#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36776#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36777#L715-36 assume !(1 == ~t10_pc~0); 36738#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 35834#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35835#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35812#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35813#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36203#L734-36 assume !(1 == ~t11_pc~0); 35913#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 35914#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36219#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35828#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35829#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36840#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36476#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36477#L1218-3 assume !(1 == ~T2_E~0); 36251#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36252#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36431#L1233-3 assume !(1 == ~T5_E~0); 36432#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36701#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36702#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37208#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 37210#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36233#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36234#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37183#L1273-3 assume !(1 == ~E_2~0); 37198#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37200#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36579#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36580#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36425#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 36426#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36922#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36422#L1313-3 assume !(1 == ~E_10~0); 36423#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 36235#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 36236#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 36178#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 36404#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 36405#L1663 assume !(0 == start_simulation_~tmp~3#1); 36076#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 36814#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 36022#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35905#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 35906#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35971#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36294#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 36760#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 36316#L1644-2 [2023-11-19 07:37:56,858 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:56,859 INFO L85 PathProgramCache]: Analyzing trace with hash 1863040740, now seen corresponding path program 1 times [2023-11-19 07:37:56,859 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:56,859 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [281809432] [2023-11-19 07:37:56,859 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:56,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:56,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:57,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:57,003 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:57,004 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [281809432] [2023-11-19 07:37:57,004 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [281809432] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:57,004 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:57,004 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:57,004 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1611188522] [2023-11-19 07:37:57,005 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:57,005 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:37:57,005 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:57,006 INFO L85 PathProgramCache]: Analyzing trace with hash 2067663241, now seen corresponding path program 1 times [2023-11-19 07:37:57,006 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:57,006 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1814767605] [2023-11-19 07:37:57,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:57,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:57,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:57,072 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:57,072 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:57,072 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1814767605] [2023-11-19 07:37:57,073 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1814767605] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:57,073 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:57,073 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:57,073 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2042916651] [2023-11-19 07:37:57,073 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:57,074 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:37:57,074 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:57,075 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:37:57,075 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:37:57,075 INFO L87 Difference]: Start difference. First operand 1488 states and 2190 transitions. cyclomatic complexity: 703 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:57,252 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:57,252 INFO L93 Difference]: Finished difference Result 2840 states and 4171 transitions. [2023-11-19 07:37:57,252 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2840 states and 4171 transitions. [2023-11-19 07:37:57,268 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2678 [2023-11-19 07:37:57,289 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2840 states to 2840 states and 4171 transitions. [2023-11-19 07:37:57,290 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2840 [2023-11-19 07:37:57,293 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2840 [2023-11-19 07:37:57,293 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2840 states and 4171 transitions. [2023-11-19 07:37:57,297 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:57,298 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2840 states and 4171 transitions. [2023-11-19 07:37:57,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2840 states and 4171 transitions. [2023-11-19 07:37:57,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2840 to 1488. [2023-11-19 07:37:57,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4704301075268817) internal successors, (2188), 1487 states have internal predecessors, (2188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:57,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2188 transitions. [2023-11-19 07:37:57,341 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2188 transitions. [2023-11-19 07:37:57,341 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:37:57,342 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2188 transitions. [2023-11-19 07:37:57,342 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-19 07:37:57,342 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2188 transitions. [2023-11-19 07:37:57,348 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:57,348 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:57,348 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:57,351 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:57,351 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:57,352 INFO L748 eck$LassoCheckResult]: Stem: 40592#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 40593#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 41574#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41575#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41042#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 41043#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40914#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40807#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40536#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40184#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40185#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40229#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40230#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41172#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41173#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41217#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40633#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40634#L1090 assume !(0 == ~M_E~0); 40676#L1090-2 assume !(0 == ~T1_E~0); 40677#L1095-1 assume !(0 == ~T2_E~0); 41364#L1100-1 assume !(0 == ~T3_E~0); 41365#L1105-1 assume !(0 == ~T4_E~0); 40456#L1110-1 assume !(0 == ~T5_E~0); 40457#L1115-1 assume !(0 == ~T6_E~0); 40843#L1120-1 assume !(0 == ~T7_E~0); 41151#L1125-1 assume !(0 == ~T8_E~0); 41623#L1130-1 assume !(0 == ~T9_E~0); 41386#L1135-1 assume !(0 == ~T10_E~0); 40638#L1140-1 assume !(0 == ~T11_E~0); 40639#L1145-1 assume !(0 == ~E_1~0); 41320#L1150-1 assume !(0 == ~E_2~0); 40820#L1155-1 assume !(0 == ~E_3~0); 40821#L1160-1 assume !(0 == ~E_4~0); 40919#L1165-1 assume !(0 == ~E_5~0); 40920#L1170-1 assume !(0 == ~E_6~0); 41558#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 41000#L1180-1 assume !(0 == ~E_8~0); 41001#L1185-1 assume !(0 == ~E_9~0); 40635#L1190-1 assume !(0 == ~E_10~0); 40636#L1195-1 assume !(0 == ~E_11~0); 41016#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40835#L525 assume !(1 == ~m_pc~0); 40274#L525-2 is_master_triggered_~__retres1~0#1 := 0; 40275#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41460#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41433#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40625#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40626#L544 assume 1 == ~t1_pc~0; 40895#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40842#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40248#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 40249#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 40480#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41120#L563 assume !(1 == ~t2_pc~0); 41306#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 40293#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40294#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40704#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 40705#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41198#L582 assume 1 == ~t3_pc~0; 40424#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40425#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40176#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40177#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 40362#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40363#L601 assume !(1 == ~t4_pc~0); 41332#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 40844#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40372#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40373#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 41327#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41599#L620 assume 1 == ~t5_pc~0; 40321#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40322#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41214#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41465#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 41608#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41609#L639 assume !(1 == ~t6_pc~0); 41149#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 40742#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40743#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40793#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 40850#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40851#L658 assume 1 == ~t7_pc~0; 41150#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41066#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41614#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41266#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 40628#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40629#L677 assume 1 == ~t8_pc~0; 40856#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40439#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40440#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40700#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 40701#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41427#L696 assume !(1 == ~t9_pc~0); 41132#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 41133#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40905#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40906#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41156#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41369#L715 assume 1 == ~t10_pc~0; 41376#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41248#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41054#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41055#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 40994#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40433#L734 assume !(1 == ~t11_pc~0); 40434#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 40921#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41003#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40172#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 40173#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41215#L1213 assume !(1 == ~M_E~0); 40991#L1213-2 assume !(1 == ~T1_E~0); 40992#L1218-1 assume !(1 == ~T2_E~0); 40207#L1223-1 assume !(1 == ~T3_E~0); 40208#L1228-1 assume !(1 == ~T4_E~0); 40967#L1233-1 assume !(1 == ~T5_E~0); 41610#L1238-1 assume !(1 == ~T6_E~0); 41325#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41326#L1248-1 assume !(1 == ~T8_E~0); 41372#L1253-1 assume !(1 == ~T9_E~0); 41373#L1258-1 assume !(1 == ~T10_E~0); 41348#L1263-1 assume !(1 == ~T11_E~0); 41349#L1268-1 assume !(1 == ~E_1~0); 41169#L1273-1 assume !(1 == ~E_2~0); 41170#L1278-1 assume !(1 == ~E_3~0); 40740#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 40741#L1288-1 assume !(1 == ~E_5~0); 41471#L1293-1 assume !(1 == ~E_6~0); 41431#L1298-1 assume !(1 == ~E_7~0); 41202#L1303-1 assume !(1 == ~E_8~0); 40750#L1308-1 assume !(1 == ~E_9~0); 40642#L1313-1 assume !(1 == ~E_10~0); 40643#L1318-1 assume !(1 == ~E_11~0); 40650#L1323-1 assume { :end_inline_reset_delta_events } true; 40651#L1644-2 [2023-11-19 07:37:57,353 INFO L750 eck$LassoCheckResult]: Loop: 40651#L1644-2 assume !false; 41264#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40557#L1065-1 assume !false; 40558#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41606#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40289#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40866#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 40755#L906 assume !(0 != eval_~tmp~0#1); 40757#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41076#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41077#L1090-3 assume !(0 == ~M_E~0); 41486#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41543#L1095-3 assume !(0 == ~T2_E~0); 41508#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41509#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40531#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40532#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40808#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40809#L1125-3 assume !(0 == ~T8_E~0); 41324#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41581#L1135-3 assume !(0 == ~T10_E~0); 40730#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40239#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40240#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40364#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40365#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40713#L1165-3 assume !(0 == ~E_5~0); 40714#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41113#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40627#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 40388#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40389#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41569#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 41570#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40948#L525-36 assume !(1 == ~m_pc~0); 40949#L525-38 is_master_triggered_~__retres1~0#1 := 0; 40489#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40490#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 40765#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40766#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40679#L544-36 assume 1 == ~t1_pc~0; 40680#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41236#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41237#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41576#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41556#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41461#L563-36 assume 1 == ~t2_pc~0; 40478#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 40237#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40238#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41442#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40964#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40965#L582-36 assume 1 == ~t3_pc~0; 40797#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40798#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40896#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40897#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41002#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40942#L601-36 assume 1 == ~t4_pc~0; 40828#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 40829#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41094#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41095#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41547#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41448#L620-36 assume 1 == ~t5_pc~0; 40881#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40882#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41309#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40855#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 40498#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40285#L639-36 assume 1 == ~t6_pc~0; 40286#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40326#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40327#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40548#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40549#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41154#L658-36 assume !(1 == ~t7_pc~0); 40298#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 40299#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41533#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40276#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 40277#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41298#L677-36 assume 1 == ~t8_pc~0; 41475#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41070#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41199#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41200#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41096#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41097#L696-36 assume 1 == ~t9_pc~0; 40988#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40989#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40930#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40931#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41114#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41115#L715-36 assume !(1 == ~t10_pc~0); 41078#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 40174#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40175#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40150#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 40151#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40541#L734-36 assume !(1 == ~t11_pc~0); 40253#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 40254#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40559#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40166#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 40167#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41178#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 40816#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40817#L1218-3 assume !(1 == ~T2_E~0); 40589#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40590#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40769#L1233-3 assume !(1 == ~T5_E~0); 40770#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41039#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41040#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41546#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41548#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40572#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40573#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41521#L1273-3 assume !(1 == ~E_2~0); 41536#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41538#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 40917#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40918#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40763#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40764#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41260#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 40760#L1313-3 assume !(1 == ~E_10~0); 40761#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 40574#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40575#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40516#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40744#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 40745#L1663 assume !(0 == start_simulation_~tmp~3#1); 40414#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41152#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40360#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40246#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 40247#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40309#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40632#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 41098#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 40651#L1644-2 [2023-11-19 07:37:57,353 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:57,354 INFO L85 PathProgramCache]: Analyzing trace with hash -268309982, now seen corresponding path program 1 times [2023-11-19 07:37:57,354 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:57,354 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1625651917] [2023-11-19 07:37:57,354 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:57,355 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:57,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:57,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:57,442 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:57,442 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1625651917] [2023-11-19 07:37:57,442 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1625651917] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:57,442 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:57,443 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:37:57,443 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1485195736] [2023-11-19 07:37:57,443 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:57,445 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:37:57,446 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:57,446 INFO L85 PathProgramCache]: Analyzing trace with hash 17254343, now seen corresponding path program 1 times [2023-11-19 07:37:57,446 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:57,446 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1968981563] [2023-11-19 07:37:57,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:57,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:57,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:57,516 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:57,517 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:57,517 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1968981563] [2023-11-19 07:37:57,517 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1968981563] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:57,517 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:57,517 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:57,518 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1453036188] [2023-11-19 07:37:57,518 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:57,518 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:37:57,519 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:57,519 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:37:57,519 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:37:57,519 INFO L87 Difference]: Start difference. First operand 1488 states and 2188 transitions. cyclomatic complexity: 701 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:57,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:57,594 INFO L93 Difference]: Finished difference Result 1488 states and 2170 transitions. [2023-11-19 07:37:57,594 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2170 transitions. [2023-11-19 07:37:57,601 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:57,608 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2170 transitions. [2023-11-19 07:37:57,609 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-19 07:37:57,610 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-19 07:37:57,610 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2170 transitions. [2023-11-19 07:37:57,613 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:57,613 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2170 transitions. [2023-11-19 07:37:57,615 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2170 transitions. [2023-11-19 07:37:57,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-19 07:37:57,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4583333333333333) internal successors, (2170), 1487 states have internal predecessors, (2170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:57,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2170 transitions. [2023-11-19 07:37:57,645 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2170 transitions. [2023-11-19 07:37:57,645 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:37:57,646 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2170 transitions. [2023-11-19 07:37:57,646 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-19 07:37:57,646 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2170 transitions. [2023-11-19 07:37:57,652 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-19 07:37:57,652 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:57,652 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:57,655 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:57,655 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:57,656 INFO L748 eck$LassoCheckResult]: Stem: 43575#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 43576#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 44557#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44558#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44024#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 44025#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43897#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43790#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43519#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43167#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43168#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43212#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 43213#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44155#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44156#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 44200#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 43616#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43617#L1090 assume !(0 == ~M_E~0); 43659#L1090-2 assume !(0 == ~T1_E~0); 43660#L1095-1 assume !(0 == ~T2_E~0); 44347#L1100-1 assume !(0 == ~T3_E~0); 44348#L1105-1 assume !(0 == ~T4_E~0); 43439#L1110-1 assume !(0 == ~T5_E~0); 43440#L1115-1 assume !(0 == ~T6_E~0); 43826#L1120-1 assume !(0 == ~T7_E~0); 44133#L1125-1 assume !(0 == ~T8_E~0); 44606#L1130-1 assume !(0 == ~T9_E~0); 44369#L1135-1 assume !(0 == ~T10_E~0); 43621#L1140-1 assume !(0 == ~T11_E~0); 43622#L1145-1 assume !(0 == ~E_1~0); 44303#L1150-1 assume !(0 == ~E_2~0); 43803#L1155-1 assume !(0 == ~E_3~0); 43804#L1160-1 assume !(0 == ~E_4~0); 43902#L1165-1 assume !(0 == ~E_5~0); 43903#L1170-1 assume !(0 == ~E_6~0); 44541#L1175-1 assume !(0 == ~E_7~0); 43982#L1180-1 assume !(0 == ~E_8~0); 43983#L1185-1 assume !(0 == ~E_9~0); 43618#L1190-1 assume !(0 == ~E_10~0); 43619#L1195-1 assume !(0 == ~E_11~0); 43998#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43818#L525 assume !(1 == ~m_pc~0); 43257#L525-2 is_master_triggered_~__retres1~0#1 := 0; 43258#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44443#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 44416#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43608#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43609#L544 assume 1 == ~t1_pc~0; 43878#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 43825#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43231#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 43232#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 43463#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44102#L563 assume !(1 == ~t2_pc~0); 44289#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 43276#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43277#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43687#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 43688#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44181#L582 assume 1 == ~t3_pc~0; 43407#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43408#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43159#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43160#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 43345#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43346#L601 assume !(1 == ~t4_pc~0); 44315#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43827#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43357#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43358#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 44310#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44582#L620 assume 1 == ~t5_pc~0; 43304#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43305#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44197#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44448#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 44591#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44592#L639 assume !(1 == ~t6_pc~0); 44131#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 43725#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43726#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43776#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 43833#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43834#L658 assume !(1 == ~t7_pc~0); 44047#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 44048#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44597#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44249#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 43611#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43612#L677 assume 1 == ~t8_pc~0; 43839#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43422#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43423#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43683#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 43684#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44410#L696 assume !(1 == ~t9_pc~0); 44114#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 44115#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43888#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43889#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 44138#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44352#L715 assume 1 == ~t10_pc~0; 44359#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44231#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44036#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44037#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 43976#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43416#L734 assume !(1 == ~t11_pc~0); 43417#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 43904#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43985#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43155#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 43156#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44198#L1213 assume !(1 == ~M_E~0); 43973#L1213-2 assume !(1 == ~T1_E~0); 43974#L1218-1 assume !(1 == ~T2_E~0); 43190#L1223-1 assume !(1 == ~T3_E~0); 43191#L1228-1 assume !(1 == ~T4_E~0); 43949#L1233-1 assume !(1 == ~T5_E~0); 44593#L1238-1 assume !(1 == ~T6_E~0); 44308#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44309#L1248-1 assume !(1 == ~T8_E~0); 44355#L1253-1 assume !(1 == ~T9_E~0); 44356#L1258-1 assume !(1 == ~T10_E~0); 44331#L1263-1 assume !(1 == ~T11_E~0); 44332#L1268-1 assume !(1 == ~E_1~0); 44152#L1273-1 assume !(1 == ~E_2~0); 44153#L1278-1 assume !(1 == ~E_3~0); 43723#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 43724#L1288-1 assume !(1 == ~E_5~0); 44454#L1293-1 assume !(1 == ~E_6~0); 44414#L1298-1 assume !(1 == ~E_7~0); 44185#L1303-1 assume !(1 == ~E_8~0); 43733#L1308-1 assume !(1 == ~E_9~0); 43625#L1313-1 assume !(1 == ~E_10~0); 43626#L1318-1 assume !(1 == ~E_11~0); 43633#L1323-1 assume { :end_inline_reset_delta_events } true; 43634#L1644-2 [2023-11-19 07:37:57,656 INFO L750 eck$LassoCheckResult]: Loop: 43634#L1644-2 assume !false; 44247#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43540#L1065-1 assume !false; 43541#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 44589#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 43272#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 43849#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 43738#L906 assume !(0 != eval_~tmp~0#1); 43740#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44058#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44059#L1090-3 assume !(0 == ~M_E~0); 44469#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44526#L1095-3 assume !(0 == ~T2_E~0); 44491#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44492#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43514#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 43515#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43791#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 43792#L1125-3 assume !(0 == ~T8_E~0); 44307#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44564#L1135-3 assume !(0 == ~T10_E~0); 43713#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43222#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43223#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43348#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 43349#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 43696#L1165-3 assume !(0 == ~E_5~0); 43697#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44095#L1175-3 assume !(0 == ~E_7~0); 43610#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 43371#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 43372#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 44552#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 44553#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43930#L525-36 assume !(1 == ~m_pc~0); 43931#L525-38 is_master_triggered_~__retres1~0#1 := 0; 43472#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43473#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 43748#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43749#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43662#L544-36 assume !(1 == ~t1_pc~0); 43664#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 44219#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44220#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 44559#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44539#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44444#L563-36 assume 1 == ~t2_pc~0; 43461#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43220#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43221#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 44425#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 43946#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43947#L582-36 assume 1 == ~t3_pc~0; 43780#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43781#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43879#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43880#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43984#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43924#L601-36 assume 1 == ~t4_pc~0; 43811#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43812#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44076#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44077#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44530#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44431#L620-36 assume 1 == ~t5_pc~0; 43864#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43865#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44292#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43838#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 43481#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43268#L639-36 assume 1 == ~t6_pc~0; 43269#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43309#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43310#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43531#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43532#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44136#L658-36 assume !(1 == ~t7_pc~0); 43281#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 43282#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44516#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43259#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 43260#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44281#L677-36 assume !(1 == ~t8_pc~0); 44051#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 44052#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44182#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44183#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44078#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44079#L696-36 assume 1 == ~t9_pc~0; 43970#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43971#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43913#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43914#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 44096#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44097#L715-36 assume 1 == ~t10_pc~0; 44242#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 43157#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43158#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43135#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 43136#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43524#L734-36 assume !(1 == ~t11_pc~0); 43236#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 43237#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43542#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43149#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43150#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44161#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 43799#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 43800#L1218-3 assume !(1 == ~T2_E~0); 43572#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43573#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43752#L1233-3 assume !(1 == ~T5_E~0); 43753#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44021#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44022#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 44529#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 44531#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43555#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43556#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44504#L1273-3 assume !(1 == ~E_2~0); 44519#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44521#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43900#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43901#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43746#L1298-3 assume !(1 == ~E_7~0); 43747#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 44243#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43743#L1313-3 assume !(1 == ~E_10~0); 43744#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 43557#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 43558#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 43499#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 43727#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 43728#L1663 assume !(0 == start_simulation_~tmp~3#1); 43390#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 44134#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 43343#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 43226#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 43227#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 43289#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43615#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 44080#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 43634#L1644-2 [2023-11-19 07:37:57,657 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:57,657 INFO L85 PathProgramCache]: Analyzing trace with hash -2032217409, now seen corresponding path program 1 times [2023-11-19 07:37:57,658 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:57,658 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1455403740] [2023-11-19 07:37:57,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:57,658 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:57,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:57,743 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:57,743 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:57,743 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1455403740] [2023-11-19 07:37:57,743 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1455403740] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:57,743 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:57,744 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:37:57,744 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [123674542] [2023-11-19 07:37:57,744 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:57,744 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:37:57,745 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:57,745 INFO L85 PathProgramCache]: Analyzing trace with hash -884328670, now seen corresponding path program 1 times [2023-11-19 07:37:57,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:57,745 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1314959374] [2023-11-19 07:37:57,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:57,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:57,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:57,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:57,841 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:57,841 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1314959374] [2023-11-19 07:37:57,841 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1314959374] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:57,841 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:57,842 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:57,842 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [668645596] [2023-11-19 07:37:57,842 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:57,843 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:37:57,843 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:57,843 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 07:37:57,843 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 07:37:57,844 INFO L87 Difference]: Start difference. First operand 1488 states and 2170 transitions. cyclomatic complexity: 683 Second operand has 5 states, 5 states have (on average 27.4) internal successors, (137), 5 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:58,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:58,321 INFO L93 Difference]: Finished difference Result 3985 states and 5734 transitions. [2023-11-19 07:37:58,321 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3985 states and 5734 transitions. [2023-11-19 07:37:58,347 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3653 [2023-11-19 07:37:58,370 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3985 states to 3985 states and 5734 transitions. [2023-11-19 07:37:58,371 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3985 [2023-11-19 07:37:58,375 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3985 [2023-11-19 07:37:58,376 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3985 states and 5734 transitions. [2023-11-19 07:37:58,382 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:58,383 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3985 states and 5734 transitions. [2023-11-19 07:37:58,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3985 states and 5734 transitions. [2023-11-19 07:37:58,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3985 to 1530. [2023-11-19 07:37:58,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1530 states, 1530 states have (on average 1.445751633986928) internal successors, (2212), 1529 states have internal predecessors, (2212), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:58,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1530 states to 1530 states and 2212 transitions. [2023-11-19 07:37:58,448 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1530 states and 2212 transitions. [2023-11-19 07:37:58,448 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-19 07:37:58,449 INFO L428 stractBuchiCegarLoop]: Abstraction has 1530 states and 2212 transitions. [2023-11-19 07:37:58,449 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-19 07:37:58,449 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1530 states and 2212 transitions. [2023-11-19 07:37:58,457 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1378 [2023-11-19 07:37:58,457 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:58,457 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:58,461 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:58,461 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:58,461 INFO L748 eck$LassoCheckResult]: Stem: 49062#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 49063#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 50070#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50071#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49517#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 49518#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49389#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49280#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49006#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48653#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48654#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48698#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48699#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49650#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49651#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49695#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49105#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49106#L1090 assume !(0 == ~M_E~0); 49148#L1090-2 assume !(0 == ~T1_E~0); 49149#L1095-1 assume !(0 == ~T2_E~0); 49846#L1100-1 assume !(0 == ~T3_E~0); 49847#L1105-1 assume !(0 == ~T4_E~0); 48925#L1110-1 assume !(0 == ~T5_E~0); 48926#L1115-1 assume !(0 == ~T6_E~0); 49316#L1120-1 assume !(0 == ~T7_E~0); 49628#L1125-1 assume !(0 == ~T8_E~0); 50129#L1130-1 assume !(0 == ~T9_E~0); 49869#L1135-1 assume !(0 == ~T10_E~0); 49110#L1140-1 assume !(0 == ~T11_E~0); 49111#L1145-1 assume !(0 == ~E_1~0); 49801#L1150-1 assume !(0 == ~E_2~0); 49293#L1155-1 assume !(0 == ~E_3~0); 49294#L1160-1 assume !(0 == ~E_4~0); 49394#L1165-1 assume !(0 == ~E_5~0); 49395#L1170-1 assume !(0 == ~E_6~0); 50053#L1175-1 assume !(0 == ~E_7~0); 49475#L1180-1 assume !(0 == ~E_8~0); 49476#L1185-1 assume !(0 == ~E_9~0); 49107#L1190-1 assume !(0 == ~E_10~0); 49108#L1195-1 assume !(0 == ~E_11~0); 49491#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49308#L525 assume !(1 == ~m_pc~0); 48743#L525-2 is_master_triggered_~__retres1~0#1 := 0; 48744#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50025#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49918#L1350 assume !(0 != activate_threads_~tmp~1#1); 49096#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49097#L544 assume 1 == ~t1_pc~0; 49368#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49315#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48717#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 48718#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 48949#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49596#L563 assume !(1 == ~t2_pc~0); 49787#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 48762#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48763#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49176#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 49177#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49676#L582 assume 1 == ~t3_pc~0; 48893#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 48894#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48645#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48646#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 48831#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48832#L601 assume !(1 == ~t4_pc~0); 49813#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49317#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48841#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48842#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 49808#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50101#L620 assume 1 == ~t5_pc~0; 48790#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48791#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49692#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49952#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 50113#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50114#L639 assume !(1 == ~t6_pc~0); 49626#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 49215#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49216#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49266#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 49323#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49324#L658 assume !(1 == ~t7_pc~0); 49540#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 49541#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50119#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49746#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 49100#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49101#L677 assume 1 == ~t8_pc~0; 49329#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 48908#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48909#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49172#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 49173#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49912#L696 assume !(1 == ~t9_pc~0); 49608#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 49609#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49378#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49379#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49633#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49851#L715 assume 1 == ~t10_pc~0; 49859#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49726#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49529#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49530#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 49469#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48902#L734 assume !(1 == ~t11_pc~0); 48903#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 49396#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49478#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48641#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 48642#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49693#L1213 assume !(1 == ~M_E~0); 49466#L1213-2 assume !(1 == ~T1_E~0); 49467#L1218-1 assume !(1 == ~T2_E~0); 48676#L1223-1 assume !(1 == ~T3_E~0); 48677#L1228-1 assume !(1 == ~T4_E~0); 49441#L1233-1 assume !(1 == ~T5_E~0); 50115#L1238-1 assume !(1 == ~T6_E~0); 49806#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49807#L1248-1 assume !(1 == ~T8_E~0); 49855#L1253-1 assume !(1 == ~T9_E~0); 49856#L1258-1 assume !(1 == ~T10_E~0); 49829#L1263-1 assume !(1 == ~T11_E~0); 49830#L1268-1 assume !(1 == ~E_1~0); 49647#L1273-1 assume !(1 == ~E_2~0); 49648#L1278-1 assume !(1 == ~E_3~0); 49213#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 49214#L1288-1 assume !(1 == ~E_5~0); 49958#L1293-1 assume !(1 == ~E_6~0); 49916#L1298-1 assume !(1 == ~E_7~0); 49680#L1303-1 assume !(1 == ~E_8~0); 49223#L1308-1 assume !(1 == ~E_9~0); 49114#L1313-1 assume !(1 == ~E_10~0); 49115#L1318-1 assume !(1 == ~E_11~0); 49122#L1323-1 assume { :end_inline_reset_delta_events } true; 49123#L1644-2 [2023-11-19 07:37:58,462 INFO L750 eck$LassoCheckResult]: Loop: 49123#L1644-2 assume !false; 49744#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49027#L1065-1 assume !false; 49028#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 50111#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 48758#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49339#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49228#L906 assume !(0 != eval_~tmp~0#1); 49230#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49551#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49552#L1090-3 assume !(0 == ~M_E~0); 49974#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50035#L1095-3 assume !(0 == ~T2_E~0); 49998#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 49999#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49001#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49002#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49281#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49282#L1125-3 assume !(0 == ~T8_E~0); 49805#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50079#L1135-3 assume !(0 == ~T10_E~0); 49202#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 48708#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 48709#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48833#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 48834#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 49185#L1165-3 assume !(0 == ~E_5~0); 49186#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 49589#L1175-3 assume !(0 == ~E_7~0); 49099#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 48857#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 48858#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 50064#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 50065#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49422#L525-36 assume 1 == ~m_pc~0; 49424#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50067#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50074#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 50075#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 49239#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49151#L544-36 assume 1 == ~t1_pc~0; 49152#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49714#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49715#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50072#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50051#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49948#L563-36 assume 1 == ~t2_pc~0; 48947#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 48706#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48707#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49927#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49438#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49439#L582-36 assume 1 == ~t3_pc~0; 49270#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49271#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49369#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49370#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49477#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49416#L601-36 assume 1 == ~t4_pc~0; 49301#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49302#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49569#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49570#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50040#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49934#L620-36 assume 1 == ~t5_pc~0; 49354#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49355#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49790#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49328#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 48968#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48754#L639-36 assume 1 == ~t6_pc~0; 48755#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 48795#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48796#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49018#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49019#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49631#L658-36 assume !(1 == ~t7_pc~0); 48767#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 48768#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50024#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48745#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 48746#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49779#L677-36 assume !(1 == ~t8_pc~0); 49544#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 49545#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49677#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49678#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49571#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49572#L696-36 assume 1 == ~t9_pc~0; 49463#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49464#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49405#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49406#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49590#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49591#L715-36 assume !(1 == ~t10_pc~0); 49553#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 48643#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48644#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48619#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48620#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49011#L734-36 assume !(1 == ~t11_pc~0); 48722#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 48723#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49029#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48635#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 48636#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49656#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49289#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49290#L1218-3 assume !(1 == ~T2_E~0); 49059#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49060#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49242#L1233-3 assume !(1 == ~T5_E~0); 49243#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49514#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49515#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50039#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50041#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 49042#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 49043#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50011#L1273-3 assume !(1 == ~E_2~0); 50028#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50030#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49392#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49393#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49236#L1298-3 assume !(1 == ~E_7~0); 49237#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49739#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 49233#L1313-3 assume !(1 == ~E_10~0); 49234#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 49044#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49045#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 48986#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49217#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 49218#L1663 assume !(0 == start_simulation_~tmp~3#1); 48883#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49629#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 48829#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 48715#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 48716#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48778#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49104#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 49574#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 49123#L1644-2 [2023-11-19 07:37:58,463 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:58,463 INFO L85 PathProgramCache]: Analyzing trace with hash -2060717699, now seen corresponding path program 1 times [2023-11-19 07:37:58,463 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:58,463 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2102937450] [2023-11-19 07:37:58,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:58,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:58,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:58,553 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:58,553 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:58,553 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2102937450] [2023-11-19 07:37:58,553 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2102937450] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:58,553 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:58,554 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:58,554 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1146995754] [2023-11-19 07:37:58,554 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:58,554 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:37:58,555 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:58,555 INFO L85 PathProgramCache]: Analyzing trace with hash -1434729917, now seen corresponding path program 1 times [2023-11-19 07:37:58,555 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:58,555 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [184715706] [2023-11-19 07:37:58,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:58,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:58,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:58,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:58,622 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:58,622 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [184715706] [2023-11-19 07:37:58,622 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [184715706] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:58,623 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:58,623 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:58,623 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [238259631] [2023-11-19 07:37:58,623 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:58,624 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:37:58,624 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:58,624 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:37:58,624 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:37:58,625 INFO L87 Difference]: Start difference. First operand 1530 states and 2212 transitions. cyclomatic complexity: 683 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:58,947 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:58,947 INFO L93 Difference]: Finished difference Result 4104 states and 5862 transitions. [2023-11-19 07:37:58,948 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4104 states and 5862 transitions. [2023-11-19 07:37:58,970 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3864 [2023-11-19 07:37:58,997 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4104 states to 4104 states and 5862 transitions. [2023-11-19 07:37:58,998 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4104 [2023-11-19 07:37:59,003 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4104 [2023-11-19 07:37:59,003 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4104 states and 5862 transitions. [2023-11-19 07:37:59,010 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:59,010 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4104 states and 5862 transitions. [2023-11-19 07:37:59,017 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4104 states and 5862 transitions. [2023-11-19 07:37:59,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4104 to 3938. [2023-11-19 07:37:59,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3938 states, 3938 states have (on average 1.430929405789741) internal successors, (5635), 3937 states have internal predecessors, (5635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:59,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3938 states to 3938 states and 5635 transitions. [2023-11-19 07:37:59,163 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3938 states and 5635 transitions. [2023-11-19 07:37:59,163 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:37:59,165 INFO L428 stractBuchiCegarLoop]: Abstraction has 3938 states and 5635 transitions. [2023-11-19 07:37:59,165 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-19 07:37:59,165 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3938 states and 5635 transitions. [2023-11-19 07:37:59,179 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3786 [2023-11-19 07:37:59,180 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:37:59,180 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:37:59,182 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:59,183 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:37:59,183 INFO L748 eck$LassoCheckResult]: Stem: 54707#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 54708#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 55741#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55742#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55164#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 55165#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55036#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 54926#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54650#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54297#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54298#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54342#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 54343#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 55300#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 55301#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 55345#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 54752#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54753#L1090 assume !(0 == ~M_E~0); 54796#L1090-2 assume !(0 == ~T1_E~0); 54797#L1095-1 assume !(0 == ~T2_E~0); 55498#L1100-1 assume !(0 == ~T3_E~0); 55499#L1105-1 assume !(0 == ~T4_E~0); 54569#L1110-1 assume !(0 == ~T5_E~0); 54570#L1115-1 assume !(0 == ~T6_E~0); 54965#L1120-1 assume !(0 == ~T7_E~0); 55278#L1125-1 assume !(0 == ~T8_E~0); 55811#L1130-1 assume !(0 == ~T9_E~0); 55527#L1135-1 assume !(0 == ~T10_E~0); 54757#L1140-1 assume !(0 == ~T11_E~0); 54758#L1145-1 assume !(0 == ~E_1~0); 55452#L1150-1 assume !(0 == ~E_2~0); 54940#L1155-1 assume !(0 == ~E_3~0); 54941#L1160-1 assume !(0 == ~E_4~0); 55041#L1165-1 assume !(0 == ~E_5~0); 55042#L1170-1 assume !(0 == ~E_6~0); 55720#L1175-1 assume !(0 == ~E_7~0); 55122#L1180-1 assume !(0 == ~E_8~0); 55123#L1185-1 assume !(0 == ~E_9~0); 54754#L1190-1 assume !(0 == ~E_10~0); 54755#L1195-1 assume !(0 == ~E_11~0); 55138#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54957#L525 assume !(1 == ~m_pc~0); 54387#L525-2 is_master_triggered_~__retres1~0#1 := 0; 54388#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55607#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 55580#L1350 assume !(0 != activate_threads_~tmp~1#1); 54742#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54743#L544 assume !(1 == ~t1_pc~0); 54963#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 54964#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54361#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 54362#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 54592#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55246#L563 assume !(1 == ~t2_pc~0); 55438#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 54406#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54407#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 54824#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 54825#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55326#L582 assume 1 == ~t3_pc~0; 54537#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 54538#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54289#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54290#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 54475#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54476#L601 assume !(1 == ~t4_pc~0); 55465#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 54966#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54485#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54486#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 55460#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55782#L620 assume 1 == ~t5_pc~0; 54434#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54435#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55342#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 55612#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 55794#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55795#L639 assume !(1 == ~t6_pc~0); 55276#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 54860#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54861#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54912#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 54971#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54972#L658 assume !(1 == ~t7_pc~0); 55187#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 55188#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55800#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 55395#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 54747#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54748#L677 assume 1 == ~t8_pc~0; 54978#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54552#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54553#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54820#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 54821#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 55570#L696 assume !(1 == ~t9_pc~0); 55258#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 55259#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 55026#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55027#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 55283#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55503#L715 assume 1 == ~t10_pc~0; 55515#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 55375#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 55176#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 55177#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 55115#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54546#L734 assume !(1 == ~t11_pc~0); 54547#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 55043#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 55125#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54285#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 54286#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55343#L1213 assume !(1 == ~M_E~0); 55112#L1213-2 assume !(1 == ~T1_E~0); 55113#L1218-1 assume !(1 == ~T2_E~0); 54320#L1223-1 assume !(1 == ~T3_E~0); 54321#L1228-1 assume !(1 == ~T4_E~0); 55088#L1233-1 assume !(1 == ~T5_E~0); 55796#L1238-1 assume !(1 == ~T6_E~0); 55458#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 55459#L1248-1 assume !(1 == ~T8_E~0); 55510#L1253-1 assume !(1 == ~T9_E~0); 55511#L1258-1 assume !(1 == ~T10_E~0); 55481#L1263-1 assume !(1 == ~T11_E~0); 55482#L1268-1 assume !(1 == ~E_1~0); 55297#L1273-1 assume !(1 == ~E_2~0); 55298#L1278-1 assume !(1 == ~E_3~0); 54858#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 54859#L1288-1 assume !(1 == ~E_5~0); 55621#L1293-1 assume !(1 == ~E_6~0); 55575#L1298-1 assume !(1 == ~E_7~0); 55330#L1303-1 assume !(1 == ~E_8~0); 54869#L1308-1 assume !(1 == ~E_9~0); 54761#L1313-1 assume !(1 == ~E_10~0); 54762#L1318-1 assume !(1 == ~E_11~0); 54769#L1323-1 assume { :end_inline_reset_delta_events } true; 54770#L1644-2 [2023-11-19 07:37:59,184 INFO L750 eck$LassoCheckResult]: Loop: 54770#L1644-2 assume !false; 55393#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 54671#L1065-1 assume !false; 54672#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 55792#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 54402#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 54988#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 54874#L906 assume !(0 != eval_~tmp~0#1); 54876#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 55199#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 55200#L1090-3 assume !(0 == ~M_E~0); 55641#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 55701#L1095-3 assume !(0 == ~T2_E~0); 55666#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55667#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54644#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 54645#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 54927#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 54928#L1125-3 assume !(0 == ~T8_E~0); 55457#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 55752#L1135-3 assume !(0 == ~T10_E~0); 54849#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 54352#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 54353#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54477#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54478#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 54833#L1165-3 assume !(0 == ~E_5~0); 54834#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 55239#L1175-3 assume !(0 == ~E_7~0); 54746#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 54501#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 54502#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 55733#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 55734#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55070#L525-36 assume !(1 == ~m_pc~0); 55071#L525-38 is_master_triggered_~__retres1~0#1 := 0; 54601#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54602#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 54884#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 54885#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54801#L544-36 assume !(1 == ~t1_pc~0); 54802#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 55363#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55364#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 55743#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 55718#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55608#L563-36 assume 1 == ~t2_pc~0; 54590#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54350#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54351#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 55589#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 55085#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55086#L582-36 assume 1 == ~t3_pc~0; 54916#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 54917#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55017#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 55018#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 55124#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55064#L601-36 assume 1 == ~t4_pc~0; 54950#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54951#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55218#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55219#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 55707#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55595#L620-36 assume 1 == ~t5_pc~0; 55003#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 55004#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55441#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54977#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 54610#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54398#L639-36 assume !(1 == ~t6_pc~0); 54400#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 54439#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54440#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54660#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54661#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 55281#L658-36 assume !(1 == ~t7_pc~0); 54411#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 54412#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55691#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54389#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 54390#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 55429#L677-36 assume !(1 == ~t8_pc~0); 55191#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 55192#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 55327#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 55328#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 55220#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 55221#L696-36 assume 1 == ~t9_pc~0; 55109#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 55110#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 55053#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55054#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 55240#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55241#L715-36 assume !(1 == ~t10_pc~0); 55201#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 54287#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54288#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54263#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 54264#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54655#L734-36 assume 1 == ~t11_pc~0; 54656#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 54367#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54673#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54279#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 54280#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55306#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 54936#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54937#L1218-3 assume !(1 == ~T2_E~0); 54704#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54705#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54888#L1233-3 assume !(1 == ~T5_E~0); 54889#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 55161#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 55162#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 55706#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 55708#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54686#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 54687#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 55679#L1273-3 assume !(1 == ~E_2~0); 55694#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 55696#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 55039#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 55040#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 54882#L1298-3 assume !(1 == ~E_7~0); 54883#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 55388#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 54879#L1313-3 assume !(1 == ~E_10~0); 54880#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 54688#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 54689#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 54628#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 54862#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 54863#L1663 assume !(0 == start_simulation_~tmp~3#1); 54527#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 55279#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 54473#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 54359#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 54360#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54422#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54751#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 55223#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 54770#L1644-2 [2023-11-19 07:37:59,184 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:59,184 INFO L85 PathProgramCache]: Analyzing trace with hash -2098164388, now seen corresponding path program 1 times [2023-11-19 07:37:59,185 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:59,185 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [423039124] [2023-11-19 07:37:59,185 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:59,185 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:59,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:59,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:59,272 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:59,272 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [423039124] [2023-11-19 07:37:59,272 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [423039124] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:59,272 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:59,272 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:59,273 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1533643243] [2023-11-19 07:37:59,273 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:59,273 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:37:59,273 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:37:59,274 INFO L85 PathProgramCache]: Analyzing trace with hash -687068353, now seen corresponding path program 1 times [2023-11-19 07:37:59,274 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:37:59,274 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1111476293] [2023-11-19 07:37:59,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:37:59,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:37:59,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:37:59,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:37:59,337 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:37:59,337 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1111476293] [2023-11-19 07:37:59,337 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1111476293] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:37:59,337 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:37:59,337 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:37:59,338 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [971197883] [2023-11-19 07:37:59,338 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:37:59,338 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:37:59,338 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:37:59,339 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:37:59,339 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:37:59,339 INFO L87 Difference]: Start difference. First operand 3938 states and 5635 transitions. cyclomatic complexity: 1699 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:37:59,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:37:59,687 INFO L93 Difference]: Finished difference Result 11017 states and 15627 transitions. [2023-11-19 07:37:59,688 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11017 states and 15627 transitions. [2023-11-19 07:37:59,739 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10667 [2023-11-19 07:37:59,778 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11017 states to 11017 states and 15627 transitions. [2023-11-19 07:37:59,778 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11017 [2023-11-19 07:37:59,789 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11017 [2023-11-19 07:37:59,790 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11017 states and 15627 transitions. [2023-11-19 07:37:59,801 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:37:59,801 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11017 states and 15627 transitions. [2023-11-19 07:37:59,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11017 states and 15627 transitions. [2023-11-19 07:38:00,087 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11017 to 10636. [2023-11-19 07:38:00,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10636 states, 10636 states have (on average 1.4207408800300865) internal successors, (15111), 10635 states have internal predecessors, (15111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:38:00,152 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10636 states to 10636 states and 15111 transitions. [2023-11-19 07:38:00,152 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10636 states and 15111 transitions. [2023-11-19 07:38:00,153 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:38:00,154 INFO L428 stractBuchiCegarLoop]: Abstraction has 10636 states and 15111 transitions. [2023-11-19 07:38:00,154 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-19 07:38:00,154 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10636 states and 15111 transitions. [2023-11-19 07:38:00,185 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10475 [2023-11-19 07:38:00,186 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:38:00,186 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:38:00,189 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:38:00,189 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:38:00,189 INFO L748 eck$LassoCheckResult]: Stem: 69673#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 69674#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 70803#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 70804#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 70149#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 70150#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 70014#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69900#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69614#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69262#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 69263#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 69307#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 69308#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 70301#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 70302#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 70354#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 69721#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 69722#L1090 assume !(0 == ~M_E~0); 69772#L1090-2 assume !(0 == ~T1_E~0); 69773#L1095-1 assume !(0 == ~T2_E~0); 70518#L1100-1 assume !(0 == ~T3_E~0); 70519#L1105-1 assume !(0 == ~T4_E~0); 69533#L1110-1 assume !(0 == ~T5_E~0); 69534#L1115-1 assume !(0 == ~T6_E~0); 69940#L1120-1 assume !(0 == ~T7_E~0); 70273#L1125-1 assume !(0 == ~T8_E~0); 70942#L1130-1 assume !(0 == ~T9_E~0); 70544#L1135-1 assume !(0 == ~T10_E~0); 69728#L1140-1 assume !(0 == ~T11_E~0); 69729#L1145-1 assume !(0 == ~E_1~0); 70466#L1150-1 assume !(0 == ~E_2~0); 69914#L1155-1 assume !(0 == ~E_3~0); 69915#L1160-1 assume !(0 == ~E_4~0); 70019#L1165-1 assume !(0 == ~E_5~0); 70020#L1170-1 assume !(0 == ~E_6~0); 70772#L1175-1 assume !(0 == ~E_7~0); 70102#L1180-1 assume !(0 == ~E_8~0); 70103#L1185-1 assume !(0 == ~E_9~0); 69723#L1190-1 assume !(0 == ~E_10~0); 69724#L1195-1 assume !(0 == ~E_11~0); 70118#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69933#L525 assume !(1 == ~m_pc~0); 69351#L525-2 is_master_triggered_~__retres1~0#1 := 0; 69352#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 70635#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 70605#L1350 assume !(0 != activate_threads_~tmp~1#1); 69712#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69713#L544 assume !(1 == ~t1_pc~0); 69936#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 69937#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69328#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 69329#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 69556#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70240#L563 assume !(1 == ~t2_pc~0); 70452#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 69370#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69371#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 69795#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 69796#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70326#L582 assume !(1 == ~t3_pc~0); 70465#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 70878#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69254#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 69255#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 69441#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69442#L601 assume !(1 == ~t4_pc~0); 70482#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 69941#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69453#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 69454#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 70475#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 70863#L620 assume 1 == ~t5_pc~0; 69400#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 69401#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70343#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 70642#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 70898#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70899#L639 assume !(1 == ~t6_pc~0); 70271#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 69834#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69835#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69885#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 69946#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69947#L658 assume !(1 == ~t7_pc~0); 70173#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 70174#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 70915#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 70402#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 69716#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 69717#L677 assume 1 == ~t8_pc~0; 69951#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 69521#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 69522#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 69791#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 69792#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 70594#L696 assume !(1 == ~t9_pc~0); 70254#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 70255#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 70002#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 70003#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 70280#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 70523#L715 assume 1 == ~t10_pc~0; 70532#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 70381#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 70161#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 70162#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 70095#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69509#L734 assume !(1 == ~t11_pc~0); 69510#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 70022#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 70105#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69252#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 69253#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70344#L1213 assume !(1 == ~M_E~0); 70093#L1213-2 assume !(1 == ~T1_E~0); 70094#L1218-1 assume !(1 == ~T2_E~0); 69285#L1223-1 assume !(1 == ~T3_E~0); 69286#L1228-1 assume !(1 == ~T4_E~0); 70069#L1233-1 assume !(1 == ~T5_E~0); 70900#L1238-1 assume !(1 == ~T6_E~0); 70473#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 70474#L1248-1 assume !(1 == ~T8_E~0); 70528#L1253-1 assume !(1 == ~T9_E~0); 70529#L1258-1 assume !(1 == ~T10_E~0); 70500#L1263-1 assume !(1 == ~T11_E~0); 70501#L1268-1 assume !(1 == ~E_1~0); 70296#L1273-1 assume !(1 == ~E_2~0); 70297#L1278-1 assume !(1 == ~E_3~0); 69830#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 69831#L1288-1 assume !(1 == ~E_5~0); 70650#L1293-1 assume !(1 == ~E_6~0); 70603#L1298-1 assume !(1 == ~E_7~0); 70331#L1303-1 assume !(1 == ~E_8~0); 69842#L1308-1 assume !(1 == ~E_9~0); 69732#L1313-1 assume !(1 == ~E_10~0); 69733#L1318-1 assume !(1 == ~E_11~0); 69740#L1323-1 assume { :end_inline_reset_delta_events } true; 69741#L1644-2 [2023-11-19 07:38:00,190 INFO L750 eck$LassoCheckResult]: Loop: 69741#L1644-2 assume !false; 79123#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 69636#L1065-1 assume !false; 69637#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 78156#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 78145#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 78144#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 69847#L906 assume !(0 != eval_~tmp~0#1); 69849#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 79554#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 70677#L1090-3 assume !(0 == ~M_E~0); 70678#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 79553#L1095-3 assume !(0 == ~T2_E~0); 70702#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 70703#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 69609#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 69610#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 69901#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 69902#L1125-3 assume !(0 == ~T8_E~0); 70814#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 70815#L1135-3 assume !(0 == ~T10_E~0); 69820#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 69821#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 79552#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 69443#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 69444#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 69806#L1165-3 assume !(0 == ~E_5~0); 69807#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 70998#L1175-3 assume !(0 == ~E_7~0); 69714#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 69715#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 70922#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 70923#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 79550#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 70047#L525-36 assume !(1 == ~m_pc~0); 70048#L525-38 is_master_triggered_~__retres1~0#1 := 0; 79107#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 79108#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 79103#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 79104#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69770#L544-36 assume !(1 == ~t1_pc~0); 69771#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 79549#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70801#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 70802#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 70908#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70636#L563-36 assume 1 == ~t2_pc~0; 69553#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 69554#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 70615#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 70616#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 70907#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 79544#L582-36 assume !(1 == ~t3_pc~0); 70664#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 70147#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70148#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 79542#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 70104#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70041#L601-36 assume !(1 == ~t4_pc~0); 70043#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 70994#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70995#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 70750#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 70751#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 70622#L620-36 assume 1 == ~t5_pc~0; 69980#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 69981#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70458#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69950#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 69575#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69362#L639-36 assume 1 == ~t6_pc~0; 69363#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69398#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69399#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69625#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 69626#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 70853#L658-36 assume !(1 == ~t7_pc~0); 69372#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 69373#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 70730#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69353#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 69354#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 70438#L677-36 assume !(1 == ~t8_pc~0); 70178#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 70179#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 70327#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 70852#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 70212#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 70213#L696-36 assume 1 == ~t9_pc~0; 70089#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 70090#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 70030#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 70031#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 70234#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 70235#L715-36 assume !(1 == ~t10_pc~0); 70192#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 70193#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69840#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 69841#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 79431#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 79429#L734-36 assume 1 == ~t11_pc~0; 79427#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 79424#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 79422#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69244#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 69245#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70305#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 70794#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 79412#L1218-3 assume !(1 == ~T2_E~0); 79410#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 79408#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 79406#L1233-3 assume !(1 == ~T5_E~0); 79405#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 78125#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 78124#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 78123#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 78122#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 78121#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 78120#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 78119#L1273-3 assume !(1 == ~E_2~0); 78117#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 78118#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 78674#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 78672#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 78112#L1298-3 assume !(1 == ~E_7~0); 78111#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 78110#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 78108#L1313-3 assume !(1 == ~E_10~0); 78106#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 78104#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 78055#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 78049#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 78048#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 78045#L1663 assume !(0 == start_simulation_~tmp~3#1); 78046#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 70274#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 69439#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 79238#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 79237#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 79131#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 79130#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 79127#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 69741#L1644-2 [2023-11-19 07:38:00,190 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:38:00,191 INFO L85 PathProgramCache]: Analyzing trace with hash 919650235, now seen corresponding path program 1 times [2023-11-19 07:38:00,191 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:38:00,191 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2098627525] [2023-11-19 07:38:00,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:38:00,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:38:00,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:38:00,269 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:38:00,269 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:38:00,270 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2098627525] [2023-11-19 07:38:00,270 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2098627525] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:38:00,270 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:38:00,270 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:38:00,270 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1644465640] [2023-11-19 07:38:00,271 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:38:00,271 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:38:00,271 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:38:00,272 INFO L85 PathProgramCache]: Analyzing trace with hash -694005602, now seen corresponding path program 1 times [2023-11-19 07:38:00,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:38:00,272 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1321108202] [2023-11-19 07:38:00,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:38:00,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:38:00,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:38:00,334 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:38:00,335 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:38:00,335 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1321108202] [2023-11-19 07:38:00,335 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1321108202] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:38:00,335 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:38:00,336 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:38:00,336 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [744661795] [2023-11-19 07:38:00,336 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:38:00,337 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:38:00,337 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:38:00,337 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:38:00,337 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:38:00,338 INFO L87 Difference]: Start difference. First operand 10636 states and 15111 transitions. cyclomatic complexity: 4479 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:38:00,515 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:38:00,515 INFO L93 Difference]: Finished difference Result 20256 states and 28666 transitions. [2023-11-19 07:38:00,515 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20256 states and 28666 transitions. [2023-11-19 07:38:00,598 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 20063 [2023-11-19 07:38:00,671 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20256 states to 20256 states and 28666 transitions. [2023-11-19 07:38:00,672 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20256 [2023-11-19 07:38:00,698 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20256 [2023-11-19 07:38:00,699 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20256 states and 28666 transitions. [2023-11-19 07:38:00,889 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:38:00,889 INFO L218 hiAutomatonCegarLoop]: Abstraction has 20256 states and 28666 transitions. [2023-11-19 07:38:00,908 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20256 states and 28666 transitions. [2023-11-19 07:38:01,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20256 to 20238. [2023-11-19 07:38:01,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20238 states, 20238 states have (on average 1.4155548967289258) internal successors, (28648), 20237 states have internal predecessors, (28648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:38:01,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20238 states to 20238 states and 28648 transitions. [2023-11-19 07:38:01,357 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20238 states and 28648 transitions. [2023-11-19 07:38:01,357 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:38:01,358 INFO L428 stractBuchiCegarLoop]: Abstraction has 20238 states and 28648 transitions. [2023-11-19 07:38:01,358 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-19 07:38:01,358 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20238 states and 28648 transitions. [2023-11-19 07:38:01,435 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 20045 [2023-11-19 07:38:01,435 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:38:01,435 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:38:01,438 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:38:01,438 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:38:01,439 INFO L748 eck$LassoCheckResult]: Stem: 100567#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 100568#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 101691#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 101692#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 101041#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 101042#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 100905#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 100790#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 100507#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 100161#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 100162#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 100206#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 100207#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 101186#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 101187#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 101236#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 100612#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 100613#L1090 assume !(0 == ~M_E~0); 100660#L1090-2 assume !(0 == ~T1_E~0); 100661#L1095-1 assume !(0 == ~T2_E~0); 101402#L1100-1 assume !(0 == ~T3_E~0); 101403#L1105-1 assume !(0 == ~T4_E~0); 100427#L1110-1 assume !(0 == ~T5_E~0); 100428#L1115-1 assume !(0 == ~T6_E~0); 100828#L1120-1 assume !(0 == ~T7_E~0); 101160#L1125-1 assume !(0 == ~T8_E~0); 101813#L1130-1 assume !(0 == ~T9_E~0); 101428#L1135-1 assume !(0 == ~T10_E~0); 100619#L1140-1 assume !(0 == ~T11_E~0); 100620#L1145-1 assume !(0 == ~E_1~0); 101350#L1150-1 assume !(0 == ~E_2~0); 100804#L1155-1 assume !(0 == ~E_3~0); 100805#L1160-1 assume !(0 == ~E_4~0); 100910#L1165-1 assume !(0 == ~E_5~0); 100911#L1170-1 assume !(0 == ~E_6~0); 101668#L1175-1 assume !(0 == ~E_7~0); 100995#L1180-1 assume !(0 == ~E_8~0); 100996#L1185-1 assume !(0 == ~E_9~0); 100614#L1190-1 assume !(0 == ~E_10~0); 100615#L1195-1 assume !(0 == ~E_11~0); 101012#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 100820#L525 assume !(1 == ~m_pc~0); 100250#L525-2 is_master_triggered_~__retres1~0#1 := 0; 100251#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 101530#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 101495#L1350 assume !(0 != activate_threads_~tmp~1#1); 100604#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 100605#L544 assume !(1 == ~t1_pc~0); 100826#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 100827#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100224#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 100225#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 100450#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 101127#L563 assume !(1 == ~t2_pc~0); 101333#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 100270#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 100271#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 100687#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 100688#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 101215#L582 assume !(1 == ~t3_pc~0); 101349#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 101764#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 100153#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 100154#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 100336#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100337#L601 assume !(1 == ~t4_pc~0); 101364#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 100829#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 100348#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 100349#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 101358#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 101749#L620 assume !(1 == ~t5_pc~0); 101176#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 101177#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 101233#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 101535#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 101778#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 101779#L639 assume !(1 == ~t6_pc~0); 101158#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 100723#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 100724#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 100774#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 100834#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 100835#L658 assume !(1 == ~t7_pc~0); 101064#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 101065#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 101790#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 101288#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 100607#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 100608#L677 assume 1 == ~t8_pc~0; 100842#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 100410#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 100411#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 100683#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 100684#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 101484#L696 assume !(1 == ~t9_pc~0); 101140#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 101141#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 100893#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 100894#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 101165#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 101407#L715 assume 1 == ~t10_pc~0; 101418#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 101268#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 101053#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 101054#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 100988#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 100404#L734 assume !(1 == ~t11_pc~0); 100405#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 100912#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 100999#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 100149#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 100150#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 101234#L1213 assume !(1 == ~M_E~0); 100985#L1213-2 assume !(1 == ~T1_E~0); 100986#L1218-1 assume !(1 == ~T2_E~0); 100184#L1223-1 assume !(1 == ~T3_E~0); 100185#L1228-1 assume !(1 == ~T4_E~0); 100962#L1233-1 assume !(1 == ~T5_E~0); 101780#L1238-1 assume !(1 == ~T6_E~0); 101356#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 101357#L1248-1 assume !(1 == ~T8_E~0); 101414#L1253-1 assume !(1 == ~T9_E~0); 101415#L1258-1 assume !(1 == ~T10_E~0); 101384#L1263-1 assume !(1 == ~T11_E~0); 101385#L1268-1 assume !(1 == ~E_1~0); 101183#L1273-1 assume !(1 == ~E_2~0); 101184#L1278-1 assume !(1 == ~E_3~0); 100721#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 100722#L1288-1 assume !(1 == ~E_5~0); 101545#L1293-1 assume !(1 == ~E_6~0); 101489#L1298-1 assume !(1 == ~E_7~0); 101219#L1303-1 assume !(1 == ~E_8~0); 100731#L1308-1 assume !(1 == ~E_9~0); 100623#L1313-1 assume !(1 == ~E_10~0); 100624#L1318-1 assume !(1 == ~E_11~0); 100632#L1323-1 assume { :end_inline_reset_delta_events } true; 100633#L1644-2 [2023-11-19 07:38:01,440 INFO L750 eck$LassoCheckResult]: Loop: 100633#L1644-2 assume !false; 117004#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 116998#L1065-1 assume !false; 116996#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 116414#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 116403#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 116401#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 116398#L906 assume !(0 != eval_~tmp~0#1); 116399#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 119342#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 119340#L1090-3 assume !(0 == ~M_E~0); 119338#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 119337#L1095-3 assume !(0 == ~T2_E~0); 119335#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 119333#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 119331#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 119329#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 119327#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 119324#L1125-3 assume !(0 == ~T8_E~0); 119322#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 119320#L1135-3 assume !(0 == ~T10_E~0); 119318#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 119316#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 119314#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 119311#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 119308#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 119306#L1165-3 assume !(0 == ~E_5~0); 119304#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 119302#L1175-3 assume !(0 == ~E_7~0); 119300#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 119298#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 119296#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 119294#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 119292#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 119290#L525-36 assume !(1 == ~m_pc~0); 119288#L525-38 is_master_triggered_~__retres1~0#1 := 0; 119286#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 119283#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 119281#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 119279#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 119277#L544-36 assume !(1 == ~t1_pc~0); 119275#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 119273#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 119270#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 119268#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 119266#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 101531#L563-36 assume !(1 == ~t2_pc~0); 100449#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 100213#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 100214#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 101505#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 100959#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100960#L582-36 assume !(1 == ~t3_pc~0); 101825#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 119262#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 119260#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 119258#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 119257#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100933#L601-36 assume !(1 == ~t4_pc~0); 100935#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 119256#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 101100#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 101101#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 119253#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 119252#L620-36 assume !(1 == ~t5_pc~0); 119251#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 119250#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 119249#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 119248#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 100468#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 100261#L639-36 assume !(1 == ~t6_pc~0); 100263#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 100298#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 100299#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 100848#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 119242#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 119241#L658-36 assume !(1 == ~t7_pc~0); 119239#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 119238#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 119237#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 119236#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 119235#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 119234#L677-36 assume 1 == ~t8_pc~0; 101677#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 101070#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 101216#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 101217#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 101742#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 101679#L696-36 assume 1 == ~t9_pc~0; 100982#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 100983#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 119228#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 119227#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 119226#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 119225#L715-36 assume 1 == ~t10_pc~0; 101280#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 101084#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 119224#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 119223#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 119222#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 119221#L734-36 assume !(1 == ~t11_pc~0); 119219#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 100531#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 100532#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 101804#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 119217#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 101683#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 101684#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 119216#L1218-3 assume !(1 == ~T2_E~0); 100564#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 100565#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 100750#L1233-3 assume !(1 == ~T5_E~0); 100751#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 101038#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 101039#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 101641#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 101838#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 100545#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 100546#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 118768#L1273-3 assume !(1 == ~E_2~0); 118767#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 118766#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 118765#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 118764#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 118763#L1298-3 assume !(1 == ~E_7~0); 118762#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 118761#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 118760#L1313-3 assume !(1 == ~E_10~0); 118759#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 118758#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 118751#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 118745#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 118744#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 101845#L1663 assume !(0 == start_simulation_~tmp~3#1); 100381#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 101812#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 117951#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 117949#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 117947#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 117945#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 117943#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 117940#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 100633#L1644-2 [2023-11-19 07:38:01,441 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:38:01,441 INFO L85 PathProgramCache]: Analyzing trace with hash -258324326, now seen corresponding path program 1 times [2023-11-19 07:38:01,442 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:38:01,442 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [615869309] [2023-11-19 07:38:01,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:38:01,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:38:01,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:38:01,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:38:01,529 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:38:01,530 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [615869309] [2023-11-19 07:38:01,530 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [615869309] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:38:01,530 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:38:01,530 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:38:01,531 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [477171963] [2023-11-19 07:38:01,531 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:38:01,532 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:38:01,532 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:38:01,533 INFO L85 PathProgramCache]: Analyzing trace with hash 512125020, now seen corresponding path program 1 times [2023-11-19 07:38:01,533 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:38:01,533 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [889751234] [2023-11-19 07:38:01,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:38:01,533 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:38:01,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:38:01,607 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:38:01,608 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:38:01,608 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [889751234] [2023-11-19 07:38:01,608 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [889751234] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:38:01,611 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:38:01,611 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:38:01,611 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [496303778] [2023-11-19 07:38:01,611 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:38:01,613 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:38:01,613 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:38:01,613 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:38:01,614 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:38:01,614 INFO L87 Difference]: Start difference. First operand 20238 states and 28648 transitions. cyclomatic complexity: 8418 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:38:02,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:38:02,000 INFO L93 Difference]: Finished difference Result 38610 states and 54461 transitions. [2023-11-19 07:38:02,000 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38610 states and 54461 transitions. [2023-11-19 07:38:02,262 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 38334 [2023-11-19 07:38:02,395 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38610 states to 38610 states and 54461 transitions. [2023-11-19 07:38:02,396 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38610 [2023-11-19 07:38:02,430 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38610 [2023-11-19 07:38:02,430 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38610 states and 54461 transitions. [2023-11-19 07:38:02,465 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:38:02,465 INFO L218 hiAutomatonCegarLoop]: Abstraction has 38610 states and 54461 transitions. [2023-11-19 07:38:02,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38610 states and 54461 transitions. [2023-11-19 07:38:03,046 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38610 to 38574. [2023-11-19 07:38:03,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38574 states, 38574 states have (on average 1.4109244568880592) internal successors, (54425), 38573 states have internal predecessors, (54425), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:38:03,243 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38574 states to 38574 states and 54425 transitions. [2023-11-19 07:38:03,243 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38574 states and 54425 transitions. [2023-11-19 07:38:03,244 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:38:03,244 INFO L428 stractBuchiCegarLoop]: Abstraction has 38574 states and 54425 transitions. [2023-11-19 07:38:03,245 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-19 07:38:03,245 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38574 states and 54425 transitions. [2023-11-19 07:38:03,374 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 38298 [2023-11-19 07:38:03,374 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:38:03,374 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:38:03,377 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:38:03,378 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:38:03,378 INFO L748 eck$LassoCheckResult]: Stem: 159420#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 159421#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 160512#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 160513#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 159880#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 159881#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 159746#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 159639#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 159363#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 159016#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 159017#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 159061#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 159062#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 160033#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 160034#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 160084#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 159465#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 159466#L1090 assume !(0 == ~M_E~0); 159514#L1090-2 assume !(0 == ~T1_E~0); 159515#L1095-1 assume !(0 == ~T2_E~0); 160245#L1100-1 assume !(0 == ~T3_E~0); 160246#L1105-1 assume !(0 == ~T4_E~0); 159283#L1110-1 assume !(0 == ~T5_E~0); 159284#L1115-1 assume !(0 == ~T6_E~0); 159679#L1120-1 assume !(0 == ~T7_E~0); 160002#L1125-1 assume !(0 == ~T8_E~0); 160622#L1130-1 assume !(0 == ~T9_E~0); 160269#L1135-1 assume !(0 == ~T10_E~0); 159471#L1140-1 assume !(0 == ~T11_E~0); 159472#L1145-1 assume !(0 == ~E_1~0); 160193#L1150-1 assume !(0 == ~E_2~0); 159653#L1155-1 assume !(0 == ~E_3~0); 159654#L1160-1 assume !(0 == ~E_4~0); 159753#L1165-1 assume !(0 == ~E_5~0); 159754#L1170-1 assume !(0 == ~E_6~0); 160485#L1175-1 assume !(0 == ~E_7~0); 159836#L1180-1 assume !(0 == ~E_8~0); 159837#L1185-1 assume !(0 == ~E_9~0); 159467#L1190-1 assume !(0 == ~E_10~0); 159468#L1195-1 assume !(0 == ~E_11~0); 159852#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 159674#L525 assume !(1 == ~m_pc~0); 159105#L525-2 is_master_triggered_~__retres1~0#1 := 0; 159106#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 160359#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 160330#L1350 assume !(0 != activate_threads_~tmp~1#1); 159457#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 159458#L544 assume !(1 == ~t1_pc~0); 159675#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 159676#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 159085#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 159086#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 159305#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 159969#L563 assume !(1 == ~t2_pc~0); 160177#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 159124#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 159125#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 159539#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 159540#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 160056#L582 assume !(1 == ~t3_pc~0); 160191#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 160572#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 159008#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 159009#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 159190#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 159191#L601 assume !(1 == ~t4_pc~0); 160207#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 159680#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 159204#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 159205#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 160202#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 160561#L620 assume !(1 == ~t5_pc~0); 160021#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 160022#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 160073#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 160365#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 160588#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 160589#L639 assume !(1 == ~t6_pc~0); 160000#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 159575#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 159576#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 159624#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 159685#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 159686#L658 assume !(1 == ~t7_pc~0); 159904#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 159905#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 160596#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 160130#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 159460#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 159461#L677 assume !(1 == ~t8_pc~0); 159484#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 159271#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 159272#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 159532#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 159533#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 160320#L696 assume !(1 == ~t9_pc~0); 159985#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 159986#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 159736#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 159737#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 160011#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 160250#L715 assume 1 == ~t10_pc~0; 160259#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 160109#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 159892#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 159893#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 159829#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 159259#L734 assume !(1 == ~t11_pc~0); 159260#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 159756#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 159841#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 159006#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 159007#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 160074#L1213 assume !(1 == ~M_E~0); 159827#L1213-2 assume !(1 == ~T1_E~0); 159828#L1218-1 assume !(1 == ~T2_E~0); 159039#L1223-1 assume !(1 == ~T3_E~0); 159040#L1228-1 assume !(1 == ~T4_E~0); 159802#L1233-1 assume !(1 == ~T5_E~0); 160590#L1238-1 assume !(1 == ~T6_E~0); 160200#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 160201#L1248-1 assume !(1 == ~T8_E~0); 160255#L1253-1 assume !(1 == ~T9_E~0); 160256#L1258-1 assume !(1 == ~T10_E~0); 160228#L1263-1 assume !(1 == ~T11_E~0); 160229#L1268-1 assume !(1 == ~E_1~0); 160026#L1273-1 assume !(1 == ~E_2~0); 160027#L1278-1 assume !(1 == ~E_3~0); 159571#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 159572#L1288-1 assume !(1 == ~E_5~0); 160370#L1293-1 assume !(1 == ~E_6~0); 160326#L1298-1 assume !(1 == ~E_7~0); 160060#L1303-1 assume !(1 == ~E_8~0); 159581#L1308-1 assume !(1 == ~E_9~0); 159475#L1313-1 assume !(1 == ~E_10~0); 159476#L1318-1 assume !(1 == ~E_11~0); 159485#L1323-1 assume { :end_inline_reset_delta_events } true; 159486#L1644-2 [2023-11-19 07:38:03,520 INFO L750 eck$LassoCheckResult]: Loop: 159486#L1644-2 assume !false; 174200#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 174158#L1065-1 assume !false; 174138#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 174131#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 174107#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 174101#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 174095#L906 assume !(0 != eval_~tmp~0#1); 174096#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 176929#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 176925#L1090-3 assume !(0 == ~M_E~0); 176920#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 176916#L1095-3 assume !(0 == ~T2_E~0); 176912#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 176908#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 176903#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 176898#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 176894#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 176890#L1125-3 assume !(0 == ~T8_E~0); 176884#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 176879#L1135-3 assume !(0 == ~T10_E~0); 176874#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 176869#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 176864#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 176858#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 176852#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 176847#L1165-3 assume !(0 == ~E_5~0); 176840#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 176834#L1175-3 assume !(0 == ~E_7~0); 176827#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 176821#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 176815#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 176808#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 176802#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 176796#L525-36 assume !(1 == ~m_pc~0); 176789#L525-38 is_master_triggered_~__retres1~0#1 := 0; 176783#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 176776#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 176769#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 176763#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 176757#L544-36 assume !(1 == ~t1_pc~0); 176750#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 176744#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 176737#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 176730#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 176723#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 176717#L563-36 assume !(1 == ~t2_pc~0); 176710#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 176705#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 176700#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 176694#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 176687#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 176681#L582-36 assume !(1 == ~t3_pc~0); 176675#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 176669#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 176663#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 176656#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 176649#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 176644#L601-36 assume 1 == ~t4_pc~0; 176638#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 176631#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 176626#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 176617#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 176610#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 176603#L620-36 assume !(1 == ~t5_pc~0); 176596#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 176204#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 176200#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 176139#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 176128#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 176127#L639-36 assume !(1 == ~t6_pc~0); 176110#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 176098#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 175991#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 175988#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 175986#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 175984#L658-36 assume !(1 == ~t7_pc~0); 175981#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 175979#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 175977#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 175974#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 175972#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 175970#L677-36 assume !(1 == ~t8_pc~0); 175968#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 175966#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 175964#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 175963#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 175960#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 175958#L696-36 assume !(1 == ~t9_pc~0); 175955#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 175953#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 175951#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 175950#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 175946#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 175944#L715-36 assume 1 == ~t10_pc~0; 175940#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 175937#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 175935#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 175933#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 175930#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 175928#L734-36 assume 1 == ~t11_pc~0; 175926#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 175923#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 175921#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 175919#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 175916#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 175914#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 175912#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 175910#L1218-3 assume !(1 == ~T2_E~0); 175908#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 175906#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 175853#L1233-3 assume !(1 == ~T5_E~0); 175786#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 175777#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 175771#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 175765#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 175759#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 175753#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 175746#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 175739#L1273-3 assume !(1 == ~E_2~0); 175730#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 175723#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 175716#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 175710#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 175705#L1298-3 assume !(1 == ~E_7~0); 175698#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 175689#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 175684#L1313-3 assume !(1 == ~E_10~0); 175679#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 175676#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 175490#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 175477#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 175467#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 175456#L1663 assume !(0 == start_simulation_~tmp~3#1); 175451#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 175209#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 175194#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 174317#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 174236#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 174235#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 174233#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 174232#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 159486#L1644-2 [2023-11-19 07:38:03,520 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:38:03,521 INFO L85 PathProgramCache]: Analyzing trace with hash 1174510393, now seen corresponding path program 1 times [2023-11-19 07:38:03,521 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:38:03,521 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1310133832] [2023-11-19 07:38:03,521 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:38:03,521 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:38:03,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:38:03,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:38:03,622 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:38:03,622 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1310133832] [2023-11-19 07:38:03,622 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1310133832] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:38:03,622 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:38:03,623 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:38:03,623 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1767201042] [2023-11-19 07:38:03,623 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:38:03,623 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:38:03,624 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:38:03,624 INFO L85 PathProgramCache]: Analyzing trace with hash 1318862556, now seen corresponding path program 1 times [2023-11-19 07:38:03,624 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:38:03,624 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [421450143] [2023-11-19 07:38:03,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:38:03,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:38:03,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:38:03,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:38:03,686 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:38:03,686 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [421450143] [2023-11-19 07:38:03,686 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [421450143] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:38:03,686 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:38:03,686 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:38:03,687 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [416061701] [2023-11-19 07:38:03,687 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:38:03,687 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:38:03,687 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:38:03,688 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 07:38:03,688 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 07:38:03,688 INFO L87 Difference]: Start difference. First operand 38574 states and 54425 transitions. cyclomatic complexity: 15867 Second operand has 5 states, 5 states have (on average 27.4) internal successors, (137), 5 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:38:04,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:38:04,404 INFO L93 Difference]: Finished difference Result 81429 states and 114189 transitions. [2023-11-19 07:38:04,404 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 81429 states and 114189 transitions. [2023-11-19 07:38:04,904 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 80964 [2023-11-19 07:38:05,419 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 81429 states to 81429 states and 114189 transitions. [2023-11-19 07:38:05,419 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 81429 [2023-11-19 07:38:05,464 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 81429 [2023-11-19 07:38:05,464 INFO L73 IsDeterministic]: Start isDeterministic. Operand 81429 states and 114189 transitions. [2023-11-19 07:38:05,573 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:38:05,573 INFO L218 hiAutomatonCegarLoop]: Abstraction has 81429 states and 114189 transitions. [2023-11-19 07:38:05,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81429 states and 114189 transitions. [2023-11-19 07:38:06,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81429 to 39669. [2023-11-19 07:38:06,226 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39669 states, 39669 states have (on average 1.3995815372204996) internal successors, (55520), 39668 states have internal predecessors, (55520), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:38:06,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39669 states to 39669 states and 55520 transitions. [2023-11-19 07:38:06,312 INFO L240 hiAutomatonCegarLoop]: Abstraction has 39669 states and 55520 transitions. [2023-11-19 07:38:06,312 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-19 07:38:06,313 INFO L428 stractBuchiCegarLoop]: Abstraction has 39669 states and 55520 transitions. [2023-11-19 07:38:06,313 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-19 07:38:06,313 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39669 states and 55520 transitions. [2023-11-19 07:38:06,627 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 39390 [2023-11-19 07:38:06,627 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:38:06,627 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:38:06,631 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:38:06,631 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:38:06,631 INFO L748 eck$LassoCheckResult]: Stem: 279437#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 279438#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 280531#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 280532#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 279896#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 279897#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 279763#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 279657#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 279380#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 279032#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 279033#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 279077#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 279078#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 280047#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 280048#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 280100#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 279482#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 279483#L1090 assume !(0 == ~M_E~0); 279531#L1090-2 assume !(0 == ~T1_E~0); 279532#L1095-1 assume !(0 == ~T2_E~0); 280256#L1100-1 assume !(0 == ~T3_E~0); 280257#L1105-1 assume !(0 == ~T4_E~0); 279297#L1110-1 assume !(0 == ~T5_E~0); 279298#L1115-1 assume !(0 == ~T6_E~0); 279695#L1120-1 assume !(0 == ~T7_E~0); 280015#L1125-1 assume !(0 == ~T8_E~0); 280643#L1130-1 assume !(0 == ~T9_E~0); 280282#L1135-1 assume !(0 == ~T10_E~0); 279488#L1140-1 assume !(0 == ~T11_E~0); 279489#L1145-1 assume !(0 == ~E_1~0); 280208#L1150-1 assume !(0 == ~E_2~0); 279671#L1155-1 assume !(0 == ~E_3~0); 279672#L1160-1 assume !(0 == ~E_4~0); 279768#L1165-1 assume !(0 == ~E_5~0); 279769#L1170-1 assume !(0 == ~E_6~0); 280506#L1175-1 assume !(0 == ~E_7~0); 279852#L1180-1 assume !(0 == ~E_8~0); 279853#L1185-1 assume !(0 == ~E_9~0); 279484#L1190-1 assume !(0 == ~E_10~0); 279485#L1195-1 assume !(0 == ~E_11~0); 279868#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 279685#L525 assume !(1 == ~m_pc~0); 279121#L525-2 is_master_triggered_~__retres1~0#1 := 0; 279122#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 280373#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 280343#L1350 assume !(0 != activate_threads_~tmp~1#1); 279474#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 279475#L544 assume !(1 == ~t1_pc~0); 279691#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 279692#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 279098#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 279099#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 279321#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 279981#L563 assume !(1 == ~t2_pc~0); 280192#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 279140#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 279141#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 279553#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 279554#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 280074#L582 assume !(1 == ~t3_pc~0); 280207#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 280600#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 279024#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 279025#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 279206#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 279207#L601 assume !(1 == ~t4_pc~0); 280222#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 279696#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 279218#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 279219#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 280217#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 280590#L620 assume !(1 == ~t5_pc~0); 280036#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 280037#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 280091#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 280379#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 280614#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 280615#L639 assume !(1 == ~t6_pc~0); 280013#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 279592#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 279593#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 279641#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 279699#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 279700#L658 assume !(1 == ~t7_pc~0); 279919#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 279920#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 280620#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 280146#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 279477#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 279478#L677 assume !(1 == ~t8_pc~0); 279499#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 279283#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 279284#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 279549#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 279550#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 280335#L696 assume !(1 == ~t9_pc~0); 279994#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 279995#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 280105#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 280022#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 280023#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 280262#L715 assume 1 == ~t10_pc~0; 280270#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 280127#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 279908#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 279909#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 279845#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 279274#L734 assume !(1 == ~t11_pc~0); 279275#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 279770#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 279855#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 279022#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 279023#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 280092#L1213 assume !(1 == ~M_E~0); 279842#L1213-2 assume !(1 == ~T1_E~0); 279843#L1218-1 assume !(1 == ~T2_E~0); 279055#L1223-1 assume !(1 == ~T3_E~0); 279056#L1228-1 assume !(1 == ~T4_E~0); 279818#L1233-1 assume !(1 == ~T5_E~0); 280616#L1238-1 assume !(1 == ~T6_E~0); 280215#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 280216#L1248-1 assume !(1 == ~T8_E~0); 280266#L1253-1 assume !(1 == ~T9_E~0); 280267#L1258-1 assume !(1 == ~T10_E~0); 280239#L1263-1 assume !(1 == ~T11_E~0); 280240#L1268-1 assume !(1 == ~E_1~0); 280041#L1273-1 assume !(1 == ~E_2~0); 280042#L1278-1 assume !(1 == ~E_3~0); 279588#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 279589#L1288-1 assume !(1 == ~E_5~0); 280387#L1293-1 assume !(1 == ~E_6~0); 280340#L1298-1 assume !(1 == ~E_7~0); 280078#L1303-1 assume !(1 == ~E_8~0); 279598#L1308-1 assume !(1 == ~E_9~0); 279492#L1313-1 assume !(1 == ~E_10~0); 279493#L1318-1 assume !(1 == ~E_11~0); 279500#L1323-1 assume { :end_inline_reset_delta_events } true; 279501#L1644-2 [2023-11-19 07:38:06,632 INFO L750 eck$LassoCheckResult]: Loop: 279501#L1644-2 assume !false; 299550#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 299540#L1065-1 assume !false; 299535#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 299530#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 299508#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 299506#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 299503#L906 assume !(0 != eval_~tmp~0#1); 299504#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 300007#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 300006#L1090-3 assume !(0 == ~M_E~0); 300005#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 300004#L1095-3 assume !(0 == ~T2_E~0); 300003#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 300002#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 300001#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 300000#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 299999#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 299998#L1125-3 assume !(0 == ~T8_E~0); 299997#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 299996#L1135-3 assume !(0 == ~T10_E~0); 299995#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 299994#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 299993#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 299992#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 299991#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 299990#L1165-3 assume !(0 == ~E_5~0); 299989#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 299988#L1175-3 assume !(0 == ~E_7~0); 299987#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 299986#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 299985#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 299984#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 299983#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 299982#L525-36 assume !(1 == ~m_pc~0); 299981#L525-38 is_master_triggered_~__retres1~0#1 := 0; 299980#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 299979#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 299978#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 299977#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 299976#L544-36 assume !(1 == ~t1_pc~0); 299975#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 299974#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 299973#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 299972#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 299971#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 299970#L563-36 assume !(1 == ~t2_pc~0); 299968#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 299967#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 299966#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 299964#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 299962#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 299960#L582-36 assume !(1 == ~t3_pc~0); 299957#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 299954#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 299951#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 299948#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 299945#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 299942#L601-36 assume !(1 == ~t4_pc~0); 299938#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 299935#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 299932#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 299929#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 299926#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 299923#L620-36 assume !(1 == ~t5_pc~0); 299920#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 299917#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 299913#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 299909#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 299905#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 299901#L639-36 assume 1 == ~t6_pc~0; 299896#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 299892#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 299887#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 299872#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 299868#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 299864#L658-36 assume !(1 == ~t7_pc~0); 299858#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 299853#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 299850#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 299844#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 299834#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 299825#L677-36 assume !(1 == ~t8_pc~0); 299819#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 299811#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 299802#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 299795#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 299794#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 299793#L696-36 assume !(1 == ~t9_pc~0); 299792#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 299790#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 299788#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 299786#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 299783#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 299781#L715-36 assume 1 == ~t10_pc~0; 299778#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 299776#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 299774#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 299771#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 299769#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 299767#L734-36 assume !(1 == ~t11_pc~0); 299764#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 299761#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 299759#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 299757#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 299755#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 299754#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 299753#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 299752#L1218-3 assume !(1 == ~T2_E~0); 299751#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 299750#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 299749#L1233-3 assume !(1 == ~T5_E~0); 299748#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 299747#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 299746#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 299745#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 299744#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 299743#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 299742#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 299741#L1273-3 assume !(1 == ~E_2~0); 299740#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 299739#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 299738#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 299736#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 299732#L1298-3 assume !(1 == ~E_7~0); 299727#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 299724#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 299720#L1313-3 assume !(1 == ~E_10~0); 299715#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 299711#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 299641#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 299634#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 299632#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 299626#L1663 assume !(0 == start_simulation_~tmp~3#1); 299625#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 299616#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 299605#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 299602#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 299601#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 299600#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 299599#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 299597#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 279501#L1644-2 [2023-11-19 07:38:06,633 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:38:06,633 INFO L85 PathProgramCache]: Analyzing trace with hash 145151095, now seen corresponding path program 1 times [2023-11-19 07:38:06,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:38:06,633 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1049743324] [2023-11-19 07:38:06,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:38:06,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:38:06,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:38:06,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:38:06,735 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:38:06,735 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1049743324] [2023-11-19 07:38:06,735 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1049743324] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:38:06,735 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:38:06,735 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:38:06,736 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [640742973] [2023-11-19 07:38:06,736 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:38:06,736 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:38:06,736 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:38:06,737 INFO L85 PathProgramCache]: Analyzing trace with hash -1287222663, now seen corresponding path program 1 times [2023-11-19 07:38:06,737 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:38:06,737 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1411017602] [2023-11-19 07:38:06,737 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:38:06,737 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:38:06,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:38:06,789 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:38:06,789 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:38:06,790 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1411017602] [2023-11-19 07:38:06,790 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1411017602] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:38:06,790 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:38:06,790 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:38:06,790 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1974539480] [2023-11-19 07:38:06,790 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:38:06,791 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:38:06,791 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:38:06,791 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:38:06,792 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:38:06,792 INFO L87 Difference]: Start difference. First operand 39669 states and 55520 transitions. cyclomatic complexity: 15867 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:38:07,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:38:07,568 INFO L93 Difference]: Finished difference Result 111500 states and 155117 transitions. [2023-11-19 07:38:07,569 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 111500 states and 155117 transitions. [2023-11-19 07:38:08,282 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 109374 [2023-11-19 07:38:08,609 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 111500 states to 111500 states and 155117 transitions. [2023-11-19 07:38:08,610 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 111500 [2023-11-19 07:38:08,670 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 111500 [2023-11-19 07:38:08,671 INFO L73 IsDeterministic]: Start isDeterministic. Operand 111500 states and 155117 transitions. [2023-11-19 07:38:08,739 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:38:08,739 INFO L218 hiAutomatonCegarLoop]: Abstraction has 111500 states and 155117 transitions. [2023-11-19 07:38:08,811 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111500 states and 155117 transitions. [2023-11-19 07:38:10,045 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111500 to 109336. [2023-11-19 07:38:10,126 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 109336 states, 109336 states have (on average 1.3932556523011634) internal successors, (152333), 109335 states have internal predecessors, (152333), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:38:10,963 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109336 states to 109336 states and 152333 transitions. [2023-11-19 07:38:10,963 INFO L240 hiAutomatonCegarLoop]: Abstraction has 109336 states and 152333 transitions. [2023-11-19 07:38:10,964 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:38:10,969 INFO L428 stractBuchiCegarLoop]: Abstraction has 109336 states and 152333 transitions. [2023-11-19 07:38:10,969 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-19 07:38:10,969 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 109336 states and 152333 transitions. [2023-11-19 07:38:11,183 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 108834 [2023-11-19 07:38:11,183 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:38:11,183 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:38:11,186 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:38:11,186 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:38:11,186 INFO L748 eck$LassoCheckResult]: Stem: 430621#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 430622#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 431748#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 431749#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 431097#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 431098#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 430963#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 430847#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 430561#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 430211#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 430212#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 430257#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 430258#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 431247#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 431248#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 431295#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 430666#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 430667#L1090 assume !(0 == ~M_E~0); 430712#L1090-2 assume !(0 == ~T1_E~0); 430713#L1095-1 assume !(0 == ~T2_E~0); 431466#L1100-1 assume !(0 == ~T3_E~0); 431467#L1105-1 assume !(0 == ~T4_E~0); 430478#L1110-1 assume !(0 == ~T5_E~0); 430479#L1115-1 assume !(0 == ~T6_E~0); 430887#L1120-1 assume !(0 == ~T7_E~0); 431218#L1125-1 assume !(0 == ~T8_E~0); 431887#L1130-1 assume !(0 == ~T9_E~0); 431494#L1135-1 assume !(0 == ~T10_E~0); 430672#L1140-1 assume !(0 == ~T11_E~0); 430673#L1145-1 assume !(0 == ~E_1~0); 431411#L1150-1 assume !(0 == ~E_2~0); 430863#L1155-1 assume !(0 == ~E_3~0); 430864#L1160-1 assume !(0 == ~E_4~0); 430968#L1165-1 assume !(0 == ~E_5~0); 430969#L1170-1 assume !(0 == ~E_6~0); 431720#L1175-1 assume !(0 == ~E_7~0); 431053#L1180-1 assume !(0 == ~E_8~0); 431054#L1185-1 assume !(0 == ~E_9~0); 430668#L1190-1 assume !(0 == ~E_10~0); 430669#L1195-1 assume !(0 == ~E_11~0); 431069#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 430879#L525 assume !(1 == ~m_pc~0); 430301#L525-2 is_master_triggered_~__retres1~0#1 := 0; 430302#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 431592#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 431557#L1350 assume !(0 != activate_threads_~tmp~1#1); 430658#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 430659#L544 assume !(1 == ~t1_pc~0); 430885#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 430886#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 430275#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 430276#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 430502#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 431185#L563 assume !(1 == ~t2_pc~0); 431396#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 430321#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 430322#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 430740#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 430741#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 431273#L582 assume !(1 == ~t3_pc~0); 431410#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 431819#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 430203#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 430204#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 430386#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 430387#L601 assume !(1 == ~t4_pc~0); 431428#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 430888#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 430396#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 430397#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 431420#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 431810#L620 assume !(1 == ~t5_pc~0); 431235#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 431236#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 431292#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 431597#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 431835#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 431836#L639 assume !(1 == ~t6_pc~0); 431216#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 430778#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 430779#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 430831#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 430893#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 430894#L658 assume !(1 == ~t7_pc~0); 431123#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 431124#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 431850#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 431350#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 430661#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 430662#L677 assume !(1 == ~t8_pc~0); 430683#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 430461#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 430462#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 430736#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 430737#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 431549#L696 assume !(1 == ~t9_pc~0); 431197#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 431198#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 431953#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 431223#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 431224#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 431471#L715 assume !(1 == ~t10_pc~0); 431770#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 431328#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 431110#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 431111#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 431046#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 430455#L734 assume !(1 == ~t11_pc~0); 430456#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 430970#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 431056#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 430199#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 430200#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 431293#L1213 assume !(1 == ~M_E~0); 431043#L1213-2 assume !(1 == ~T1_E~0); 431044#L1218-1 assume !(1 == ~T2_E~0); 430234#L1223-1 assume !(1 == ~T3_E~0); 430235#L1228-1 assume !(1 == ~T4_E~0); 431016#L1233-1 assume !(1 == ~T5_E~0); 431837#L1238-1 assume !(1 == ~T6_E~0); 431418#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 431419#L1248-1 assume !(1 == ~T8_E~0); 431477#L1253-1 assume !(1 == ~T9_E~0); 431478#L1258-1 assume !(1 == ~T10_E~0); 431449#L1263-1 assume !(1 == ~T11_E~0); 431450#L1268-1 assume !(1 == ~E_1~0); 431243#L1273-1 assume !(1 == ~E_2~0); 431244#L1278-1 assume !(1 == ~E_3~0); 430776#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 430777#L1288-1 assume !(1 == ~E_5~0); 431604#L1293-1 assume !(1 == ~E_6~0); 431554#L1298-1 assume !(1 == ~E_7~0); 431277#L1303-1 assume !(1 == ~E_8~0); 430786#L1308-1 assume !(1 == ~E_9~0); 430676#L1313-1 assume !(1 == ~E_10~0); 430677#L1318-1 assume !(1 == ~E_11~0); 430684#L1323-1 assume { :end_inline_reset_delta_events } true; 430685#L1644-2 [2023-11-19 07:38:11,187 INFO L750 eck$LassoCheckResult]: Loop: 430685#L1644-2 assume !false; 524825#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 524822#L1065-1 assume !false; 524821#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 524818#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 524808#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 524807#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 524805#L906 assume !(0 != eval_~tmp~0#1); 524806#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 525103#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 525101#L1090-3 assume !(0 == ~M_E~0); 525099#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 525097#L1095-3 assume !(0 == ~T2_E~0); 525096#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 525095#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 525094#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 525093#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 525092#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 525091#L1125-3 assume !(0 == ~T8_E~0); 525090#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 525089#L1135-3 assume !(0 == ~T10_E~0); 525088#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 525087#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 525086#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 525085#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 525084#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 525083#L1165-3 assume !(0 == ~E_5~0); 525082#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 525081#L1175-3 assume !(0 == ~E_7~0); 525080#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 525079#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 525078#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 525077#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 525075#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 525074#L525-36 assume !(1 == ~m_pc~0); 525073#L525-38 is_master_triggered_~__retres1~0#1 := 0; 525072#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 525071#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 525069#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 525068#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 525067#L544-36 assume !(1 == ~t1_pc~0); 525066#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 525065#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 525064#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 525063#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 525062#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 525061#L563-36 assume !(1 == ~t2_pc~0); 525059#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 525057#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 525055#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 525053#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 525051#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 525049#L582-36 assume !(1 == ~t3_pc~0); 525047#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 525045#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 525043#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 525041#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 525039#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 525037#L601-36 assume !(1 == ~t4_pc~0); 525034#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 525032#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 525029#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 525027#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 525025#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 525023#L620-36 assume !(1 == ~t5_pc~0); 525021#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 525019#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 525017#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 525015#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 525013#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 525011#L639-36 assume 1 == ~t6_pc~0; 525008#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 525006#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 525003#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 525001#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 524999#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 524997#L658-36 assume !(1 == ~t7_pc~0); 524994#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 524992#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 524990#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 524988#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 524986#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 524984#L677-36 assume !(1 == ~t8_pc~0); 524982#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 524980#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 524977#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 524975#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 524973#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 524966#L696-36 assume !(1 == ~t9_pc~0); 524964#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 524962#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 524960#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 524958#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 524955#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 524953#L715-36 assume !(1 == ~t10_pc~0); 524951#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 524949#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 524947#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 524945#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 524943#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 524939#L734-36 assume !(1 == ~t11_pc~0); 524936#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 524934#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 524932#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 524929#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 524927#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 524925#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 524923#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 524921#L1218-3 assume !(1 == ~T2_E~0); 524919#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 524917#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 524915#L1233-3 assume !(1 == ~T5_E~0); 524913#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 524910#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 524908#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 524906#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 524904#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 524902#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 524900#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 524898#L1273-3 assume !(1 == ~E_2~0); 524896#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 524894#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 524892#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 524890#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 524888#L1298-3 assume !(1 == ~E_7~0); 524886#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 524884#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 524882#L1313-3 assume !(1 == ~E_10~0); 524880#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 524878#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 524863#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 524856#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 524854#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 524850#L1663 assume !(0 == start_simulation_~tmp~3#1); 524849#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 524846#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 524836#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 524834#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 524832#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 524830#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 524827#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 524826#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 430685#L1644-2 [2023-11-19 07:38:11,187 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:38:11,188 INFO L85 PathProgramCache]: Analyzing trace with hash -1619665514, now seen corresponding path program 1 times [2023-11-19 07:38:11,188 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:38:11,188 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [578159981] [2023-11-19 07:38:11,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:38:11,189 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:38:11,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:38:11,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:38:11,272 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:38:11,273 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [578159981] [2023-11-19 07:38:11,273 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [578159981] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:38:11,273 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:38:11,274 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:38:11,274 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [618674702] [2023-11-19 07:38:11,274 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:38:11,274 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:38:11,275 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:38:11,275 INFO L85 PathProgramCache]: Analyzing trace with hash 145612056, now seen corresponding path program 1 times [2023-11-19 07:38:11,275 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:38:11,275 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [78107769] [2023-11-19 07:38:11,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:38:11,276 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:38:11,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:38:11,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:38:11,328 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:38:11,328 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [78107769] [2023-11-19 07:38:11,328 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [78107769] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:38:11,328 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:38:11,328 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:38:11,329 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1728425603] [2023-11-19 07:38:11,329 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:38:11,329 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:38:11,329 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:38:11,330 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:38:11,330 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:38:11,330 INFO L87 Difference]: Start difference. First operand 109336 states and 152333 transitions. cyclomatic complexity: 43029 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:38:12,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:38:12,408 INFO L93 Difference]: Finished difference Result 230331 states and 320947 transitions. [2023-11-19 07:38:12,409 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 230331 states and 320947 transitions. [2023-11-19 07:38:13,883 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 229352 [2023-11-19 07:38:14,472 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 230331 states to 230331 states and 320947 transitions. [2023-11-19 07:38:14,472 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 230331 [2023-11-19 07:38:14,556 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 230331 [2023-11-19 07:38:14,556 INFO L73 IsDeterministic]: Start isDeterministic. Operand 230331 states and 320947 transitions. [2023-11-19 07:38:14,652 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:38:14,652 INFO L218 hiAutomatonCegarLoop]: Abstraction has 230331 states and 320947 transitions. [2023-11-19 07:38:14,746 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 230331 states and 320947 transitions. [2023-11-19 07:38:16,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 230331 to 121125. [2023-11-19 07:38:16,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 121125 states, 121125 states have (on average 1.395343653250774) internal successors, (169011), 121124 states have internal predecessors, (169011), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:38:17,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121125 states to 121125 states and 169011 transitions. [2023-11-19 07:38:17,297 INFO L240 hiAutomatonCegarLoop]: Abstraction has 121125 states and 169011 transitions. [2023-11-19 07:38:17,297 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:38:17,298 INFO L428 stractBuchiCegarLoop]: Abstraction has 121125 states and 169011 transitions. [2023-11-19 07:38:17,298 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-19 07:38:17,298 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 121125 states and 169011 transitions. [2023-11-19 07:38:17,543 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 120518 [2023-11-19 07:38:17,543 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:38:17,543 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:38:17,545 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:38:17,545 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:38:17,545 INFO L748 eck$LassoCheckResult]: Stem: 770298#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 770299#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 771448#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 771449#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 770776#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 770777#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 770643#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 770526#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 770240#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 769888#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 769889#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 769934#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 769935#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 770935#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 770936#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 770988#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 770344#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 770345#L1090 assume !(0 == ~M_E~0); 770393#L1090-2 assume !(0 == ~T1_E~0); 770394#L1095-1 assume !(0 == ~T2_E~0); 771168#L1100-1 assume !(0 == ~T3_E~0); 771169#L1105-1 assume !(0 == ~T4_E~0); 770157#L1110-1 assume !(0 == ~T5_E~0); 770158#L1115-1 assume !(0 == ~T6_E~0); 770569#L1120-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 770906#L1125-1 assume !(0 == ~T8_E~0); 771575#L1130-1 assume !(0 == ~T9_E~0); 771191#L1135-1 assume !(0 == ~T10_E~0); 770350#L1140-1 assume !(0 == ~T11_E~0); 770351#L1145-1 assume !(0 == ~E_1~0); 771688#L1150-1 assume !(0 == ~E_2~0); 770545#L1155-1 assume !(0 == ~E_3~0); 770546#L1160-1 assume !(0 == ~E_4~0); 771687#L1165-1 assume !(0 == ~E_5~0); 771422#L1170-1 assume !(0 == ~E_6~0); 771423#L1175-1 assume !(0 == ~E_7~0); 771686#L1180-1 assume !(0 == ~E_8~0); 771685#L1185-1 assume !(0 == ~E_9~0); 771684#L1190-1 assume !(0 == ~E_10~0); 771683#L1195-1 assume !(0 == ~E_11~0); 771388#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 771389#L525 assume !(1 == ~m_pc~0); 771682#L525-2 is_master_triggered_~__retres1~0#1 := 0; 771379#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 771279#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 771249#L1350 assume !(0 != activate_threads_~tmp~1#1); 770335#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 770336#L544 assume !(1 == ~t1_pc~0); 770567#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 770568#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 769953#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 769954#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 770869#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 770870#L563 assume !(1 == ~t2_pc~0); 771092#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 771093#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 770541#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 770542#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 770963#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 770964#L582 assume !(1 == ~t3_pc~0); 771110#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 771514#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 769880#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 769881#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 771673#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 771598#L601 assume !(1 == ~t4_pc~0); 771128#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 771129#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 771669#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 771668#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 771603#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 771604#L620 assume !(1 == ~t5_pc~0); 770924#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 770925#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 771667#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 771635#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 771636#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 771579#L639 assume !(1 == ~t6_pc~0); 771580#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 770459#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 770460#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 771524#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 770575#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 770576#L658 assume !(1 == ~t7_pc~0); 770905#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 771542#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 771543#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 771044#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 770338#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 770339#L677 assume !(1 == ~t8_pc~0); 770582#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 770140#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 770141#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 771209#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 771660#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 771659#L696 assume !(1 == ~t9_pc~0); 770883#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 770884#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 771670#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 770912#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 770913#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 771173#L715 assume !(1 == ~t10_pc~0); 771556#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 771557#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 770788#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 770789#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 770726#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 770727#L734 assume !(1 == ~t11_pc~0); 771647#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 771646#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 771053#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 771054#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 770985#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 770986#L1213 assume !(1 == ~M_E~0); 771645#L1213-2 assume !(1 == ~T1_E~0); 771644#L1218-1 assume !(1 == ~T2_E~0); 771643#L1223-1 assume !(1 == ~T3_E~0); 771642#L1228-1 assume !(1 == ~T4_E~0); 771530#L1233-1 assume !(1 == ~T5_E~0); 771531#L1238-1 assume !(1 == ~T6_E~0); 771641#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 771122#L1248-1 assume !(1 == ~T8_E~0); 771179#L1253-1 assume !(1 == ~T9_E~0); 771180#L1258-1 assume !(1 == ~T10_E~0); 771148#L1263-1 assume !(1 == ~T11_E~0); 771149#L1268-1 assume !(1 == ~E_1~0); 770932#L1273-1 assume !(1 == ~E_2~0); 770933#L1278-1 assume !(1 == ~E_3~0); 770457#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 770458#L1288-1 assume !(1 == ~E_5~0); 771292#L1293-1 assume !(1 == ~E_6~0); 771244#L1298-1 assume !(1 == ~E_7~0); 770968#L1303-1 assume !(1 == ~E_8~0); 770467#L1308-1 assume !(1 == ~E_9~0); 770354#L1313-1 assume !(1 == ~E_10~0); 770355#L1318-1 assume !(1 == ~E_11~0); 770364#L1323-1 assume { :end_inline_reset_delta_events } true; 770365#L1644-2 [2023-11-19 07:38:17,546 INFO L750 eck$LassoCheckResult]: Loop: 770365#L1644-2 assume !false; 839857#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 839844#L1065-1 assume !false; 839845#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 837814#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 837805#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 835929#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 835930#L906 assume !(0 != eval_~tmp~0#1); 852439#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 852904#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 852898#L1090-3 assume !(0 == ~M_E~0); 852894#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 852890#L1095-3 assume !(0 == ~T2_E~0); 852885#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 852878#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 852871#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 852863#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 852855#L1120-3 assume !(0 == ~T7_E~0); 852856#L1125-3 assume !(0 == ~T8_E~0); 853336#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 853335#L1135-3 assume !(0 == ~T10_E~0); 853334#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 853333#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 853332#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 853330#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 853328#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 853326#L1165-3 assume !(0 == ~E_5~0); 853324#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 853322#L1175-3 assume !(0 == ~E_7~0); 853320#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 853318#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 853316#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 853314#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 853312#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 853310#L525-36 assume !(1 == ~m_pc~0); 853308#L525-38 is_master_triggered_~__retres1~0#1 := 0; 853306#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 853304#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 853302#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 853300#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 853298#L544-36 assume !(1 == ~t1_pc~0); 853296#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 853294#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 853292#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 853290#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 853288#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 853286#L563-36 assume 1 == ~t2_pc~0; 853284#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 853281#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 853279#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 853237#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 853236#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 853225#L582-36 assume !(1 == ~t3_pc~0); 853216#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 853206#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 853198#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 853195#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 853192#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 853191#L601-36 assume !(1 == ~t4_pc~0); 853157#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 853155#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 853153#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 853151#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 853149#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 853147#L620-36 assume !(1 == ~t5_pc~0); 853144#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 853142#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 853140#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 853138#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 853136#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 853133#L639-36 assume !(1 == ~t6_pc~0); 853097#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 853087#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 853078#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 853071#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 853065#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 853059#L658-36 assume !(1 == ~t7_pc~0); 853054#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 853049#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 853044#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 853039#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 853034#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 853030#L677-36 assume !(1 == ~t8_pc~0); 853025#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 853020#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 853014#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 853008#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 853003#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 852997#L696-36 assume 1 == ~t9_pc~0; 852991#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 852983#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 852976#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 852970#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 852965#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 852961#L715-36 assume !(1 == ~t10_pc~0); 852955#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 852949#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 852944#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 852939#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 852934#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 852928#L734-36 assume !(1 == ~t11_pc~0); 852921#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 852917#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 852913#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 852909#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 852903#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 852897#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 852893#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 852889#L1218-3 assume !(1 == ~T2_E~0); 852884#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 852877#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 852870#L1233-3 assume !(1 == ~T5_E~0); 852862#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 852750#L1243-3 assume !(1 == ~T7_E~0); 852743#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 852737#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 852729#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 852723#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 852716#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 852710#L1273-3 assume !(1 == ~E_2~0); 852703#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 852697#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 852690#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 852683#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 852676#L1298-3 assume !(1 == ~E_7~0); 852670#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 852664#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 852658#L1313-3 assume !(1 == ~E_10~0); 852655#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 852653#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 852541#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 852529#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 852523#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 852516#L1663 assume !(0 == start_simulation_~tmp~3#1); 852512#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 852484#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 839879#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 839880#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 839875#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 839876#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 839866#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 839867#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 770365#L1644-2 [2023-11-19 07:38:17,546 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:38:17,547 INFO L85 PathProgramCache]: Analyzing trace with hash 948156820, now seen corresponding path program 1 times [2023-11-19 07:38:17,547 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:38:17,547 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1987161290] [2023-11-19 07:38:17,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:38:17,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:38:17,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:38:17,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:38:17,614 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:38:17,615 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1987161290] [2023-11-19 07:38:17,615 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1987161290] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:38:17,615 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:38:17,615 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:38:17,615 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [454901420] [2023-11-19 07:38:17,616 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:38:17,616 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:38:17,616 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:38:17,616 INFO L85 PathProgramCache]: Analyzing trace with hash 362485887, now seen corresponding path program 1 times [2023-11-19 07:38:17,617 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:38:17,617 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1854289414] [2023-11-19 07:38:17,617 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:38:17,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:38:17,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:38:17,666 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:38:17,666 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:38:17,666 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1854289414] [2023-11-19 07:38:17,666 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1854289414] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:38:17,666 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:38:17,667 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:38:17,667 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [454409527] [2023-11-19 07:38:17,667 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:38:17,667 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:38:17,667 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:38:17,668 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:38:17,668 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:38:17,668 INFO L87 Difference]: Start difference. First operand 121125 states and 169011 transitions. cyclomatic complexity: 47918 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:38:17,986 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:38:17,986 INFO L93 Difference]: Finished difference Result 109336 states and 152007 transitions. [2023-11-19 07:38:17,986 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 109336 states and 152007 transitions. [2023-11-19 07:38:18,964 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 108834 [2023-11-19 07:38:19,207 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 109336 states to 109336 states and 152007 transitions. [2023-11-19 07:38:19,207 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 109336 [2023-11-19 07:38:19,260 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 109336 [2023-11-19 07:38:19,261 INFO L73 IsDeterministic]: Start isDeterministic. Operand 109336 states and 152007 transitions. [2023-11-19 07:38:19,302 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:38:19,302 INFO L218 hiAutomatonCegarLoop]: Abstraction has 109336 states and 152007 transitions. [2023-11-19 07:38:19,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109336 states and 152007 transitions. [2023-11-19 07:38:20,449 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109336 to 109336. [2023-11-19 07:38:20,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 109336 states, 109336 states have (on average 1.3902740177068853) internal successors, (152007), 109335 states have internal predecessors, (152007), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:38:20,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109336 states to 109336 states and 152007 transitions. [2023-11-19 07:38:20,807 INFO L240 hiAutomatonCegarLoop]: Abstraction has 109336 states and 152007 transitions. [2023-11-19 07:38:20,807 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:38:20,808 INFO L428 stractBuchiCegarLoop]: Abstraction has 109336 states and 152007 transitions. [2023-11-19 07:38:20,808 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-19 07:38:20,808 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 109336 states and 152007 transitions. [2023-11-19 07:38:21,113 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 108834 [2023-11-19 07:38:21,114 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:38:21,114 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:38:21,116 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:38:21,116 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:38:21,117 INFO L748 eck$LassoCheckResult]: Stem: 1000765#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1000766#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1001874#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1001875#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1001237#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1001238#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1001103#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1000992#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1000708#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1000359#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1000360#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1000405#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1000406#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1001385#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1001386#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1001435#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1000811#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1000812#L1090 assume !(0 == ~M_E~0); 1000858#L1090-2 assume !(0 == ~T1_E~0); 1000859#L1095-1 assume !(0 == ~T2_E~0); 1001603#L1100-1 assume !(0 == ~T3_E~0); 1001604#L1105-1 assume !(0 == ~T4_E~0); 1000627#L1110-1 assume !(0 == ~T5_E~0); 1000628#L1115-1 assume !(0 == ~T6_E~0); 1001032#L1120-1 assume !(0 == ~T7_E~0); 1001358#L1125-1 assume !(0 == ~T8_E~0); 1001992#L1130-1 assume !(0 == ~T9_E~0); 1001629#L1135-1 assume !(0 == ~T10_E~0); 1000816#L1140-1 assume !(0 == ~T11_E~0); 1000817#L1145-1 assume !(0 == ~E_1~0); 1001555#L1150-1 assume !(0 == ~E_2~0); 1001008#L1155-1 assume !(0 == ~E_3~0); 1001009#L1160-1 assume !(0 == ~E_4~0); 1001108#L1165-1 assume !(0 == ~E_5~0); 1001109#L1170-1 assume !(0 == ~E_6~0); 1001851#L1175-1 assume !(0 == ~E_7~0); 1001193#L1180-1 assume !(0 == ~E_8~0); 1001194#L1185-1 assume !(0 == ~E_9~0); 1000813#L1190-1 assume !(0 == ~E_10~0); 1000814#L1195-1 assume !(0 == ~E_11~0); 1001209#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1001024#L525 assume !(1 == ~m_pc~0); 1000449#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1000450#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1001724#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1001694#L1350 assume !(0 != activate_threads_~tmp~1#1); 1000803#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1000804#L544 assume !(1 == ~t1_pc~0); 1001030#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1001031#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1000423#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1000424#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1000652#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1001323#L563 assume !(1 == ~t2_pc~0); 1001541#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1000469#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1000470#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1000885#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1000886#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1001413#L582 assume !(1 == ~t3_pc~0); 1001554#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1001931#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1000351#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1000352#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1000535#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1000536#L601 assume !(1 == ~t4_pc~0); 1001569#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1001033#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1000545#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1000546#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1001564#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1001925#L620 assume !(1 == ~t5_pc~0); 1001375#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1001376#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1001432#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1001729#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1001946#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1001947#L639 assume !(1 == ~t6_pc~0); 1001356#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1000924#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1000925#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1000976#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1001038#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1001039#L658 assume !(1 == ~t7_pc~0); 1001263#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1001264#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1001957#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1001492#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1000806#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1000807#L677 assume !(1 == ~t8_pc~0); 1000828#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1000610#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1000611#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1000881#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1000882#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1001683#L696 assume !(1 == ~t9_pc~0); 1001336#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1001337#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1002047#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1001363#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1001364#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1001608#L715 assume !(1 == ~t10_pc~0); 1001891#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1001467#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1001251#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1001252#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1001186#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1000604#L734 assume !(1 == ~t11_pc~0); 1000605#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1001110#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1001196#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1000347#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1000348#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1001433#L1213 assume !(1 == ~M_E~0); 1001183#L1213-2 assume !(1 == ~T1_E~0); 1001184#L1218-1 assume !(1 == ~T2_E~0); 1000382#L1223-1 assume !(1 == ~T3_E~0); 1000383#L1228-1 assume !(1 == ~T4_E~0); 1001155#L1233-1 assume !(1 == ~T5_E~0); 1001948#L1238-1 assume !(1 == ~T6_E~0); 1001562#L1243-1 assume !(1 == ~T7_E~0); 1001563#L1248-1 assume !(1 == ~T8_E~0); 1001615#L1253-1 assume !(1 == ~T9_E~0); 1001616#L1258-1 assume !(1 == ~T10_E~0); 1001587#L1263-1 assume !(1 == ~T11_E~0); 1001588#L1268-1 assume !(1 == ~E_1~0); 1001382#L1273-1 assume !(1 == ~E_2~0); 1001383#L1278-1 assume !(1 == ~E_3~0); 1000922#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1000923#L1288-1 assume !(1 == ~E_5~0); 1001737#L1293-1 assume !(1 == ~E_6~0); 1001688#L1298-1 assume !(1 == ~E_7~0); 1001417#L1303-1 assume !(1 == ~E_8~0); 1000933#L1308-1 assume !(1 == ~E_9~0); 1000820#L1313-1 assume !(1 == ~E_10~0); 1000821#L1318-1 assume !(1 == ~E_11~0); 1000829#L1323-1 assume { :end_inline_reset_delta_events } true; 1000830#L1644-2 [2023-11-19 07:38:21,117 INFO L750 eck$LassoCheckResult]: Loop: 1000830#L1644-2 assume !false; 1083632#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1083624#L1065-1 assume !false; 1083617#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1083527#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1083513#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1083507#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1083498#L906 assume !(0 != eval_~tmp~0#1); 1083499#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1084096#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1084093#L1090-3 assume !(0 == ~M_E~0); 1084091#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1084089#L1095-3 assume !(0 == ~T2_E~0); 1084087#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1084085#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1084083#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1084081#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1084079#L1120-3 assume !(0 == ~T7_E~0); 1084077#L1125-3 assume !(0 == ~T8_E~0); 1084074#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1084072#L1135-3 assume !(0 == ~T10_E~0); 1084070#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1084068#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1084066#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1084065#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1084064#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1084063#L1165-3 assume !(0 == ~E_5~0); 1084062#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1084061#L1175-3 assume !(0 == ~E_7~0); 1084060#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1084059#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1084058#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1084056#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1084055#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1084054#L525-36 assume !(1 == ~m_pc~0); 1084053#L525-38 is_master_triggered_~__retres1~0#1 := 0; 1084052#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1084050#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1084049#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 1084048#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1084047#L544-36 assume !(1 == ~t1_pc~0); 1084046#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1084045#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1084044#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1084043#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1084042#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1084041#L563-36 assume !(1 == ~t2_pc~0); 1084039#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1084037#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1084035#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1084033#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1084031#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1084029#L582-36 assume !(1 == ~t3_pc~0); 1084027#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1084025#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1084023#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1084021#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1084019#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1084017#L601-36 assume !(1 == ~t4_pc~0); 1084014#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1084012#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1084009#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1084007#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1084005#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1084003#L620-36 assume !(1 == ~t5_pc~0); 1084001#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1083999#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1083997#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1083995#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 1083993#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1083991#L639-36 assume 1 == ~t6_pc~0; 1083988#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1083986#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1083983#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1083981#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1083979#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1083977#L658-36 assume !(1 == ~t7_pc~0); 1083974#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1083972#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1083970#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1083968#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1083966#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1083964#L677-36 assume !(1 == ~t8_pc~0); 1083962#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1083960#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1083957#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1083955#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1083953#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1083948#L696-36 assume !(1 == ~t9_pc~0); 1083945#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1083943#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1083941#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1083939#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 1083936#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1083934#L715-36 assume !(1 == ~t10_pc~0); 1083932#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1083930#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1083928#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1083926#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1083924#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1083922#L734-36 assume !(1 == ~t11_pc~0); 1083917#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 1083915#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1083913#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1083911#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1083908#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1083906#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1083904#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1083902#L1218-3 assume !(1 == ~T2_E~0); 1083900#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1083898#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1083896#L1233-3 assume !(1 == ~T5_E~0); 1083894#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1083892#L1243-3 assume !(1 == ~T7_E~0); 1083889#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1083887#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1083885#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1083883#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1083881#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1083879#L1273-3 assume !(1 == ~E_2~0); 1083877#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1083875#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1083873#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1083871#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1083869#L1298-3 assume !(1 == ~E_7~0); 1083867#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1083865#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1083863#L1313-3 assume !(1 == ~E_10~0); 1083861#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1083859#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1083844#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1083837#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1083835#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1083830#L1663 assume !(0 == start_simulation_~tmp~3#1); 1083828#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1083699#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1083688#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1083685#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1083682#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1083670#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1083657#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1083648#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1000830#L1644-2 [2023-11-19 07:38:21,118 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:38:21,118 INFO L85 PathProgramCache]: Analyzing trace with hash 1086953880, now seen corresponding path program 1 times [2023-11-19 07:38:21,118 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:38:21,119 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [749601656] [2023-11-19 07:38:21,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:38:21,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:38:21,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:38:21,219 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:38:21,219 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:38:21,219 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [749601656] [2023-11-19 07:38:21,220 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [749601656] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:38:21,220 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:38:21,220 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:38:21,220 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [693275741] [2023-11-19 07:38:21,220 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:38:21,221 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:38:21,221 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:38:21,221 INFO L85 PathProgramCache]: Analyzing trace with hash 825218844, now seen corresponding path program 1 times [2023-11-19 07:38:21,222 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:38:21,222 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [328863285] [2023-11-19 07:38:21,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:38:21,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:38:21,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:38:21,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:38:21,286 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:38:21,287 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [328863285] [2023-11-19 07:38:21,287 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [328863285] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:38:21,287 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:38:21,287 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:38:21,288 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [409464183] [2023-11-19 07:38:21,288 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:38:21,288 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:38:21,288 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:38:21,289 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:38:21,289 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:38:21,289 INFO L87 Difference]: Start difference. First operand 109336 states and 152007 transitions. cyclomatic complexity: 42703 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:38:22,931 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:38:22,931 INFO L93 Difference]: Finished difference Result 229309 states and 316962 transitions. [2023-11-19 07:38:22,931 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 229309 states and 316962 transitions. [2023-11-19 07:38:23,651 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 228232 [2023-11-19 07:38:24,985 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 229309 states to 229309 states and 316962 transitions. [2023-11-19 07:38:24,986 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 229309 [2023-11-19 07:38:25,089 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 229309 [2023-11-19 07:38:25,089 INFO L73 IsDeterministic]: Start isDeterministic. Operand 229309 states and 316962 transitions. [2023-11-19 07:38:25,180 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:38:25,181 INFO L218 hiAutomatonCegarLoop]: Abstraction has 229309 states and 316962 transitions. [2023-11-19 07:38:25,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 229309 states and 316962 transitions. [2023-11-19 07:38:26,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 229309 to 121125. [2023-11-19 07:38:26,910 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 121125 states, 121125 states have (on average 1.3846522187822496) internal successors, (167716), 121124 states have internal predecessors, (167716), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:38:27,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121125 states to 121125 states and 167716 transitions. [2023-11-19 07:38:27,150 INFO L240 hiAutomatonCegarLoop]: Abstraction has 121125 states and 167716 transitions. [2023-11-19 07:38:27,150 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:38:27,151 INFO L428 stractBuchiCegarLoop]: Abstraction has 121125 states and 167716 transitions. [2023-11-19 07:38:27,151 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2023-11-19 07:38:27,151 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 121125 states and 167716 transitions. [2023-11-19 07:38:27,451 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 120518 [2023-11-19 07:38:27,451 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:38:27,451 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:38:27,453 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:38:27,453 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:38:27,454 INFO L748 eck$LassoCheckResult]: Stem: 1339422#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1339423#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1340560#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1340561#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1339889#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1339890#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1339760#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1339648#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1339363#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1339014#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1339015#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1339058#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1339059#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1340039#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1340040#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1340091#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1339468#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1339469#L1090 assume !(0 == ~M_E~0); 1339511#L1090-2 assume !(0 == ~T1_E~0); 1339512#L1095-1 assume !(0 == ~T2_E~0); 1340263#L1100-1 assume !(0 == ~T3_E~0); 1340264#L1105-1 assume !(0 == ~T4_E~0); 1339280#L1110-1 assume !(0 == ~T5_E~0); 1339281#L1115-1 assume !(0 == ~T6_E~0); 1339687#L1120-1 assume !(0 == ~T7_E~0); 1340010#L1125-1 assume !(0 == ~T8_E~0); 1340692#L1130-1 assume !(0 == ~T9_E~0); 1340291#L1135-1 assume !(0 == ~T10_E~0); 1339473#L1140-1 assume !(0 == ~T11_E~0); 1339474#L1145-1 assume !(0 == ~E_1~0); 1340209#L1150-1 assume !(0 == ~E_2~0); 1339664#L1155-1 assume !(0 == ~E_3~0); 1339665#L1160-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1340683#L1165-1 assume !(0 == ~E_5~0); 1340534#L1170-1 assume !(0 == ~E_6~0); 1340535#L1175-1 assume !(0 == ~E_7~0); 1340852#L1180-1 assume !(0 == ~E_8~0); 1340851#L1185-1 assume !(0 == ~E_9~0); 1340850#L1190-1 assume !(0 == ~E_10~0); 1340849#L1195-1 assume !(0 == ~E_11~0); 1340499#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1340500#L525 assume !(1 == ~m_pc~0); 1340848#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1340489#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1340389#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1340358#L1350 assume !(0 != activate_threads_~tmp~1#1); 1339459#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1339460#L544 assume !(1 == ~t1_pc~0); 1339685#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1339686#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1340207#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1339303#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1339304#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1339974#L563 assume !(1 == ~t2_pc~0); 1340191#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1340192#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1339660#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1339661#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1340066#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1340067#L582 assume !(1 == ~t3_pc~0); 1340208#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1340634#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1340635#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1340545#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1339187#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1339188#L601 assume !(1 == ~t4_pc~0); 1340834#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1340833#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1340832#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1340831#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1340830#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1340829#L620 assume !(1 == ~t5_pc~0); 1340828#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1340827#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1340826#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1340825#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1340824#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1340823#L639 assume !(1 == ~t6_pc~0); 1340821#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1340820#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1340819#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1340818#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1340817#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1340816#L658 assume !(1 == ~t7_pc~0); 1340814#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1340813#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1340812#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1340811#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1340810#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1340809#L677 assume !(1 == ~t8_pc~0); 1340808#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1340807#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1340806#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1340805#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1340804#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1340803#L696 assume !(1 == ~t9_pc~0); 1340801#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1340799#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1340797#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1340795#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1340794#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1340793#L715 assume !(1 == ~t10_pc~0); 1340792#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1340791#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1340790#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1340789#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1340788#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1340787#L734 assume !(1 == ~t11_pc~0); 1340785#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1340784#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1340783#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1340782#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1340781#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1340780#L1213 assume !(1 == ~M_E~0); 1340779#L1213-2 assume !(1 == ~T1_E~0); 1340778#L1218-1 assume !(1 == ~T2_E~0); 1340777#L1223-1 assume !(1 == ~T3_E~0); 1340776#L1228-1 assume !(1 == ~T4_E~0); 1340775#L1233-1 assume !(1 == ~T5_E~0); 1340774#L1238-1 assume !(1 == ~T6_E~0); 1340773#L1243-1 assume !(1 == ~T7_E~0); 1340772#L1248-1 assume !(1 == ~T8_E~0); 1340771#L1253-1 assume !(1 == ~T9_E~0); 1340770#L1258-1 assume !(1 == ~T10_E~0); 1340769#L1263-1 assume !(1 == ~T11_E~0); 1340768#L1268-1 assume !(1 == ~E_1~0); 1340767#L1273-1 assume !(1 == ~E_2~0); 1340766#L1278-1 assume !(1 == ~E_3~0); 1340765#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1339576#L1288-1 assume !(1 == ~E_5~0); 1340405#L1293-1 assume !(1 == ~E_6~0); 1340352#L1298-1 assume !(1 == ~E_7~0); 1340071#L1303-1 assume !(1 == ~E_8~0); 1339587#L1308-1 assume !(1 == ~E_9~0); 1339477#L1313-1 assume !(1 == ~E_10~0); 1339478#L1318-1 assume !(1 == ~E_11~0); 1339485#L1323-1 assume { :end_inline_reset_delta_events } true; 1339486#L1644-2 [2023-11-19 07:38:27,454 INFO L750 eck$LassoCheckResult]: Loop: 1339486#L1644-2 assume !false; 1359779#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1359770#L1065-1 assume !false; 1359766#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1359690#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1359681#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1401673#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1398245#L906 assume !(0 != eval_~tmp~0#1); 1398246#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1435268#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1435267#L1090-3 assume !(0 == ~M_E~0); 1435266#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1435265#L1095-3 assume !(0 == ~T2_E~0); 1435264#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1435263#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1435262#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1435261#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1435259#L1120-3 assume !(0 == ~T7_E~0); 1435257#L1125-3 assume !(0 == ~T8_E~0); 1435255#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1435252#L1135-3 assume !(0 == ~T10_E~0); 1435251#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1435250#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1435245#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1435243#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1435240#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1435239#L1165-3 assume !(0 == ~E_5~0); 1435238#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1435237#L1175-3 assume !(0 == ~E_7~0); 1435236#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1435235#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1435234#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1435233#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1435232#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1435231#L525-36 assume !(1 == ~m_pc~0); 1435230#L525-38 is_master_triggered_~__retres1~0#1 := 0; 1435229#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1435228#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1435227#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 1435226#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1435225#L544-36 assume !(1 == ~t1_pc~0); 1435224#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1435223#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1435222#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1435221#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1435220#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1435219#L563-36 assume !(1 == ~t2_pc~0); 1435217#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1435216#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1435215#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1435214#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1435213#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1435212#L582-36 assume !(1 == ~t3_pc~0); 1435211#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1435210#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1435209#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1435208#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1435207#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1435206#L601-36 assume 1 == ~t4_pc~0; 1435204#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1435202#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1435201#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1435200#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1435199#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1435198#L620-36 assume !(1 == ~t5_pc~0); 1435197#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1435196#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1435195#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1435194#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 1435193#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1435192#L639-36 assume !(1 == ~t6_pc~0); 1435191#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1435189#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1435188#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1435187#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1435186#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1435185#L658-36 assume !(1 == ~t7_pc~0); 1435183#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1435182#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1435181#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1435180#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1435179#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1435178#L677-36 assume !(1 == ~t8_pc~0); 1435177#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1435176#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1435175#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1435174#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1435173#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1435172#L696-36 assume !(1 == ~t9_pc~0); 1435171#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1435169#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1435167#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1435165#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 1435163#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1435162#L715-36 assume !(1 == ~t10_pc~0); 1435161#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1435160#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1435159#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1435158#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1435157#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1435156#L734-36 assume 1 == ~t11_pc~0; 1435155#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1435153#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1435152#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1435151#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1435150#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1435149#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1435148#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1435147#L1218-3 assume !(1 == ~T2_E~0); 1435146#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1435145#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1435144#L1233-3 assume !(1 == ~T5_E~0); 1435143#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1435142#L1243-3 assume !(1 == ~T7_E~0); 1435141#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1435140#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1435139#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1435138#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1435137#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1435136#L1273-3 assume !(1 == ~E_2~0); 1435135#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1435133#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1435131#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1435129#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1435126#L1298-3 assume !(1 == ~E_7~0); 1435124#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1435122#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1435120#L1313-3 assume !(1 == ~E_10~0); 1435118#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1435116#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1435098#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1435091#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1435088#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1435014#L1663 assume !(0 == start_simulation_~tmp~3#1); 1435012#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1435004#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1434993#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1434991#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1434988#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1434986#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1434822#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1434820#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1339486#L1644-2 [2023-11-19 07:38:27,455 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:38:27,455 INFO L85 PathProgramCache]: Analyzing trace with hash 968512406, now seen corresponding path program 1 times [2023-11-19 07:38:27,455 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:38:27,456 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1109069066] [2023-11-19 07:38:27,456 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:38:27,456 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:38:27,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:38:27,532 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:38:27,532 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:38:27,532 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1109069066] [2023-11-19 07:38:27,532 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1109069066] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:38:27,532 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:38:27,533 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:38:27,533 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2137817994] [2023-11-19 07:38:27,533 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:38:27,533 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:38:27,534 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:38:27,534 INFO L85 PathProgramCache]: Analyzing trace with hash -1344743491, now seen corresponding path program 1 times [2023-11-19 07:38:27,534 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:38:27,534 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1768036256] [2023-11-19 07:38:27,534 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:38:27,535 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:38:27,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:38:27,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:38:27,585 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:38:27,585 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1768036256] [2023-11-19 07:38:27,585 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1768036256] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:38:27,585 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:38:27,585 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:38:27,586 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [105217456] [2023-11-19 07:38:27,586 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:38:27,586 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:38:27,586 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:38:27,587 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:38:27,587 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:38:27,587 INFO L87 Difference]: Start difference. First operand 121125 states and 167716 transitions. cyclomatic complexity: 46623 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:38:28,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:38:28,910 INFO L93 Difference]: Finished difference Result 181684 states and 250784 transitions. [2023-11-19 07:38:28,910 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 181684 states and 250784 transitions. [2023-11-19 07:38:29,602 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 180882 [2023-11-19 07:38:29,986 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 181684 states to 181684 states and 250784 transitions. [2023-11-19 07:38:29,986 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 181684 [2023-11-19 07:38:30,056 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 181684 [2023-11-19 07:38:30,056 INFO L73 IsDeterministic]: Start isDeterministic. Operand 181684 states and 250784 transitions. [2023-11-19 07:38:30,134 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:38:30,134 INFO L218 hiAutomatonCegarLoop]: Abstraction has 181684 states and 250784 transitions. [2023-11-19 07:38:30,211 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181684 states and 250784 transitions. [2023-11-19 07:38:31,948 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181684 to 109336. [2023-11-19 07:38:32,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 109336 states, 109336 states have (on average 1.3784297943952586) internal successors, (150712), 109335 states have internal predecessors, (150712), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:38:32,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109336 states to 109336 states and 150712 transitions. [2023-11-19 07:38:32,204 INFO L240 hiAutomatonCegarLoop]: Abstraction has 109336 states and 150712 transitions. [2023-11-19 07:38:32,205 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:38:32,205 INFO L428 stractBuchiCegarLoop]: Abstraction has 109336 states and 150712 transitions. [2023-11-19 07:38:32,205 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2023-11-19 07:38:32,206 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 109336 states and 150712 transitions. [2023-11-19 07:38:33,161 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 108834 [2023-11-19 07:38:33,161 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:38:33,161 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:38:33,163 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:38:33,163 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:38:33,164 INFO L748 eck$LassoCheckResult]: Stem: 1642242#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1642243#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1643392#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1643393#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1642710#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1642711#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1642578#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1642468#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1642183#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1641833#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1641834#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1641877#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1641878#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1642870#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1642871#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1642925#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1642290#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1642291#L1090 assume !(0 == ~M_E~0); 1642339#L1090-2 assume !(0 == ~T1_E~0); 1642340#L1095-1 assume !(0 == ~T2_E~0); 1643091#L1100-1 assume !(0 == ~T3_E~0); 1643092#L1105-1 assume !(0 == ~T4_E~0); 1642104#L1110-1 assume !(0 == ~T5_E~0); 1642105#L1115-1 assume !(0 == ~T6_E~0); 1642508#L1120-1 assume !(0 == ~T7_E~0); 1642837#L1125-1 assume !(0 == ~T8_E~0); 1643530#L1130-1 assume !(0 == ~T9_E~0); 1643115#L1135-1 assume !(0 == ~T10_E~0); 1642294#L1140-1 assume !(0 == ~T11_E~0); 1642295#L1145-1 assume !(0 == ~E_1~0); 1643037#L1150-1 assume !(0 == ~E_2~0); 1642483#L1155-1 assume !(0 == ~E_3~0); 1642484#L1160-1 assume !(0 == ~E_4~0); 1642583#L1165-1 assume !(0 == ~E_5~0); 1642584#L1170-1 assume !(0 == ~E_6~0); 1643366#L1175-1 assume !(0 == ~E_7~0); 1642666#L1180-1 assume !(0 == ~E_8~0); 1642667#L1185-1 assume !(0 == ~E_9~0); 1642288#L1190-1 assume !(0 == ~E_10~0); 1642289#L1195-1 assume !(0 == ~E_11~0); 1642682#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1642500#L525 assume !(1 == ~m_pc~0); 1641920#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1641921#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1643214#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1643183#L1350 assume !(0 != activate_threads_~tmp~1#1); 1642279#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1642280#L544 assume !(1 == ~t1_pc~0); 1642504#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1642505#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1641900#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1641901#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1642127#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1642803#L563 assume !(1 == ~t2_pc~0); 1643025#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1641942#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1641943#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1642361#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1642362#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1642896#L582 assume !(1 == ~t3_pc~0); 1643036#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1643466#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1641825#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1641826#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1642009#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1642010#L601 assume !(1 == ~t4_pc~0); 1643056#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1642509#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1642023#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1642024#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1643047#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1643457#L620 assume !(1 == ~t5_pc~0); 1642858#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1642859#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1642915#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1643220#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1643480#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1643481#L639 assume !(1 == ~t6_pc~0); 1642835#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1642401#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1642402#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1642453#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1642514#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1642515#L658 assume !(1 == ~t7_pc~0); 1642739#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1642740#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1643496#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1642974#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1642282#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1642283#L677 assume !(1 == ~t8_pc~0); 1642308#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1642091#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1642092#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1642357#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1642358#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1643170#L696 assume !(1 == ~t9_pc~0); 1642820#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1642821#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1643594#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1642846#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1642847#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1643096#L715 assume !(1 == ~t10_pc~0); 1643413#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1642951#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1642725#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1642726#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1642659#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1642079#L734 assume !(1 == ~t11_pc~0); 1642080#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1642588#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1642671#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1641823#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1641824#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1642916#L1213 assume !(1 == ~M_E~0); 1642657#L1213-2 assume !(1 == ~T1_E~0); 1642658#L1218-1 assume !(1 == ~T2_E~0); 1641856#L1223-1 assume !(1 == ~T3_E~0); 1641857#L1228-1 assume !(1 == ~T4_E~0); 1642631#L1233-1 assume !(1 == ~T5_E~0); 1643482#L1238-1 assume !(1 == ~T6_E~0); 1643045#L1243-1 assume !(1 == ~T7_E~0); 1643046#L1248-1 assume !(1 == ~T8_E~0); 1643100#L1253-1 assume !(1 == ~T9_E~0); 1643101#L1258-1 assume !(1 == ~T10_E~0); 1643074#L1263-1 assume !(1 == ~T11_E~0); 1643075#L1268-1 assume !(1 == ~E_1~0); 1642863#L1273-1 assume !(1 == ~E_2~0); 1642864#L1278-1 assume !(1 == ~E_3~0); 1642397#L1283-1 assume !(1 == ~E_4~0); 1642398#L1288-1 assume !(1 == ~E_5~0); 1643226#L1293-1 assume !(1 == ~E_6~0); 1643179#L1298-1 assume !(1 == ~E_7~0); 1642901#L1303-1 assume !(1 == ~E_8~0); 1642409#L1308-1 assume !(1 == ~E_9~0); 1642298#L1313-1 assume !(1 == ~E_10~0); 1642299#L1318-1 assume !(1 == ~E_11~0); 1642309#L1323-1 assume { :end_inline_reset_delta_events } true; 1642310#L1644-2 [2023-11-19 07:38:33,164 INFO L750 eck$LassoCheckResult]: Loop: 1642310#L1644-2 assume !false; 1734295#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1734292#L1065-1 assume !false; 1659416#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1659417#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1702950#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1702946#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1702947#L906 assume !(0 != eval_~tmp~0#1); 1707213#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1734570#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1734569#L1090-3 assume !(0 == ~M_E~0); 1734568#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1734567#L1095-3 assume !(0 == ~T2_E~0); 1734566#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1734565#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1734564#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1734563#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1734562#L1120-3 assume !(0 == ~T7_E~0); 1734561#L1125-3 assume !(0 == ~T8_E~0); 1734560#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1734559#L1135-3 assume !(0 == ~T10_E~0); 1734558#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1734557#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1734556#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1734555#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1734554#L1160-3 assume !(0 == ~E_4~0); 1734553#L1165-3 assume !(0 == ~E_5~0); 1734552#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1734551#L1175-3 assume !(0 == ~E_7~0); 1734550#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1734549#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1734548#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1734547#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1734546#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1734545#L525-36 assume !(1 == ~m_pc~0); 1734544#L525-38 is_master_triggered_~__retres1~0#1 := 0; 1734543#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1734542#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1734541#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 1734540#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1734538#L544-36 assume !(1 == ~t1_pc~0); 1734536#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1734534#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1734532#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1734530#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1734528#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1734526#L563-36 assume !(1 == ~t2_pc~0); 1734523#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1734521#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1734519#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1734517#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1734515#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1734513#L582-36 assume !(1 == ~t3_pc~0); 1734510#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1734508#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1734506#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1734504#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1734502#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1734500#L601-36 assume !(1 == ~t4_pc~0); 1734497#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1734495#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1734493#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1734491#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1734489#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1734486#L620-36 assume !(1 == ~t5_pc~0); 1734484#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1734482#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1734480#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1734478#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 1734476#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1734474#L639-36 assume !(1 == ~t6_pc~0); 1734472#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1734469#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1734467#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1734465#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1734463#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1734461#L658-36 assume !(1 == ~t7_pc~0); 1734457#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1734455#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1734453#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1734451#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1734449#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1734446#L677-36 assume !(1 == ~t8_pc~0); 1734444#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1734442#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1734440#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1734438#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1734436#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1734434#L696-36 assume 1 == ~t9_pc~0; 1734431#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1734428#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1734425#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1734422#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1734420#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1734418#L715-36 assume !(1 == ~t10_pc~0); 1734415#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1734412#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1734409#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1734406#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1734404#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1734402#L734-36 assume !(1 == ~t11_pc~0); 1734399#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 1734397#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1734395#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1734393#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1734391#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1734389#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1734386#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1734384#L1218-3 assume !(1 == ~T2_E~0); 1734382#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1734380#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1734378#L1233-3 assume !(1 == ~T5_E~0); 1734376#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1734374#L1243-3 assume !(1 == ~T7_E~0); 1734372#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1734370#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1734368#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1734366#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1734364#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1734362#L1273-3 assume !(1 == ~E_2~0); 1734360#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1734358#L1283-3 assume !(1 == ~E_4~0); 1734356#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1734354#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1734352#L1298-3 assume !(1 == ~E_7~0); 1734350#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1734348#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1734346#L1313-3 assume !(1 == ~E_10~0); 1734344#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1734342#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1734332#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1734325#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1734323#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1734320#L1663 assume !(0 == start_simulation_~tmp~3#1); 1734319#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1734316#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1734306#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1734305#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1734304#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1734303#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1734301#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1734299#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1642310#L1644-2 [2023-11-19 07:38:33,165 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:38:33,165 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 1 times [2023-11-19 07:38:33,165 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:38:33,165 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [773918096] [2023-11-19 07:38:33,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:38:33,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:38:33,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:38:33,190 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:38:33,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:38:33,351 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:38:33,352 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:38:33,352 INFO L85 PathProgramCache]: Analyzing trace with hash -581218526, now seen corresponding path program 1 times [2023-11-19 07:38:33,352 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:38:33,352 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1782622751] [2023-11-19 07:38:33,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:38:33,368 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:38:33,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:38:33,434 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:38:33,434 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:38:33,434 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1782622751] [2023-11-19 07:38:33,434 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1782622751] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:38:33,434 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:38:33,435 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:38:33,435 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [692170147] [2023-11-19 07:38:33,435 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:38:33,435 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:38:33,436 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:38:33,436 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:38:33,436 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:38:33,437 INFO L87 Difference]: Start difference. First operand 109336 states and 150712 transitions. cyclomatic complexity: 41408 Second operand has 3 states, 3 states have (on average 47.333333333333336) internal successors, (142), 3 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:38:33,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:38:33,843 INFO L93 Difference]: Finished difference Result 121125 states and 167171 transitions. [2023-11-19 07:38:33,843 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 121125 states and 167171 transitions. [2023-11-19 07:38:34,280 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 120518